Photodetection element
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HAMAMATSU PHOTONICS KK
- Filing Date
- 2026-01-28
- Publication Date
- 2026-08-06
Smart Images
Figure JP2026002905_06082026_PF_FP_ABST
Abstract
Description
Photodetector
[0001] This disclosure relates to a photodetector.
[0002] Known photodetectors include a semiconductor substrate comprising a first surface and a second surface facing each other (see, for example, Patent Document 1). The semiconductor substrate is provided with a plurality of avalanche photodiodes, each electrically connected to a corresponding quenching element and operating in Geiger mode. The semiconductor substrate includes a substrate layer including the second surface and a semiconductor layer including the first surface. Each of the plurality of avalanche photodiodes is arranged within the semiconductor layer and includes a semiconductor region having a conductivity type different from that of the semiconductor layer.
[0003] Japanese Patent Publication No. 2018-113397
[0004] In the photodetector equipped with the semiconductor substrate described above, quantum efficiency and avalanche probability affect the detection efficiency. Quantum efficiency indicates the probability that incident light generates carriers. Avalanche probability indicates the probability that the generated carriers cause avalanche multiplication. Detection efficiency indicates the ratio of the number of detected photons to the number of incident photons. For example, if the avalanche probability or quantum efficiency increases, the detection efficiency in the photodetector described above improves. However, if the avalanche probability increases, the quantum efficiency may decrease, and if the quantum efficiency increases, the avalanche probability may decrease. Therefore, a photodetector that increases both the avalanche probability and quantum efficiency will improve detection efficiency.
[0005] This disclosure aims to provide a photodetector that improves detection efficiency.
[0006] One aspect of the present disclosure of a photodetector includes [1] a semiconductor substrate comprising a plurality of avalanche photodiodes, each having a first surface and a second surface facing each other, each electrically connected to a corresponding quenching element and operating in Geiger mode, wherein the semiconductor substrate comprises a substrate layer including the second surface, a first semiconductor layer including the first surface and having a first conductivity type, and a second semiconductor layer bonded to the first semiconductor layer between the substrate layer and the first semiconductor layer and having the first conductivity type, wherein the semiconductor substrate has trenches between adjacent avalanche photodiodes, and each of the plurality of avalanche photodiodes is arranged within the first semiconductor layer. The photodetector comprises a first semiconductor region having a second conductivity type different from the first conductivity type, and a second semiconductor region having the second conductivity type, which is located within the first semiconductor layer between the first semiconductor region and the second semiconductor layer, is bonded to the first semiconductor region so as not to be in contact with the first semiconductor region and the first semiconductor layer, and the trench opens to the first surface and reaches at least the second semiconductor layer, the second semiconductor region has an impurity concentration lower than that of the first semiconductor region, and is spaced apart from the second semiconductor layer in a direction in which the first surface and the second surface face each other, and the impurity concentration of the first semiconductor layer is higher than that of the second semiconductor layer.
[0007] The avalanche probability is affected by the strength of the electric field generated in the first semiconductor layer, including the first surface, when a voltage is applied to the photodetector. For example, the stronger the electric field, the more likely avalanche multiplication is to occur, and therefore the avalanche probability increases. In the photodetector described in [1] above, the first semiconductor layer, including the first surface, has a higher impurity concentration than the second semiconductor layer. Therefore, in the photodetector described in [1] above, the strength of the electric field generated in the first semiconductor layer increases when a voltage is applied. The quantum efficiency is affected by the ease with which the depletion layer spreads from the first semiconductor region in the direction in which the first and second surfaces face each other. The ease with which the depletion layer spreads is affected by the impurity concentration in the region where the depletion layer can spread. For example, if the impurity concentration in the region where the depletion layer can spread is low, the ease with which the depletion layer spreads improves. In the photodetector described in [1] above, the impurity concentration in the second semiconductor layer is lower than the impurity concentration in the first semiconductor layer. Therefore, in the second semiconductor layer, the depletion layer tends to spread in the direction in which the first and second surfaces face each other, compared to the first semiconductor layer. That is, in the photodetector described in [1] above, compared to a configuration in which the first and second semiconductor layers have the same impurity concentration, the depletion layer tends to spread from the first semiconductor region in the direction in which the first and second surfaces face each other. From the above, the photodetector described in [1] above increases both the avalanche probability and the quantum efficiency. Therefore, the photodetector described in [1] above improves the detection efficiency.
[0008] One aspect of the present disclosure is a photodetector element described in [1] above, which is a photodetector element described in [2] above, wherein each of the plurality of avalanche photodiodes is arranged in the first semiconductor layer so as to be located between the second semiconductor region and the second semiconductor layer and is bonded to the second semiconductor region, and further includes a third semiconductor region having the first conductivity type, wherein the third semiconductor region has an impurity concentration higher than that of the first semiconductor layer. In the photodetector element described in [2] above, the third semiconductor region having an impurity concentration higher than that of the first semiconductor layer is bonded to the second semiconductor region. The third semiconductor region having an impurity concentration higher than that of the first semiconductor layer increases the avalanche probability. Therefore, the photodetector element described in [2] above further improves the detection efficiency.
[0009] One aspect of the present disclosure is a photodetector described in [2] above, wherein the difference between the impurity concentration in the third semiconductor region and the impurity concentration in the first semiconductor layer is smaller than the difference between the impurity concentration in the first semiconductor layer and the impurity concentration in the second semiconductor layer. The photodetector described in [3] above further increases both the avalanche probability and the quantum efficiency. Therefore, the photodetector described in [3] above further improves the detection efficiency.
[0010] One aspect of the present disclosure is a photodetector [4] "the photodetector according to [2] or [3] above, wherein, when viewed from the direction in which the first surface and the second surface face each other, the third semiconductor region has a width greater than the width of the first semiconductor region." In the photodetector according to [4] above, the width of the third semiconductor region is greater than the width of the first semiconductor region. The third semiconductor region having a width greater than the width of the first semiconductor region suppresses a decrease in the region of the first semiconductor region that functions as a multiplication region. Therefore, the photodetector according to [4] above suppresses a decrease in avalanche probability. As a result of the above, the photodetector according to [4] above suppresses a decrease in detection efficiency.
[0011] One aspect of the present disclosure is a photodetector according to any one of [2] to [4], which is a photodetector according to [5], wherein, when viewed from the direction in which the first surface and the second surface face each other, the second semiconductor region has a width greater than the width of the third semiconductor region. When the electric field increases locally in the first semiconductor region, an unintended breakdown may occur at the location in the first semiconductor region where the electric field increases locally, at a voltage lower than the voltage that operates the avalanche photodiode in Geiger mode. Hereinafter, the unintended breakdown may be referred to as "edge breakdown". In the photodetector according to [5], the second semiconductor region has a width greater than the width of the third semiconductor region. The second semiconductor region having a width greater than the width of the third semiconductor region suppresses the local increase in the electric field in the first semiconductor region. Therefore, the photodetector according to [5] suppresses the occurrence of edge breakdown.
[0012] One aspect of the present disclosure is a photodetector according to any one of [1] to [5] above, wherein the semiconductor substrate is located between the substrate layer and the second semiconductor layer and further includes a third semiconductor layer having the first conductivity type, and the third semiconductor layer has an impurity concentration higher than that of the first semiconductor layer. In the photodetector according to [6] above, the third semiconductor layer having an impurity concentration higher than that of the first semiconductor layer is located between the substrate layer and the second semiconductor layer. The third semiconductor layer suppresses, for example, the inflow of carriers generated by light incident on the semiconductor substrate from the substrate layer to the second semiconductor layer. Therefore, the photodetector according to [6] above suppresses the generation of noise.
[0013] One aspect of the present disclosure is a photodetector according to any one of [1] to [6] above, wherein the second semiconductor layer has a thickness greater than that of the first semiconductor layer. In the photodetector according to [7] above, the second semiconductor layer has a thickness greater than that of the first semiconductor layer. The second semiconductor layer having a thickness greater than that of the first semiconductor layer increases the region in which the depletion layer can spread. Therefore, the photodetector according to [7] above further increases the quantum efficiency. As a result, the photodetector according to [7] above further improves the detection efficiency.
[0014] One aspect of the present disclosure is a photodetector according to any one of [1] to [7] above, wherein, when viewed from the direction in which the first surface and the second surface face each other, each corner of the first semiconductor region is rounded. The photodetector according to [8] above suppresses the concentration of electric fields at each corner of the first semiconductor region.
[0015] One aspect of the present disclosure is a photodetector according to any one of [1] to [8] above, wherein each of the plurality of avalanche photodiodes extends along the trench in the direction in which the first surface and the second surface face each other and constitutes a side surface of the trench, and further includes a fourth semiconductor region having the first conductivity type, wherein the fourth semiconductor region has an impurity concentration higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer. In the photodetector according to [9] above, the impurity concentration of the fourth semiconductor region constituting the side surface of the trench is higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer. Therefore, the photodetector according to [9] above can further improve detection efficiency.
[0016] This disclosure provides a photodetector that improves detection efficiency.
[0017] Figure 1 is a diagram showing the cross-sectional configuration of a photodetector element according to one embodiment. Figure 2 is a circuit diagram showing the relationship between an avalanche photodiode and a quenching element. Figure 3 is a plan view showing the configuration of multiple avalanche photodiodes. Figure 4 is a diagram showing the change in impurity concentration. Figure 5 is a diagram showing the change in electric field strength. Figure 6 is a diagram showing the change in electric field strength. Figure 7 is a diagram showing the cross-sectional configuration of a photodetector element according to a modified example of this embodiment. Figure 8 is a diagram showing the cross-sectional configuration of a photodetector element according to a modified example of this embodiment.
[0018] The embodiments will be described in detail below with reference to the attached drawings. In this description, the same reference numerals will be used for elements that are the same or have the same function, and redundant explanations will be omitted.
[0019] First, the photodetector element 1 according to this embodiment will be described with reference to Figures 1 to 4. Figure 1 is a diagram showing the cross-sectional configuration of the photodetector element according to this embodiment. Figure 2 is a circuit diagram showing the relationship between the avalanche photodiode and the quenching element. Figure 3 is a plan view showing the configuration of multiple avalanche photodiodes. Figure 4 is a diagram showing the change in impurity concentration.
[0020] As shown in Figure 1, the photodetector 1 comprises a semiconductor substrate 11 on which a plurality of avalanche photodiodes (APDs) are provided. The semiconductor substrate 11 includes, for example, a substrate containing silicon (Si). For example, the semiconductor substrate 11 has a polygonal shape in plan view. In this embodiment, the semiconductor substrate 11 has a rectangular shape in plan view. For example, the rectangular shape includes shapes where each corner is chamfered and shapes where each corner is rounded. The semiconductor substrate 11 includes two opposing surfaces 11a and 11b. For example, surface 11a includes the surface of the semiconductor substrate 11, and surface 11b includes the back surface of the semiconductor substrate 11. In this embodiment, the photodetector 1 is a surface-incident type photodetector, and surface 11a includes the light incidence surface to the semiconductor substrate 11.
[0021] For example, the direction in which surfaces 11a and 11b face each other includes a first direction D1. In this embodiment, the first direction D1 includes a direction perpendicular to surfaces 11a and 11b. For example, two directions that intersect the first direction D1 and are along surfaces 11a and 11b include a second direction D2 and a third direction D3. The first direction D1, the second direction D2, and the third direction D3 intersect each other, for example. In this embodiment, the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other.
[0022] The semiconductor substrate 11 includes a plurality of cells U. For example, the plurality of cells U may be arranged in a one-dimensional or two-dimensional array. In the photodetector element 1, a signal corresponding to the light incident on each cell U is extracted from each cell U. Each cell U includes an avalanche photodiode APD that is electrically connected to a corresponding quenching element R1. In this embodiment, each of the plurality of avalanche photodiodes APD is electrically connected to a corresponding quenching element R1. For example, the quenching element R1 may include a quenching resistor or a quenching circuit including a transistor. In the photodetector element 1, a plurality of cells U, each including an avalanche photodiode APD that is electrically connected to a corresponding quenching element R1, may be connected in parallel to form a single channel. Alternatively, in the photodetector element 1, each of the plurality of cells U may constitute a single channel.
[0023] As shown in Figure 2, each avalanche photodiode APD is connected in series with the corresponding quenching element R1. The cathodes of each avalanche photodiode APD are connected in common, and the anodes are connected in common via the quenching element R1. Each of the multiple avalanche photodiodes APD operates in Geiger mode. In Geiger mode, a reverse bias voltage greater than the breakdown voltage of the avalanche photodiode APD is applied between the anode and cathode of the avalanche photodiode APD. In the photodetector element 1, a negative potential is applied to the anode and a positive potential is applied to the cathode.
[0024] For example, the quenching element R1 may be provided on the semiconductor substrate 11. That is, in the photodetector element 1, the semiconductor substrate 11 may include the quenching element R1. Alternatively, the quenching element R1 may be provided on a circuit board that processes the signals extracted from each cell U. The circuit board may include, for example, an ASIC (Application Specific Integrated Circuit).
[0025] The semiconductor substrate 11 has a thickness of, for example, 100 μm or more and 700 μm or less. In this embodiment, the semiconductor substrate 11 has a thickness of 208 μm. For example, the thickness of the semiconductor substrate 11 includes the length of the semiconductor substrate 11 in a first direction D1. That is, the thickness direction of the semiconductor substrate 11 includes, for example, the first direction D1. The length of the semiconductor substrate 11 in a first direction D1 includes, for example, the distance between surfaces 11a and 11b in the first direction D1.
[0026] The semiconductor substrate 11 includes a substrate layer 12, a semiconductor layer 13, a semiconductor layer 14, and a semiconductor layer 15. The substrate layer 12 includes a surface 11b. The substrate layer 12 includes, for example, the back surface of the semiconductor substrate 11. The substrate layer 12 has a thickness T1. The thickness T1 is, for example, 100 μm or more and 650 μm or less. In this embodiment, the thickness T1 is 200 μm. For example, the thickness T1 includes the length of the substrate layer 12 in the first direction D1.
[0027] The semiconductor layer 13 is disposed on the substrate layer 12. The semiconductor layer 13 includes a surface 11a. The semiconductor layer 13 includes, for example, the surface of the semiconductor substrate 11. For example, if surface 11a includes a first surface, then surface 11b includes a second surface.
[0028] The semiconductor layer 13 has a thickness T2. The thickness T2 is, for example, 0.1 μm or more and 5 μm or less. In the present embodiment, the thickness T2 is 1 μm. For example, the thickness T2 includes the length in the first direction D1 that the semiconductor layer 13 has. The semiconductor layer 13 has a first conductivity type. The first conductivity type includes, for example, a p-type. In the present embodiment, the semiconductor layer 13 includes a p+-type semiconductor layer. The “+” attached to the conductivity type indicates a high impurity concentration. The semiconductor layer 13 has an impurity concentration of, for example, 1.0×10 １３ cm －３ or more and 1.0×10 １７ cm －３ or less. The impurity concentration that the semiconductor layer 13 has includes, for example, the concentration of p-type impurities.
[0029] The semiconductor layer 14 is disposed on the substrate layer 12. In the present embodiment, the semiconductor layer 14 is disposed between the substrate layer 12 and the semiconductor layer 13. The semiconductor layer 14 is joined to the semiconductor layer 13 between the substrate layer 12 and the semiconductor layer 13.
[0030] The semiconductor layer 14 has a thickness T3. The thickness T3 is, for example, 1 μm or more and 50 μm or less. In the present embodiment, the thickness T3 is 5 μm. For example, the thickness T3 includes the length in the first direction D1 that the semiconductor layer 14 has. The semiconductor layer 14 has a first conductivity type. In the present embodiment, the semiconductor layer 14 includes a p-type semiconductor layer. The semiconductor layer 14 has an impurity concentration of, for example, 1.0×10 １２ cm －３ or more and 1.0×10 １６ cm －３ or less. The impurity concentration that the semiconductor layer 14 has includes, for example, the concentration of p-type impurities.
[0031] The semiconductor layer 15 is disposed on the substrate layer 12. The semiconductor layer 15 is disposed between the substrate layer 12 and the semiconductor layer 14. In the present embodiment, the semiconductor layer 15 is joined to the substrate layer 12 and the semiconductor layer 14 between the substrate layer 12 and the semiconductor layer 14. In the present embodiment, the semiconductor substrate 11 includes only the substrate layer 12, the semiconductor layer 13, the semiconductor layer 14, and the semiconductor layer 15. In the present embodiment, in the semiconductor substrate 11, the substrate layer 12, the semiconductor layer 15, the semiconductor layer 14, and the semiconductor layer 13 are arranged in this order. For example, when the semiconductor layer 13 includes a first semiconductor layer, the semiconductor layer 14 includes a second semiconductor layer, and the semiconductor layer 15 includes a third semiconductor layer.
[0032] The semiconductor layer 15 has a thickness T4. The thickness T4 is, for example, 0.5 μm or more and 10 μm or less. In the present embodiment, the thickness T4 is 2 μm. For example, the thickness T4 includes the length in the first direction D1 that the semiconductor layer 15 has. The semiconductor layer 15 has a first conductivity type. In the present embodiment, the semiconductor layer 15 includes a p+-type semiconductor layer. The semiconductor layer 15 has an impurity concentration of, for example, 1.0×10 １７ cm －３ or more and 1.0×10 ２１ cm －３ or less. The impurity concentration that the semiconductor layer 15 has includes, for example, the concentration of p-type impurities.
[0033] For example, thicknesses T1, T2, T3, and T4 may be different from each other. In this embodiment, thickness T3 is greater than thicknesses T2 and T4. That is, semiconductor layer 14 has a thickness T3 that is greater than the thickness T2 of semiconductor layer 13 and the thickness T4 of semiconductor layer 15. The ratio of thickness T2 to thickness T3 may be, for example, 0.2% or more and 90% or less. The ratio of thickness T4 to thickness T3 may be, for example, 1.0% or more and 90% or less. In this embodiment, thickness T2 is less than thickness T4. That is, semiconductor layer 13 has a thickness T2 that is less than the thickness T4 of semiconductor layer 15. The ratio of thickness T2 to thickness T4 may be, for example, 10% or more and 90% or less. In this embodiment, thickness T1 is greater than thicknesses T2, T3, and T4. That is, in this embodiment, the relationship between the magnitudes of thicknesses T1, T2, T3, and T4 satisfies the relationship T1 > T3 > T4 > T2. The thickness T1 may be less than or equal to the thicknesses T2, T3, and T4.
[0034] In the semiconductor substrate 11, trenches TR are provided between adjacent avalanche photodiodes APDs. The trenches TR open to the surface 11a. The trenches TR extend in a first direction D1. That is, the depth direction of the trenches TR includes the thickness direction of the semiconductor substrate 11. The trenches TR reach at least the semiconductor layer 14. In this embodiment, the trenches TR reach the semiconductor layer 14 but do not reach the semiconductor layer 15. The bottom of the trenches TR is located within the semiconductor layer 14.
[0035] In this embodiment, the trenches TR physically separate adjacent cells U from each other among a plurality of cells U. The trenches TR surround each cell U when viewed from the first direction D1 on the surface 11a. The adjacent cells U are electrically isolated from each other by the trenches TR. In this embodiment, the trenches TR are arranged in a grid pattern on the semiconductor substrate 11 when viewed from the first direction D1 on the surface 11a.
[0036] A light-shielding member 16 may be placed in the trench TR. That is, the photodetector 1 may be equipped with a light-shielding member 16. The light-shielding member 16 may contain a material that reflects light or a material that absorbs light. The light-shielding member 16 may contain, for example, tungsten (W). The light-shielding member 16 is formed, for example, by filling the trench TR with a material that reflects light or a material that absorbs light.
[0037] The photodetector element 1 further comprises a wiring layer 17. In this embodiment, the wiring layer 17 includes an insulating layer 171, an electrode 172, an electrode 173, and an insulating layer 174. The insulating layer 171 is arranged on a surface 11a. Contact holes are formed in the insulating layer 171 at positions corresponding to each of the multiple avalanche photodiodes (APDs).
[0038] The electrode 172 is positioned on the insulating layer 171. For example, the electrode 172 is positioned on the insulating layer 171 so as to be spaced apart from the electrode 173 in a second direction D2. The electrode 172 includes one end that is electrically connected to one end of the quenching element R1 and the other end that is electrically connected to an electrode pad (not shown). For example, a bonding wire for extracting a signal is connected to the electrode pad.
[0039] The electrode 173 is arranged on the insulating layer 171. The electrode 173 includes one end that is electrically connected to a corresponding avalanche photodiode APD among a plurality of avalanche photodiodes APD, and the other end that is electrically connected to the quenching element R1. In this embodiment, the one end of the electrode 173 is electrically connected to the corresponding avalanche photodiode APD through a contact hole formed in the insulating layer 171. That is, each of the plurality of avalanche photodiodes APD is electrically connected to the corresponding quenching element R1 via the electrode 173. The other end of the electrode 173 is electrically connected to the other end of the quenching element R1. As described above, one end of the electrode 172 is electrically connected to one end of the quenching element R1, and the electrode pad is connected to the other end of the electrode 172. That is, the electrode pad is electrically connected to the corresponding avalanche photodiode APD via the electrode 172, the quenching element R1, and the electrode 173.
[0040] The insulating layer 174 is arranged on the surface 11a. The insulating layer 174 is arranged on the surface 11a so as to cover the insulating layer 171, electrode 172, and electrode 173. For example, the insulating layer 174 covers the entire insulating layer 171, electrode 172, and electrode 173. When the quenching element R1 is provided on the semiconductor substrate 11, the quenching element R1 may be arranged on the insulating layer 174 or directly on the surface 11a.
[0041] As shown in Figure 1, the photodetector 1 includes, for example, a plurality of lenses 18. The plurality of lenses 18 are arranged on a wiring layer 17. The lenses 18 are arranged to be located on corresponding cells U among a plurality of cells U. The photodetector 1 does not necessarily have to include a plurality of lenses 18.
[0042] Each of the multiple avalanche photodiodes (APDs) includes a semiconductor region 21, a semiconductor region 22, a semiconductor region 23, and a semiconductor region 24. The semiconductor region 21 is located within the semiconductor layer 13. For example, the semiconductor region 21 is located within the semiconductor layer 13 such that its surface aligns with the surface 11a. In this embodiment, the semiconductor region 21 has a surface that is exposed from the semiconductor layer 13. The surface of the semiconductor region 21, together with the surface of the semiconductor layer 13, constitutes the surface 11a. That is, the semiconductor region 21 includes a portion of the surface 11a. In this embodiment, the surface of the semiconductor region 21 and the surface of the semiconductor layer 13 are located on the same plane. One end of an electrode 173 is electrically connected to the semiconductor region 21 via a contact hole formed in the insulating layer 171.
[0043] As shown in Figure 3, when viewed from the first direction D1, the semiconductor region 21 has a rectangular shape. In Figure 3, in order to clearly show the relative sizes of the shapes and widths of the semiconductor regions 21, 22, and 23, all other elements except the semiconductor regions 21, 22, 23 and the trench TR are omitted from the illustration. When viewed from the first direction D1, the semiconductor region 21 includes, for example, four corners C1. In this embodiment, when viewed from the first direction D1, each corner C1 of the semiconductor region 21 is rounded. That is, in this embodiment, the semiconductor region 21 has a rectangular shape with each corner C1 rounded. It can also be said that each corner C1 of the semiconductor region 21 is formed in a rounded shape.
[0044] The semiconductor region 21 has a width W1. The width W1 is, for example, 3 μm or more and 40 μm or less. In this embodiment, the width W1 is 4 μm. For example, the width W1 includes the length of the semiconductor region 21 in the second direction D2. The width W1 may also include the length of the semiconductor region 21 in the third direction D3. The width W1 may be set based on, for example, the aperture ratio required for an avalanche photodiode APD. The semiconductor region 21 has a second conductivity type different from the first conductivity type. The second conductivity type includes, for example, the n type. In this embodiment, the semiconductor region 21 includes an n+ type semiconductor region. The semiconductor region 21 is, for example, 1.0 × 10 １７ cm －３ The above 1.0 x 10２１ cm －３ The following impurity concentrations are present. The impurity concentrations in the semiconductor region 21 include, for example, the concentration of n-type impurities.
[0045] The semiconductor region 22 is located within the semiconductor layer 13. The semiconductor region 22 is located within the semiconductor layer 13 so as to be situated between the semiconductor region 21 and the semiconductor layer 14. For example, the semiconductor region 22 is spaced apart from the semiconductor layer 14. As shown in Figure 1, in this embodiment, the semiconductor region 22 is spaced apart from the semiconductor layer 14 in the first direction D1.
[0046] As shown in Figure 3, when viewed from the first direction D1, the semiconductor region 22 has, for example, a rectangular shape. When viewed from the first direction D1, the semiconductor region 22 includes, for example, four corners C2. In this embodiment, when viewed from the first direction D1, each corner C2 of the semiconductor region 22 is rounded. That is, in this embodiment, the semiconductor region 22 has a rectangular shape with each corner C2 rounded. It can also be said that each corner C2 of the semiconductor region 22 is formed in a rounded shape. In this embodiment, when viewed from the first direction D1, the semiconductor region 22 surrounds the semiconductor region 21. That is, when viewed from the first direction D1, the semiconductor region 21 is located inside the semiconductor region 22.
[0047] The semiconductor region 22 has a width W2. The width W2 is, for example, 4 μm or more and 45 μm or less. In this embodiment, the width W2 is 5 μm. For example, the width W2 includes the length of the semiconductor region 22 in the second direction D2. The width W2 may also include the length of the semiconductor region 22 in the third direction D3. The semiconductor region 22 has a first conductivity type. In this embodiment, the semiconductor region 22 includes a p-type semiconductor region. The semiconductor region 22 is, for example, 1.0 × 10 １４ cm －３ The above 1.0 x 10 １８ cm －３ The following impurity concentrations are present. The impurity concentrations in the semiconductor region 22 include, for example, the concentration of p-type impurities.
[0048] As shown in Figure 1, the semiconductor region 23 is located within the semiconductor layer 13. The semiconductor region 23 is located within the semiconductor layer 13 so as to be between the semiconductor region 21 and the semiconductor region 22. That is, the semiconductor region 23 is located within the semiconductor layer 13 between the semiconductor region 21 and the semiconductor region 22. The semiconductor region 23 is bonded to the semiconductor region 21 near surface 11a and to the semiconductor region 22 near surface 11b. In this embodiment, the semiconductor region 23 is bonded to the semiconductor region 21 so as not to be in contact with the semiconductor layer 13.
[0049] In a cross-section along the first direction D1, the semiconductor region 23 and the semiconductor layer 14 are spaced apart from each other in the first direction D1. That is, in a cross-section along the first direction D1, the semiconductor layer 14 is spaced apart from the semiconductor region 23 in the first direction D1. The distance between the semiconductor layer 14 and the semiconductor region 23 in the first direction D1 is greater than the thickness of the semiconductor region 22. The distance between the semiconductor layer 14 and the semiconductor region 23 in the first direction D1 may be, for example, 1 μm or more and 50 μm or less.
[0050] Viewed from a first direction D1, the semiconductor region 23 has a rectangular shape. Viewed from a first direction D1, the semiconductor region 23 includes, for example, four corners C3. In this embodiment, viewed from a first direction D1, each corner C3 of the semiconductor region 23 is rounded. That is, in this embodiment, the semiconductor region 23 has a rectangular shape with rounded corners C3. It can also be said that each corner C3 of the semiconductor region 23 is formed in a rounded shape. In this embodiment, viewed from a first direction D1, the semiconductor region 23 surrounds the semiconductor regions 21 and 22. That is, in this embodiment, viewed from a first direction D1, the semiconductor regions 21 and 22 are located inside the semiconductor region 23.
[0051] The semiconductor region 23 has a width W3. The width W3 is, for example, 5 μm or more and 50 μm or less. In this embodiment, the width W3 is 6 μm. For example, the width W3 includes the length of the semiconductor region 23 in the second direction D2. The width W3 may also include the length of the semiconductor region 23 in the third direction D3. The semiconductor region 23 has a second conductivity type. In this embodiment, the semiconductor region 23 includes an n-type semiconductor region. The semiconductor region 21 and the semiconductor region 23 constitute a pn junction with the semiconductor region 22. The semiconductor region 23 is, for example, 1.0 × 10 １５ cm －３ The above 1.0 x 10 １９ cm －３ The following impurity concentrations are present. The impurity concentrations in the semiconductor region 23 include, for example, the concentration of n-type impurities.
[0052] The semiconductor region 24 is located within the semiconductor substrate 11. The semiconductor region 24 extends along the trench TR in the first direction D1. For example, the semiconductor region 24 extends along the trench TR from semiconductor layer 13 to semiconductor layer 14. In this embodiment, the semiconductor region 24 extends along the trench TR from surface 11a to semiconductor layer 14. The semiconductor region 24 constitutes the side surface of the trench TR. That is, the semiconductor region 24 is exposed to the trench TR. For example, if semiconductor region 21 includes a first semiconductor region, semiconductor region 23 includes a second semiconductor region, semiconductor region 22 includes a third semiconductor region, and semiconductor region 24 includes a fourth semiconductor region.
[0053] As shown in Figure 1, the depth of the semiconductor region 24 may be less than the depth of the trench TR. For example, the depth of the semiconductor region 24 includes the length of the semiconductor region 24 in the first direction D1. For example, the depth of the trench TR includes the length of the trench TR in the first direction D1. At positions deeper than the semiconductor region 24, for example, the semiconductor layer 14 constitutes the side surface of the trench TR. That is, the side surface of the trench TR includes a portion composed of the semiconductor region 24 and a portion composed of the semiconductor layer 14. Alternatively, the depth of the semiconductor region 24 may be the same as the depth of the trench TR. If the depth of the semiconductor region 24 and the depth of the trench TR are the same, the entire side surface of the trench TR may be composed of the semiconductor region 24.
[0054] The semiconductor region 24 has a first conductivity type. In this embodiment, the semiconductor region 24 includes a p+ type semiconductor region. The semiconductor region 24 is, for example, 1.0 × 10 １５ cm －３ The above 1.0 x 10 １９ cm －３ The following impurity concentrations are present. The impurity concentration in the semiconductor region 24 includes, for example, the concentration of p-type impurities.
[0055] The semiconductor region 24 having the aforementioned impurity concentration is formed, for example, by providing a trench TR in the semiconductor substrate 11, and then injecting p+ type impurities into the semiconductor layers 13 and 14 from the side of the trench TR while the semiconductor substrate 11 is tilted. Alternatively, the semiconductor region 24 may be formed, for example, by providing a trench TR in the semiconductor substrate 11, and then injecting p+ type impurities into the semiconductor layers 13 and 14 from the side of the trench TR while the injection source is tilted.
[0056] As described above, in this embodiment, when viewed from the first direction D1, semiconductor region 23 surrounds semiconductor region 21 and semiconductor region 22. Therefore, in this embodiment, width W3 is greater than widths W1 and W2. That is, when viewed from the first direction D1, semiconductor region 23 has a width W3 that is greater than the width W1 of semiconductor region 21 and the width W2 of semiconductor region 22. The ratio of width W3 to width W2 is, for example, 120% or more. The ratio of width W3 to width W1 is, for example, 160% or more. In this embodiment, when viewed from the first direction D1, semiconductor region 22 surrounds semiconductor region 21. Therefore, in this embodiment, width W2 is greater than width W1. That is, when viewed from the first direction D1, semiconductor region 22 has a width W2 that is greater than the width W1 of semiconductor region 21. The ratio of width W2 to width W1 is, for example, 120% or more. In other words, in this embodiment, the relative sizes of widths W1, W2, and W3 satisfy the relationship W3 > W2 > W1.
[0057] For example, as shown in Figure 4, the impurity concentration in the photodetector 1 changes with respect to the first direction D1. That is, the impurity concentration in the photodetector 1 changes with respect to the thickness direction of the semiconductor substrate 11. Figure 4 shows the change in impurity concentration with respect to the first direction D1 at the location where the avalanche photodiode APD is provided on the semiconductor substrate 11. The horizontal axis of Figure 4 represents the position in the first direction D1 on the semiconductor substrate 11. The vertical axis of Figure 4 shows the impurity concentration at the corresponding position on a logarithmic scale. In Figure 4, moving in the positive direction of the horizontal axis indicates approaching surface 11b, and moving in the negative direction of the horizontal axis indicates approaching surface 11a. In Figure 4, the area between position P1 and position P2 corresponds to the semiconductor region 22. The area between position P2 and position P3 corresponds to the semiconductor layer 13. The area between position P3 and position P4 corresponds to the semiconductor layer 14.
[0058] As shown in Figure 4, the impurity concentration in semiconductor region 22 is higher than that in semiconductor layer 13. For example, the ratio of the impurity concentration in semiconductor region 22 to the impurity concentration in semiconductor layer 13 is 110% or more. The impurity concentration in semiconductor layer 13 is higher than that in semiconductor layer 14. For example, the ratio of the impurity concentration in semiconductor layer 13 to the impurity concentration in semiconductor layer 14 is 110% or more.
[0059] The impurity concentration in semiconductor layer 15 is higher than that in semiconductor layer 13. For example, the ratio of the impurity concentration in semiconductor layer 15 to the impurity concentration in semiconductor layer 13 is 110% or more. The impurity concentration in semiconductor region 23 is lower than that in semiconductor region 21. For example, the ratio of the impurity concentration in semiconductor region 21 to the impurity concentration in semiconductor region 23 is 110% or more. The impurity concentration in semiconductor region 24 is higher than that in semiconductor layer 13 and semiconductor layer 14. For example, the ratio of the impurity concentration in semiconductor region 24 to the impurity concentration in semiconductor layer 13 is 110% or more. For example, the ratio of the impurity concentration in semiconductor region 24 to the impurity concentration in semiconductor layer 14 is 110% or more.
[0060] The difference between the impurity concentration in semiconductor region 22 and the impurity concentration in semiconductor layer 13 is smaller than the difference between the impurity concentration in semiconductor layer 13 and the impurity concentration in semiconductor layer 14. For example, the ratio of the difference between the impurity concentration in semiconductor layer 13 and the impurity concentration in semiconductor layer 14 to the difference between the impurity concentration in semiconductor region 22 and the impurity concentration in semiconductor layer 13 is 110% or more.
[0061] In the photodetector 1, quantum efficiency and avalanche probability affect detection efficiency. Quantum efficiency indicates the probability that incident light generates carriers. Avalanche probability indicates the probability that the generated carriers cause avalanche multiplication. Detection efficiency indicates the ratio of the number of detected photons to the number of incident photons. For example, in a photodetector equipped with a semiconductor substrate containing a single semiconductor layer, an increase in avalanche probability may decrease quantum efficiency, and an increase in quantum efficiency may decrease avalanche probability. Here, with reference to Figure 5, the relationship between quantum efficiency and avalanche probability in the above photodetector equipped with a semiconductor substrate containing a single semiconductor layer will be explained in more detail.
[0062] Figure 5 shows the change in electric field strength. The horizontal axis of Figure 5 indicates the position in the first direction D1 of the photodetector, and the vertical axis of Figure 5 indicates the electric field strength generated at the corresponding position. In Figure 5, moving in the positive direction of the horizontal axis indicates approaching surface 11b, and moving in the negative direction of the horizontal axis indicates approaching surface 11a. In Figure 5, the higher the peak electric field strength generated before position P5, the higher the avalanche probability. The peak electric field strength generated before position P5 includes, for example, the maximum value of the electric field strength generated before position P5. In Figure 5, the wider the region where the electric field is generated after position P5, the more easily the depletion layer expands, and the higher the quantum efficiency. In Figure 5, change G1 shows the relationship between the position in the first direction D1 and the electric field strength when the impurity concentration of the single semiconductor layer is approximately the same as the impurity concentration of semiconductor layer 13. Change G2 shows the relationship between the position in the first direction D1 and the electric field strength when the impurity concentration of the single semiconductor layer is approximately the same as that of the semiconductor layer 14.
[0063] In change G1, the impurity concentration of the single semiconductor layer and the impurity concentration of the semiconductor layer 13 are approximately the same, so the peak intensity of the electric field generated before position P5 is higher compared to change G2. Therefore, it can be seen that the avalanche probability is higher in change G1 compared to change G2. However, after position P5, the region where the electric field is generated only extends to position P6, and it can be seen that the depletion layer does not expand easily compared to change G2, where the region where the electric field is generated extends beyond position P6. In other words, in the photodetector exhibiting change G1, the avalanche probability increases while the quantum efficiency decreases compared to the photodetector exhibiting change G2.
[0064] In change G2, since the impurity concentration of the single semiconductor layer and the impurity concentration of the semiconductor layer 14 are approximately the same, the region where an electric field is generated extends beyond position P6, indicating that the depletion layer is more likely to expand compared to change G1. However, compared to change G1, the peak intensity of the electric field generated before position P5 is lower in change G2. Therefore, it can be seen that the avalanche probability is lower in change G2 compared to change G1. In other words, in the photodetector exhibiting change G2, the quantum efficiency increases while the avalanche probability decreases compared to the photodetector exhibiting change G1. Thus, in a photodetector equipped with a semiconductor substrate containing the single semiconductor layer, an increase in either the avalanche probability or the quantum efficiency leads to a decrease in the other.
[0065] Next, with reference to Figure 6, the relationship between the position in the first direction D1 and the strength of the electric field generated at that position in the photodetector 1 will be explained. Figure 6 is a diagram showing the change in electric field strength. The horizontal axis of Figure 6 shows the position in the first direction D1 in the photodetector 1, and the vertical axis of Figure 6 shows the strength of the electric field generated at the corresponding position. In Figure 6, change G3 shows the relationship between the position in the first direction D1 and the strength of the electric field in the photodetector 1. In change G3, for example, position P5 corresponds to the interface between semiconductor layer 13 and semiconductor layer 14. As shown in Figure 6, in change G3, it can be seen that the peak strength of the electric field generated before position P5 is about the same as the peak strength of the electric field in change G1. In addition, in change G3, it can be seen that the region where the electric field is generated extends beyond position P6, similar to change G2.
[0066] Thus, in the photodetector 1, the semiconductor layer 13 including surface 11a has a higher impurity concentration than the semiconductor layer 14, so when a voltage is applied, the strength of the electric field generated in the semiconductor layer 13 increases. In the photodetector 1, the impurity concentration of the semiconductor layer 14 is lower than that of the semiconductor layer 13, so the depletion layer in the semiconductor layer 14 spreads more easily in the first direction D1 compared to the semiconductor layer 13. That is, in the photodetector 1, the depletion layer spreads more easily from the semiconductor region 21 in the first direction D1 compared to a configuration in which the semiconductor layers 13 and 14 have the same impurity concentration. From the above, the photodetector 1 increases both the avalanche probability and the quantum efficiency. Therefore, the photodetector 1 improves the detection efficiency.
[0067] When the electric field increases locally in the semiconductor region 21, an unintended breakdown may occur at the point in the semiconductor region 21 where the electric field increases, at a voltage lower than the voltage required to operate the avalanche photodiode APD in Geiger mode. Hereinafter, this unintended breakdown may be referred to as "edge breakdown." In the photodetector element 1, the semiconductor region 23 is joined to the semiconductor region 21 so that it does not come into contact with the semiconductor layer 13. The semiconductor region 23, which is joined to the semiconductor region 21 so that it does not come into contact with the semiconductor layer 13, suppresses the localized increase in the electric field in the semiconductor region 21. Therefore, the photodetector element 1 suppresses the occurrence of edge breakdown.
[0068] In the photodetector element 1, trenches TR that reach at least the semiconductor layer 14 are provided between adjacent avalanche photodiodes APDs. Therefore, the photodetector element 1 suppresses the occurrence of crosstalk between adjacent avalanche photodiodes APDs.
[0069] In the photodetector 1, a semiconductor region 22 having a higher impurity concentration than that of the semiconductor layer 13 is bonded to the semiconductor region 23. The semiconductor region 22 having a higher impurity concentration than that of the semiconductor layer 13 increases the avalanche probability. Therefore, the photodetector 1 further improves the detection efficiency.
[0070] In the photodetector element 1, the semiconductor region 23 is spaced apart from the semiconductor layer 14 in the first direction D1. The photodetector element 1 reliably realizes a configuration in which the semiconductor region 22 is positioned within the semiconductor layer 13 between the semiconductor region 21 and the semiconductor layer 14.
[0071] In the photodetector 1, the difference between the impurity concentration in the semiconductor region 22 and the impurity concentration in the semiconductor layer 13 is smaller than the difference between the impurity concentration in the semiconductor layer 13 and the impurity concentration in the semiconductor layer 14. The photodetector 1 further increases the avalanche probability and quantum efficiency. Therefore, the photodetector 1 further improves the detection efficiency.
[0072] In the photodetector 1, when viewed from the first direction D1, the semiconductor region 22 has a width W2 that is greater than the width W1 of the semiconductor region 21. The semiconductor region 22 having a width W2 greater than the width W1 of the semiconductor region 21 suppresses a decrease in the region of the semiconductor region 21 that functions as a multiplication region. For example, the semiconductor region 22 can make the entire semiconductor region 21 function as a multiplication region. Therefore, the photodetector 1 suppresses a decrease in avalanche probability. From the above, the photodetector 1 suppresses a decrease in detection efficiency.
[0073] In the photodetector 1, when viewed from the first direction D1, the semiconductor region 23 has a width W3 that is larger than the width W2 of the semiconductor region 22. The semiconductor region 23 having a width W3 that is larger than the width W2 of the semiconductor region 22 suppresses the localized increase in the electric field in the semiconductor region 21. Therefore, the photodetector 1 suppresses the occurrence of edge breakdown.
[0074] In the photodetector 1, a semiconductor layer 15 having a higher impurity concentration than the semiconductor layer 13 is located between the substrate layer 12 and the semiconductor layer 14. The semiconductor layer 15 suppresses the inflow of carriers generated by light incident on the semiconductor substrate from the substrate layer 12 to the semiconductor layer 14. Therefore, the photodetector 1 suppresses the generation of noise.
[0075] In the photodetector 1, the semiconductor layer 14 has a thickness T3 that is greater than the thickness T2 of the semiconductor layer 13. The semiconductor layer 14, having a thickness T3 greater than the thickness T2 of the semiconductor layer 13, increases the region in which the depletion layer can expand. Therefore, the photodetector 1 further increases its quantum efficiency. As a result of the above, the photodetector 1 further improves its detection efficiency.
[0076] In the photodetector element 1, each corner C1 of the semiconductor region 21 is rounded when viewed from the first direction D1. Therefore, the photodetector element 1 suppresses the concentration of electric fields at each corner of the semiconductor region 21.
[0077] In the photodetector element 1, each of the multiple avalanche photodiodes APDs extends along the trench TR in the first direction D1 and constitutes the side surface of the trench TR, and includes a semiconductor region 24 having a first conductivity type. The semiconductor region 24 has an impurity concentration higher than the impurity concentration of the semiconductor layer 13 and the semiconductor layer 14.
[0078] 1.0 x 10 １５ cm －３ The above 1.0 x 10 １９ cm －３ The semiconductor region 24 having the following impurity concentrations causes variations in the electric field strength in the photodetector 1. That is, the semiconductor region 24 having the above-mentioned impurity concentrations makes the distribution of electric field strength in the photodetector 1 non-uniform. The electric field strength in the photodetector 1 is distributed such that the electric field strength is higher in the direction from surface 11b to surface 11a within the first direction D1. The electric field strength in the photodetector 1 changes not only with respect to the first direction D1 but also with respect to the second direction D2. Due to the above-mentioned variations in electric field strength, the voltage that completely depletes the semiconductor layer 14 in the photodetector 1 becomes higher than the breakdown voltage. Hereinafter, the voltage that completely depletes the semiconductor layer 14 is sometimes simply referred to as the "total depletion voltage".
[0079] In a photodetector 1 where semiconductor layer 13 has a higher impurity concentration than semiconductor layer 14, the relationship between the total depletion voltage and the breakdown voltage affects the detection efficiency. For example, if the total depletion voltage is lower than the breakdown voltage, semiconductor layer 14 is completely depleted, but the peak intensity of the electric field generated in semiconductor layer 13 does not increase easily. On the other hand, if the total depletion voltage is greater than or equal to the breakdown voltage, both the complete depletion of semiconductor layer 14 and an increase in the peak intensity of the electric field generated in semiconductor layer 13 can be achieved. That is, if the total depletion voltage is greater than or equal to the breakdown voltage, the detection efficiency can be further improved. If the impurity concentration of semiconductor region 24 is higher than the impurity concentration of semiconductor layer 13 and semiconductor layer 14, a configuration in which the total depletion voltage is greater than or equal to the breakdown voltage can be easily realized. Therefore, the photodetector 1 can further improve its detection efficiency.
[0080] Next, the configuration of the modified photodetector 1A will be described with reference to Figures 7 and 8. Figures 7 and 8 show the cross-sectional configuration of the photodetector according to the modified embodiment. The photodetector 1A differs from the photodetector 1 described above in terms of the configuration of the light incident surface. The differences between the photodetector 1 and the photodetector 1A described above will be mainly explained below.
[0081] Unlike photodetector element 1, which is a surface-incident type photodetector, photodetector element 1A is a back-incident type photodetector. In this modified example, surface 11b includes the light incidence surface. As shown in Figure 7, in this modified example, the semiconductor substrate 11 does not include the substrate layer 12. In this modified example, instead of the substrate layer 12, the semiconductor layer 15 includes surface 11b, and the semiconductor layer 15 also functions as the substrate layer 12. In addition to the semiconductor layer 13, semiconductor layer 14, and semiconductor layer 15, the semiconductor substrate 11 may also include an oxide film. The oxide film may be formed, for example, on surface 11b included by the semiconductor layer 15.
[0082] In this modified example, the trench TR opens to surface 11a and reaches the semiconductor layer 15. In this modified example, the trench TR penetrates the semiconductor layer 15 and also opens to surface 11b. The trench TR penetrates semiconductor layer 13, semiconductor layer 14, and semiconductor layer 15. In other words, in this modified example, the trench TR penetrates the semiconductor substrate 11.
[0083] In this modified example, the depth of the semiconductor region 24 is the same as the depth of the trench TR. That is, the semiconductor region 24 extends in the first direction D1 along the trench TR from surface 11a to surface 11b. Therefore, in this modified example, the entire side surface of the trench TR is composed of the semiconductor region 24. In this modified example, the depth of the semiconductor region 24 may be less than the depth of the trench TR. As shown in Figure 8, the photodetector element 1A, which is a back-surface incident type photodetector element, may also be equipped with a plurality of lenses 18. In the photodetector element 1A as well, the lenses 18 are arranged to be located on the corresponding cell U among a plurality of cells U.
[0084] While embodiments and modifications of this disclosure have been described above, this disclosure is not necessarily limited to the embodiments and modifications described above, and various modifications are possible without departing from its essence.
[0085] Each of the multiple avalanche photodiodes (APDs) may have an impurity concentration higher than that of the semiconductor region 21 and may not include a semiconductor region 22 that is bonded to the semiconductor region 23. A photodetector 1 in which each of the multiple avalanche photodiodes (APDs) includes a semiconductor region 22 further improves detection efficiency, as described above.
[0086] The difference between the impurity concentration in the semiconductor region 22 and the impurity concentration in the semiconductor layer 13 does not have to be smaller than the difference between the impurity concentration in the semiconductor layer 13 and the impurity concentration in the semiconductor layer 14. In other words, the difference between the impurity concentration in the semiconductor region 22 and the impurity concentration in the semiconductor layer 13 may be greater than or equal to the difference between the impurity concentration in the semiconductor layer 13 and the impurity concentration in the semiconductor layer 14. A photodetector 1 in which the difference between the impurity concentration in the semiconductor region 22 and the impurity concentration in the semiconductor layer 13 is smaller than the difference between the impurity concentration in the semiconductor layer 13 and the impurity concentration in the semiconductor layer 14 will have an even greater detection efficiency, as described above.
[0087] When viewed from the first direction D1, the semiconductor region 22 does not have to have a width W2 that is greater than the width W1 of the semiconductor region 21. That is, the width W2 may be less than or equal to the width W1. When viewed from the first direction D1, the photodetector 1 in which the semiconductor region 22 has a width W2 that is greater than the width W1 of the semiconductor region 21 suppresses a decrease in detection efficiency, as described above.
[0088] Viewed from the first direction D1, the semiconductor region 23 does not have to have a width W3 that is greater than the width W2 of the semiconductor region 22. That is, the width W3 may be less than or equal to the width W2. As described above, a photodetector 1 in which the semiconductor region 23 has a width W3 that is greater than the width W2 of the semiconductor region 22 suppresses the occurrence of edge breakdown.
[0089] The semiconductor substrate 11 does not necessarily have to include a semiconductor layer 15 having a higher impurity concentration than the semiconductor layer 13. A photodetector 1 in which the semiconductor substrate 11 includes a semiconductor layer 15 having a higher impurity concentration than the semiconductor layer 13 suppresses noise generation as described above.
[0090] The semiconductor layer 14 does not have to have a thickness T3 greater than the thickness T2 of the semiconductor layer 13. That is, the thickness T3 may be less than or equal to the thickness T2. A photodetector 1 in which the semiconductor layer 14 has a thickness T3 greater than the thickness T2 of the semiconductor layer 13 will have an even greater detection efficiency, as described above.
[0091] When viewed from the first direction D1, each corner C1 of the semiconductor region 21 does not have to be rounded. When viewed from the first direction D1, the photodetector element 1 in which each corner C1 of the semiconductor region 21 is rounded suppresses the concentration of the electric field at each corner C1 of the semiconductor region 21, as described above.
[0092] Each of the multiple avalanche photodiodes (APDs) does not need to include a semiconductor region 24 having an impurity concentration higher than that of semiconductor layer 13 and semiconductor layer 14. If each of the multiple avalanche photodiodes (APDs) does not include a semiconductor region 24, the side surface of the trench TR may be composed of semiconductor layers 13 and 14. A photodetector element 1 in which each of the multiple avalanche photodiodes (APDs) includes a semiconductor region 24 having the above-described impurity concentration can, as described above, further improve detection efficiency.
[0093] The impurity concentration in the semiconductor region 24 may be less than or equal to the impurity concentration in the semiconductor layer 13, or less than or equal to the impurity concentration in the semiconductor layer 14. The semiconductor region 24 having an impurity concentration greater than or equal to the impurity concentration in the semiconductor layer 13 homogenizes the distribution of electric field intensity in the photodetector element 1. Therefore, the photodetector element 1 in which the impurity concentration in the semiconductor region 24 is greater than or equal to the impurity concentration in the semiconductor layer 13 suppresses the generation of noise.
[0094] 1, 1A...Photodetector element, 11...Semiconductor substrate, 12...Substrate layer, 13...Semiconductor layer, 14...Semiconductor layer, 15...Semiconductor layer, 21...Semiconductor region, 22...Semiconductor region, 23...Semiconductor region, APD...Avalanche photodiode, C1...Angle, R1...Quenching element, TR...Trench, W1, W2, W3...Width.
Claims
1. A semiconductor substrate comprising a plurality of avalanche photodiodes, each having a first surface and a second surface facing each other, each electrically connected to a corresponding quenching element and operating in Geiger mode, wherein the semiconductor substrate comprises: a substrate layer including the second surface; a first semiconductor layer including the first surface and having a first conductivity type; a second semiconductor layer bonded to the first semiconductor layer between the substrate layer and the first semiconductor layer and having the first conductivity type, wherein the semiconductor substrate has trenches between adjacent avalanche photodiodes among the plurality of avalanche photodiodes, each of the plurality of avalanche photodiodes comprises: a first semiconductor region disposed within the first semiconductor layer and having a second conductivity type different from the first conductivity type; a second semiconductor region disposed within the first semiconductor layer so as to be located between the first semiconductor region and the second semiconductor layer, bonded to the first semiconductor region so as not to be in contact with the first semiconductor layer, and having the second conductivity type, wherein the trenches open to the first surface and reach at least the second semiconductor layer. The second semiconductor region has an impurity concentration lower than that of the first semiconductor region, and is spaced apart from the second semiconductor layer in a direction in which the first surface and the second surface face each other, and the impurity concentration of the first semiconductor layer is higher than that of the second semiconductor layer, in a photodetector element.
2. The photodetector element according to claim 1, wherein each of the plurality of avalanche photodiodes is disposed within the first semiconductor layer so as to be located between the second semiconductor region and the second semiconductor layer and is bonded to the second semiconductor region, and further includes a third semiconductor region having the first conductivity type, the third semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor layer.
3. The photodetector according to claim 2, wherein the difference between the impurity concentration in the third semiconductor region and the impurity concentration in the first semiconductor layer is smaller than the difference between the impurity concentration in the first semiconductor layer and the impurity concentration in the second semiconductor layer.
4. The photodetector according to claim 2 or 3, wherein, when viewed from the direction in which the first surface and the second surface face each other, the third semiconductor region has a width greater than the width of the first semiconductor region.
5. The photodetector according to any one of claims 2 to 4, wherein, when viewed from the direction in which the first surface and the second surface face each other, the second semiconductor region has a width greater than the width of the third semiconductor region.
6. The photodetector according to any one of claims 1 to 5, wherein the semiconductor substrate further includes a third semiconductor layer having the first conductivity type, and the third semiconductor layer has an impurity concentration higher than the impurity concentration of the first semiconductor layer.
7. The photodetector according to any one of claims 1 to 6, wherein the second semiconductor layer has a thickness greater than the thickness of the first semiconductor layer.
8. The photodetector according to any one of claims 1 to 7, wherein, when viewed from the direction in which the first surface and the second surface are facing each other, each corner of the first semiconductor region is rounded.
9. The photodetector according to any one of claims 1 to 8, wherein each of the plurality of avalanche photodiodes further includes a fourth semiconductor region having the first conductivity type, which extends along the trench in the direction in which the first surface and the second surface face each other and constitutes a side surface of the trench, and the fourth semiconductor region has an impurity concentration higher than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer.