Sputtering target material, oxide semiconductor layer, and thin film transistor

Abstract

The present invention addresses the problem of providing a sputtering target material in which the generation of particles is suppressed. This sputtering target material is composed of an oxide that contains In, Ga, Zn, Sn, and an additive element (X) (X represents at least one element that is selected from the group consisting of elemental tantalum (Ta), elemental niobium (Nb), elemental aluminum (Al), and elemental silicon (Si)). The atomic ratio of each element satisfies formulae (1) to (5). (1): 0.20 ≤ In / (In + Ga + Sn + Zn + X) ≤ 0.30, (2): 0.24 ≤ Ga / (In + Ga + Sn + Zn + X) ≤ 0.45, (3): 0.30 ≤ Zn / (In + Ga + Sn + Zn + X) ≤ 0.50, (4): 0.0001 ≤ Sn / (In + Ga + Sn + Zn + X) ≤ 0.02, (5): 0.0001 ≤ X / (In + Ga + Sn + Zn + X) ≤ 0.03

Description

Sputtering target material, oxide semiconductor layer, and thin-film transistor

[0001] This invention relates to a sputtering target material. Furthermore, this invention relates to an oxide semiconductor layer and a thin-film transistor obtained using the sputtering target material.

[0002] In the field of thin-film transistors (hereinafter also called "TFTs") used in flat panel displays (hereinafter also called "FPDs"), oxide semiconductors, such as In-Ga-Zn composite oxide (hereinafter also called "IGZO"), are attracting attention as FPDs become more sophisticated, replacing conventional amorphous silicon, and their practical application is progressing. IGZO has the advantage of exhibiting high field-effect mobility and low leakage current. In recent years, as FPDs have become even more sophisticated, materials exhibiting even higher field-effect mobility than that of IGZO have been proposed.

[0003] For example, Patent Document 1 describes a semiconductor device comprising an oxide semiconductor TFT having a stacked structure including a channel oxide semiconductor layer and a protective oxide semiconductor layer. The protective oxide semiconductor layer described in the same document is an In-Ga-Zn-O semiconductor layer in which the atomic ratio of In, Ga, and Zn is In:Ga:Zn = 1:3:6.

[0004] Patent Document 2 describes a thin-film transistor comprising an oxide semiconductor layer having a first oxide semiconductor layer and a second oxide semiconductor layer, wherein the first and second oxide semiconductor layers are made of oxide semiconductor thin films containing In, Ga, Zn, and Sn, and O, respectively.

[0005] Japanese Patent Publication No. US2019 / 148558A1 2020-136302

[0006] The oxide semiconductor thin films described in Patent Documents 1 and 2 are generally formed by sputtering. When the present inventors fabricated a target material made of an oxide with the composition described in these documents and performed sputtering, it was found that a large amount of particles were generated depending on the composition of the metal constituting the oxide, which was found to be one of the causes of deterioration in the yield of the oxide semiconductor thin film. Therefore, the object of the present invention is to provide a target material made of an oxide in which the generation of particles during sputtering is suppressed.

[0007] The present invention provides a sputtering target material composed of an oxide containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta), niobium (Nb), aluminum (Al), and silicon (Si)), wherein the atomic ratio of each element satisfies formulas (1) to (5) (where X is the sum of the content ratios of the additive elements). 0.20≦In / (In+Ga+Sn+Zn+X)≦0.30 (1) 0.24≦Ga / (In+Ga+Sn+Zn+X)≦0.45 (2) 0.30≦Zn / (In+Ga+Sn+Zn+X)≦0.50 (3) 0.0001≦Sn / (In+Ga+Sn+Zn+X)≦0.02 (4) 0.0001≦X / (In+Ga+Sn+Zn+X)≦0.03 (5)

[0008] The present invention also provides an oxide semiconductor layer comprising: a first oxide semiconductor layer containing at least indium (In) element; and a second oxide semiconductor layer disposed adjacent to the first oxide semiconductor layer, wherein the second oxide semiconductor layer is composed of an oxide containing indium (In) element, gallium (Ga) element, zinc (Zn) element, tin (Sn) element, and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta) element, niobium (Nb) element, aluminum (Al) element, and silicon (Si) element), and the atomic ratio of each element satisfies formulas (1) to (5) above (where X is the sum of the content ratios of the additive elements).

[0009] Furthermore, the present invention provides a thin-film transistor comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; an oxide semiconductor layer disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the oxide semiconductor layer; and a protective layer disposed on the source electrode, the drain electrode and the oxide semiconductor layer, wherein the first oxide semiconductor layer in the oxide semiconductor layer is located on the substrate side.

[0010] Figure 1 is a schematic diagram showing the structure of a thin-film transistor (TFT) manufactured using the sputtering target material of the present invention.

[0011] The present invention will be described below based on its preferred embodiments. The present invention relates to a sputtering target material (hereinafter also referred to as "target material"). The target material of the present invention is composed of an oxide containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and an additive element (X). The additive element (X) consists of at least one element selected from the group consisting of tantalum (Ta), niobium (Nb), aluminum (Al), and silicon (Si).

[0012] The target material of the present invention contains In, Ga, Zn, Sn, and X (additive elements) as constituent metallic elements. In addition to these elements, trace elements may be intentionally or inevitably included, to the extent that they do not impair the effects of the present invention. Examples of trace elements include elements contained in organic additives described later and media raw materials such as ball mills that are mixed in during the manufacture of the target material. Examples of trace elements in the target material of the present invention include Fe, Cr, Ni, W, Zr, Na, Mg, K, Ca, Ti, Y, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Pb. The content of each is preferably 100 ppm by mass (hereinafter also referred to as "ppm") or less, more preferably 80 ppm or less, and even more preferably 50 ppm or less, based on the total mass of the target material of the present invention. The total amount of these trace elements is preferably 500 ppm or less, more preferably 300 ppm or less, and even more preferably 100 ppm or less. If the target material of the present invention contains trace elements, the mass of the target material also includes the mass of the trace elements. The target material of the present invention preferably contains In, Ga, Zn, Sn, and X (additive elements) and O (oxygen element), with the remainder being unavoidable impurities.

[0013] The target material of the present invention is preferably composed of a sintered body containing the above-mentioned oxide. There are no particular restrictions on the shape of such sintered body and sputtering target material, and conventionally known shapes, such as flat plate type and cylindrical shape, can be used.

[0014] In the present invention, it is preferable that the atomic ratios of the constituent metal elements, namely In, Ga, Zn, Sn, and X, are within a specific range, as this improves the various performance characteristics of the oxide semiconductor device formed from the target material. Specifically, with respect to In, it is preferable to satisfy the atomic ratio expressed by the following formula (1) (wherein X is the sum of the content ratios of the additive elements. The same applies to formulas (2) to (5) below). 0.20 ≤ In / (In + Ga + Sn + Zn + X) ≤ 0.30 (1) With respect to Ga, it is preferable to satisfy the atomic ratio expressed by the following formula (2). 0.24 ≤ Ga / (In + Ga + Sn + Zn + X) ≤ 0.45 (2) With respect to Zn, it is preferable to satisfy the atomic ratio expressed by the following formula (3). 0.30 ≤ Zn / (In + Ga + Sn + Zn + X) ≤ 0.50 (3) With respect to Sn, it is preferable to satisfy the atomic ratio expressed by the following formula (4). 0.0001 ≤ Sn / (In + Ga + Sn + Zn + X) ≤ 0.02 (4) For X, it is preferable to satisfy the atomic ratio expressed by the following formula (5): 0.0001 ≤ X / (In + Ga + Sn + Zn + X) ≤ 0.03 (5)

[0015] By satisfying all of the above equations (1) to (5) in terms of the atomic ratios of In, Ga, Zn, Sn, and X, arcing can be suppressed during sputtering using the target material of the present invention, and consequently, particle generation can be suppressed. From the viewpoint of making this advantage even more pronounced, it is preferable that the following equation (1-2) is satisfied for In, and even more preferable that (1-3) is satisfied. 0.20 < In / (In + Ga + Sn + Zn + X) < 0.30 (1-2) 0.202 ≤ In / (In + Ga + Sn + Zn + X) ≤ 0.29 (1-3)

[0016] From the same viewpoint as above, it is preferable that Ga satisfies equation (2-2) below, and more preferably that it satisfies (2-3). It is preferable that Zn satisfies equation (3-2) below, and more preferably that it satisfies (3-3). It is preferable that Sn satisfies equation (4-2) below, and more preferably that it satisfies (4-3). It is preferable that X satisfies equation (5-2) below, and more preferably that it satisfies (5-3).

[0017] 0.245≦Ga / (In+Ga+Sn+Zn+X)≦0.445 (2-2) 0.25≦Ga / (In+Ga+Sn+Zn+X)≦0.44 (2-3) 0.305≦Zn / (In+Ga+Sn+Zn+X)≦0.495 (3-2) 0.31≦Zn / (In+Ga+Sn+Zn+X)≦0.49 (3-3) 0.0002≦Sn / (In+Ga+Sn+Zn+X)≦0.015 (4-2) 0.0005≦Sn / (In+Ga+Sn+Zn+X)≦0.01 (4-3) 0.0002≦X / (In+Ga+Sn+Zn+X)≦0.025 (5-2) 0.0005≦X / (In+Ga+Sn+Zn+X)≦0.02 (5-3)

[0018] As described above, one or more additive elements (X) are selected from Ta, Nb, Al, and Si. These elements can be used individually or in combination of two or more. In particular, using Ta as additive element (X) is preferable from the viewpoint of the overall performance of the oxide semiconductor device manufactured from the target material of the present invention, and from the viewpoint of economic efficiency in manufacturing the target material.

[0019] A high field-effect mobility of an oxide semiconductor element with a cap layer formed using the target material of the present invention is desirable from the standpoint of improving the functionality of the FPD, which results in good transfer characteristics of the TFT element, an oxide semiconductor element. More specifically, a TFT equipped with an oxide semiconductor element with a cap layer formed using the target material of the present invention has a field-effect mobility (cm²). ２ / Vs) is 7.8 cm ２It is preferable that the value is 8.0 cm or higher, and the value is 8.0 cm or higher. ２ It is even more preferable that the value be greater than or equal to / Vs, and 8.2 cm ２ It is even more preferable that the field effect mobility is greater than or equal to / Vs. The larger the field effect mobility value, the better it is from the standpoint of improving the functionality of the FPD, but a field effect mobility of 15.0 cm is preferable. ２ If the value is around / Vs, a sufficiently satisfactory level of performance can be obtained.

[0020] The target material of the present invention is characterized not only by the atomic ratio of In, Ga, Zn, Sn, and X, but also by its high relative density. Specifically, the target material of the present invention exhibits a high relative density of preferably 98% or more. Such a high relative density is desirable because it makes it possible to suppress the occurrence of arcing and, consequently, particle generation when sputtering is performed using the target material of the present invention. From this viewpoint, the target material of the present invention is more preferably 98.5% or more, even more preferably 99% or more, even more preferably 99.5% or more, particularly preferably 99.8% or more, and especially preferably 100% or more. The target material of the present invention having such a relative density is suitably manufactured by the method described later. The relative density is measured according to the Archimedes method. The specific measurement method will be described in detail in the examples described later.

[0021] The target material of the present invention is also characterized by its high strength. Specifically, the target material of the present invention preferably exhibits a high flexural strength of 100 MPa or more. By exhibiting such a high flexural strength, when sputtering is performed using the target material of the present invention, even if abnormal discharge occurs unintentionally during sputtering, it is preferable because cracks are less likely to occur in the target material. From this perspective, the target material of the present invention more preferably has a flexural strength of 105 MPa or more, still more preferably 110 MPa or more, and even more preferably 115 MPa or more. The target material of the present invention having such a flexural strength is preferably manufactured by the method described later. The flexural strength is measured in accordance with JIS R1601. The specific measurement method will be described in detail in the examples described later.

[0022] The target material of the present invention is also characterized by its low bulk resistivity. The fact that the bulk resistivity is low is advantageous in that DC sputtering can be performed using the target material. From this perspective, the target material of the present invention preferably has a bulk resistivity of 20.0×10 －３ Ω·cm or less at 25°C, more preferably 15.0×10 －３ Ω·cm or less, even more preferably 10.0×10 －３ Ω·cm or less, still more preferably 9.0×10 －３ Ω·cm or less. The target material of the present invention having such a bulk resistivity is preferably manufactured by the method described later. The bulk resistivity is measured by the DC four-probe method. The specific measurement method will be described in detail in the examples described later.

[0023] The target material of the present invention preferably has a Vickers hardness of 450 HV or higher, from the viewpoint of preventing cracking of the target material during sputtering. From the viewpoint of further enhancing this advantage, the target material of the present invention is more preferably 470 HV or higher, even more preferably 480 HV or higher, and even more preferably 500 HV or higher. The target material of the present invention having such a Vickers hardness is suitably manufactured by the method described later. The Vickers hardness is measured in accordance with JIS-R-1610:2003. The specific measurement method will be described in detail in the examples described later.

[0024] The arithmetic mean roughness Ra (JIS-B-0601:2013) of the target material surface of the present invention can be appropriately adjusted by the grit size of the grinding wheel used during grinding. When sputtering is performed using a target material with a small arithmetic mean roughness Ra, it is preferable that abnormal discharge is suppressed during sputtering. From this viewpoint, the target material of the present invention preferably has an arithmetic mean roughness Ra of 3.2 μm or less, more preferably 1.6 μm or less, and even more preferably 1.2 μm or less. The arithmetic mean roughness Ra is measured by a surface roughness measuring instrument.

[0025] As described above, the target material of the present invention is composed of an oxide containing In, Ga, Zn, Sn, and X. This oxide may include an oxide of In, an oxide of Ga, an oxide of Zn, an oxide of Sn, or an oxide of X. Alternatively, this oxide may include a composite oxide of any two or more elements selected from the group consisting of In, Ga, Zn, Sn, and X. Specific examples of composite oxides include In-Ga composite oxide, In-Zn composite oxide, Ga-Zn composite oxide, etc. Or, In-Ga-Zn composite oxide, etc. However, it is not limited to these.

[0026] Next, a preferred method for manufacturing the target material of the present invention will be described. In this manufacturing method, oxide powder, which is the raw material for the target material, is molded into a predetermined shape to obtain a molded body, and this molded body is fired to obtain a sintered target material. Methods known in the art can be used to obtain the molded body. In particular, using a slip casting method or a CIP molding method is preferable because it can produce a dense target material.

[0027] The slip casting method is also called the slip casting method. To perform the slip casting method, first, a slurry containing raw material powder and organic additives is prepared using a dispersion medium.

[0028] As the raw material powder, oxide powder, hydroxide powder, or carbonate powder is preferable. As oxide powders, In oxide powder, Ga oxide powder, Zn oxide powder, Sn oxide powder, and X oxide powder can be used. As an In oxide, for example In ２ O ３ For example, Ga can be used. ２ O ３ For example, ZnO can be used as a Zn oxide. For example, SnO ２ For example, Ta can be used as the X oxide powder. ２ O ５ , Nb ２ O ５ Al ２ O ３ and SiO ２ This can be used. In this manufacturing method, it is preferable to perform calcination after mixing all of these raw material powders. By mixing and molding all the raw material powders at room temperature and then performing calcination, a dense target material with high relative density can be easily obtained.

[0029] The amounts of In oxide powder, Ga oxide powder, Zn oxide powder, Sn oxide powder, and X oxide powder used are preferably adjusted so that the atomic ratios of In, Ga, Zn, Sn, and X in the target material satisfy the range described above.

[0030] The particle size of the raw material powder is determined by the cumulative volume particle size D at 50% of the cumulative volume, as measured by laser diffraction scattering particle size distribution analysis. ５０ The particle size is preferably 0.1 μm to 2.5 μm. By using raw material powder having a particle size within this range, a target material with high relative density can be easily obtained.

[0031] The aforementioned organic additives are substances used to suitably adjust the properties of the slurry and molded articles. Examples of organic additives include binders, dispersants, and plasticizers. Binders are added to increase the strength of the molded articles. As binders, those commonly used when obtaining molded articles in known powder sintering methods can be used. An example of a binder is polyvinyl alcohol. Dispersants are added to improve the dispersibility of the raw material powder in the slurry. Examples of dispersants include polycarboxylic acid-based dispersants and polyacrylic acid-based dispersants. Plasticizers are added to improve the plasticity of the molded articles. Examples of plasticizers include polyethylene glycol (PEG) and ethylene glycol (EG).

[0032] There are no particular restrictions on the dispersion medium used when preparing a slurry containing raw material powder and organic additives. Depending on the purpose, water and water-soluble organic solvents such as alcohol can be appropriately selected and used. There are no particular restrictions on the method of preparing a slurry containing raw material powder and organic additives. For example, a method of mixing raw material powder, organic additives, dispersion medium, and zirconia balls in a ball mill can be used.

[0033] Once the slurry is obtained in this way, it is poured into a mold, and then the dispersion medium is removed to produce a molded body. Examples of molds that can be used include metal molds, plaster molds, and resin molds that remove the dispersion medium by pressurization.

[0034] On the other hand, in the CIP molding method, a slurry similar to the slurry used in the slip molding method is spray-dried to obtain a dried powder. The obtained dried powder is then filled into a mold and CIP molding is performed.

[0035] Once the molded body is obtained in this way, it is then fired. The firing of the molded body can generally be carried out in an oxygen-containing atmosphere. In particular, firing in an air atmosphere is convenient. The firing temperature is preferably 1400°C to 1600°C, more preferably 1450°C to 1550°C, and even more preferably 1480°C to 1530°C. The firing time is preferably 1 hour to 100 hours, more preferably 2 hours to 50 hours, and even more preferably 3 hours to 30 hours. The heating rate is preferably 5°C / hour to 500°C / hour, more preferably 10°C / hour to 450°C / hour, and even more preferably 20°C / hour to 400°C / hour.

[0036] The target material obtained in this way can be processed to a predetermined size by grinding or other processes. A sputtering target can be obtained by bonding this to a substrate. The sputtering target obtained in this way is suitably used in the manufacture of oxide semiconductors. For example, the target material of the present invention can be used in the manufacture of TFTs. Figure 1 schematically shows an example of a TFT element 1. The TFT element 1 shown in the figure is formed on one surface of a substrate 10 made of glass or the like. A gate electrode 20 is arranged on one surface of the substrate 10.

[0037] The gate electrode 20 is generally formed by sputtering a metallic material such as Al, Cu, Ti, or Mo to a thickness of approximately 100 nm to 500 nm. After forming a photoresist on top of it, it is patterned by dry etching or wet etching. The photoresist is then removed by appropriate stripping and cleaning.

[0038] As shown in Figure 1, in the TFT element 1, a gate insulating layer 30 is arranged to cover the gate electrode 20. The gate insulating layer 30 is generally made of SiO2 by plasma CVD. ２ Ya SiN Ｘ It is formed by depositing a film. The film thickness is approximately 150 nm to 500 nm.

[0039] An oxide semiconductor layer 40 is placed on the gate insulating layer 30. The oxide semiconductor layer 40 is formed by sputtering using an oxide semiconductor target with Ar gas and O ２ The film is deposited in a gas atmosphere. The thickness of the oxide semiconductor layer 40 is approximately 20 nm to 100 nm.

[0040] A source electrode 60 and a drain electrode 61 are arranged on the oxide semiconductor layer 40. The source electrode 60 is formed by depositing a metallic material such as Al, Cu, Ti, or Mo by sputtering and then patterning it, similar to the gate electrode 20. Dry etching is often used when forming the source electrode 60, and it is necessary to remove the source electrode 60 on the oxide semiconductor layer 40 when forming the TFT channel region. In this case, a second oxide semiconductor layer 42 is generally used to protect the first oxide semiconductor layer 41 from process damage. In Figure 1, two layers, a first oxide semiconductor layer 41 and a second oxide semiconductor layer 42, are used as the oxide semiconductor layer 40, but a third oxide semiconductor layer may be formed between the first oxide semiconductor layer 41 and the second oxide semiconductor layer 42. In that case, if the first oxide semiconductor layer 41 has the highest In content and the second oxide semiconductor layer 42 has the lowest In content, good TFT characteristics and reliability are easily obtained.

[0041] As shown in Figure 1, a protective layer 70 is placed on the source electrode 60, the drain electrode 61, and the exposed oxide semiconductor layer 40 so as to cover them. The protective layer 70 is generally made using plasma CVD. ２ Ya SiN Ｘ This is a film that has been deposited. The thickness of the protective layer 70 is approximately 150 nm to 500 nm.

[0042] The oxide semiconductor layer 40 in the TFT element 1 has a two-layer stacked structure. Specifically, the oxide semiconductor layer 40 comprises a first oxide semiconductor layer 41 located on the substrate 10 side and a second oxide semiconductor layer 42 located on the source electrode 60 and drain electrode 61 side. The second oxide semiconductor layer 42 is adjacent to the first oxide semiconductor layer 41 and is disposed on the first oxide semiconductor layer 41.

[0043] The first oxide semiconductor layer 41 preferably functions as a channel layer in the TFT device 1. For this purpose, the first oxide semiconductor layer 41 preferably contains at least In, and more preferably In, Ga, and Zn. In addition, the first oxide semiconductor layer 41 may also contain Sn and dodo element X in addition to the aforementioned elements.

[0044] On the other hand, the second oxide semiconductor layer 42 preferably functions as a cap layer in the TFT element 1. The second oxide semiconductor layer 42 is preferably composed of an oxide containing In, Ga, Zn, Sn, and X, and the atomic ratio of each element preferably satisfies the above-described formulas (1) to (5). The second oxide semiconductor layer 42 is suitably formed by sputtering using the target material of the present invention described above.

[0045] With respect to the embodiments described above, the present invention further discloses the following sputtering target material, oxide semiconductor layer, and thin-film transistor: [1] A sputtering target material composed of an oxide containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta), niobium (Nb), aluminum (Al), and silicon (Si), wherein the atomic ratio of each element satisfies formulas (1) to (5) (where X is the sum of the content ratios of the additive elements). 0.20 ≤ In / (In + Ga + Sn + Zn + X) ≤ 0.30 (1) 0.24 ≤ Ga / (In + Ga + Sn + Zn + X) ≤ 0.45 (2) 0.30 ≤ Zn / (In + Ga + Sn + Zn + X) ≤ 0.50 (3) 0.0001 ≤ Sn / (In + Ga + Sn + Zn + X) ≤ 0.02 (4) 0.0001 ≤ X / (In + Ga + Sn + Zn + X) ≤ 0.03 (5) [2] The sputtering target material described in [1], wherein the relative density is 98% or more. [3] The sputtering target material described in [1] or [2], wherein the flexural strength is 100 MPa or more. [4] A sputtering target material according to any one of [1] to [3], having a Vickers hardness of 450 HV or higher. [5] A bulk resistivity of 20.0 × 10 at 25°C. －３ A sputtering target material described in any one of [1] to [4], having a value of Ω·cm or less.

[0046] [6] An oxide semiconductor layer comprising a first oxide semiconductor layer containing at least indium (In) element, and a second oxide semiconductor layer disposed adjacent to the first oxide semiconductor layer, wherein the second oxide semiconductor layer is composed of an oxide containing indium (In) element, gallium (Ga) element, zinc (Zn) element, tin (Sn) element, and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta) element, niobium (Nb) element, aluminum (Al) element, and silicon (Si) element), and the atomic ratio of each element satisfies formulas (1) to (5) (where X is the sum of the content ratios of the additive elements). 0.20 ≤ In / (In + Ga + Sn + Zn + X) ≤ 0.30 (1) 0.24 ≤ Ga / (In + Ga + Sn + Zn + X) ≤ 0.45 (2) 0.30 ≤ Zn / (In + Ga + Sn + Zn + X) ≤ 0.50 (3) 0.0001 ≤ Sn / (In + Ga + Sn + Zn + X) ≤ 0.02 (4) 0.0001 ≤ X / (In + Ga + Sn + Zn + X) ≤ 0.03 (5) [7] The oxide semiconductor layer according to [6], wherein the second oxide semiconductor layer has a stacked structure on the first oxide semiconductor layer. [8] A thin-film transistor comprising: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; an oxide semiconductor layer as described in [7] disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the oxide semiconductor layer; and a protective layer disposed on the source electrode, the drain electrode and the oxide semiconductor layer, wherein the first oxide semiconductor layer in the oxide semiconductor layer is located on the substrate side. [9] The thin-film transistor as described in [8], wherein the first oxide semiconductor layer is a channel layer and the second oxide semiconductor layer is a cap layer.

[0047] The present invention will be described in more detail below with reference to examples. However, the scope of the present invention is not limited to these examples. Unless otherwise specified, "%" means "mass%".

[0048] [Examples 1 to 14] Average particle size D ５０ In２ O ３ Powder and average particle size D ５０ Ga is 2.0 μm ２ O ３ Powder and average particle size D ５０ ZnO powder with a particle size of 0.8 μm and average particle size D ５０ SnO ２ Powder and average particle size D ５０ Ta is 0.6 μm ２ O ５ Powder or average particle size D ５０ Nb is 0.7 μm ２ O ５ Powder or average particle size D ５０ Al ２ O ３ Powder or average particle size D ５０ SiO is 0.6 μm ２ The powders were dry-mixed using a ball mill with zirconia balls to prepare a mixed raw material powder. Average particle size D of each powder. ５０ The particle size distribution was measured using a particle size analyzer (HRA) manufactured by Nikkiso Co., Ltd. Water was used as the solvent, and the measurement was performed at a refractive index of 2.20 for the substance being measured. The mixing ratio of each powder was such that the atomic ratios of In, Ga, Zn, Sn, Ta, Nb, Al, or Si were as shown in Table 1 below.

[0049] In a pot containing the prepared mixed raw material powder, 0.2% of the binder relative to the mixed raw material powder, 0.6% of the dispersant relative to the mixed raw material powder, and 20% of the water relative to the mixed raw material powder were added, and a slurry was prepared by ball milling with zirconia balls.

[0050] The prepared slurry was poured into a metal mold with a filter in between, and then the water in the slurry was drained to obtain a molded body. This molded body was then fired to produce a sintered body. The firing was carried out in an atmosphere with an oxygen concentration of 20 volume%, at a firing temperature of 1500°C, a firing time of 10 hours, a heating rate of 300°C / hour, and a cooling rate of 50°C / hour.

[0051] The sintered body obtained in this manner was machined to obtain an oxide sintered body (target material) with dimensions of 210 mm in width, 710 mm in length, and 6 mm in thickness. A #170 grinding wheel was used for machining. The surface roughness Ra of the target material was 1.0 μm.

[0052] [Comparative Example 1] A mixed raw material powder was prepared such that the atomic ratio of each element was In:Ga:Zn = 1:3:6. The target material was obtained in the same manner as in Example 1. The target material in this comparative example consists of an oxide containing only In, Ga, and Zn.

[0053] [Comparative Examples 2 to 11] Average particle size D ５０ In ２ O ３ Powder and average particle size D ５０ Ga is 2.0 μm ２ O ３ Powder and average particle size D ５０ ZnO powder with a particle size of 0.8 μm and average particle size D ５０ SnO ２ Powder and average particle size D ５０ Ta is 0.6 μm ２ O ５ The powders were dry-mixed using a ball mill with zirconia balls to prepare a mixed raw material powder. Average particle size D of each powder. ５０ The particle size distribution was measured using a particle size analyzer (HRA) manufactured by Nikkiso Co., Ltd. Water was used as the solvent, and the measurement was performed at a refractive index of 2.20 for the substance being measured. The mixing ratio of each powder was set so that the atomic ratios of In, Ga, Zn, Sn, and Ta matched the values ​​shown in Table 2 below.

[0054] [Target material for channel layer deposition] A mixed raw material powder was prepared as a target material for channel layer deposition, with an atomic ratio of In:Ga:Zn = 1:1:1. The target material was obtained in the same manner as in Example 1, except for this. This target material consists of an oxide containing only In, Ga, and Zn.

[0055] The proportion of each metal contained in the target materials obtained in the examples and comparative examples was measured by ICP emission spectroscopy. It was confirmed that the atomic ratio of each element was the same as that of the raw material ratios shown in Tables 1 and 2.

[0056] [Evaluation 1] For the target materials obtained in Examples 1 to 14 and Comparative Example 1, the relative density, flexural strength, Vickers hardness, and bulk resistivity were measured by the following methods. The results are shown in Table 1.

[0057] [Relative density] The air mass of the target material was divided by the volume (the underwater mass of the target material / the specific gravity of water at the measurement temperature), and the percentage value with respect to the theoretical density ρ (g / cm ３ ) based on the following formula (i) was taken as the relative density (unit: %).

[0058]

[0059] (In the formula, Ci represents the content (mass %) of the constituent substances of the target material, and ρi represents the density (g / cm ３ ) of each constituent substance corresponding to Ci.) In the present invention, when the X element is Ta, the content (mass %) of the constituent substances of the target material is considered as In ２ O ３ , Ga ２ O ３ , ZnO, SnO ２ , Ta ２ O ５ and, for example, C1: the mass % of In ２ O ３ in the target material ρ1: the density of In ２ O ３ (7.18 g / cm ３ ) C2: the mass % of Ga ２ O ３ in the target material ρ2: the density of Ga ２ O ３ (5.95 g / cm ３ ) C3: the mass % of ZnO in the target material ρ3: the density of ZnO (5.60 g / cm ３ ) C4: the mass % of SnO ２ in the target material ρ4: the density of SnO ２ (6.95 g / cm ３ ) C5: the mass % of Ta ２ O ５ in the target material ρ5: the density of Ta ２ O ５ (8.74 g / cm ３By applying () to formula (i), the theoretical density ρ can be calculated. When using Nb as the X element, Ci: Nb in the target material ２ O ５ mass percentage of, ρi: Nb ２ O ５ density of (4.47 g / cm ３ When using Al as the X element, Ci: Al in the target material ２ O ３ mass percentage of, ρi: Al ２ O ３ density of (3.98 g / cm ３ When using Si as the X element, Ci: SiO in the target material ２ mass percentage of, ρi: SiO ２ density of (2.20 g / cm ３ can be applied to formula (i). In ２ O ３ mass percentage of, Ga ２ O ３ mass percentage of, mass percentage of ZnO, SnO ２ mass percentage of and mass percentage of X oxide can be obtained from the analysis results of each element of the target material by ICP emission spectrometry.

[0060] [Flexural strength] Measured using an autograph (registered trademark) AGS-500B manufactured by Shimadzu Corporation. Using a test piece cut out from the target material (total length 36 mm or more, width 4.0 mm, thickness 3.0 mm), it was measured according to the measurement method of three-point flexural strength of JIS-R-1601 (Test method for flexural strength of fine ceramics).

[0061] [Vickers Hardness] Vickers hardness was measured using the MHT-1 Vickers hardness tester manufactured by Matsuzawa Co., Ltd. The cut surface obtained by cutting the target material was polished in stages using emery paper #180, #400, #800, #1000, and #2000, and finally buffed to a mirror finish to be used as the measurement surface. The surface opposite to the measurement surface was polished using the same emery paper #180 so that it was parallel to the measurement surface, and a test piece was obtained. Using the above test piece, the Vickers hardness was measured with a load of 1 kgf according to the hardness measurement method of JIS-R-1610:2003 (Hardness Test Method for Fine Ceramics). The measurement was performed at 10 different positions on one test piece, and the arithmetic mean was taken as the Vickers hardness of the target material.

[0062] [Bulk Resistivity] Bulk resistivity was measured using the JIS standard DC four-probe method with a Loresta® HP MCP-T410 manufactured by Mitsubishi Chemical. The probe (series four-probe probe TYPE ESP) was brought into contact with the surface of the processed target material, and measurements were taken in AUTO RANGE mode. A total of 15 measurement points were set: 5 points at approximately equal intervals in the horizontal direction and 3 points at approximately equal intervals in the vertical direction. The average value of each measurement was taken as the bulk resistivity of the target material.

[0063] [Evaluation 2] Sputtering was performed using the target materials of Examples 1 to 14 and Comparative Example 1, and the number of arcing events was measured. The results are shown in Table 1. A DC magnetron sputtering apparatus was used for sputtering. The sputtering conditions were as follows: ・Ultimate vacuum: 3 × 10⁻⁶ －６ [Pa] • Sputtering pressure: 0.4 [Pa] • Oxygen partial pressure: 1 × 10⁻⁶ －３ [Pa] ・Input power amount time: 2W / cm ２ - Time: The number of arcing events that occurred during 48 hours of sputtering was measured using an arcing counter (model: μArc Monitor MAM Genesis MAM Data Collector Ver. 2.02) manufactured by LANDMARK TECHNOLOGY.

[0064] [Evaluation 3] Using Examples 1 to 14, Comparative Examples 2 to 11, and the target material for channel layer deposition, a TFT element 1 having the structure shown in Figure 1 was fabricated by photolithography. In the fabrication of the TFT element 1, first, a Mo thin film was deposited as the gate electrode 20 on a glass substrate (OA-10 manufactured by Nippon Electric Glass Co., Ltd.) 10 using a DC sputtering apparatus. Next, a SiOx thin film was deposited as the gate insulating layer 30 under the following conditions. Deposition apparatus: Plasma CVD apparatus PD-2202L manufactured by Samco Corporation Deposition gas: SiH ４ / N ２ O Deposition pressure: 110 Pa Set temperature: 400°C Next, a first oxide semiconductor layer (channel layer) 41 was deposited using a target material for channel layer deposition, and then a second oxide semiconductor layer (cap layer) 42 was deposited on top of it using the target materials obtained in Examples 1 to 14 and Comparative Examples 2 to 11, respectively. The thickness of the first oxide semiconductor layer (channel layer) 41 was 30 nm, and the thickness of the second oxide semiconductor layer (cap layer) 42 was 50 nm. Deposition equipment: DC sputtering equipment SML-464 manufactured by Tokki Co., Ltd. Ultimate vacuum: 1 × 10 －４ Below Pa, sputtered gas: Ar / O ２ Mixed gas / sputter gas pressure: 0.4 Pa·O ２ Gas partial pressure: 5% when depositing the channel layer, 50% when depositing the cap layer. Substrate temperature: Room temperature. Sputtering power: 3 W / cm². ２ Next, a Mo thin film was deposited as the source electrode 60 and drain electrode 61 using the DC sputtering apparatus. A SiOx thin film was deposited as the protective layer 70 using the plasma CVD apparatus. Finally, heat treatment was performed at 300°C.

[0065] The transfer characteristics of the TFT element 1 obtained in this manner were measured at a drain voltage Vd = 5V. The measured transfer characteristics were expressed as the field effect mobility μ (cm²). ２The values ​​are (Vs) and threshold voltage Vth (V). The transfer characteristics were measured using a Semiconductor Device Analyzer B1500A manufactured by Agilent Technologies, Inc. The measurement results are shown in Table 2. It is preferable that the threshold voltage is between 0V and 2V.

[0066] Next, PBTS (Positive Bias Temperature Stress), NBTS (Negative Bias Temperature Stress), and NBTIS (Negative Bias Temperature Illustration Stress) were measured for TFT element 1 using a Semiconductor Device Analyzer B1500A manufactured by Agilent Technologies, Inc. For PBTS, the gate voltage was set to +30V, the source voltage and drain voltage to 0V, and a DC voltage was applied for 1 hour to a TFT element 1 heated to 60°C, and the change in Vth was measured. For NBTS, the gate voltage was set to -30V, the source voltage and drain voltage to 0V, and a DC voltage was applied for 1 hour to a TFT element 1 heated to 60°C, and the change in Vth was measured. For NBTIS, 1000 cd / m ２ The device was irradiated with white LED light, the gate voltage was set to -30V, the source voltage and drain voltage to 0V, and a DC voltage was applied for 1 hour to measure the change in Vth. The measurement results are shown in Table 2. In PBTS measurement, it is preferable that the change in Vth is between 0V and 1.8V. In NBTS measurement, it is preferable that the change in Vth is between -0.7V and 0V. In NBTIS measurement, it is preferable that the change in Vth is between -2.0V and 0V.

[0067]

[0068]

[0069] As is clear from the results shown in Table 1, the target materials obtained in Examples 1 to 14 showed a reduced number of arcing events compared to the target material in Comparative Example 1. Furthermore, as is clear from the results shown in Table 2, the TFTs equipped with cap layers formed from the target materials obtained in each example exhibited better transmission characteristics and reliability compared to the TFTs equipped with cap layers formed from the target materials obtained in the comparative example.

[0070] As described in detail above, the present invention provides a target material made of oxide in which particle generation is suppressed during sputtering. Furthermore, the present invention provides an oxide semiconductor layer and a thin-film transistor manufactured by sputtering using such a target material.

Claims

It is composed of an oxide containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta), niobium (Nb), aluminum (Al), and silicon (Si)). A sputtering target material in which the atomic ratio of each element satisfies formulas (1) to (5) (wherein X is the sum of the content ratios of the added elements). 0.20≦In / (In+Ga+Sn+Zn+X)≦0.30 (1) 0.24≦Ga / (In+Ga+Sn+Zn+X)≦0.45 (2) 0.30≦Zn / (In+Ga+Sn+Zn+X)≦0.50 (3) 0.0001≦Sn / (In+Ga+Sn+Zn+X)≦0.02 (4) 0.0001≦X / (In+Ga+Sn+Zn+X)≦0.03 (5) 　 The sputtering target material according to claim 1, wherein the relative density is 98% or higher. 　 The sputtering target material according to claim 1 or 2, wherein the bending strength is 100 MPa or more. 　 The sputtering target material according to claim 1 or 2, wherein the Vickers hardness is 450 HV or higher. The bulk resistivity at 25°C is 20.0 × 10⁻⁶. －３ The sputtering target material according to claim 1 or 2, wherein the size is Ω·cm or less. 　 A first oxide semiconductor layer containing at least the element indium (In), An oxide semiconductor layer comprising a second oxide semiconductor layer disposed adjacent to a first oxide semiconductor layer, The second oxide semiconductor layer is composed of an oxide containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and an additive element (X) (where X represents at least one element selected from the group consisting of tantalum (Ta), niobium (Nb), aluminum (Al), and silicon (Si)). An oxide semiconductor layer in which the atomic ratio of each element satisfies formulas (1) to (5) (wherein X is the sum of the content ratios of the aforementioned additive elements). 0.20≦In / (In+Ga+Sn+Zn+X)≦0.30 (1) 0.24≦Ga / (In+Ga+Sn+Zn+X)≦0.45 (2) 0.30≦Zn / (In+Ga+Sn+Zn+X)≦0.50 (3) 0.0001≦Sn / (In+Ga+Sn+Zn+X)≦0.02 (4) 0.0001≦X / (In+Ga+Sn+Zn+X)≦0.03 (5) 　 The oxide semiconductor layer according to claim 6, wherein the second oxide semiconductor layer has a stacked structure disposed on the first oxide semiconductor layer. 　 circuit board and A gate electrode disposed on the substrate, A gate insulating layer disposed on the gate electrode, The oxide semiconductor layer according to claim 7 is disposed on the gate insulating layer, Source electrode and drain electrode disposed on the oxide semiconductor layer, A thin-film transistor comprising the source electrode, the drain electrode, and a protective layer disposed on the oxide semiconductor layer, A thin-film transistor in which the first oxide semiconductor layer in the oxide semiconductor layer is located on the substrate side. 　 The thin-film transistor according to claim 8, wherein the first oxide semiconductor layer is a channel layer and the second oxide semiconductor layer is a cap layer.

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