Contour extraction edge-based wafer image characterization for manufacturing process calibration

Abstract

A computing system can aggregate a plurality of wafer images depicting a portion of an electronic device into a reference image. The electronic device has physical structures manufactured using one or more lithographic process. The computing system can determine which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images include image data corresponding background image data. The computing system can compare the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device, and generate a gauge file to include a set of the wafer images that are selected based on the comparison.

Description

202419284 CONTOUR EXTRACTION EDGE-BASED WAFER IMAGE CHARACTERIZATION FOR MANUFACTURING PROCESS CALIBRATIONTECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to contour extraction edge-based wafer image characterization for manufacturing process calibration.BACKGROUND

[0002] In a design flow for fabricating integrated circuits, a physical design of an integrated circuit can describe specific geometric elements, often referred to as a layout design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the integrated circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.

[0003] Descriptions for physical designs of integrated circuits can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among202419284 other features, it includes a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway, EDDM, and Open Artwork System Interchange Standard (OASIS). These various industry formats are used to define the geometrical information in layout designs that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.

[0004] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or nonexposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0005] Each time that a layer of material is exposed to radiation, a mask is created to expose only the desired areas to the radiation, and to protect the other areas from exposure.202419284 The mask is created from circuit layout data. That is, the geometric elements described in a layout design define the relative locations or areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design, after which the mask can be used in a photolithographic process to manufacture the integrated circuits described in the physical designs.

[0006] After manufacture, wafer images of the integrated circuit can be captured, for example, using x-ray machines or a scanning electron microscope (SEM). These wafer images are often utilized to inspect a quality of the lithographed patterns, detect defects and analyze the root causes that have led to the defects, and use the wafer images to develop and calibrate optical proximity correction (OPC) models for an optical proximity correction process that can adjust amplitude of light transmitted through a lithographic mask by modifying the mask layout design data employed to create the mask. Since the accuracy of the wafer images used to develop the OPC models directly correlates to the accuracy of the OPC process and actual lithography results, most design teams scrutinize the wafer images to eliminate ones that have poor quality or include defects, so those defective wafer images do not propagate downstream and negatively impact manufacturing. Conventional techniques capture multiple wafer images of the same portion of the silicon wafer and identify defective wafer images by a manual review process and / or by comparing critical dimension (CD) measurements corresponding to distances between patterns on the silicon wafer. Those wafer images deemed aberrant during manual review or by the critical dimension measurements comparison can be removed for subsequent use in downstream processes, such as OPC model calibration, contour extraction, defect detection and root cause analysis, or the like. There have been some automated techniques to evaluate wafer202419284 image quality and acceptability, which utilize conventional image analysis techniques to analyze the wafer images against an expected image. Since defects in physical structures of electronics tend to be sufficiently small relative to the size of the wafer images, these automated techniques, however, often fail to effectively differentiate between the wafer images.SUMMARY

[0007] This application discloses a computing system implementing an wafer image system that can aggregate a plurality of wafer images depicting a portion of an electronic device into a reference image. The electronic device has physical structures manufactured using one or more lithographic process. The computing system implementing the wafer image system can determine which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images include image data corresponding background image data. The computing system implementing the wafer image system can compare the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device, and generate a gauge file to include a set of the wafer images that are selected based on the comparison. Embodiments of will be described below in greater detail.DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.202419284

[0009] Figure 3 illustrates an example wafer image system with edge-based image selection that may be implemented according to various embodiments.

[0010] Figure 4 illustrates a flowchart showing an example implementation of wafer image processing with edge-based image selection according to various examples.

[0011] Figure 5 illustrates a flowchart showing an example implementation of deviation threshold modification during wafer image processing with edge-based image selection according to various examples.

[0012] Figures 6A and 6B illustrates example window-based classification of wafer image edges according to various examples.DETAILED DESCRIPTIONIllustrative Operating Environment

[0013] Various examples may be implemented through the execution of software instructions by a computing device 101, such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processor unit 105 and a system memory 107. The processor unit 105 may be any type of programmable electronic device for executing software instructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processor unit 105.202419284

[0014] The processor unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processor unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101, one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0015] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a202419284 modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0016] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one or more computing devices that include the components of the computing device 101 illustrated in Figure 1, which include only a subset of the components illustrated in Figure 1, or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0017] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.202419284

[0018] Each processor core 201A and 201B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201A and 201B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201A and 201B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201A and 201B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.Wafer Image Defect Detection and Characterization for Manufacturing Process Calibration

[0019] Figure 3 illustrates an example wafer image system 300 with edge-based image selection that may be implemented according to various embodiments. Figure 4 illustrates a flowchart showing an example implementation of wafer image processing with edge-based image selection according to various examples. Referring to Figures 3 and 4, the wafer image system 300 can obtain multiple wafer images 301 depicting of a portion of an202419284 electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design. In some embodiments, the wafer images 301 can be generated by an x-ray machine or a scanning electron microscope (SEM) system that can be utilized to collect measurements during optical lithographic experiments for different features on a wafer, for example, performed by a foundry at a manufacturing process node. The wafer image 301 can include geometrical patterns, such as L / S (line-space), C / H (contact-hole), pillars with different scan types, SRAM structure and Logic structure, or the like.

[0020] The wafer image system 300 can include an edge-based analysis system 310 to identify which portions in the wafer images 301 correspond to the physical structures in the electronic device. In some embodiments, the edge-based analysis system 310 can differentiate image data in the wafer images 301 into two different classifications, i.e., image data having an edge that corresponds to the physical structures in the electronic device and image data corresponding to background pixels not associated with the physical structures in the electronic device.

[0021] The edge-based analysis system 310 can include an reference image system 312 that, in a block 401 of Figure 4, can aggregate a plurality of the wafer images 301 depicting a portion of an electronic device into a reference image. In some embodiments, the reference image system 312 can average pixel values from the wafer images 301 and populate the reference image with the averaged pixel values.

[0022] The edge-based analysis system 310 can include an windowing system 314 to partition the wafer images 301 and the reference image into multiple different windows. In202419284 some embodiments, the windows can be set of contiguous, non-overlapping blocks having the same shape that, when combined, cover the entire wafer image 301 or reference image. The windows, in other embodiments, may include one or more shapes that differ in size and / or at least partially overlap each other. Some example embodiments of windows for wafer images 301 will be decribed below with reference to Figures 6A and 6B in greater detail.

[0023] The edge-based analysis system 310, in a block 402 of Figure 4, can perform an edgebased analysis on the reference image and each of the wafer images 301 to identify which portions of the images include image data corresponding to the physical structures of the electronic device. In some embodiments, the edge-based analysis system 310 can include a threshold setting system 316 to set a deviation threshold for the edge-based analysis. For example, the edge-based analysis system 310 can calculate an image data deviation metric for each of the windows of the reference image and the wafer images 301, such as standard deviation, variance, or the like, associated with the image data, and then aggregate or average the image data deviation metric to determin the deviation threshold for the edgebased analysis.

[0024] The edge-based analysis system 310 can perform the edge-based analysis on the reference image and each of the wafer images 301 by comparing the image data deviation metric for each of the windows of the reference image and the wafer images 301 against the deviation threshold. When the image data deviation metric exceeds the deviation threshold, a window classification system 318 included in the edge-based analysis system 310 can classify the window of the reference image or the wafer images 301 as corresponding to edge image data of the physical structures of the electronic device.202419284 Conversely, when the image data deviation metric falls below the deviation threshold, the window classification system 318 can classify the window of the reference image or the wafer images 301 as corresponding to background image data.

[0025] In some embodiments, the edge-based analysis system 310 can perform a deviation threshold verification process, which can analyze the classifications of the windows of the reference image and the wafer images 301 and iteratively modify the deviation threshold based on the classifications. For example, the edge-based analysis system 310 utilize a number or percentage of windows classificed as corresponding to edges of physical structures to determine whether to alter the deviation threshold. By iteratively modifying the deviation threshold, the edge-based analysis system 310 can adjust the classification of the windows of the reference image and the wafer images 301 to effectively differentiate between the windows of the reference image and the wafer images 301 having edge image data from those having background image data. Embodiments of the edge-based analysis will be described below in greater detail with reference to Figure 5.

[0026] Figure 5 illustrates a flowchart showing an example implementation of deviation threshold modification during wafer image processing with edge-based image selection according to various examples. Referring to Figures 3 and 5, the edge-based analysis system 310, in a block 501, can determine a window size to capture structures of an electronic image in wafer images 301 and a reference image. In some embodiments, the window size can be associated with a size of a critical dimension of the physical structures in the electronic device, correspond to a size of potential lithography defects capable of being captured in the wafer images 301, or the like.202419284

[0027] The edge-based analysis system 310, in a block 502, can calculate deviation metrics of image data within each of the windows of the wafer images and reference image. In some embodiments, the edge-based analysis system 310 can calculate the standard deviation of the image data, variances of the image data, or other image data deviation metrics of the image data within each of the windows of the wafer images and reference image.

[0028] The edge-based analysis system 310, in a block 503, can set a deviation threshold level based on the deviation metrics. In some embodiments, the edge-based analysis system 310 can set the deviation threshold level as an average of the standard deviations, variances, other image data deviation metrics associated with the windows within the reference image and / or the wafer images 301.

[0029] The edge-based analysis system 310, in a block 504, can compare the deviation metrics of each window to the deviation threshold level. When the deviation metrics fall below the deviation threshold, the edge-based analysis system 310 can bin the window into a group corresponding to background image data. When the deviation metrics exceed the deviation threshold, the edge-based analysis system 310 can bin the window into another group corresponding to edge image data. The edge-based analysis system 310 can accumulate a count of the number of windows or a percentage of windows in the bins corresponding to edge image data and corresponding to background image data.

[0030] The edge-based analysis system 310, in a block 505, can determine whether a number of windows falls within an edge image data range or background image data range. The edge image data range can correspond to a number of windows or a percentage of202419284 windows expected to be classified as including edge image data. The background image data range can correspond to a number of windows or a percentage of windows expected to be classified as including background image data. In some embodiments, these ranges can be predefined with set counts or percentages, while in other embodiments, these ranges can be set dynamically based on a content of the wafer images 301, such as a pattern type or device classification for the portion of the electronic device depicted in the wafer images 301.

[0031] When in the edge-based analysis system 310 determines a count or percentage of windows binned into groups corresponding to edge image data or background image data falls outside of the edge image data range or the background image data range, respectively, execution can return to block 503, wherein the edge-based analysis system 310 can set a new deviation threshold. For example, when the edge-based analysis system 310 determines too few windows were binned into the group corresponding to edge image data, the edge-based analysis system 310 can alter the edge image data range or the background image data range, to allow additional windows in the wafer images 301 and reference image to be binned into the group corresponding to edge image data. Conversely, when the edgebased analysis system 310 determines too many windows were binned into the group corresponding to edge image data, the edge-based analysis system 310 can alter the edge image data range or the background image data range, to capture fewer windows in the wafer images 301 and reference image to be binned into the group corresponding to edge image data.

[0032] When the edge-based analysis system 310 determines the count or percentage of windows binned into the groups corresponding to edge image data or background image202419284 data falls inside of the edge image data range or the background image data range, respectively, execution can proceed to the block 506, where the edge-based analysis system 310 can separately classify each window in the wafer images 301 and the references image as corresponding to the physical structures or background of the electronic device. In some embodiments, the edge-based analysis system 310 can classify the windows binned in the group corresponding to edge image data as edge windows and can classify the windows binned into the group corresponding to background image data as background windows. Embodiments of the wafer image processing with edge-based image selection is described below in Figures 6A and 6B.

[0033] Figures 6A and 6B illustrates example window -based classification of wafer image edges according to various examples. Referring to Figures 3, 6A, and 6B, the edge-based analysis system 310 can to sub-divide or partition a wafer image 601. In some embodiments, the edge-based analysis system 310 can sub-divide the wafer image 501 with differing sized windows, for example, selected or determined based on the underlying image characteristics of the wafer image 601.

[0034] The edge-based analysis system 310 can analyze each of windows to determine whether the pixel data within the blocks of the wafer image 501 correspond to a background portion of the wafer image 601 or an edge portion of the wafer image 601. In some embodiments, the edge-based analysis system 310 can identify deviation metrics of the pixel data within each of the windows, for example, by calculating a standard deviation, variance or other deviation metric of the pixel values in each of the windows, and then classify the windows as corresponding to a background portion of the wafer image 601 or an edge portion of the wafer image 601 based on the calculated standard deviation, variance or202419284 other deviation metric of the pixel values. In some embodiments, the edge-based analysis system 310 can compare the deviation metrics for the windows against a deviation threshold to determine the classification for the windows. For example, when the edgebased analysis system 310 determines the deviation metric of pixel values within a window exceeds the deviation threshold, the edge-based analysis system 310 can classify the window as corresponding to edge image data. When the edge-based analysis system 310 determines the deviation metric of pixel values within a window falls below the deviation threshold, the edge-based analysis system 310 can classify the window as including background image data. Figure 6B shows a wafer image with edge windows 620, which has the wafer image 610 along with those windows that correspond edge image data depicting physical structures of the electronic device.

[0035] Referring back to Figure 3 and 4, the wafer image system 300 can include an image selection system 320 to utilze the windows classifed as corresponding to edge image data from the reference image and the wafer images 301 to select wafer images to undergo further processing by a physical verificaiton tool 330. The image selection system 320 can include an image scoring system 322 that, in a block 403 of Figure 4, can compare portions of the reference image that include the physical structures to the portions of the wafer images 301 that include the physical structures. In some embodiments, the image scoring system 322 can compare windows classified as corresponding to edges in the reference image against those in the wafer images 301 by performing a modified version of a structural similarity index measure (SSIM) algorithm on the wafer images 301 and the reference image. The modified SSIM algorithm, in some embodiments, can be implemented using the following equation of a structural portion of the SSIM algorithm.202419284

[0036] Equation 1:Modified SSIM(x,y) = s(x,y) =

[0037]

[0038] In Equation 1, the portions of the wafer images corresponding to edge windows, represented by x and y, can each include a set of pixels to be compared using the modifiedSSIM algorithm. A standard deviation σxof the pixel set corresponding to portions of thewafer images corresponding to edge windows x and a standard deviationof the pixel set corresponding to portions of the wafer images corresponding to edge windows y, along witha constant C and a cross-correlationof the edge windows of wafer images x and y can be utilized to determine a similarity s between the pixel sets.

[0039] The image selection system 320, in a block 405 of Figure 4, can select a set of one or more of the wafer images based on the image processing scores for the wafer images 301. In some embodiments, the image selection system 320 can determine which of the wafer images 301 have image processing scores falling below a threshold score value, which indicates the pixels in the edges in the corresponding wafer image 301 deviate from the pixels in the edges reference image beyond a predetermined level or magnitude. The image selection system 320 can output the selected wafer images 302 to the physical verification tool 330 for further processing and usage.

[0040] The image selection system 320 can include a gauge file system 334 that, in a block 406 of Figure 4, can generate the gauge file 303 to include the selected wafer images 302. In some embodiments, the gauge file system 334 can utilize the wafer images selected by202419284 the image selection system 320 for use in generating the gauge file 303 or the gauge file system 334 can select the wafer images 301 to include in the gauge file 303 based on the classifications of the wafer images 301. In some examples, a gauge can represent a set of similar features of an integrated circuit and include an aggregated measurement value to associate with those features. The gauge file system 334 can output in the gauge file 303 for use to the physical verification tool 330 or other electronic design tool. The physical verification tool 340 can utilize selected wfer images 302 and / or the gauge file 303 to calibrate other electronic design automation tools, such as optical proximity correction (OPC) calibration, or the like.

[0041] The physical verification tool 330, in some embodiments, can utilize the selected wafer images 302 to train a contour extraction system, which identify the edges or contours in the selected wafer images 302 and extract them. In some embodiments, the physical verification tool 330 can use the selected wafer images 302 to set parameters for the contour extraction operations, such as parameters to indicate a number of pixels in the selected wafer images 302 to utilize to identify contours, to indicate a pixel value deviation to annunciate a contour, or the like. The physical verification tool 330 can include an extraction engine to extract image contours corresponding to the physical structures of the electronic device from the selected wafer images 302 of the electronic device using the parameters. The physical verification tool 330 can output the extracted image contours, which can be utilized to gather measurements or metrology data associated with the manufactured electronic device, identify manufacturing variations in the electronic device, or the like.202419284

[0042] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0043] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0044] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which202419284 may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0045] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer-readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini- computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non- removable media, or any combination thereof.

[0046] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.202419284 Conclusion

[0047] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to design processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

[0048] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0049] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

202419284CLAIMS1. A method comprising:aggregating, by a computing system, a plurality of wafer images depicting a portion of an electronic device into a reference image, wherein the electronic device has physical structures manufactured using one or more lithographic process;determining, by the computing system, which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data, wherein the windows correspond to subsets of image data in the reference image and in the wafer images.comparing, by the computing system, the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device; andgenerating, by the computing system, a gauge file to include a set of the wafer images that are selected based, at least in part, on the comparison of the windows of the reference image that including image data corresponding to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

2. The method of claim 1, further comprising determining, by the computing system, image processing scores for each of the wafer images based, at least in part, on the comparison of the windows of the reference image that including image data corresponding202419284 to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

3. The method of claim 2, further comprising selecting, by the computing system, the set of the wafer images based, at least in part, on the image processing scores.

4. The method of claim 1, wherein the comparing of the windows of the reference image to the windows of the wafer images is performed without comparing the windows that include the background image data.

5. The method of claim 1, wherein comparing of the windows of the reference image to the windows of the wafer images is performed using at least a structural portion of a structural similarity index measure (SSIM) algorithm on the wafer images and the reference image.

6. The method of claim 1, further comprising:determining, by the computing system, a deviation threshold for differentiating between image data corresponding to the physical structures of the electronic device and background image data;calculating, by the computing system, a deviation metric for each of the windows in the reference image and in the wafer images; anddetermining, by the computing system, which of the windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images202419284 that include image data corresponding background image data based on a comparison of the deviation metrics to the deviation threshold.

7. The method of claim 6, further comprising iteratively modifying, by the computing system, the deviation threshold based on the determination of which of the windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data.

8. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:aggregating a plurality of wafer images depicting a portion of an electronic device into a reference image, wherein the electronic device has physical structures manufactured using one or more lithographic process;determining which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data, wherein the windows correspond to subsets of image data in the reference image and in the wafer images.comparing the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device; and202419284 generating a gauge file to include a set of the wafer images that are selected based, at least in part, on the comparison of the windows of the reference image that including image data corresponding to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

9. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising determining image processing scores for each of the wafer images based, at least in part, on the comparison of the windows of the reference image that including image data corresponding to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

10. The apparatus of claim 9, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising selecting the set of the wafer images based, at least in part, on the image processing scores.

11. The apparatus of claim 8, wherein the comparing of the windows of the reference image to the windows of the wafer images is performed without comparing the windows that include the background image data.

12. The apparatus of claim 8, wherein comparing of the windows of the reference image to the windows of the wafer images is performed using at least a structural portion of202419284 a structural similarity index measure (SSIM) algorithm on the wafer images and the reference image.

13. The apparatus of claim 8, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:determining a deviation threshold for differentiating between image data corresponding to the physical structures of the electronic device and background image data;calculating a deviation metric for each of the windows in the reference image and in the wafer images; anddetermining which of the windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data based on a comparison of the deviation metrics to the deviation threshold.

14. The apparatus of claim 13, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising iteratively modifying the deviation threshold based on the determination of which of the windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data.

15. A system comprising:202419284 a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to:aggregate a plurality of wafer images depicting a portion of an electronic device into a reference image, wherein the electronic device has physical structures manufactured using one or more lithographic process;determine which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data, wherein the windows correspond to subsets of image data in the reference image and in the wafer images.compare the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device; andgenerate a gauge file to include a set of the wafer images that are selected based, at least in part, on the comparison of the windows of the reference image that including image data corresponding to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

16. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to determine image processing scores for each of the wafer images based, at least in part, on the comparison of202419284 the windows of the reference image that including image data corresponding to the physical structures of the electronic device and the windows of the wafer images include image data corresponding to the physical structures of the electronic device.

17. The system of claim 16, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to select the set of the wafer images based, at least in part, on the image processing scores.

18. The system of claim 15, wherein the comparing of the windows of the reference image to the windows of the wafer images is performed without comparing the windows that include the background image data.

19. The system of claim 15, wherein comparing of the windows of the reference image to the windows of the wafer images is performed using at least a structural portion of a structural similarity index measure (SSIM) algorithm on the wafer images and the reference image.

20. The system of claim 15, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:determine a deviation threshold for differentiating between image data corresponding to the physical structures of the electronic device and background image data;calculate a deviation metric for each of the windows in the reference image and in the wafer images; and202419284 determine which of the windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images that include image data corresponding background image data based on a comparison of the deviation metrics to the deviation threshold.

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