Determining analysis windows of an integrated circuit (IC) design for analyzing the IC design

Abstract

A computer-implemented method is provided for determining a plurality of analysis windows of an integrated circuit (IC) design for analyzing the IC design, wherein the IC design may include a plurality of patterns. The method may include providing the IC design; determining a plurality of clusters in the IC design, wherein the respective cluster includes similar patterns; and determining the respective analysis window including a configurable number or type of different clusters.

Description

DETERMINING ANALYSIS WINDOWS OF AN INTEGRATED CIRCUIT (IC) DESIGN FOR ANALYZING THE IC DESIGNTECHNICAL FIELD

[0001] The present disclosure is directed, in general, to electronic design automation (EDA) and, more specifically, to the determination of analysis windows of an integrated circuit (IC) design for analyzing the IC design. Such electronic design automation systems and determining analysis windows of an IC design for analyzing the IC design systems are collectively referred to herein as product systems.BACKGROUND

[0002] The development of electronic devices with electronic circuits typically involves many steps known as a design flow. This design flow typically starts with a specification for a new electronic device to be implemented with an electronic circuit, such as an integrated circuit (IC). The specification of the electronic device can be transformed into an electronic device design, such as a netlist, for example, by a schematic capture tool or by synthesizing a logical design, sometimes referred to as a register transfer level (RTL) description of the electronic device. The netlist may be specified in an Electronic Design Interchange Format (EDIF) or the like, which can describe nets or connectivity between various components or parts in the electronic device design.

[0003] The design flow may continue by verifying functionality of the electronic device design, for example, by simulating, emulating, or prototyping the electronic device design and verifying that the results of the simulation or emulation correspond with an expected output from the electronic device design. The functionality also can be verified by formally verifying with one or more solvers or statically checking the electronic device design for various attributes that may be problematic during operation of the electronic device built utilizing the electronic device design.

[0004] Once the electronic device design has been functionally verified, the design flow may utilize the logical design to generate a layout design for the electronic device. This procedure can be implemented in different ways, but typically, through the use of a layout tool, which can place and interconnect various components or parts into a representation of an electronic circuit. For example, the layout tool implemented in a computing system can present a graphical view of the electronic circuit and allow a designer to utilize the layout tool to place parts from a library onto the electronic circuit in the graphical view.

[0005] The layout of the electronic circuit may then physically be verified, e.g., to address functional yield challenges in IC designs or process deficiencies which may occur during the manufacture of IC designs. Such a physical verification helps to provide accurate circuit behavior with precise device parameters, while being manufacturable with a desired quality and manufacture yield. In certain respects, the present patent disclosure primarily focusses on the physical verification of an electronic circuit layout, e.g., by determining analysis windows of an IC design for analyzing the IC design in the context of physical verification of the IC design. By way of example, the analysis may involve model calibration or inspection using the respective analysis window.

[0006] Currently, there exist product systems and solutions which support determining analysis windows of an IC design for analyzing the IC design. Such product systems may benefit from improvements.BRIEF SUMMARY

[0007] Variously disclosed embodiments include methods and computer systems that may be used to facilitate determining a plurality of analysis windows of an IC design for analyzing the IC design.

[0008] According to a first aspect, a computer-implemented method for determining a plurality of analysis windows of an IC design for analyzing the IC design is provided, wherein the IC design may include a plurality of patterns, and wherein the method may include: providing the IC design; determining a plurality of clusters in the IC design, wherein the respective cluster includes similar patterns; and determining the respective analysis window including a configurable number or type of different clusters.

[0009] According to a second aspect, a computer system may be arranged and configured to execute the steps of this computer-implemented method according to the first aspect.

[0010] According to a third aspect, a computer program product may include computer program code that, when executed by the computer system according to the second aspect, causes the computer system to carry out the method according to the first aspect.

[0011] According to a fourth aspect, a computer-readable medium may include the computer program product according to the third aspect. By way of example, the described computer-readable medium may be non-transitory and may further be a software component on a storage device.

[0012] The foregoing has outlined broadly the technical features of the present disclosure so that those skilled in the art may better understand the detailed description that follows.Additional features and advantages of the disclosure are described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiments disclosed as a basis for determining a plurality of analysis windows of an IC design for analyzing the IC design or for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0013] Also, before undertaking the detailed description below, various definitions for certain words and phrases are provided throughout this patent document and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While certain terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.

[0014] Embodiments are described below in greater detail.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Fig. 1 depicts a functional block diagram of example systems that facilitates determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system.

[0016] Figs. 2-3 depict different aspects of example methodologies that facilitate determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system, respectively.

[0017] Figs. 4-6 depict a flow diagram of an example methodology that facilitates determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system, respectively.

[0018] Fig. 7 depicts a block diagram of a data processing system in which an embodiment can be implemented.DETAILED DESCRIPTION

[0019] Various technologies that pertain to systems and methods for determining a plurality of analysis windows of an integrated circuit (IC) design for analyzing the IC design in a product system is now described with reference to the drawings, where like reference numerals represent like elements throughout. The drawings discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope ofthe disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged apparatus. It is to be understood that functionality that is described as being carried out by certain system elements may be performed by multiple elements. Similarly, for instance, an element may be configured to perform functionality that is described as being carried out by multiple elements. The numerous innovative teachings of the present patent document are described with reference to exemplary non-limiting embodiments.

[0020] With reference to Fig. 1, a functional block diagram of an example computer system or data processing system 100 is depicted that facilitates determining a plurality of analysis windows 130 of an integrated circuit (IC) design 120 for analyzing the IC design 120 in a product system 100. The processing system 100 may include an integrated circuit (IC) analysis (ICA) system 118 which may, in certain examples, may include at least one processor 102 that is configured to execute at least one application software component 106 from a memory 104 accessed by the processor 102. The application software component 106 may be configured (i.e., programmed) to cause the processor 102 to carry out various acts and functions described herein. For example, the described application software component 106 may include and / or correspond to one or more components of an application for determining a plurality of analysis windows 130 of an integrated circuit (IC) design 120 for analyzing the IC design 120, wherein the application software component 106 may be configured to generate and store product data in a data store 108 such as a database.

[0021] By way of example, the ICA system 118 may be cloud-based, internet-based and / or be operated by a provider providing support for determining a plurality of analysis windows 130 of an integrated circuit (IC) design 120 for analyzing the IC design 120. In certain examples, the user may be located close to the ICA system 118 or remote to the ICA system 118, e.g., anywhere else, e.g., using a mobile device for connecting to the ICA system 118, e.g., via the internet, wherein the mobile device may include an input device 110 and a display device 112. In certain examples, the ICA system 118 may be installed and run on a user’s device, such as a computer, laptop, pad, on-premises computing facility, or the like.

[0022] Determining a plurality of analysis windows 130 of an integrated circuit (IC) design 120 for analyzing the IC design 120 may be a challenging and time-consuming process that may require highly skilled engineers with years of training. For example, advanced knowledge in electronics, physics, and other scientific domains may be required. A full IC chip may have billions of patterns, and it is needed to choose few locations, e.g., in therange of hundreds or thousands, which can be used within an analysis budget, e.g., the budget of inspection tools or a calibration process. In certain examples, all types of patterns on the IC chip may be taken into consideration to provide quality of the IC chip, accuracy of the inspection results, and accuracy of the calibration process. Hence, a challenge may include, within a limited inspection or calibration budget, to select the lowest number of inspection or calibration locations in a full IC chip with the highest diversity to different patterns to achieve as much as possible full coverage to different types of patterns in the full chip automatically and efficiently. In other words, the challenge may include finding a minimum number of windows to cover as many different patterns as possible.

[0023] According to another approach, a random selection of analysis locations may be done but regularly results in very low coverage to different types of patterns in a full IC chip. Further, according to yet another approach, very experienced experts may select the analysis windows who are fully aware of the design of the IC chip and the patterns included in the full IC chip, and the fabrication process and problematic patterns that can affect the model calibration, the quality of the process, or the yield. Herein, manual selection approach needs very talented and experienced experts who are very rare and expensive and who are subject to human error. In addition, no one will be 100% aware of all types of patterns of all designs across all IC chips. Further, no one will be 100% aware of all problems that can be done by different types of patterns during different fabrication steps. Hence, determining a plurality of analysis windows 130 of an integrated circuit (IC) design 120 for analyzing the IC design 120 may be a long and not efficient process.

[0024] To enable the enhanced determination of a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120, the described product system or processing system 100 may include at least one input device 110 and at least one display device 112 (such as a display screen). The described processor 102 may be configured to generate a graphical user interface (GUI) 114 through the display device 112. Such a GUI 114 may include GUI elements such as buttons, links, search boxes, lists, text boxes, images, or scroll bars usable by a user to provide inputs through the input device 110 that cause determining of a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120. By way of example, the GUI 114 may include an ICA user interface (UI) 116 provided to a user.

[0025] In an example embodiment, a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120 may be determined, wherein the IC design 120 includes a plurality of patterns 122.

[0026] By way of example, an integrated circuit (IC) 152, also known as a microchip, a computer chip, or simply a chip, may be a small electronic device made up of multiple interconnected electronic components such as transistors, resistors, and capacitors. For example, an IC design 120 may include a representation of the IC 152 in terms of planar geometric shapes which correspond to the patterns 120 of metal, oxide, or semiconductor layers that may make up the components of the IC. The IC design can be one for a whole chip or a portion of a full-chip design. In certain examples, the IC design 120 may include a final design of an IC on wafer or its corresponding photomask. In certain examples, the IC design 120 may include the shape or layout of patterns 120 and optionally the interconnected electronic components of the IC 152 which is to be developed or manufactured. Herein, the patterns 120 may correspond to the interconnects, such as metal lines electrically connecting components of the IC 152. In certain examples, the patterns 120 may correspond to conductor paths connecting the electronic components of the IC. By way of example, the mentioned patterns 120 may be realized on a substrate, such as a silicon wafer, using photolithography. Further, patterns 122 may occur at one or more different IC layers of a full stack IC 152 which may include: a metal layer representing the metal interconnects used to route signals and provide electrical connections; a via layer representing the vias, which are vertical connections between different metal layers; a diffusion layer representing the regions where active components like transistors are formed; a poly layer representing the polysilicon regions used to create gates, resistors, and other components; a contact layer representing the contact areas used to connect metal layers to the underlying diffusion and poly layers; a well layer representing the well regions that isolate different components and provide electrical isolation; and other layers in the IC stack which may not yet be covered by the above layers.

[0027] The stack of an IC may include one or more of the above layers, including one or more of one of the above layers.

[0028] The IC design 120 or the corresponding manufactured IC 152 may have a certain geometric size, wherein the respective analysis window 130 may be much smaller than the IC design 120 or the corresponding manufactured IC. 152 Accordingly, the respective analysis window 130 may correspond to a certain part of the IC design 120 or the corresponding manufactured IC 152 which may be analyzed with one or more analysis steps, e.g., using an analysis tool, in certain examples, an inspection with an inspection tool 134 that may have a maximum area of inspection. By way of example, the geometric size of the respective analysis window 130 or of all analysis windows 130 may be limited, e.g., by properties of theanalysis tool, and in further examples, a fixed geometric size of the respective analysis window 130 or of all analysis windows 130 may be used. As mentioned above, finding a minimum number of such analysis windows 130 to cover as many different patterns 122 as possible is desirable, e.g., to analyze or inspect the IC design 120 or the corresponding manufactured IC as good as possible optionally with limited analysis resources.

[0029] By way of example, the application software component 106 and / or the processor 102 may be configured to provide the IC design 120.

[0030] In certain examples, the IC design 120 may be determined by a user or engineer. The IC design 120 may be provided and stored in the data store 108 of the ICA system 118, e.g., by the user using the ICA UI 116 and / or the input device 110. In certain examples, the IC design 120 may be received, e.g., via an application programming interface (API), from another data source 108’.

[0031] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine a plurality of clusters 124 in the IC design 120, wherein the respective cluster 124 includes similar patterns 122.

[0032] The respective cluster 124 may be understood as a virtual pool of all similar patterns 122 as if a label was added to all similar patterns 122 and to label them as being part of a certain cluster 124. In certain examples, the similar patterns 122 of a respective cluster 124 may scattered in the entire IC design 120. Herein, the respective cluster 124 may be much smaller than the IC design 120 and the respective analysis window 130. Further, the respective cluster 124 may include two or more similar patterns 122 so that the respective cluster 124 may be larger than a pattern 122. In certain examples, the respective cluster 124 may be chosen or determined such that exclusively similar patterns 122 are included and accordingly, no differing patterns 122 are included in the respective cluster 124. Below, more details are provided on a similarity of patterns 122 which may relate to similar properties of the patterns 122 which included in the respective cluster 124.

[0033] By way of example, the IC design 120 may be analyzed to identify similar patterns 122. Similar patterns 122 may be assigned to a respective cluster 124. Herein, similar patterns 122 may have similar points of interest.

[0034] By analyzing the IC design 120 to identify similar patterns 122, a plurality of clusters 124 in the IC design 120 may be determined, wherein the different clusters 124 may include a number of similar patterns 122, respectively.

[0035] In further examples, there may be very rare patterns 122 which, e.g., occur in the IC design 120 only once, five, seven, ten, 50, or 100 times or any number that can be chosen. Such very rare patterns 122 may, in certain examples, be neglected when determining the analysis windows 130 which may increase the coverage of the patterns 122 by the clusters 124 and eventually by the plurality of analysis windows 130 significantly.

[0036] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the respective analysis window 130 including a configurable number or type of different clusters 124.

[0037] As mentioned above, the geometric size of the respective analysis window 130 or of all analysis windows 130 may be limited or fixed, e.g., by the user. By way of example, the respective analysis window 130 may be chosen or positioned in the IC design 120 such that the respective analysis window 130 corresponds to a certain part of the IC design 120 which includes the configurable number of different clusters 124 or the configurable type of different clusters 124. By way of example, the center of the respective analysis window 130 may be chosen to be the position of a respective representative pattern 122 of the respective cluster 124. The respective part of the IC design 120 corresponding to the respective analysis windows 130 may hence include a plurality of clusters 124 of the IC design 120. Herein, the respective analysis window 130, e.g., with the highest diversity of covered different patterns 122 or with the highest number of covered patterns 122, may be determined using a suitable configuration of the number or type of different clusters 124. Certain examples of such configurations are explained below.

[0038] By way of example, the determination of the respective analysis window 130 may be done iteratively, e.g., after a first analysis window 130 including the highest diversity of covered different patterns 122 has been determined, a second analysis window 130 may be determined which may include the second highest diversity of covered different patterns 122 or the highest diversity of covered different patterns 122 which are not yet covered by the first analysis window 130. Accordingly, further analysis windows 130 may be determined using the same approach. In further examples, the iterative determination of the respective analysis window 130 may involve determining a first analysis window 130 including the highest number of covered patterns 122, and the determination of a second analysis window 130 including the second highest number of covered patterns 122 which are not yet covered by the first analysis window 130. Again, further analysis windows 130 may be determined using the same approach.

[0039] By way of example, the application software component 106 and / or the processor 102 may further be configured to embed the determined respective analysis window 130 in the IC design 120, e.g., such that the IC design 120 includes information on the determined respective analysis window 130. By way of example, the IC design 120 may then include information on the position and / or size of the determined respective analysis window 130 within the IC design 120. In certain examples, the coordinates of the respective analysis window 130 may be provided as the x- and y-position of the center of the respective analysis window 130 along with the size of the respective analysis window 130 or as the four x- and y-positions of the four corners or edges of the respective analysis window 130. Embedding the determined respective analysis window 130 in the IC design 120 may facilitate executing the analysis of the IC design 120, the corresponding wafer or mask by the analysis tool 134 or the corresponding IC manufacturing machine 150. This facilitation may be achieved through transmitting the IC design 120 including information on the determined respective analysis window 130 to the analysis tool 134 or the corresponding IC manufacturing machine 150 in one file and by avoiding a later merge of the information on the determined respective analysis window 130 into the IC design 120, e.g., by the analysis tool 134 or the corresponding IC manufacturing machine 150, which may be an error-prone process, e.g., resulting in erroneous off-sets or misalignments of the determined respective analysis window 130 with respect to the IC design 120.

[0040] The determined respective analysis window 130 optionally as part of the IC design 120 may further be stored in the data store 108. The application software component 106 and / or the processor 102 may, in certain examples, further be configured to output the determined respective analysis window 130, optionally as part of the IC design 120, to a user, e.g., by displaying the determined respective analysis window 130 to the user via the ICA UI 116. In further examples, the application software component 106 and / or the processor 102 may further be configured to transmit the determined respective analysis window 130, optionally as part of the IC design 120, to an analysis tool 134 and / or an IC manufacturing machine 150.

[0041] In further examples, the configurable number of different clusters 124 may correspond to the largest number of different clusters 124 included in the respective analysis window 130. In certain examples, the configurable type of different clusters 124 may correspond to the respective cluster 124 including a small number, a medium number, or a large number of patterns 122.

[0042] As explained above, the respective cluster 124 may include or exclusively include similar patterns 122. By way of example, the position of the respective analysis window 130 may be chosen such that the part of the IC design 120 covered by the respective analysis window 130 covers as many different patterns 122 as possible. Accordingly, the respective analysis window 130 may cover as many different clusters 124 as possible. In this manner, the respective analysis window 130 with the highest diversity of covered different patterns 122 may be determined. Therefore, considering the largest number of different clusters 124 may contribute to smartly and efficiently determine the locations of the analysis windows 130, e.g., to cover all types of different patterns 122 in the chip, e.g., within a limited analysis, inspection, or calibration budget.

[0043] Herein, the largest number of different clusters 124 may be determined by checking different potential positions of the respective analysis window 130 and determining the corresponding number of different clusters 124 included in the respective, checked analysis window 130. The respective, checked analysis window 130 may be selected that includes the largest number of different clusters 124. If a plurality of analysis windows 130 is determined iteratively, the next analysis window 130 may be determined which may include the next highest diversity of covered different clusters 124 or the highest diversity of covered different clusters 124 which are not yet covered by the first analysis window 130.

[0044] In further examples, the position of the respective analysis window 130 may be chosen such that the part of the IC design 120 covered by the respective analysis window 130 covers a small number, a medium number, or a large number of patterns 122. Herein, depending on the IC design 120 or the application of the corresponding IC 152, the small, medium, or large number of patterns 122 covered by the respective cluster 124 may have advantages. For example, depending on the IC design 120 or the application of the corresponding IC 152, the respective analysis window 130 may cover clusters 124 that cover as many patterns 122 as possible by using the small, medium, or large number of patterns 122. In certain examples, the small number of covered patterns 122 may lead to a large diversity of the covered patterns 122. The present example of covering a different number of patterns 122 per cluster 124 may also contribute to smartly and efficiently determine the locations of the analysis windows 130, e.g., to cover as many patterns 122 as possible in the chip, e.g., within a limited analysis, inspection, or calibration budget.

[0045] Herein, the largest number of covered patterns 122 may be determined by checking different potential positions of the respective analysis window 130 and determiningthe corresponding number of covered patterns 122 included in the respective, checked analysis window 130. The respective, checked analysis window 130 may be selected that includes the largest number of covered patterns 122. If a plurality of analysis windows 130 is determined iteratively, the next analysis window 130 may be determined which may include the next highest number covered patterns 122 or the next highest number covered patterns 122, which are not yet covered by the first analysis window 130.

[0046] In certain examples, the determination of the respective analysis window 130 may be performed using a combination of the two approaches of considering the largest number of covered different clusters 124 and the largest number of covered patterns 122. By way of example, a weighting factor may be used to reconcile the diverging approaches favoring the largest number either of covered different clusters 124 or of covered patterns 122.

[0047] In certain examples, the application software component 106 and / or the processor 102 may further be configured to determine the number of occurrences of the respective pattern 122 in the respective cluster 124; and to determine a representative pattern 122 among the patterns 122 of a representative cluster 124 among the clusters 124 as the center of the respective analysis window 130, wherein the respective representative pattern 122 has a configurable number of occurrences in the respective cluster 124.

[0048] The respective cluster 124 may include or exclusively include similar patterns 122, wherein the number of occurrences of the similar patterns 122 in the respective cluster 124 may be determined. Additionally, or alternatively, the number of occurrences of the respective pattern 122 in the complete IC design 120 may be determined. For both variants, low-frequency, medium -frequency, and high-frequency clusters 124 may be determined that have a small, medium, and high number of occurrences of the similar patterns 122, respectively. Herein, the small, medium, and high number of occurrences may correspond to the above-mentioned, configurable number of occurrences. Depending on the configured number of occurrences, there may be a specific representative pattern 122 which matches the configurable number of occurrences in the respective cluster 124, and correspondingly that may be a specific representative cluster 124 which includes the mentioned representative pattern 122. By way of example, if there the respective representative cluster 124 includes two or more similar patterns 122, an arbitrary selection of one of these similar patterns 122 may be done to identify the respective representative pattern 122 of the respective representative cluster 124.

[0049] The center and hence the position of the respective analysis window 130 may, in certain examples, be determined by identifying the position of the representative pattern 122 as the center of the respective analysis window 130.

[0050] In certain examples, selecting a low-frequency pattern 122 may lead to a positioning of the respective analysis window 130 covering a comparably large number of different clusters 124, e.g., since in the vicinity of comparatively rare patterns 122, more frequently occurring or high-frequency patterns 122 may be arranged in the IC design 120 so that a reasonable mix of rare patterns 122 and frequently occurring patterns 122 may be covered by the respective analysis window 130.

[0051] In further examples, selecting a high-frequency pattern 122 may leads to a positioning of the respective analysis window covering a comparably large number of similar clusters 124. And by way of example, selecting a medium-frequency pattern 122 may be an approximate implementation of the above-mentioned combination of considering the largest number of covered different clusters 124 and the largest number of covered patterns 122.

[0052] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the number of occurrences of different representative patterns 122 within the respective analysis window 130; and to discard the respective analysis window 130 if the number of occurrences of different representative patterns 122 within the respective analysis window 130 is smaller than a configurable number.

[0053] In certain examples, a considered analysis window 130 may cover one or more different representative patterns 122, wherein the respective representative pattern 122 matches the configurable number of occurrences in the respective cluster 124 or in the IC design 120. Discarding the respective analysis window 130 if the number of occurrences of different representative patterns 122 within the respective analysis window 130 is smaller than a configurable number may contribute to speed up the process of determining the respective analysis window 130. E.g., in an iterative process, those analysis windows 130 may be favored and selected in one process step which cover more than one respective representative pattern 122 and hence cover comparably diverse patterns 122.

[0054] In certain examples, determining the respective analysis window 130 includes dividing the IC design 120 into a plurality of areas 132 of the size of respective the analysis window 130, wherein the application software component 106 and / or the processor 102 may further be configured to determine the number of occurrences of different clusters 124 withinthe respective area 132; and to identify the respective area 132 as the respective analysis window 130 if the respective area 132 includes a configurable number of different clusters 124.

[0055] Dividing the IC design 120 into a plurality of areas 132 of the size of respective the analysis window 130 may be done for IC designs 120 with a rectangular shape by segmenting the two axes that span the rectangle into segments, e.g., a number x of segments on the x-axis and a number y of segments on the y-axis of the rectangle. The IC design 120 may then be divided into x*y areas 132. Similar approaches may be used for IC designs 120 of other geometric shapes, such as circular, squared, etc. shape.

[0056] Herein, the size of the areas 132 and hence the granularity of the segmentation of the IC design 120 may be determined by the size of the analysis window 130 since the size and shape of the respective area 132 may be equal or at least approximately equal to the size and shape of the analysis window 130.

[0057] For each of the areas 132, the number of occurrences of different clusters 124 may be determined. In this manner, the respective area 132, e.g., with the highest diversity of covered different patterns 122 or different clusters 124 may be determined. The respective analysis window 130 may be selected to be the area 132 which includes the configurable number of different clusters 124, e.g., the highest number of different clusters 124 or a number that is greater than a preconfigurable threshold. Hence, using the areas 132 and the configurable number of different clusters 124 in the respective area 132 to determine the respective analysis window 130 may contribute to smartly and efficiently determine the locations of the analysis windows 130, e.g., to cover all types of different patterns 122 in the chip, e.g., within a limited analysis, inspection, or calibration budget.

[0058] By way of example, in an iterative process, those areas 132 may be selected to be the respective analysis window 130 in one process step which cover at least the configurable number of different clusters 124 and hence cover comparably diverse patterns 122 which may speed up the determination of the respective analysis window 130.

[0059] By way of example, the application software component 106 and / or the processor 102 may further be configured to determine the number of different patterns 122 or clusters 124 included in the determined analysis windows 130; and stop determining the analysis windows 130 if all different patterns or clusters 124 of the IC design 120 are included in the determined analysis windows 130 or if a threshold with respect to the number of windows 130 is reached.

[0060] Herein, the clusters 124 may be considered to be different if the clusters 124 include different patterns 122. The determination of the analysis windows 130 may be done iteratively, e.g., using one of the above-mentioned approaches. The iteration may be stopped, e.g., if a threshold with respect to the number of analysis windows 130 is reached, wherein the threshold may reflect a certain limited analysis, inspection, or calibration budget. In certain examples, the iteration may be stopped if all different patterns or clusters 124 of the IC design 120 are included in the determined analysis windows 130. In both examples, the suggested method may be superior to other approaches since the suggested method may cover more of the relevant patterns 122 or clusters 124 or may require less analysis windows 130 than other approaches. Further, the suggested method may require less computation resources, such as processing or memory resources, than other approaches.

[0061] In certain examples, the size of the respective analysis window 130 is configurable by the user. In further examples, the size of the respective analysis window 130 may depend on the type of analysis, such as model calibration or inspection, e.g., different models used for calibration or different tools used for inspection.

[0062] By way of example, the similar patterns 122 of the respective cluster 124 may have similar geometrical properties, similar optical properties, similar electric properties, similar IC manufacturing processes parameters, or any combination of thereof.

[0063] The similarity of the patterns 122 which may be a criterion for the clustering of patterns 122 may, in certain examples, depend on IC manufacturing processes parameters related to the respective pattern 122, such as a lithography parameters, such as exposure parameters, resist parameters, optical parameters, mask parameters, wafer parameters, e.g., including imaging intensity or frequency, exposure times, an exposure dose, the photoresist, etc... The IC manufacturing processes parameters may further relate to parameters of different steps of IC the manufacturing process such as etching, deposition, diffusion, annealing and thermal processes, stress, etc., e.g., including an etching time, a deposition or a doping processes to manufacture the respective pattern 122, temperatures like a bake temperature. Further, electrical parameters or properties may be considered, e.g., to cluster patterns based on their electrical behavior. Further, any other parameters related to the design, or IC fabrication process may be considered to identify similar patterns 122.

[0064] Further, the similarity of the patterns 122 may depend on geometrical properties of the respective pattern 122, e.g., the shape of electric conductors or vias included by the respective pattern 122, e.g., perpendicular conductors, the length of conductors, etc. Thesimilarity of the patterns 122 may depend on electric properties of the patterns 122, e.g., an electrical resistance, electric inductance, electric capacitance, or a delay, gain, noise, IR-drop, and / or skew relating to the patterns 122. Further, the similarity of the patterns 122 may depend on optical properties, e.g., relating to the photolithography process, such as printability or manufacturability of the respective pattern, e.g., parameters relating to resolution enhancement techniques available for the respective pattern 122, such as optical proximity correction, sub-resolution assist features, source mask optimization, and / or multipatterning. Herein, the above-mentioned criteria for the similarity of the patterns 122 may, in certain examples, combined.

[0065] In further examples, the above-mentioned criteria for the similarity of the patterns 122 may be tuned, e.g., such that trade-off between similarity and the determined number of clusters 124 may be achieved. Tuning the clustering may avoid too many but highly specific clusters 124 on the one hand and too few but coarse clusters 124 on the other hand.

[0066] By way of example, clustering the IC design 120, i.e., determining clusters 124 of similar patterns 122, may be done using unsupervised clustering techniques.

[0067] In certain examples, analyzing the IC design 120 includes calibrating a model using the respective analysis windows 130, wherein the model characterizes at least one manufacturing step of the IC.

[0068] By way of example, the model may be used in imaging, e.g., for photolithography, or for the transfer of the IC design 120 from the mask to the wafer. The model may be extended to any process model relating to a manufacturing step of the IC, e.g., etching, deposition, diffusion, doping processes, or annealing or thermal processes. In certain examples, the model may include chemical-mechanical polishing (CMP) models, stress models, design rule check (DRC) models, electromigration models, electrical models, interconnect models, thermal models, etc. relating to the manufacturing of the IC.

[0069] The model calibration may aim to cover all different patterns 122 within the IC chip for a high accuracy to the models. Additionally, according to one aspect, a goal is to choose the respective analysis window 130 such that as many as possible of different patters 122 are covered, wherein all different patters 122 may be covered by the analysis windows 130.

[0070] The model may include the above-mentioned IC manufacturing processes parameters, such as the explained lithography parameters, process parameters, or theelectrical parameters. Further, the model may include parameters relating to optical proximity correction, sub-resolution assist features, source mask optimization, and / or multi-patterning.

[0071] Herein, the above-mentioned parameters of the model may, in certain examples, combined, e.g., using a preconfigurable logic linking the parameters and optionally weighting the model parameters and hence the model. For a high-quality IC fabrication and hence to get high-quality ICs, the mentioned parameters of the model may be tuned. In certain examples, a short time to calibrate the parameters of the model may be desirable.

[0072] By way of example, input data for the respective model parameter may be obtained from the IC manufacturing process, e.g., sensor data from the wafer or from the mask, wherein this input data may then be used to calibrate the model parameters or refine the current calibration of the model parameters. The mentioned input data may be obtained from the wafer or from the mask using the mentioned analysis windows 130.

[0073] By way of example, analyzing the IC design 120 includes inspecting a lithography mask or a wafer manufactured according to the IC design 120 with an inspection tool 134 using the respective analysis window 130.

[0074] The inspection tool 134 may include a scanning electron microscope (SEM) which is a type of electron microscope that produces images of a sample by scanning the surface with a focused beam of electrons. The electrons interact with atoms in the sample, producing various signals that contain information about the surface topography and composition of the sample. The electron beam is scanned in a raster scan pattern, and the position of the beam is combined with the intensity of the detected signal to produce an image. In further examples, the inspection tool 134 may include an optical microscope, also referred to as a light microscope, which is a type of microscope that commonly uses visible light and a system of lenses to generate magnified images of small objects. Further, by way of example, the inspection tool 134 may include a transmission electron microscope (TEM) using a microscopy technique in which a beam of electrons is transmitted through a specimen to form an image. The specimen is most often an ultrathin section less than 100 nm thick or a suspension on a grid. An image is formed from the interaction of the electrons with the sample as the beam is transmitted through the specimen. The image is then magnified and focused onto an imaging device, such as a fluorescent screen, a layer of photographic film, or a detector such as a scintillator attached to a charge-coupled device or a direct electron detector. In yet further examples, the inspection tool 134 may include scanning capacitance microscope (SCM) which may use a narrow probe electrode which is positioned in contact orclose proximity of a sample's surface and scanned, wherein in the present context, the sample maybe the wafer, e.g., of an IC 152 manufactured or printed according to the IC design 120, and wherein the respective analysis window 130 of the wafer is scanned and hence inspected. Herein, scanning capacitance microscopy may characterize the surface of the sample using information obtained from the change in electrostatic capacitance between the surface and the probe. In certain examples, other inspection methods and corresponding inspection tools 134 may be used, e.g., for optical inspection of the respective analysis window 130 of a lithography mask or of a wafer manufactured according to the IC design 120, etc.

[0075] By way of example, the mentioned inspection may be used on regular basis to inspect the wafer or the mask from time to time to check the quality of IC fabrication process, or to control and monitor the IC fabrication process.

[0076] Further analysis methods may include model validation and verification, process calibration and optimization, defect detection, chip / mask quality assurance, process monitoring, which results in enhancing the IC manufacturing yield, decreasing TAT (turnaround time) of the IC fabrication process, and reducing the IC fabrication process cost.

[0077] In further examples, the application software component 106 and / or the processor 102 may further be configured to transmit the IC design 120 to an IC manufacturing machine 150, and optionally to cause the IC manufacturing machine 150 to manufacture one or more ICs 152 according to the transmitted, IC layout 120.

[0078] In certain examples, the transmission of the IC layout 120 to an IC manufacturing machine 150 and optionally, the manufacture of the one or more ICs 152 by the IC manufacturing machine 150 may only be done or triggered after the above-mentioned analysis which uses the determined respective analysis window 130, e.g., if analyzing the IC design has successfully been completed, e.g., the above-mentioned model has successfully been calibrated using the respective analysis window 130 and / or the respective analysis window 130 of a lithography mask or of a wafer manufactured according to the IC design 120 has successfully been inspected with an inspection tool 134.

[0079] By way of example, the application software component 106 and / or the processor 102 may further be configured to cause the IC manufacturing machine 150 to manufacture one or more ICs according to the transmitted IC design 120.

[0080] The application software component 106 and / or the processor 102 may carry out an analogous method of determining of a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120. Also, the explained examples may be combined toobtain a more detailed method of determining of a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120. Further, a computer-readable medium 160 which may include a computer program product 162 is shown in Fig. 1, wherein the computer program product 162 may be encoded with executable instructions, that when executed, cause the computer system 100 or and / or the ICA system 118 to carry out the described method.

[0081] The advantages of the suggested method may include the option of automating the determination of a plurality of analysis windows 130 of an IC design 120. Contrary to other approaches which may rely on a random selection, or a manual selection based on human experience of the analysis windows 130, the suggested method allows for selecting or determining the locations of the analysis windows 130 automatically. Further, the suggested method may smartly and efficiently determine the locations of the analysis windows 130, e.g., to cover all types of patterns 122 in the chip, e.g., within a limited analysis, inspection, or calibration budget. Random and manual selection cannot do that. In addition, in certain examples, the suggested method may detect all types of defects in the wafer, whereas manual or random selection of the analysis windows 130 can miss many defects. Among the benefits of the suggested method may further be that it is an automatic solution with no need of human experts to select the locations of the analysis windows 130.

[0082] By way of example, the suggested method may furthermore cover all types of patterns 122 in the chip from the first round that will reduce turnaround time (“TAT”). For example, model calibration can take into consideration all types of patterns 122 from the first round, which means having a good model and good manufacturing of patterns 122 on the wafer from the first round. There is no need to re-calibrate the models and doing inspections multiple times to get models with high quality. In certain examples, the suggested method may find the lowest number of locations of the analysis windows 130 to cover the highest number of different patterns 122. The suggested method may, in certain examples, cover all types of patterns 122 within number of locations less than an analysis or inspection budget and save inspection time and cost. In further examples, the suggested method may be used in regular basis to inspect the wafer or mask from time to time to check quality of the IC fabrication process, or to control and monitor the IC fabrication process. Therefore, the suggested method may enhance the production yield and reduce costs. By way of example, a corresponding model calibration and verification to all types of patterns 122 may guarantee a good fabrication of different patterns 122 on the wafer and enhance yield. The suggested method may further be used for early defect detection: By covering all types of patterns 122in an analysis or inspection process, problematic patterns 122 may be detected and may be avoided or fixed in the IC fabrication process to enhance the production yield. In certain respects, the simplicity and smartness of the suggested method may be to find the best locations to be used in the analysis, inspection, or calibration process instead of scanning all locations in the full chip to find the best location which consumes huge runtime and memory.

[0083] Fig. 2 depicts a second aspect of another example methodology that facilitates determining a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120 in a product system.

[0084] The illustrated IC design 120 includes a plurality of patterns 122 which are indicated in Fig. 2 using lines, dots, and boxes. A plurality of clusters 124 in the IC design 120 may be determined, wherein the respective cluster 124 includes similar patterns 122. Further, the number of occurrences of the respective pattern 122 in the respective cluster 124 may be determined. A representative pattern 122 among the patterns 122 of a representative cluster 124 may be determined among the clusters 124 may be determined as the center of the respective analysis window 130, wherein the respective representative pattern 122 has a configurable number of occurrences in the respective cluster 124. In Fig. 2, the respective representative cluster 124 is indicated with a box with a dashed line, wherein the respective representative cluster 124 is the center of the respective analysis window 130.

[0085] In certain examples, the number of occurrences of different representative patterns 122 within the respective analysis window 130 may be determined, wherein the respective analysis window 130 may be discarded if the number of occurrences of different representative patterns 122 within the respective analysis window 130 is smaller than a configurable number.

[0086] Fig. 3 depicts a depicts a third aspect of yet another example methodology that facilitates determining a plurality of analysis windows 130 of an IC design 120 for analyzing the IC design 120 in a product system.

[0087] Similarly to Fig. 2, the illustrated IC design 120 includes a plurality of patterns 122 which are indicated in Fig. 3 using lines, dots, and boxes. The IC design 120 is divided into a plurality of areas 132 of the size of the respective analysis window 130, wherein the areas 132 have the shape of a rectangle. Herein, the division of the IC design 120 into the areas 132 in Fig. 3 is for illustration purposes only. In real IC designs, there could be thousands of areas 132 in the x-direction and thousands of areas 132 in the y-direction resulting in millions of areas 132 into which the IC design may be divided. It is understoodthat the number of the analysis windows may depend on the layout size and the window size. The number of occurrences of different clusters 124 within the respective area 132 may be determined, wherein the respective area 132 is identified as the respective analysis window 130 if the respective area 132 includes a configurable number of different clusters 124.

[0088] These acts may include an act M04 of providing the IC design; an act M06 of determining a plurality of clusters in the IC design, wherein the respective cluster includes similar patterns; and an act M08 of determining the respective analysis window including a configurable number or type of different clusters. At MIO the methodology may end.

[0089] It should further be appreciated that the methodology Ml may include other acts and features discussed previously with respect to the computer-implemented method of determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system.

[0090] Fig. 5 depicts a flow diagram of a further example methodology M2 that facilitates determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system. The method may start at M02, and the methodology M2 may include several acts carried out through operation of at least one processor. Herein, the IC design may include a plurality of patterns.

[0091] These acts may include an act M04 of unsupervised clustering of the patterns in the IC design or of patterns that need to be covered in an analysis, such as inspection, model calibration, etc.; an act M06 of calculating the frequency of the cluster which is the number of occurrences of the patterns in the respective cluster; an act M08 of choosing a representative of “x” clusters with the lowest frequency, wherein alternatively a medium or the highest frequency could be chosen based on a user preference or an application; an act M10 of finding patterns from other clusters within analysis window to this “x” clusters; an act M12 of calculating the total number of covered and uncovered clusters; an act M14 of getting uncovered clusters; an act M16 of checking if the analysis budget has been reached or if all clusters are covered; if the answer is “Yes”, the methodology M2 may end at Ml 8, and if the answer is “No” repeating acts M08 to M16 with uncovered clusters so that the clusters that will be proceed at this point are the one which are not covered yet.

[0092] By way of example, “x” clusters may mean the number of clusters that may be processed in parallel. In other words, the representative of 1 cluster may be chosen, or alternatively, the representatives of 2, 10, 100, or 1000 or any other number of clusters may be chosen and be processed in parallel. Herein, the number of chosen clusters may bedetermined by the user based on the user’s preference. Usually, few clusters to be proceed per iteration may result in longer run time and higher coverage within a smaller number of windows.

[0093] Fig. 6 depicts a flow diagram of a further example methodology M3 that facilitates determining a plurality of analysis windows of an IC design for analyzing the IC design in a product system. The method may start at M02, and the methodology M3 may include several acts carried out through operation of at least one processor. Herein, the IC design may include a plurality of patterns.

[0094] These acts may include an act M04 of unsupervised clustering of the patterns in the IC design or of patterns that need to be covered in an analysis, such as inspection, model calibration, etc.; an act M06 of dividing the IC design 120 into areas; an act M08 of finding the area(s) with the highest number of different patterns; an act M10 of calculating the total number of covered and uncovered clusters; an act M12 of getting uncovered clusters; an act M14 of checking if the analysis budget has been reached or if all clusters are covered; if the answer is “Yes”, the methodology M3 may end at M16, and if the answer is “No” repeating acts M08 to M14 with uncovered clusters so that the clusters that will be proceed at this point are the one which are not covered yet. In certain examples, the user may determine how many areas are to be processed in parallel. Herein, the number of chosen areas may be determined by the user based on the user’s preference. Usually, few areas to be proceed per iteration may result in longer run time and higher coverage within a smaller number of windows.

[0095] Further, the methodology Ml, M2, and M3 or individual steps thereof may be combined to include the above-described acts.

[0096] Fig. 7 depicts a block diagram of a data processing system 1000 (also referred to as a computer system) in which an embodiment can be implemented, for example, as a portion of a product system, and / or other system operatively configured by software or otherwise to perform the processes as described herein. The data processing system 1000 may comprise, for example, the computer or IT system or data processing system 100 mentioned above. The data processing system depicted comprises at least one processor 1002 (e.g., a CPU) that may be connected to one or more bridges / controllers / buses 1004 (e.g., a north bridge, a south bridge). One of the buses 1004, for example, may comprise one or more VO buses such as a PCI Express bus. Also connected to various buses in the depicted example may comprise a main memory 1006 (RAM) and a graphics controller 1008. The graphics controller 1008 may be connected to one or more display devices 1010. It should also benoted that in certain embodiments one or more controllers (e.g., graphics, south bridge) may be integrated with the CPU (on the same chip or die). Examples of CPU architectures comprise IA-32, x86-64, and ARM processor architectures.

[0097] Other peripherals connected to one or more buses may comprise communication controllers 1012 (Ethernet controllers, WiFi controllers, cellular controllers) operative to connect to a local area network (LAN), Wide Area Network (WAN), a cellular network, and / or other wired or wireless networks 1014 or communication equipment.

[0098] Further components connected to various busses may comprise one or more EO controllers 1016 such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (connected to speakers and / or microphones). It should also be appreciated that various peripherals may be connected to the EO controlled s) (via various ports and connections) comprising input devices 1018 (e.g., keyboard, mouse, pointer, touch screen, touch pad, drawing tablet, trackball, buttons, keypad, game controller, gamepad, camera, microphone, scanners, motion sensing devices that capture motion gestures), output devices 1020 (e.g., printers, speakers) or any other type of device that is operative to provide inputs to or receive outputs from the data processing system. Also, many devices referred to as input devices or output devices may both provide inputs and receive outputs of communications with the data processing system. For example, the processor 1002 may be integrated into a housing (such as a tablet) that comprises a touch screen that serves as both an input and display device. Further, certain input devices (such as a laptop) may comprise a plurality of different types of input devices (e.g., touch screen, touch pad, keyboard). Also, other peripheral hardware 1022 connected to the I / O controllers 1016 may comprise any type of device, machine, or component that is configured to communicate with a data processing system.

[0099] Additional components connected to various busses may comprise one or more storage controllers 1024 (e.g., SATA). A storage controller may be connected to a storage device 1026 such as one or more storage drives and / or any associated removable media, which can be any suitable non-transitory machine usable or machine-readable storage medium. Examples comprise nonvolatile devices, volatile devices, read only devices, writable devices, ROMs, EPROMs, magnetic tape storage, floppy disk drives, hard disk drives, solid-state drives (SSDs), flash memory, optical disk drives (CDs, DVDs, Blu-ray), and other known optical, electrical, or magnetic storage devices drives and / or computermedia. Also, in certain examples, a storage device such as an SSD may be connected directly to an I / O bus 1004 such as a PCI Express bus.

[0100] A data processing system in accordance with an embodiment of the present disclosure may comprise an operating system 1028, software / firmware 1030, and data stores 1032 (that may be stored on a storage device 1026 and / or the memory 1006). Such an operating system may employ a command line interface (CLI) shell and / or a graphical user interface (GUI) shell. The GUI shell permits multiple display windows to be presented in the graphical user interface simultaneously, with each display window providing an interface to a different application or to a different instance of the same application. A cursor or pointer in the graphical user interface may be manipulated by a user through a pointing device such as a mouse or touch screen. The position of the cursor / pointer may be changed and / or an event, such as clicking a mouse button or touching a touch screen, may be generated to actuate a desired response. Examples of operating systems that may be used in a data processing system may comprise Microsoft Windows™, Linux™, UNIX™, iOS™, and Android™ operating systems. Also, examples of data stores comprise data files, data tables, relational database (e.g., Oracle™, Microsoft SQL™ Server), database servers, or any other structure and / or device that is capable of storing data, which is retrievable by a processor.

[0101] The communication controllers 1012 may be connected to the network 1014 (not a part of data processing system 1000), which can be any public or private data processing system network or combination of networks, as known to those of skill in the art, comprising the Internet. Data processing system 1000 can communicate over the network 1014 with one or more other data processing systems such as a server 1034 (also not part of the data processing system 1000). However, an alternative data processing system may correspond to a plurality of data processing systems implemented as part of a distributed system in which processors associated with several data processing systems may be in communication by way of one or more network connections and may collectively perform tasks described as being performed by a single data processing system. Thus, it is to be understood that when referring to a data processing system, such a system may be implemented across several data processing systems organized in a distributed system in communication with each other via a network.

[0102] Further, the term “controller” means any device, system, or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware,software, or some combination of at least two of the same. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.

[0103] In addition, data processing systems may be implemented as virtual machines in a virtual machine architecture or cloud environment. For example, the processor 1002 and associated components may correspond to a virtual machine executing in a virtual machine environment of one or more servers. Examples of virtual machine architectures comprise VMware ESCi, Microsoft Hyper- V, Xen, and KVM.

[0104] Those of ordinary skill in the art will appreciate that the hardware depicted for the data processing system may vary for particular implementations. For example, the data processing system 1000 in this example may correspond to a computer, workstation, server, PC, notebook computer, tablet, mobile phone, and / or any other type of apparatus / system that is operative to process data and carry out functionality and features described herein associated with the operation of a data processing system, computer, processor, and / or a controller discussed herein. The depicted example is provided for the purpose of explanation only and is not meant to imply architectural limitations with respect to the present disclosure.

[0105] Also, the processor described herein may be located in a server that is remote from the display and input devices described herein. In such an example, the described display device and input device may be comprised in a client device that communicates with the server (and / or a virtual machine executing on the server) through a wired or wireless network (which may comprise the Internet). In some embodiments, such a client device, for example, may execute a remote desktop application or may correspond to a portal device that carries out a remote desktop protocol with the server in order to send inputs from an input device to the server and receive visual information from the server to display through a display device. Examples of such remote desktop protocols comprise Teradici's PCoIP, Microsoft's RDP, and the RFB protocol. In such examples, the processor described herein may correspond to a virtual processor of a virtual machine executing in a physical processor of the server.

[0106] As used herein, the terms “component” and “system” are intended to encompass hardware, software, or a combination of hardware and software. Thus, for example, a system or component may be a process, a process executing on a processor, or a processor.Additionally, a component or system may be localized on a single device or distributed across several devices.

[0107] Also, as used herein a processor corresponds to any electronic device that is configured via hardware circuits, software, and / or firmware to process data. For example, processors described herein may correspond to one or more (or a combination) of a microprocessor, CPU, FPGA, ASIC, or any other integrated circuit (IC) or other type of circuit that is capable of processing data in a data processing system, which may have the form of a controller board, computer, server, mobile phone, and / or any other type of electronic device.

[0108] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of data processing system 1000 may conform to any of the various current implementations and practices known in the art.

[0109] Also, the words or phrases used herein should be construed broadly, unless expressly limited in certain examples. For example, the terms “comprise” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The singular forms “a,” “an,” and “the” are intended to comprise the plural forms as well, unless the context clearly indicates otherwise. Further, the term “and / or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term “or” is inclusive, meaning and / or, unless the context clearly indicates otherwise. The phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to comprise, be comprised within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.

[0110] Also, although the terms “first,” “second,” “third,” and so forth may be used herein to describe various elements, functions, or acts, these elements, functions, or acts should not be limited by these terms. These numeral adjectives are used to distinguish different elements, functions or acts from each other. For example, a first element, function, or act could be termed a second element, function, or act, and, similarly, a second element, function, or act could be termed a first element, function, or act, without departing from the scope of the present disclosure.

[0111] In addition, phrases such as “processor is configured to” carry out one or more functions or processes, may mean the processor is operatively configured to or operably configured to carry out the functions or processes via software, firmware, and / or wired circuits. For example, a processor that is configured to carry out a function / process may correspond to a processor that is executing the software / firmware, which is programmed to cause the processor to carry out the function / process and / or may correspond to a processor that has the software / firmware in a memory or storage device that is available to be executed by the processor to carry out the function / process. It should also be noted that a processor that is “configured to” carry out one or more functions or processes, may also correspond to a processor circuit particularly fabricated or “wired” to carry out the functions or processes (e.g., an ASIC or FPGA design). Further the phrase “at least one” before an element (e.g., a processor) that is configured to carry out more than one function may correspond to one or more elements (e.g., processors) that each carry out the functions and may also correspond to two or more of the elements (e.g., processors) that respectively carry out different ones of the one or more different functions.

[0112] In addition, the term “adjacent to” may mean that an element is near to but not in contact with a further element or that the element is in contact with the further portion, unless the context clearly indicates otherwise.

[0113] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0114] None of the description in the present patent document should be read as implying that any particular element, step, act, or function is an essential element, which must be included in the claim scope. The scope of patented subject matter is defined only by the allowed claims.

Claims

CLAIMS1. A computer-implemented method for determining a plurality of analysis windows of an integrated circuit (IC) design for analyzing the IC design, wherein the IC design comprises a plurality of patterns, the method comprising:providing the IC design;determining a plurality of clusters in the IC design, wherein a respective cluster comprises similar patterns; anddetermining a respective analysis window comprising a configurable number or type of different clusters of the plurality of clusters.

2. The computer-implemented method of claim 1, further comprising: embedding the determined respective analysis window in the IC design.

3. The computer-implemented method of claim 1 or 2, wherein the configurable number of different clusters corresponds to a largest number of different clusters included in the respective analysis window, and / orwherein the configurable type of different clusters corresponds to the respective cluster comprising a small number, a medium number, or a large number of similar patterns.

4. The computer-implemented method of one of the preceding claims, further comprising:determining a number of occurrences of the respective pattern in the respective cluster; anddetermining a representative pattern among the patterns of a representative cluster among the clusters as a center of the respective analysis window,wherein the respective representative pattern has a configurable number of occurrences in the respective cluster.

5. The computer-implemented method of claim 4, further comprising: determining a number of occurrences of different representative patterns within the respective analysis window; anddiscarding the respective analysis window when the number of occurrences of the different representative patterns within the respective analysis window is smaller than a configurable number.

6. The computer-implemented method of one of claims 1 to 3, wherein the determining of the respective analysis window comprises dividing the IC design into a plurality of areas of a size of respective the analysis window, andwherein the method further comprises:determining a number of occurrences of different clusters within the respective area; andidentifying the respective area as the respective analysis window when the respective area comprises a configurable number of different clusters.

7. The computer-implemented method of one of the preceding claims, further comprising:determining a number of different patterns or clusters included in the determined analysis windows; andstopping determining the analysis windows when all different patterns or clusters of the IC design are included in the determined analysis windows or when a threshold with respect to the number of windows is reached.

8. The computer-implemented method of one of the preceding claims, wherein the similar patterns of the respective cluster have similar geometrical properties, similar optical properties, similar electric properties, similar IC manufacturing processes parameters, or any combination thereof.

9. The computer-implemented method of one of the preceding claims, further comprising:calibrating a model using the respective analysis window, andwherein the model characterizes at least one manufacturing step of the IC.

10. The computer-implemented method of one of the preceding claims, further comprising:inspecting a lithography mask or a wafer manufactured according to the IC design with an inspection tool using the respective analysis window.

11. The computer-implemented method of one of the preceding claims, further comprising:transmitting the IC design to an IC manufacturing machine.

12. The computer-implemented method of claim 11, further comprising: causing the IC manufacturing machine to manufacture one or more ICs according to the transmitted IC design.

13. A computer system arranged and configured to execute the steps of the computer-implemented method of one of the preceding claims.

14. A computer program product, including computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of claims 1 to 12.

15. A computer-readable medium comprising a computer program product including computer program code that, when executed by a computer system, causes the computer system to carry out the method of one of claims 1 to 12.

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