Efficient initial credit exchange for source-synchronous links
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- GOOGLE LLC
- Filing Date
- 2025-02-03
- Publication Date
- 2026-08-06
Smart Images
Figure US2025014339_06082026_PF_FP_ABST
Abstract
Description
EFFICIENT INITIAL CREDIT EXCHANGE FOR SOURCE-SYNCHRONOUS LINKSBACKGROUND
[0001] With shrinking device geometries, silicon designers can implement more-complex device structures and systems. A System-on-Chip (SoC) can have multiple subsystems that operate on different power and / or clock domains. As SoCs grow larger, communication latency between subsystems can increase, leading to the use of source-synchronous links for communications between subsystems. Credit exchanges are used to manage communications source-synchronous links; however, there are opportunities to improve the initialization of source-synchronous links in SoCs.SUMMARY
[0002] In aspects, methods, devices, systems, and means for an efficient initial credit exchange for source-synchronous links are described in which an initiator receives, from a target, an indication that the receiver of the target is alive and receives, from the target, initial credits for an amount of data that can be received by the target. The initiator counts the initial credits received from the target and transmits one or more clock cy cles of data to the target, the one or more clock cycles being equal to or less than a number of the counted initial credits counted by the initiator.
[0003] In aspects, methods, devices, systems, and means for an efficient initial credit exchange for source-synchronous links are described in which a target transmits, to an initiator, an indication that the receiver of the target is alive and transmits, to the initiator, initial credits for an amount of data that can be received by the target. The target receives one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than a number of the transmitted initial credits, and for each received clock cycle of data, the target transmits a credit to the initiator that is effective to enable the initiator to transmit an additional clock cycle of data to the target.
[0004] The details of one or more implementations of an efficient initial credit exchange for source-synchronous links are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the description and drawings, and from the claims. This summary is provided to introduce subject matter that is further described in the Detailed Description and Drawings. Accordingly, this summary’ is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.BRIEF DESCRIPTION OF THE DRAWINGS
[0005] This disclosure describes apparatuses of and techniques for implementing an efficient initial credit exchange for source-synchronous links with reference to the following drawings. The use of same or similar reference numbers throughout the description and the figures may indicate like features or components:FIG. 1 illustrates an example operating environment that includes user devices in which aspects of an efficient initial credit exchange for source-synchronous links can be implemented;FIG. 2 illustrates an example system environment that includes subsystems in a system-on-chip that communicate using source-synchronous links in which an efficient initial credit exchange for source-synchronous links can be implemented in accordance with one or more aspects;FIG. 3 illustrates an example of an interconnection configuration between an initiator and target configuration for source-synchronous links with which an efficient initial credit exchange for source-synchronous links can be implemented in accordance with one or more aspects;FIG. 4 illustrates an example signaling and data transaction diagram between an initiator and a target in accordance with one or more aspects of an efficient initial credit exchange for source-synchronous links;FIG. 5 illustrates an example method for an efficient initial credit exchange for source- synchronous links in accordance with one or more aspects;FIG. 6 illustrates an example method for an efficient initial credit exchange for source- synchronous links in accordance with one or more aspects; andFIG. 7 illustrates an example system-on-chip (SoC) environment in which aspects of an efficient initial credit exchange for source-synchronous links may be implemented.DET ILED DESCRIPTION
[0006] SoCs and particularly Mobile SoCs have multiple subsystems which operate on different voltage and clock domains, and with different resets. The use of protocol-agnostic source-synchronous interface links can interconnect two such subsystems and ease the implementation of timing at the SoC level. As such, the source-synchronous link can operate on independent sender and receiver voltages and clocks. The source-synchronous link that uses credit exchanges can also can pass data through intermediate stages in the SoC for the purpose of clock recovery to maintain timing. While a credit-exchange-based scheme is more efficient than other communication techniques between subsystems in SoCs (e.g., more efficiently handles large communication latencies across an SoC), there are typically multiple link pairs in a SoC (e.g., in the order of hundreds of link pairs).
[0007] Establishing initial credits for credit-based link pairs can require hardcoding the initial credit values across both the sender and the receiver side of the link during the design process. Design hardcoding adds difficultly to the SoC design process and is error-prone as well. Alternatively, additional wires in the SoC can be added to send a credit initialization command through a separate interface from the target side of the link to the initiator side of the link. Thetechniques for efficient initial credit exchange for source-synchronous links described below eliminate the hardcoding of initial credits and additional initialization wires for initializing creditbased source-synchronous link pairs. This technique also minimizes toggling of source-synchronous clock signal across source-synchronous links, thereby reducing power consumption. The technique additionally reduces the number of wires required in a SoC that reduces the complexity of interconnection in the SoC.Example Environment
[0008] FIG. 1 illustrates an example environment 100 that includes a user device 102 in which aspects of an efficient initial credit exchange for source-synchronous links can be implemented. The user device 102 may be implemented as any suitable device, some of which are illustrated as a smart-phone 104, a tablet computer 106, a laptop computer 108, a wearable computing device 110 (e.g., smart-watch), a broadband router 112 (e g., mobile hotspot), and automotive computing system 114 (e.g., navigation and entertainment system). Although not shown, the user device 102 may also be implemented as any of a mobile station (e.g., fixed- or mobile-STA), a mobile communication device, a client device, a user equipment, a mobile phone, an entertainment device, a gaming device, a mobile gaming console, a personal media device, a media playback device, a health monitoring device, a drone, a camera, a wearable smart-device, an Internet home appliance capable of wireless Internet access and browsing, an loT device, and / or other ty pes of user devices. The user device 102 may provide other functions or include components or interfaces omitted from FIG. 1 for the sake of clarity or visual brevity7.
[0009] In this example, some components of the user device 102 are implemented as a system-on-chip 116 (SoC 116), although these components may be implemented separately or in other configurations (e.g., integrated circuits or systems). As shown in FIG. 1, the SoC 116 includes a processor core 118 and memory 120, which may' include computer-readable media, memory media, and / or storage media. The processor core 118 may be implemented as a general-purposeprocessor core (e.g., of a multicore central -processing unit (CPU) or application processor (AP)), an application-specific integrated circuit (ASIC), graphics processing unit (GPU), or a processor core with other components of the user device 102 integrated therewith. The memory 120 can include any suitable type of computer-readable media, memory media, and / or storage media. For example, the memory 120 may include read-only memory (ROM), programmable ROM (PROM), random access memory’ (RAM), dynamic RAM (DRAM), static RAM (SRAM), or Flash memory. In the context of this disclosure, the memory’ 120 of the user device 102 is implemented as a hardware-based or physical storage device, which does not include transitory signals or carrier waves. Applications, firmware, and / or an operating system (not shown) of the user device 102 can be embodied on the memory 120 as processor-executable instructions, which the processor core 118 may execute to provide various functionalities of the user device 102. The memory 120 may also store device data, such as user data or user media that is accessible by the applications, firmware, or operating system of the user device 102.
[0010] In this example, the SoC 116 also includes instances of input / output logic 122 (I / O logic 122). The I / O logic 122 may include circuitry configured to interface control logic of the processor core 118 with various analog and / or digital I / O circuits of the user device 102. For example, the I / O logic 122 can enable the processor core 118 or other control logic to interface with sensors, data ports, transceivers, or other components of the user device 102. In various implementations, respective circuitry’ of the processor core 118, memory’ 120, and I / O logic 122 may operate at different voltages provided by a power system 128 of the user device 102 that includes a power supply 130.
[0011] In this example, the SoC 116 can include multiple subsystems 126 (illustrated as 126A, 126B, 126C) that are connected by source-synchronous communication links. The subsystems 126 can also be connected to the processor core 118, the memory 120, and the I / O logic 122 by source-synchronous communication links. The processor core 118, the memory 120, and the I / O logic 122 can also be interconnected to each other by source-synchronous communication links.
[0012] In aspects, the power system 128 includes one or more power supplies 130, which provide regulated power to the components of the user device 102 and / or the SoC 116. In various implementations, a user device 102 may include or be configured with a display 132, transceivers 134, I / O ports 136. or sensors 138, which can receive power from the power supplies 130 of the power system 128. The power supplies 130 of the power system 128 may include any suitable type of power supply, such as linear regulators, switch-mode power supplies, multiphase switching regulators, or the like. In some cases, the power supplies 130 are configured to provide power at different respective voltage levels for the various components of the user device 102. For example, one of the power supplies 130 may include a switching regulator configured to step battery power (e.g., 3.7 to 4.2 V) or external power (e.g., 5.0 V) down to power at a voltage (e.g., 1.2 V) at which the I / O logic 122 is configured to operate.
[0013] The display 132, transceivers 134, I / O ports 136 and / or sensors 138 of the user device 102 may be configured in any suitable fashion and can be operably coupled with the I / O logic 122. For example, the display 132 may be coupled with the processor core 118 or another processor of the SoC 116 (e.g., graphics processing unit (GPU), not shown) and configured to graphically present an operating system or applications of the user device 102. The transceivers 134 enable the user device 102 to communicate data (e.g., device data) over wired or wireless networks according to any suitable communication protocol. The I / O ports 136 of the user device 102 may include USB ports, coaxial cable ports, and other serial or parallel connectors (including internal connectors) useful to couple the user device to various components, peripherals, or accessories such as keyboards, microphones, or cameras. Alternatively or additionally, the sensors 138 can enable the user device 102 to sense various properties, variances, stimuli, or characteristics of an environment in which the user device 102 operates. For example, the sensors 138 may include a motion sensor, an ambient light sensor, an acoustic sensor, a capacitive sensor, an infrared sensor, a temperature sensor, a radar sensor, or a magnetometer.
[0014] FIG. 2 illustrates, at 200, an example of a source-synchronous link between a sender and a receiver, such as between subsystems 126A and 126B in FIG. 1. In this example, the sender block 202 of subsystem 126A is illustrated (the receiver of subsystem 126A and its associated links are omitted for the sake of illustration clarity) and the asynchronous FIFO 206 (First-In-First-Out) and the receiver block 208 of the subsystem 126B are illustrated (the sender of subsystem 126B and its associated links are omitted for the sake of illustration clarity). For illustration clarity, the source-synchronous link connections are illustrated in a simplified manner and are discussed in greater detail with respect to FIG. 3.
[0015] The subsystem 126A includes the sender block 202 that operates in a sender voltage domain and transmits data to the receiver block 208 in the subsystem 126B. Optionally, the subsystem 126A can include a sync-down bridge 204 that is present if optional repeaters and retimers 210 are employed, and the repeaters and retimers 210 operate on a retimer voltage or receiver voltage that is different than the sender voltage. The optional repeaters and retimers 210 are employed to amplify signals and perform clock recovery on data transmitted across the source-synchronous link, particularly when larger distances within the SoC 216 need to be traversed between the sender block 202 and the receiver block 208. The use of the repeaters and retimers 210 also increase latency for data traversing the source-synchronous link.
[0016] The subsystem 126B includes the asynchronous FIFO 206 and the receiver block 208. The receiver block 208 and portions of the asynchronous FIFO 206 operate in a receiver voltage domain, which may be the same or different than the sender voltage or the retimer voltage. In this example, the size of the buffer in the asynchronous FIFO 206 is known to the sender block 202 so that the sender will not overrun the asynchronous FIFO 206 with data that is greater than the buffer size.
[0017] FIG. 3 illustrates, at 300, an example of interconnections for a source-synchronous link between an initiator and a target, such as between initiator 302 and target 304. For example, theinitiator 302 is included in subsystem 126A and the target 304 is included in subsystem 126B. The operation of the source-synchronous link is illustrated in greater detail with respect to FIG. 4.
[0018] The initiator 302 includes a request transmitter 306 and a response receiver 308. The target 304 includes a request receiver 310 and a response transmitter 312. Upon power-up, the initiator 302 requests, at 330, that the target 304 turns on its source-synchronous clock and the target 304 uses the initiator-RX-link-alive 314 connection (e.g.. a wire within the SoC) to initiate transmission of data from the initiator 302 to the target 304. The target 304 uses the initiator credits 328 connection to provide initial credits and on-going credits to the initiator 302 to enable the initiator 302 to transmit data to the target 304 using the initiator clock 316 and initiator data 318 connections. The received initiator credits 328 are forwarded from the response receiver 308 to the request transmitter 306, at 334, to enable the request transmitter 306 to send data to the target 304.
[0019] Upon power-up, the target 304 requests, at 332, that the initiator 302 turns on its source-synchronous clock and the initiator 302 uses the target-RX-link-alive 322 connection to initiate transmission of data from the target 304 to the initiator 302. The initiator 302 uses the target credits 320 connection to provide initial credits and on-going credits to the target 304 to enable the target 304 to transmit data to the initiator 302 using the target clock 324 and target data 326 connections. The received target credits 320 are forwarded from the request receiver 310 to the response transmitter 312, at 336, to enable the response transmitter 312 to send data to the initiator 302.
[0020] FIG. 4 illustrates, at 400, an example signaling and data transaction diagram betw een an initiator and a target in accordance with one or more aspects of an efficient initial credit exchange for source-synchronous links. For the initiator 302 to target 304 data path in the source-synchronous link, at 405, the target 304 indicates to the initiator 302 that the receive (RX) link for the target 304 is alive (e.g., active or powered-up, such that data transfer can happen). The target304 indicates that the RX link is alive by changing the signal on the initiator-RX-link-alive connection 314 from a logical “0” to “1.”
[0021] At 410, the target 304 provides initial credits to the initiator 302 for transmission of data from the initiator 302 to the target 304. For example, the target 304 uses the initiator credit wire 328 to indicate both a total number of credits available to the initiator at initialization and to return credits to the initiator as data is received over the initiator clock 316 and initiator data 318 wires. All initial credits are sent back-to-back in a single burst on the initiator credits connection (without any other additional information) from the target end of the source synchronous link tow ards the initiator end of the source synchronous link. The single burst of credits refers to a number of clock cycles of the target clock 324 for which the initiator credits connection is at a logical high level. By indicating the total number of credits available to the initiator at initialization, the need to hardcode the number of initial credits into the initiator 302 and the target 304 or to add additional initialization wires for initializing credit-based source-synchronous link pairs betw een the initiator 302 and the target 304 is eliminated. The number of initial credits is selected based on the roundtrip delay (e.g., as determined during the design of the SoC) between the initiator 302 and the target 304 to avoid running out of credits while the target continuously receives data from the initiator. To determine the number of available credits, the initiator counts the number of clock cycles on the target clock wire 324 while the signal on the initiator credit wire 328 is high (at a logic level “1”) with one clock cycle indicating one credit. Optionally or additionally, once the initiator 302 has received any of the credits from the target, the initiator can immediately begin transmitting data without receiving the entirety of the initial credits.
[0022] At 415, the initiator 302 counts the available credits (by counting the number of clock cycles that the signal on the initiator credit wire 328 is high (at the logic level “1”)). The initiator 302 starts counting the available number of credits by waiting for the power-up condition of link and a positive edge on the initiator credits wire 328. The initiator 302 stops counting for the available number of credits by waiting for the negative edge of the signal on the initiator creditswire 328. If credits are available at 420, the initiator 302 transmits a clock cycle of data for each received credit, up to the total number of available credits at 425. If no credits are available at 420, the initiator 302 returns to 415 and waits for more credits to become available.
[0023] At 430. the target 304 counts the number of available credits based on the data received at 425, and at 435. the target 304 sends the available credits to the initiator 302 to continue data transmission from the initiator 302 to the target 304. The transmission of credits from the target 304 to the initiator 302 and data from the initiator 302 to the target 304 continues as long as the logic level on the initiator-RX-link-alive wire remains high.
[0024] For transmission of data in the opposite direction, from the target 304 to the initiator 302 in the source-synchronous link pair, the process is the same as for the data transmission from the initiator 302 to the target 304. The initiator 302 indicates that the initiator is available to receive data by setting a signal on the target-RX-link-alive wire 322 to a logical high level CT”). The initiator 302 provides initial credits to the target 304 for transmission of data from the initiator 302 to the target 304 over the target credits wire 320. With credits received by the target 304, the target 304 transmits data bits for up to the total number of available credits received from the initiator using the target clock 324 and target data 326 wires. The transmission of credits from the initiator 302 to the target 304 and data from the target 304 to the initiator 302 continues as long as the logic level on the target-RX-link-alive wire remains high.
[0025] In a typical SoC system there are low7power considerations that can add complexity to managing data communications within the SoC. With the techniques described herein, one end of the source-synchronous link (initiator or target) can power dow n independently of the other end and can power up independently. During power-down the RX-link-alive signal will go dowor (from a logical 1 to 0), indicating to the link partner that no data transfer can happen and the link partner will discontinue data transmission. During pow er-up the RX link -alive signal will go up (from a logical 0 to 1), which will restart the initial credit exchange between the initiator 302 and the target 304.Example Methods
[0026] Example methods 500 and 600 are described with reference to FIGs. 5 and 6, respectively, in accordance with one or more aspects of implementing an efficient initial credit exchange for source-synchronous links. Generally, the methods 500 and 600 illustrate sets of operations (or acts) that may be performed in. but not necessarily limited to. the order or combinations in which the operations are shown herein. Further, any of one or more of the operations may be repeated, combined, reorganized, skipped, or linked to provide a wide array of additional and / or alternate methods. In portions of the following discussion, reference may be made to the environment 100 of FIG. 1, components of FIGs. 2-4, a system of FIG. 7, and / or entities detailed in FIG. 1 or other figures, reference to which is made for example only. The techniques and apparatuses described in this disclosure are not limited to an embodiment or performance by one entity or multiple entities operating on one device or those described with reference to the figures.
[0027] FIG. 5 illustrates an example method 500 for efficient initial credit exchange for source-synchronous links in accordance with one or more aspects, including operations performed with the initiator 302 and / or the target 304. At 502, an initiator receives, from a target, an indication that the receiver of the target is alive. For example, the initiator (e.g., the initiator 302) receives from the target (e.g., the target 304) an indication that the receiver of the target is alive. The target indicates that the RX link is alive by changing the signal on the initiator-RX-link-alive 314 wire from logical “0” to “1.”
[0028] At 504, the initiator receives, from the target, initial credits for an amount of data that can be received by the target. For example, the initiator receives, from the target, initial credits over the initiator credit wire 328 to indicate both a total number of credits available to the initiator at initialization of communication between the initiator and the target.
[0029] At 506, the initiator counts the initial credits received from the target. For example, the initiator counts the available credits (by counting the number of clock cycles that the signal on an initiator credit wire (e.g., the initiator credit wire 328) is high (at the logic level “1”)). The initiator starts counting the available number of credits by waiting for the power up condition of link and a positive edge on the initiator credits wire. The initiator stops counting for the available number of credits by waiting for the negative edge of the initiator credits wire.
[0030] At 508, the initiator transmits one or more clock cycles of data to the target, the one or more clock cycles being equal to or less than the number of the counted initial credits. For example, the initiator transmits a clock cycle of data for each credit up to the total number of available credits.
[0031] FIG. 6 illustrates an example method 600 for efficient initial credit exchange for source-synchronous links in accordance with one or more aspects, including operations performed with the initiator 302 and / or the target 304. At 602, the target transmits, to the initiator, an indication that the receiver of the target is alive. For example, the target (e.g., the target 304) transmits to the initiator (e.g., the initiator 302) an indication that the receiver of the target is alive. The target indicates that the RX link is alive by changing the signal on the initiator-RX-link-alive 314 wire from“0” to “1.”
[0032] At 604, the target transmits, to the initiator, initial credits for an amount of data that can be received by the target. For example, the target uses the initiator credit wire (e.g., the initiator credit wire 328) to indicate a total number of credits available to the initiator at initialization.
[0033] At 606, the target receives one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than a number of the transmitted initial credits. For example, the target receives one or more clock cycles of data from the initiator, the one or more clock cycles of data being equal to or less than a number of the initial credits transmitted to the initiator at step 604.
[0034] At 608, for each received clock cycle of data, the target transmits a credit to the initiator that is effective to enable the initiator to transmit an additional clock cycle of data to the target. For example, the target counts the number of available credits based on the data received at step 606 and sends a credit to the initiator for each clock cycle of received data to continue data reception from the initiator.Example Systems
[0035] FIG. 7 illustrates an example system-on-chip (SoC) in which aspects of an efficient initial credit exchange for source-synchronous links can be implemented. In aspects, the SoC 700 may represent similar or alternate configurations of the SoC 116 as described with reference to FIG. 1. Accordingly, the SoC 700 may be embodied as or within any type of user device 102, user equipment, apparatus, other device, or system as described with reference to FIGs. 1-6. Although described with reference to chip-based packaging, the components shown in FIG. 7 may be embodied as other systems or component configurations, such as, and without limitation, a power management integrated-circuit (PMIC), a power regulation circuit, an LDO integrated-circuit, a Field-Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), an Application-Specific Standard Product (ASSP), a digital signal processor (DSP), Complex Programmable Logic Devices (CPLD), system in package (SiP), package on package (PoP), a graphics processing unit (GPU), a machine-learning engine, processing and communication chip set, communication co-processor, sensor co-processor, or the like.
[0036] In this example, the SoC 700 includes communication transceivers 702 and a wireless modem 704 that enable wired or wireless communication of data 706 (e.g., received data, data that is being received, data scheduled for broadcast, packetized, or the like). In some aspects, the wireless modem 704 is implemented as a multi-mode multi-band modem or baseband processor that is configurable to communicate in accordance with various communication protocols and / or in different frequency bands. The wireless modem 704 may include a transceiver interface (notshown) for communicating encoded or modulated signals with transceiver circuitry, and / or controlling a radio frequency (RF) front end.
[0037] The data 706 or other system content can include configuration settings of the system or various components, media content stored by the system, and / or information associated with a user of the system. Media content stored on the system-on-chip 700 may include any type of audio, video, and / or image data. The system-on-chip 700 also includes an instance of I / O logic 708, which may be configured similar to I / O logic 122 as described throughout this disclosure. In some implementations, the I / O logic 708 of the SoC 700 is configured as one or more data inputs 708 via which any type of data, media content, and / or inputs can be received, such as user input, user-selectable inputs (explicit or implicit), or any other type of audio, video, and / or image data received from a content and / or data source. Alternatively or additionally, the I / O logic 708 may include various data interfaces, which can be implemented as any one or more of a serial and / or parallel interface, a wireless interface, a network interface, and as any other type of communication interface enabling communication with other devices or systems.
[0038] The system-on-chip 700 includes one or more processor cores 710, which process various computer-executable instructions to control the operation of the system-on-chip 700 and to enable any suitable functionalities of the system-on-chip 700. Alternatively or additionally, the system-on-chip 700 can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry7that is implemented in connection with processing and control circuits, which are generally shown at 712. Although not shown, the system-on-chip 700 may also include abus, interconnect, crossbar, or fabric that couples the various components within the system.
[0039] The system 700 also includes a memory 714 (e.g., computer-readable media), such as one or more memory7circuits that enable persistent and / or non-transitory data storage, and thus do not include transitory7signals or carrier waves. Examples of the memory 714 include ROM, RAM, DRAM, SRAM, or Flash memory7. The memory7714 provides data storage for the system data 706, as w ell as for firmw are 716, applications 718, and any other types of information and / or datarelated to operational aspects of the system-on-chip 700. For example, the firmware 716 can be maintained as processor-executable instructions of an operating system (e.g., real-time OS) within the memory 714 and executed on one or more of the processor cores 710.
[0040] The applications 718 may include a system manager, such as any form of a control application, software application, signal-processing and control module, code that is native to a particular system, an abstraction module, a machine learning module, or gesture module and so on. The memory 714 may also store system components or utilities for implementing any suitable functionalities of the system-on-chip 700. In some aspects, the system-on-chip 700 also includes additional processors or co-processors to enable other functionalities, such as a graphics processor 720, audio processor 722, and image sensor processor 724. The graphics processor 720 may render graphical content associated with a user interface, operating system, or applications of the system-on-chip 700. In some cases, the audio processor 722 encodes or decodes audio data and signals, such as audio signals and information associated with voice calls or encoded audio data for playback. The image sensor processor 724 may be coupled to an image sensor and provide image data processing, video capture, and other visual media conditioning and processing functions.
[0041] In aspects, the system-on-chip 700 includes a power system 128, which may be implemented as described with reference to FIGs. 1-6. Alternatively or additionally, the processor cores 710 or other lower-voltage circuitry of the SoC 700 can be coupled to an output node or rail of the power system 132.
[0042] The system-on-chip 700 may also include a security processor 726 to support various security, encryption, and cryptographic operations, such as to provide secure communication protocols and encrypted data storage. Although not shown, the security processor 726 may include one or more cryptographic engines, cipher libraries, hashing modules, or random number generators to support encry ption and cryptographic processing of information or communications of the system-on-chip 700. Alternatively or additionally, the system-on-chip 700 can include amachine learning (ML) engine 728 and / or a sensor interface 730. Generally, the ML engine 728 may include one or more ML models, artificial intelligence (Al) models, or deep neural networks (DNNs) and a processor core for executing the models and / or networks. The sensor interface 730 can enable the system-on-chip 700 to receive data from various sensors, such as capacitance and motion sensors of a user device in which the system-on-chip is embodied.
[0043] The system-on-chip 700 may also include one or more subsystems 126 as described above with reference to FIG. 2. Each subsystem 126 can include one or more initiators 302 and targets 304 for communication with other subsystems, including the communication transceivers 702, the wireless modem 704, the I / O logic 708. the one or more processor cores 710, the processing and control circuits 712, the memory 714, the graphics processor 720, the audio processor 722, the image sensor processor 724, the security processor 726, the ML engine 728, and / or the sensor interface 730.
[0044] Generally, the components, modules, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry ), manual processing, or any combination thereof. Some operations of the example methods may be described in the general context of executable instructions stored on computer-readable storage memory7that is local and / or remote to a computer processing system, and implementations can include software applications, programs, functions, and the like. Alternatively, or in addition, any of the functionality7described herein can be performed, at least in part, by one or more hardware logic components, such as, and without limitation, LDOs, PMICs, FPGAs, ASICs, ASSPs, SoCs, CPLDs, GPUs, ML engines, co-processors, context hubs, motion co-processors, sensor coprocessors, or the like.
[0045] In the following some examples are described:Example 1 : A method of transmitting data to a target by an initiator in a system-on-chip (SoC), the method comprising the initiator:receiving, from the target, an indication that the receiver of the target is alive;receiving, from the target, initial credits for an amount of data that can be received by the target;counting the initial credits received from the target; andtransmitting one or more clock cycles of data to the target, the one or more clock cycles being equal to or less than a number of the counted initial credits.Example 2: The method of example 1, further comprising:receiving, from the target, additional credits; andtransmitting one or more clock cycles of data to the target, the one or more clock cycles being equal to or less than the number of received additional credits.Example 3: The method of example 1 or example 2, further comprising:receiving, from the target, an indication that the receiver of the target is not alive; and discontinuing the transmitting of the data to the target.Example 4: The method of any one of the preceding examples, wherein the number of initial credits is selected based on a roundtrip delay between the initiator and the target, and wherein the number of initial credits is selected to avoid running out of credits while continuously transmitting data from the initiator to the target.Example 5: The method of any one of the preceding examples, wherein the initial credits are received in a single burst on the initiator credit connection from the target.Example 6: The method of any one of the preceding examples, wherein the initiator begins the transmitting of the data to the target as soon as a first credit is received.Example 7: The method of any one of the preceding examples, further comprising:receiving the initial credits over an initiator credits wire from the target.Example 8: The method of any one of the preceding examples, further comprising: receiving the additional credits over an initiator credits wire from the target.Example 9: A method of receiving data from an initiator by a target in a system-on-chip (SoC), the method comprising the target:transmitting, to the initiator, an indication that the receiver of the target is alive; transmitting, to the initiator, initial credits for an amount of data that can be received by the target;receiving one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than a number of the transmitted initial credits; andfor each received clock cycle of data, transmitting a credit to the initiator that is effective to enable the initiator to transmit an additional clock cycle of data to the target.Example 10: The method of example 9, further comprising:transmitting, to the initiator, additional credits; andreceiving one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than the number of transmitted additional credits.Example 11 : The method of example 9 or example 10, further comprising:transmitting, to the initiator, an indication that the receiver of the target is not alive; and discontinuing the reception of the data from the initiator.Example 12: The method of any one of examples 9 to 11, wherein the number of initial credits is selected based on a roundtrip delay between the initiator and the target.Example 13: The method of example 12, wherein the number of initial credits is selected to avoid running out of credits while continuously receiving data from the initiator.Example 14: The method of any one of examples 9 to 13, further comprising:transmitting the initial credits over an initiator credits wire to the initiator.Example 15: The method of any one of examples 9 to 14, further comprising:transmitting the additional credits over an initiator credits wire to the initiator.Example 16: The method of examples 14 or 15. wherein the initial credits are transmitted in a single burst on an initiator credit connection from the target to the initiator.Example 17: A System-on-Chip (SoC) comprising:initiator logic; andtarget logic;the initiator logic and the target logic configured to perform any one of the methods of the preceding examples.Example 18 : The SoC of claim 17, wherein the initiator logic and the target logic are running on different clocks, and wherein the initiator logic and the target logic have different resets.Example 19: The SoC of claim 17 or claim 18, wherein the initiator logic and the target logic have different power domains.Although aspects of an efficient initial credit exchange for source-synchronous links have been described in language specific to features and / or methods, the subject of the appended claims isnot necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of an efficient initial credit exchange for source-synchronous links and other equivalent features and methods are intended to be within the scope of the appended claims. Further, various different aspects are described, and it is to be appreciated that each described aspect can be implemented independently or in connection with one or more other described aspects.
Claims
CLAIMSWhat is claimed is:
1. A method of transmitting data to a target by an initiator in a system-on-chip (SoC), the method comprising the initiator:receiving, from the target, an indication that the receiver of the target is alive; receiving, from the target, initial credits for an amount of data that can be received by the target, the initial credits being received in a single burst on an initiator credit connection from the target;counting the initial credits received from the target; andtransmitting one or more clock cycles of data to the target, the one or more clock cycles being equal to or less than a number of the counted initial credits.
2. The method of claim 1, further comprising:receiving, from the target, additional credits; andtransmitting one or more clock cycles of data to the target, the one or more clock cycles being equal to or less than the number of received additional credits.
3. The method of claim 1 or claim 2, further comprisingreceiving, from the target, an indication that the receiver of the target is not alive; and discontinuing the transmitting of the data to the target.
4. The method of any one of the preceding claims, wherein the number of initial credits is selected based on a roundtrip delay between the initiator and the target, and wherein the number of initial credits is selected to avoid running out of credits while continuously transmitting data from the initiator to the target.
5. The method of any one of the preceding claims, wherein the initiator begins the transmitting of the data to the target as soon as a first credit is received.
6. The method of any one of the preceding claims, further comprising: receiving the initial credits over an initiator credits wire from the target.
7. A method of receiving data from an initiator by a target in a system-on-chip (SoC), the method comprising the target:transmitting, to the initiator, an indication that the receiver of the target is alive; transmitting, to the initiator, initial credits for an amount of data that can be received by the target the initial credits being transmitted in a single burst on an initiator credit connection from the target to the initiator;receiving one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than a number of the transmitted initial credits; andfor each received clock cycle of data, transmitting a credit to the initiator that is effective to enable the initiator to transmit an additional clock cycle of data to the target.
8. The method of claim 7, further comprising:transmitting, to the initiator, additional credits; andreceiving one or more clock cycles of data from the initiator, the one or more clock cycles being equal to or less than the number of transmitted additional credits.
9. The method of claim 7 or claim 8, further comprising:transmitting, to the initiator, an indication that the receiver of the target is not alive; and discontinuing the reception of the data from the initiator.
10. The method of any one of claims 7 to 9, wherein the number of initial credits is selected based on a roundtrip delay between the initiator and the target.
11. The method of claim 10, wherein the number of initial credits is selected to avoid running out of credits while continuously receiving data from the initiator.
12. The method of any one of claims 8 to 11, further comprising:transmitting the initial credits and the additional credits over an initiator credits wire to the initiator.
13. A System-on-Chip (SoC) comprising:initiator logic; andtarget logic;the initiator logic and the target logic configured to perform any one of the methods of the preceding claims.
14. The SoC of claim 13, wherein the initiator logic and the target logic are running on different clocks, and wherein the initiator logic and the target logic have different resets.
15. The SoC of claim 13 or claim 14, wherein the initiator logic and the target logic have different power domains.