Semi self-aligned contact fabrication for backside power delivery

Abstract

A method of forming a contact to a source / drain (S / D) region of a semiconductor structure includes forming a sidewall nitride layer on inner surfaces of an S / D recess that is aligned with the S / D region, depositing a bottom layer on a bottom surface of the S / D recess, forming a protection layer on shoulder portions of the S / D recess, removing the bottom layer, and forming the contact to the S / D region within the S / D recess.

Description

SEMI SELF-ALIGNED CONTACT FABRICATION FOR BACKSIDE POWER DELIVERY BACKGROUNDField

[0001] Embodiments described herein generally relate to semiconductor device fabrication, and more particularly, to forming a semiconductor structure for backside power delivery.Description of the Related Art

[0002] Traditionally, chips are constructed with transistors on a front side of a silicon wafer and all interconnects that power them and transmit their data signals built above them. One of the key technologies to enable scaling below 3 nm involves delivering of power on a back side of a chip. This backside power delivery eliminates the need to share interconnect resources between signals and power lines on a front side of the chip as power is moved to the back side of the chip. Backside power delivery further eliminates the need for a power delivery track from lower layer front side interconnects, leading to cost savings. Backside power delivery also allows different metal layers to be optimally fabricated, such as wider lines for an operating voltage Vdd and a common ground voltage Vss, and thinner lines to carry signals.

[0003] However, backside power delivery creates new challenges, such as patterning electrical contact features isolated from one another by isolation modules on a backside of a chip within tight spaces without impacting performance of transistors on a front side of the chip, as the electrical contacts can easily short to a gate in a source / drain (S / D) region. Using a shallow placeholder formed and aligned with the S / D region in the front side of the chip has shown beneficial in fabricating electrical contacts from the backside. However, this scheme still requires lithography and etch processes from the backside, which creates shoulder regions near the placeholder and a contact, causing shorting to a gate.

[0004] Therefore, there is a need for methods for overcoming such challenges in backside power delivery devices.SUMMARY

[0005] Embodiments of the present disclosure provide a method of forming a contact to a source / drain (S / D) region of a semiconductor structure. The method includes forming a sidewall nitride layer on inner surfaces of an S / D recess that is aligned with the S / D region, depositing a bottom layer on a bottom surface of the S / D recess, forming a protection layer on shoulder portions of the S / D recess, removing the bottom layer, and forming the contact to the S / D region within the S / D recess.

[0006] Embodiments of the present disclosure also provide a method of forming a contact to a source / drain (S / D) region of a semiconductor structure. The method includes forming an S / D recess that is aligned with a placeholder and the S / D region formed on a substrate, forming a sidewall oxide layer on inner surfaces of the S / D recess, covering the sidewall oxide layer on shoulder portions of the S / D recess with a bottom layer, removing the sidewall oxide layer not covered by the bottom layer selectively against the bottom layer and leaving a protection layer on the shoulder portions of the S / D recess, removing the bottom layer and the placeholder, forming a sidewall nitride layer on exposed inner surfaces of the S / D recess, removing a portion of the sidewall nitride layer at the bottom the S / D recess, and forming the contact to the S / D region within the S / D recess.

[0007] Embodiments of the present disclosure further provide a method of forming contacts to source / drain (S / D) regions of a semiconductor structure. The method includes forming a sidewall nitride layer on inner surfaces of a first S / D recess that is aligned with a first S / D region in a p-channel region of the semiconductor structure and a second S / D recess that is aligned with a second S / D region in an n-channel region of the semiconductor structure, depositing a bottom layer on bottom surfaces of the first S / D recess and the second S / D recess, depositing a blocking nitride layer on exposed inner surfaces of the first S / D recess and the second S / D recess, covering exposed surfaces of the n-channel region of the semiconductor structure with a first blocking mask, removing a portion of the blocking nitride layer at the bottom of the first S / D recess and leaving a first protection layer on shoulder portions of the first S / D recess, removing the bottom layer in the first S / D recess, removing the first blocking mask, removing a portion of the blocking nitride layer at the bottom of the second S / D recess and leaving a second protection layer on shoulder portions of the second S / Drecess in the second S / D recess, forming a first cavity in the first S / D recess, and forming a first contact epi layer within the first cavity.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the disclosure, as the disclosure may admit to other equally effective embodiments.

[0009] Figure 1 is a schematic top view of a multi-chamber processing system, according to one or more embodiments of the present disclosure.

[0010] Figure 2 depicts a process flow diagram of a method of forming a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to a first embodiment of the present disclosure.

[0011] Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M, 3N, 30, 3P, 3Q, 3R, 3S, 3T, 3U, and 3V are cross-sectional views of a portion of a semiconductor structure, corresponding to various states of the method of Figure 2.

[0012] Figure 4 depicts a process flow diagram of a method of forming a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to a second embodiment of the present disclosure.

[0013] Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, and 5L are cross-sectional views of a portion of a semiconductor structure 300, corresponding to various states of the method 400.

[0014] Figure 6 depicts a process flow diagram of a method of forming a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to a third embodiment of the present disclosure.

[0015] Figures 7A, 7B, 7C, 7D, 7E, 7F, 7G, and 7H are cross-sectional views of a portion of the semiconductor structure, corresponding to various states of the method of Figure 6.

[0016] To facilitate understanding, identical reference numerals have been used,where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. In the figures and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. The directions represented by the arrows in the drawings are assumed to be positive directions for convenience. It is contemplated that elements disclosed in some embodiments may be beneficially utilized on other implementations without specific recitation.DETAILED DESCRIPTION

[0017] The embodiments described herein provide methods for forming metal contacts isolated from one another by an inter-layer dielectric (ILD), by replacing portions of a chip with dielectric material, from a backside of the chip, while protecting source / drain (S / D) epitaxial (epi) layers on a front side of the chip. The methods described herein include etching of a silicon (Si) substrate without affecting source / drain (S / D) epitaxial (epi) regions which can be n-type (e.g., Si:P) or p-type (e.g., SiGe:B) in devices with no inner spacers, using a conformal extension region formed of silicon germanium (SiGe).

[0018] The embodiments described herein provide semi self-aligned methods for forming a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET). In the methods described herein, a recess is formed by direct lithography and etch on a backside of a substrate to be aligned with a placeholder formed on a front side of the substrate, where the recess has a larger critical dimension (CD) than the placeholder. Shoulder portions generated by the direct lithography and etch within the recess are protected during subsequent integration processing steps, such that the risk of shorting to a gate is eliminated.

[0019] The embodiments described herein include a first embodiment, a second embodiment, and a third embodiment. In the first embodiment, a contact epi layer is not formed in a p-channel MOS (p-MOS) transistor region or in an n-channel MOS (n-MOS) transistor region. In the second embodiment, a contact epi layer is formed in a p-channel MOS (p-MOS) transistor region and not in an n-channel MOS (n-MOS) transistor region. In the third embodiment, a contact epi layer is formed in both a p-channel MOS (p-MOS) transistor region and an n-channel MOS (n-MOS) transistorregion.

[0020] Figure 1 is a schematic top view of a multi-chamber processing system 100, according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in and transferred between the various chambers without exposing the substrates to an ambient environment exterior to the processing system 100 (e.g., an atmospheric ambient environment such as may be present in a fab). For example, the substrates can be processed in and transferred between the various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment among various processes performed on the substrates in the processing system 100. Accordingly, the processing system 100 may provide for an integrated solution for some processing of substrates.

[0021] Examples of a processing system that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer® or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.

[0022] In the illustrated example of Figure 1, the factory interface 102 includes a docking station 132 and factory interface robots 134 to facilitate transfer of substrates. The docking station 132 is adapted to accept one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134 adapted to transfer the substrates from the factory interface 102 to the load lock chambers 104, 106.

[0023] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers. Generally, any port is open for transferring a substrate therethrough. Otherwise, the port is closed.

[0024] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 134 transfers a substrate from a FOUR 136 through a port 140 or 142 to a load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 with an interior low pressure or vacuum environment (which may include an inert gas). Hence, the pumping down of the load lock chamber 104 or 106 facilitates passing the substrate between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0025] With the substrate in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 144 or 146. The transfer robot 112 is then capable of transferring the substrate to and / or between any of the processing chambers 120, 122 through the respective ports 152, 154 for processing and the holding chambers 116, 118 through the respective ports 148, 150 for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing the substrate in the holding chamber 116 or 118 through the port 156 or 158 and is capable of transferring the substrate to and / or between any of the processing chambers 124, 126, 128, 130 through the respective ports 160, 162, 164, 166 for processing and theholding chambers 116, 118 through the respective ports 156, 158 for holding to await further transfer. The transfer and holding of the substrate within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.

[0026] The processing chambers 120, 122, 124, 126, 128, 130 can be any appropriate chamber for processing a substrate. In some examples, the processing chamber 120 can be capable of performing etch processes, the processing chamber 122 can be capable of performing cleaning processes, the processing chamber 124 can be capable of performing selective removal processes, the processing chamber 126 can be capable of performing chemical vapor deposition (CVD) deposition processes, and the processing chambers 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 120 may be a Selectra™ Etch chamber available from Applied Materials of Santa Clara, Calif. The processing chamber 122 may be a SiCoNi™ Pre-clean chamber available from Applied Materials of Santa Clara, Calif. The processing chamber 126 may be a W*Z™ chamber available from Applied Materials of Santa Clara, Calif. The processing chamber 128, or 130 may be a Centura™ Epi chamber available from Applied Materials of Santa Clara, Calif.

[0027] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 may control the operation of the processing system 100 using a direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate performance of the processing system 100.

[0028] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 may be one of any form of a general purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 174 are coupled to the CPU 170 and may comprise cache, clock circuits, input / output subsystems, power supplies, and the like. Thevarious methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction code stored in the memory 172 (or in memory of a particular processing chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chambers to perform processes in accordance with the various methods.

[0029] Other processing systems can be in other configurations. For example, more or fewer processing chambers may be coupled to a transfer apparatus. In the illustrated example, the transfer apparatus includes the transfer chambers 108, 110 and the holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0030] Figure 2 depicts a process flow diagram of a method 200 of forming a semiconductor structure 300 that may form a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to a first embodiment of the present disclosure. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M, 3N, 30, 3P, 3Q, 3R, 3S, 3T, 3U, and 3V are cross-sectional views of a portion of the semiconductor structure 300, corresponding to various states of the method 200. It should be understood that Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, 3J, 3K, 3L, 3M, 3N, 30, 3P, 3Q, 3R, 3S, 3T, 3U, and 3V illustrate only partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method illustrated in Figure 2 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0031] As shown in Figure 3A, the semiconductor structure 300 includes a fin-shaped column 302 formed on a front side of a substrate 304. The fin-shaped column 302 includes a stack of alternating channel layers 306 and replacement-metal-gate (RMG) stacks 308 in the Z direction. Through the fin-shaped column 302, a source / drain (S / D) region including an S / D epi layer 310 (also referred to as an “L2 layer”) and anS / D epi liner 312 (also referred to as an “L1 layer”) surrounding the S / D epi layer 310 is formed. Within the substrate 304, a placeholder 314 is formed and aligned with the S / D epi layer 310 in the Z direction. The channel layers 306 will be electrically connected to a backside contact to be formed via the S / D region.

[0032] The term “substrate” as used herein refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate 304 may be a silicon-based material or any suitable insulating materials or conductive materials as needed. The substrate 304 may include a material such as crystalline silicon (e.g., Si<100>, Si <110>, or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0033] The channel layers 306 may be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). Each of the RMG stacks 308 includes a gate metal (e.g., titanium nitride (TiN), titanium aluminum carbide (TiAIC), or tungsten (W)) and a high-k material (e.g., hafnium oxides (HfO2), hafnium zirconium oxide (HfZrO2), and aluminum oxide (AI2O3)).

[0034] The S / D epi layer 310 may be formed of epitaxially grown silicon (Si) doped with p-type dopants such as boron (B) or gallium (Ga), or silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between 35 % and 65%, doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1019cm-3and 5x 1021cm-3, depending upon the desired conductive characteristic of the S / D epi layer 310.

[0035] The S / D epi liner 312 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 5 % and about 25 %, for example, between about 5.5 % and about 6%, lightly doped with p-type dopants such as boron (B) or gallium (Ga), or n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1 x 1018cm-3and 5 x 1021crrr3, depending upon the desired conductive characteristic of the S / D epi liner 312.

[0036] The placeholder 314 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 15 % and about 50 %, or metal such as titanium nitride (TiN).

[0037] The method 200 starts with block 202, in which a lithography process is performed to form a patterned mask 316 on the backside of the substrate 304, as shown in Figure 3A. The mask 316 may be formed of silicon nitride (SisN4), silicon oxide (SiC>2), aluminum oxide (AI2O3), or metal nitride.

[0038] In block 204, a lithography and etch process is performed to partially etch the substrate 304, and form an S / D recess 318 aligned with the S / D epi layer 310 in the Z direction, as shown in Figure 3B.

[0039] The lithography and etch process may be any appropriate lithography and etch processes, using the mask 316, such as photolithography and dry anisotropic etching, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0040] In block 206, a placeholder removal process is performed to remove the placeholder 314 (e.g., silicon germanium (SiGe) with high germanium (Ge) ratio, or metal such as titanium nitride (TiN)) selectively to the substrate 304 (e.g., silicon (Si)) and the S / D epi liner 312 (e.g., silicon germanium (SiGe) with low germanium (Ge) ratio) and extend S / D recess 318 to expose the S / D epi liner 312, as shown in Figure 3C. The S / D epi liner 312 (e.g., silicon germanium (SiGe) with low germanium (Ge) ratio) has etch selectivity from the placeholder 314 (e.g., silicon germanium (SiGe) with high germanium (Ge) ratio, or metal such as titanium nitride (TiN)), and thus acts as an etch stop layer during the placeholder removal process.

[0041] In the placeholder removal process, the S / D recess 318 is formed to have a larger CD than the placeholder 314, in order to allow a process margin. Thus, shoulder portions 318S that protrude on inner sidewalls of the S / D recess 318 are formed. In the subsequent steps, a protection layer is formed on the shoulder portions 318S such that the shoulder portions 318S will not be exposed when a backside contact is formed within the S / D recess 318.

[0042] The placeholder removal process may include any appropriate dry anisotropic etching or wet etching process, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0043] In block 208, a sidewall nitridation process is performed to form a sidewall nitride layer 320 on exposed inner surfaces of the S / D recess 318, as shown in Figure 3D.

[0044] The sidewall nitride layer 320 may be formed of silicon nitride (SisN4) having a thickness of between about 5 nm and about 10 nm.

[0045] The sidewall nitridation process may be a plasma treatment process, such as a decoupled plasma nitridation (DPN) process, a decoupled plasma (DPX) process, a decoupled plasma plus (DPX+) process, or a rapid thermal nitridation (RTN) process performed in a processing chamber, such as a Radiance™ chamber, available from Applied Materials, Inc., Santa Clara, Calif, or the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1. Gases that may be used in the plasma treatment process include nitrogen containing gas, such as nitrogen (N2), ammonia (NH3), or mixtures thereof.

[0046] In block 210, a bottom-up deposition process is performed to selectively deposit a bottom layer 322 on a bottom surface 324 of the S / D recess 318 and on the mask 316, as shown in Figure 3E. The bottom layer 322 may be silicon oxide (SiC ) or carbon.

[0047] The bottom-up deposition process may include a directional selective fill (DSF) process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0048] In block 212, a blocking nitride deposition process is performed to deposit a blocking nitride layer 326 on exposed inner surfaces of the S / D recess 318 and on the bottom layer 322 on the mask 316, as shown in Figure 3F. The blocking nitride layer 326 may be formed of silicon nitride (SisN4) having a thickness of between about 5 nm and about 10 nm. In these embodiments, the bottom layer 322 is silicon oxide (SiC ).

[0049] The blocking nitride deposition process may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD), performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0050] In block 214, a nitride bottom open etch process is performed to remove a portion of the blocking nitride layer 326 at the bottom of the S / D recess 318 and leave a protection layer 328 on the shoulder portions 318S (shown in Figure 3C) of the S / D recess 318, as shown in Figure 3G. The protection layer 328 is silicon nitride (SisN4).

[0051] The nitride bottom open etch process may include an anisotropic remote plasma assisted dry etch process, such as a reactive ion etching (RIE) process, in a processing chamber, such as the processing chamber 124 shown in Figure 1, using a plasma formed from a gas including argon (Ar), helium (He), nitrogen (N2), or a combination thereof. The plasma effluents directionally bombard and remove the portion of the blocking nitride layer 326 at the bottom of the S / D recess 318.

[0052] In some embodiments, alternatively to blocks 212 and 214, in block 216, a selective deposition process is performed to selectively deposit a protection layer 328 on the shoulder portions 318S (shown in Figure 3C) of the S / D recess 318, as shown in Figure 3H. The protection layer 328 is silicon nitride (SisN4) or aluminum oxide (AI2O3). In these embodiments, the bottom layer 322 is carbon.

[0053] The selective deposition process may include a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0054] In block 218, a bottom layer removal process is performed to remove the bottom layer 322, as shown in Figure 3I.

[0055] The bottom layer removal process may include any appropriate etch process.

[0056] In block 220, a cavity etch process is performed to form a cavity 330 into the S / D epi liner 312 and the S / D epi layer 310 within the S / D recess 318, as shown in Figure 3J.

[0057] The cavity 330 may have a V-shape, a U-shape, or any other shape, and enlarge a contact area of a metal fill to be formed within the S / D recess 318, to minimize parasitic resistance.

[0058] The cavity etch process includes an etch process using an etching gas including halogen-containing gas, such as chlorine (CI2), hydrogen chloride (HCI), or hydrogen fluoride (HF), carbon-containing fluorine (F) chemistries, such astetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F), bromine-containing chemistries such as HBr, and carrier gas, such as argon (Ar), or helium (He), performed in an etch chamber, such as the processing chamber 120 shown in Figure 1.

[0059] In block 222, a backside contact formation process is performed to form a backside contact to the S / D epi layer 310, including a barrier layer 332 and metal fill 334, as shown in Figure 3K.

[0060] The barrier layer 332 may be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAIC), tungsten nitride (WN), or tungsten (W). A deposition process to form the barrier layer 332 may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0061] The metal fill 334 may be formed of contact metal material, such as tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or titanium nitride (TiN). A contact metallization process to form the metal fill 334 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor, such as WFe, or a cobalt-containing precursor, in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0062] In some embodiments, as indicated by broken arrows in Figure 2, the bottom-up deposition process in block 210 is performed before the placeholder removal process in block 206. As shown in Figure 3L, a bottom layer 322’ is selectively deposited on exposed inner surfaces of the S / D recess 318 and on the mask 316. The bottom layer 322’ may be formed of silicon nitride (SisN4).

[0063] Subsequently, in block 224, a sidewall removal process is performed to remove a portion of the bottom layer 322’ on inner surfaces of the S / D recess 318, as shown in Figure 3M.

[0064] The sidewall removal process may include any appropriate etch process.

[0065] Subsequently, the placeholder removal process in block 206 is performed to remove the placeholder 314 (e.g., silicon germanium (SiGe) with high germanium (Ge) ratio, or metal such as titanium nitride (TiN)) selectively to the substrate 304 (e.g., silicon (Si)), the S / D epi liner 312 (e.g., silicon germanium (SiGe) with low germanium(Ge) ratio), and the bottom layer 322’ (e.g., silicon nitride (Si3N4)), and leave a protection layer 328 on the shoulder portions 318S (shown in Figure 30) of the S / D recess 318, as shown in Figure 3N. The protection layer 328 is silicon nitride (Si3N4).

[0066] Subsequently, the sidewall nitridation process in block 208 is performed to form a sidewall nitride layer 320 on inner surfaces of the S / D recess 318, as shown in Figure 30.

[0067] The cavity etch process in block 220 is then performed to form a cavity 330 into the S / D epi liner 312 and the S / D epi layer 310 within the S / D recess 318, as shown in Figure 3P.

[0068] The backside contact formation process in block 222 is performed to form a backside contact from the backside of the substrate 304 to the S / D epi layer 310, including a barrier layer 332 and metal fill 334, as shown in Figure 3Q.

[0069] In some embodiments, as indicated by double arrows in Figure 2, alternatively to blocks 206-218, in block 226, a substrate removal process is performed to partially remove the substrate 304 selectively to the placeholder 314 and widen the S / D recess 318, as shown in Figure 3R.

[0070] After the substrate removal process, the S / D recess 318 may have CD of between about 15 nm and about 30 nm.

[0071] The substrate removal process may include any isotropic etch process, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0072] Subsequently, in block 228, a directional oxidation process is performed to form a sidewall oxide layer 336 on exposed inner sidewalls of the S / D recess 318, as shown in Figure 3S.

[0073] The sidewall oxide layer 336 may be formed of silicon nitride (SiC ) having a thickness of between about 5 nm and about 10 nm.

[0074] The directional oxidation process may be a plasma treatment process, such as a decoupled plasma plus (DPX+) process, performed in a processing chamber, such as a Radiance™ chamber, available from Applied Materials, Inc., Santa Clara, Calif, or the processing chambers 120, 122, 124, 126, 128, and 130 shown in Figure 1.

[0075] Subsequently, in block 230, a bottom-up deposition process and an oxide removal process are performed. As shown in Figure 3T, a bottom layer 322 to cover the sidewall oxide layer 336 on the shoulder portions 318S (shown in Figure 3R) of the S / D recess 318 is formed in the bottom-up deposition process, and the sidewall oxide layer 336 not covered by the bottom layer 322 are removed selectively against the bottom layer 322 in the oxide removal process. The bottom layer 322 may be formed of carbon. A protection layer 328 is left on the shoulder portions 318S of the S / D recess 318. The protection layer 328 is silicon nitride (SiC ).

[0076] The bottom-up deposition process may be the same or similar to the bottom-up deposition process in block 210. The oxide removal process may include any appropriate etch process.

[0077] Subsequently, in block 232, a bottom layer removal process and a placeholder removal process are performed. As shown in Figure 3U, the bottom layer 322 is removed in the bottom layer removal process, and the placeholder 314 is removed in the placeholder removal process.

[0078] The bottom layer removal process may be the same or similar to the bottom layer removal process in block 218. The placeholder removal process may be the same or similar to the placeholder removal process in block 206.

[0079] Subsequently, in block 234, a sidewall nitridation process and a nitride bottom open etch process are performed. As shown in Figure 3V, a sidewall nitride layer 320 is formed on exposed inner surfaces of the S / D recess 318, in the sidewall nitridation process, and a portion of the sidewall nitride layer 320 at the bottom the S / D recess 318 is removed.

[0080] The sidewall nitridation process may be the same or similar to the sidewall nitridation process in block 208. The nitride bottom open etch process may be the same or similar to the nitride bottom open etch process in block 214.

[0081] Figure 4 depicts a process flow diagram of a method 400 of forming a semiconductor structure 500 that may form a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to a second embodiment of the present disclosure. In the semiconductor structure 500, a contact epi layer is formed in a p-channel MOS (p-MOS) transistor region and not in an n-channel MOS (n-MOS) transistor region. Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G,5H, 51, 5J, 5K, and 5L are cross-sectional views of a portion of the semiconductor structure 300, corresponding to various states of the method 400. It should be understood that Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51, 5J, 5K, and 5L illustrate only partial schematic views of the semiconductor structure 500, and the semiconductor structure 500 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method illustrated in Figure 4 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0082] As shown in Figure 5A, the semiconductor structure 500 includes a p-MOS region 502P and an n-MOS region 502N. Each of the p-MOS region 502P and the n-MOS region 502N includes a fin-shaped column 302 formed on a front side of a substrate 304. The fin-shaped column 302 includes a stack of alternating channel layers 306 and replacement-metal-gate (RMG) stacks 308 in the Z direction. Through the fin-shaped column 302, a source / drain (S / D) region including an S / D epi layer 310 (also referred to as an “L2 layer”) and an S / D epi liner 312 (also referred to as an “L1 layer”) surrounding the S / D epi layer 310 is formed.

[0083] In the p-MOS region 502P, the S / D epi layer 310 may be formed of epitaxially grown silicon (Si) doped with p-type dopants such as boron (B) or gallium (Ga), with a concentration of between about 1019cm-3and 5 x- 1021cm-3, and the S / D epi liner 312 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 5 % and about 25 %, for example, between about 5.5 % and about 6%, lightly doped with p-type dopants such as boron (B) or gallium (Ga), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0084] In the n-MOS region 502N, the S / D epi layer 310 may be formed of epitaxially grown silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between 35 % and 65%, doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1019cm-3and 5 x 1021cm-3, and the S / D epi liner 312 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 5 % and about 25 %, for example, between about 5.5 % and about 6%, lightly doped with n-type dopants such as phosphorus (P),arsenic (As), or antimony (Sb), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0085] The method 400 starts with block 402, in which the lithography process in block 202, the lithography and etch process in block 204, the placeholder removal process in block 206, the sidewall nitridation process in block 208, and the bottom-up deposition process in block 210 are performed to deposit a bottom layer 322 on bottom surfaces 324 of the S / D recesses 318 in both the p-MOS region 502P and the n-MOS region 502N, as shown in Figure 5A. The bottom layer 322 may be silicon oxide (SiO2).

[0086] In block 404, the blocking nitride deposition process in block 212 is performed to deposit a blocking nitride layer 326 on exposed inner surfaces of the S / D recess 318 and on the bottom layer 322 on the mask 316 in both the p-MOS region 502P and the n-MOS region 502N, as shown in Figure 5B.

[0087] In block 406, an n-side masking process is performed to cover exposed surfaces of the n-MOS region 502N with an n-side blocking mask 504N, as shown in Figure 5C. Subsequently the nitride bottom open etch process in block 214 is performed to remove a portion of the blocking nitride layer 326 at the bottom of the S / D recess 318 and leave a protection layer 328 on the shoulder portions 318S (shown in Figure 3C) of the S / D recess 318 in the p-MOS region 502P, as shown in Figure 5C. The protection layer 328 is silicon nitride (SisN4). The n-side blocking mask 504N may be formed of aluminum oxide (AI2O3), spin-on carbon, or spin-on silicon oxide (SiO2).

[0088] The n-side masking process may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0089] In block 408, the bottom layer removal process in block 218 is performed to remove the bottom layer 322 in the p-MOS region 502P, and subsequently the n-side blocking mask 504N is removed by ashing or wet etching, as shown in Figure 5D. Subsequently, the nitride bottom open etch process in block 214 is performed to remove a portion of the blocking nitride layer 326 at the bottom of the S / D recess 318 and leave a protection layer 328 on the shoulder portions 318S (shown in Figure 3C) of the S / D recess 318 in the n-MOS region 502N, as shown in Figure 5D. The protection layer 328 is silicon nitride (SisN4).

[0090] In block 410, the cavity etch process in block 220 is performed to form a cavity 330 into the S / D epi liner 312 and the S / D epi layer 310 within the S / D recess 318 in the p-MOS region 502P, as shown in Figure 5E. Simultaneously, the blocking nitride layer 326 at the bottom of the S / D recess 318 and the bottom layer 322 on the mask 316 is removed.

[0091] In block 412, a contact formation process is performed to form a contact epi layer 506 within the cavity 330 in the p-MOS region 502P, as shown in Figure 5F.

[0092] The contact epi layer 506 is formed as an interface between the S / D epi layer 310 and a metal fill to be formed within the S / D recess 318, to minimize parasitic resistance. The contact epi layer 506 is formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between 25% and 65%, doped with p-type dopants such as boron (B) or gallium (Ga), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3, with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0093] The contact formation process may include a pre-clean process and a selective epitaxial deposition process. The pre-clean process may be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1. The selective epitaxial deposition process includes an epitaxial deposition process and an etch process, performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0094] The epitaxial deposition process may use a deposition gas including a silicon-containing precursor, a germanium containing precursor, and a dopant source. The silicon-containing precursor may include disilane (Si2He), silane (SiH4), tetrasilane (Si4H ), or a combination thereof. The germanium-containing precursor may include germane (GeF ), germanium tetrachloride (GeCk), and digermane (Ge2He). The dopant source may include, for example, boron, or gallium, depending upon the desired conductive characteristic of the contact epi layer 506. The dopant source may include a precursor diborane (B2H6).

[0095] The etch process may use an etching gas that includes an etchant gas and a carrier gas. The etchant gas may include halogen-containing gas, such as hydrogen chloride (HCI), chlorine (CI2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0096] The contact formation process may be performed at a low temperature less than about 400°C and at a pressure of between 5 Torr and 600 Torr. A cycle of the epitaxial deposition and etch processes may be repeated as needed to obtain a desired thickness of the contact epi layer 506. A thickness of the contact epi layer 506 may be between about 10 A and about 100 A.

[0097] In block 414, a liner deposition process is performed to deposit a liner 508 on exposed surfaces of both the p-MOS region 502P and the n-MOS region 502N, as shown in Figure 5G. The liner 508 may be formed of aluminum oxide (AI2O3). The liner deposition process may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0098] In block 416, a p-side masking process is performed to cover exposed surface of the p-MOS region 502P with a p-side blocking mask 504P, as shown in Figure 5I. The p-side blocking mask 504P may be formed of aluminum oxide (AI2O3), spin-on carbon, or spin-on silicon oxide (SiO2).

[0099] The p-side masking process may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0100] In block 418, the cavity etch process in block 220 is performed to form a cavity 330 into the S / D epi liner 312 and the S / D epi layer 310 in the n-MOS region 502N, and subsequently the p-side blocking mask 504P is removed by ashing or wet etching as shown in Figure 5J. Simultaneously, the liner 508 in the n-MOS region 502N is removed.

[0101] In block 420, a liner removal process is performed to remove the liner 508 in the p-MOS region 502P, as shown in Figure 5K. The liner removal process may include any appropriate wet etching.

[0102] In block 422, the backside contact formation process in block 222 is performed to form a backside contact from the backside of the substrate 304 to the S / D epi layer 310, including a barrier layer 332 and metal fill 334, in both the p-MOS region 502P and n-MOS region 502N, as shown in Figure 5L.

[0103] Figure 6 depicts a process flow diagram of a method 600 of forming a semiconductor structure 700 that may form a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET), according to athird embodiment of the present disclosure. In the semiconductor structure 700, a contact epi layer is formed in both a p-channel MOS (p-MOS) transistor region and an n-channel MOS (n-MOS) transistor region. Figures 7A, 7B, 7C, 7D, 7E, 7F, 7G, and 7H are cross-sectional views of a portion of the semiconductor structure 700, corresponding to various states of the method 600. It should be understood that Figures 7A, 7B, 7C, 7D, 7E, 7F, 7G, and 7H illustrate only partial schematic views of the semiconductor structure 700, and the semiconductor structure 700 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method illustrated in Figure 6 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0104] As shown in Figure 7A, the semiconductor structure 700 includes a p-MOS region 502P and an n-MOS region 502N. Each of the p-MOS region 502P and the n-MOS region 502N includes a fin-shaped column 302 formed on a front side of a substrate 304. The fin-shaped column 302 includes a stack of alternating channel layers 306 and replacement-metal-gate (RMG) stacks 308 in the Z direction. Through the fin-shaped column 302, a source / drain (S / D) region including an S / D epi layer 310 (also referred to as an “L2 layer”) and an S / D epi liner 312 (also referred to as an “L1 layer”) surrounding the S / D epi layer 310 is formed.

[0105] In the p-MOS region 502P, the S / D epi layer 310 may be formed of epitaxially grown silicon (Si) doped with p-type dopants such as boron (B) or gallium (Ga), with a concentration of between about 1019cm-3and 5 x- 1021cm-3, and the S / D epi liner 312 may be formed of silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between about 5 % and about 25 %, for example, between about 5.5 % and about 6%, lightly doped with p-type dopants such as boron (B) or gallium (Ga), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0106] In the n-MOS region 502N, the S / D epi layer 310 may be formed of epitaxially grown silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between 35 % and 65%, doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1019cm-3and 5 x 1021cm-3, and the S / D epi liner 312 may be formed of silicon germanium (SiGe) with a ratio ofgermanium (Ge) ranging between about 5 % and about 25 %, for example, between about 5.5 % and about 6%, lightly doped with n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0107] The method 600 starts with block 602, in which the processes in blocks 402-412 are performed to form a contact epi layer 506 within of the cavity 330 in the p-MOS region 502P, as shown in Figure 5F.

[0108] In block 604, a recess fill process is performed to fill the S / D recesses 318 with a plug fill layer 702, as shown in Figure 7A. The plug fill layer 702 may be formed of aluminum oxide (AI2O3). The recess fill process may include any appropriate deposition process, such as chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0109] In block 606, a plug fill etch back process is performed to remove an overfill portion of the plug fill layer 702, as shown in Figure 7B. The plug fill etch back process may include a wet etch or dry etch process.

[0110] In block 608, the p-side masking process in block 416 is performed to cover exposed surface of the p-MOS region 502P with a p-side blocking mask 504P, as shown in Figure 7C.

[0111] In block 610, a plug fill pull out process is performed to remove the plug fill layer 702 in the S / D recess 318 in the n-MOS region 502, as shown in Figure 7D. Subsequently, the p-side blocking mask 504P is removed by ashing or wet etching.

[0112] In block 612, the cavity etch process in block 220 is performed to form a cavity 330 into the S / D epi liner 312 and the S / D epi layer 310 in the n-MOS region 502N, as shown in Figure 7E. Simultaneously, the plug fill layer 702 in the p-MOS region 502P is partially removed.

[0113] In block 614, the contact formation process in block 412 is performed to form a contact epi layer 506 within of the cavity 330 in the n-MOS region 502N, as shown in Figure 6F.

[0114] The contact epi layer 506 is formed as an interface between the S / D epi layer 310 and a metal fill to be formed within the S / D recess 318, to minimize parasitic resistance. The contact epi layer 506 is formed of epitaxially grown silicon (Si), dopedwith n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb), with a concentration of between about 1 x 1018cm-3and 5 x 1021cm-3.

[0115] In block 616, a plug fill removal process is performed to remove the plug fill layer 702 in the p-MOS region 502P, as shown in Figure 7G. The plug fill removal process may include any appropriate wet etch process.

[0116] In block 618, the backside contact formation process in block 222 is performed to form a backside contact from the backside of the substrate 304 to the S / D epi layer 310, including a barrier layer 332 and metal fill 334, in both the p-MOS region 502P and n-MOS region 502N, as shown in Figure 7H.

[0117] The embodiments described herein provide methods for forming a semiconductor structure for backside power delivery for a gate-all-around field-effect transistor (GAA FET). In the methods described herein, a recess is formed by direct lithography and etch on a backside of a substrate to be aligned with a placeholder formed on a front side of the substrate, where the recess has a larger critical dimension (CD) than the placeholder. Shoulder portions generated by the direct lithography and etch within the recess are protected during subsequent integration processing steps, such that the risk of shorting to a gate is eliminated.

[0118] It should be noted that the methods described herein can be applied to devices other than gate-all-around field-effect transistor (GAA FET) devices, such as forksheet transistor devices and complementary field-effect transistor (CFET) devices.

[0119] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:

1. A method of forming a contact to a source / drain (S / D) region of a semiconductor structure, comprising:forming a sidewall nitride layer on inner surfaces of an S / D recess that is aligned with the S / D region;depositing a bottom layer on a bottom surface of the S / D recess;forming a protection layer on shoulder portions of the S / D recess; removing the bottom layer; andforming the contact to the S / D region within the S / D recess.

2. The method of claim 1, wherein the sidewall nitride layer comprises silicon nitride (SisN4).

3. The method of claim 1 , wherein:forming the sidewall nitride layer comprises a plasma treatment process; and depositing the bottom layer comprises a directional selective fill process.

4. The method of claim 1 , wherein:the bottom layer comprises silicon oxide (SiC>2), andforming the protection layer comprises:depositing a blocking nitride layer on exposed inner surfaces of the S / D recess; andremoving a portion of the blocking nitride layer at the bottom of the S / D recess and leaving the protection layer on the shoulder portions of the S / D recess.

5. The method of claim 4, wherein the blocking nitride layer and the protection layer each comprise silicon nitride (SisN4).

6. The method of claim 1 , wherein:the bottom layer comprises carbon, andforming the protection layer comprises selectively depositing the protection layer on the shoulder portions of the S / D recess.

7. The method of claim 6, wherein the protection layer comprises silicon nitride (SisN4) or aluminum oxide (AI2O3).

8. The method of claim 1 , wherein:the S / D region is formed on a front side of a substrate, andthe contact is formed from a backside of the substrate.

9. A method of forming a contact to a source / drain (S / D) region of a semiconductor structure, comprising:forming an S / D recess that is aligned with a placeholder and the S / D region formed on a substrate;forming a sidewall oxide layer on inner surfaces of the S / D recess; covering the sidewall oxide layer on shoulder portions of the S / D recess with a bottom layer;removing the sidewall oxide layer not covered by the bottom layer selectively against the bottom layer and leaving a protection layer on the shoulder portions of the S / D recess;removing the bottom layer and the placeholder;forming a sidewall nitride layer on exposed inner surfaces of the S / D recess; removing a portion of the sidewall nitride layer at the bottom the S / D recess; andforming the contact to the S / D region within the S / D recess.

10. The method of claim 9, wherein:the placeholder comprises silicon germanium (SiGe),the sidewall oxide layer comprises silicon nitride (SiC>2),the bottom layer comprises carbon,the sidewall nitride layer comprises silicon nitride (SisN4), andthe protection layer comprises silicon nitride (SiC ).

11. The method of claim 9, wherein:forming the S / D recess comprises an isotropic etch process,forming the sidewall oxide layer comprises directional oxidation process, covering the sidewall oxide layer comprises a directional selective fill process, andforming the sidewall nitride layer comprises a plasma treatment process.

12. The method of claim 9, wherein:the S / D region is formed on a front side of a substrate, andthe contact is formed from a backside of the substrate.

13. A method of forming contacts to source / drain (S / D) regions of a semiconductor structure, comprising:forming a sidewall nitride layer on inner surfaces of a first S / D recess that is aligned with a first S / D region in a p-channel region of the semiconductor structure and a second S / D recess that is aligned with a second S / D region in an n-channel region of the semiconductor structure;depositing a bottom layer on bottom surfaces of the first S / D recess and the second S / D recess;depositing a blocking nitride layer on exposed inner surfaces of the first S / D recess and the second S / D recess;covering exposed surfaces of the n-channel region of the semiconductor structure with a first blocking mask;removing a portion of the blocking nitride layer at the bottom of the first S / D recess and leaving a first protection layer on shoulder portions of the first S / D recess;removing the bottom layer in the first S / D recess;removing the first blocking mask;removing a portion of the blocking nitride layer at the bottom of the second S / D recess and leaving a second protection layer on shoulder portions of the second S / D recess in the second S / D recess;forming a first cavity in the first S / D recess; andforming a first contact epi layer within the first cavity.

14. The method of claim 13, wherein:the sidewall nitride layer comprises silicon nitride (SisN4),the bottom layer comprises silicon oxide (SiC>2),the blocking nitride layer comprises silicon nitride (Si3N4),the first protection layer and the second protection layer each comprise silicon nitride (Si3N4), andthe first contact epi layer comprises silicon germanium (SiGe).

15. The method of claim 13, wherein:forming the sidewall nitride layer comprises a plasma treatment process depositing the bottom layer comprises a directional selective fill process, and forming the first contact epi layer comprises a selective epitaxial deposition process.

16. The method of claim 13, further comprising:forming a liner on exposed inner surfaces of the first S / D recess and the second S / D recess;covering exposed surfaces of the p-channel region of the semiconductor structure with a second blocking mask;forming a second cavity in the second S / D recess;removing the second blocking mask and the liner; andforming the contacts to the first S / D region within the first S / D recess and to the second S / D region within the second S / D recess.

17. The method of claim 16, wherein the liner comprises aluminum oxide (AI2O3).

18. The method of claim 13, further comprising:filling the first S / D recess and the second S / D recess with a plug fill layer; covering exposed surfaces of the p-channel region of the semiconductor structure with a second blocking mask;removing the plug fill layer in the second S / D recess;forming a second cavity in the second S / D recess;forming a second contact epi layer within the second cavity;removing the plug fill layer in the first S / D recess; andforming the contacts to the first S / D region within the first S / D recess and to thesecond S / D region within the second S / D recess.

19. The method of claim 18, wherein:the plug fill layer comprises aluminum oxide (AI2O3), andthe second contact epi layer comprises silicon germanium (SiGe).

20. The method of claim 18, wherein forming the second contact epi layer comprises a selective epitaxial deposition process.

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