Logical to physical translation table adapted to facilitate tracking of data of a storage space of a memory sub-system cached or buffered in a memory space of the memory sub-system

Abstract

A memory sub-system having: memory cells of a first type to provide a memory space; and memory cells of a second type to provide a physical storage space. A controller of the memory sub-system is configured to: store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; store, the memory space, a copy of a data portion addressable in the logical storage space; configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; and store information to identify a location, in the memory space, at which the data portion is cached or buffered.

Description

PCT Application Attorney Docket No. 120426-312101 / WO LOGICAL TO PHYSICAL TRANSLATION TABLE ADAPTED TO FACILITATE TRACKING OF DATA OF A STORAGE SPACE OF A MEMORY SUB-SYSTEM CACHED OR BUFFERED IN A MEMORY SPACE OF THE MEMORY SUB-SYSTEMRELATED APPLICATION

[0001] The present application claims priority to U.S. Pat. App. Ser. No. 19 / 044,094, filed Feb. 3, 2025 and entitled “Logical to Physical Translation Table Adapted to Facilitate Tracking of Data of a Storage Space of a Memory Sub-System Cached or Buffered in a Memory Space of the Memory Sub-System,” the entire disclosure of which is hereby incorporated herein by reference.TECHNICAL FIELD

[0002] At least some embodiments disclosed herein relate to memory systems in general, and more particularly, but not limited to memory sub-systems configured to provide both memory and storage.BACKGROUND

[0003] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0005] FIG. 1 illustrates an example computing system having a host system and a memory sub-system configured in accordance with some embodiments of the present disclosure.

[0006] FIG. 2 shows a memory sub-system having a storage space and a memory space that are both accessible to a host system according to one embodiment.

[0007] FIG. 3 shows a technique of using a storage access request to transfer data between a storage space and a memory space of a memory sub-system according to one embodiment.

[0008] FIG. 4 shows a technique of using a memory access request for data transferred between a storage space and a memory space of a memory sub-system according to one embodiment.

[0009] FIG. 5 to FIG. 7 show techniques to cause a memory sub-system to transfer data between a storage space of the memory sub-system and a memory space of the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system according to some embodiments.

[0010] FIG. 8 shows error correction encoding and decoding for data transfers between a storage space and a memory space of the memory sub-system according to one embodiment.

[0011] FIG. 9 to FIG. 13 show configurations of a memory sub-system having one or more connections to a host system for storage access and memory access according to some embodiments.

[0012] FIG. 14 shows communications to load a portion of data stored at a logical block address in a memory sub-system to a host system according to one embodiment.

[0013] FIG. 15 shows communications to store data from a host system to a logical block address in a memory sub-system according to one embodiment.

[0014] FIG. 16 and FIG. 17 show management of memory in a memory space of a memory sub-system according to one embodiment.

[0015] FIG. 18 shows integrating memory allocation requests in storage access requests according to some embodiments.

[0016] FIG. 19 shows examples of opcodes that can be used in a storage access request according to one embodiment.

[0017] FIG. 20 shows a technique to track locations in a storage space of a memory subsystem having data buffered in a memory space of the memory sub-system according to one embodiment.

[0018] FIG. 21 shows a technique to map an allocated memory block to a logical memory space according to one embodiment.

[0019] FIG. 22 shows a logical to physical mapping configured to facilitate tracking of buffered storage locations in a memory sub-system according to one embodiment.

[0020] FIG. 23 shows mapping of an allocated memory block to a logical block address in a memory sub-system according to one embodiment.

[0021] FIG. 24 shows mapping of an allocated memory block to a logical block address through a predetermined relation between a logical memory space and a logical storage space in a memory sub-system according to one embodiment.

[0022] FIG. 25 and FIG.26 show mapping of an allocated memory block to a logical block address having misalignment with a logical memory region in a memory sub-system according to one embodiment.

[0023] FIG. 27 shows a method to map between physical memory chunks and logical storage blocks in a memory sub-system having data buffered in the physical memory chunks according to one embodiment.

[0024] FIG. 28 shows a method to map between physical memory chunks and logicalPCT Application Attorney Docket No. 120426-312101 / WO memory regions of a predetermined size in a memory sub-system according to one embodiment.

[0025] FIG. 29 shows a method to track memory chunks allocated to buffer data in a storage space based on a predetermined mapping between a logical memory space and a logical storage space in a memory sub-system according to one embodiment.

[0026] FIG. 30 is a block diagram of an example computer system in which embodiments of the present disclosure can operate.DETAILED DESCRIPTION

[0027] At least some aspects of the present disclosure are directed to techniques to facilitate efficient access of a storage space of a memory sub-system at a granularity level smaller than the level of an atomic read or write operation in the memory sub-system in retrieving data from memory cells or programming data into the memory cells.

[0028] A memory sub-system, such as a solid-state drive, can be configured to read or write data in a storage space according to a logical block addressing (LBA) block size. For example, to execute a read command, a solid-state drive retrieves at least one LBA block of data from a page of memory cells via an atomic read operation, in which the solid-state drive senses the states of the memory cells to determine the data stored in the memory cells and, decodes raw data corresponding to the states using an error correction code technique to recover the data stored in the page. To execute a write command, the solid-state drive encodes the data, having the LBA block size and to be programmed into the memory cells of the page, to generate encoded data, and programs the memory cells in the page in an atomic write operation, in which the solid state drive programs the states of the memory cells to represent the encoded data to represent the data being written into the page. The LBA block size is typically 512 bytes or larger (e.g., 4096 bytes) for improved efficiency of the solid-state drive in executing read and write commands.

[0029] However, some applications typically use a small chunk of data stored in an LBA block in a typical computation task. For example, a chunk of 128 bytes of data is typically used at a time for inference computations of an artificial neural network (ANN). It is inefficient to move an entire block of data, according to the LBA block size of 512 bytes or more (e.g., 4096 bytes), from the solid-state drive into the main memory of a processor only for the processor to use a chunk / sub block of 128 bytes of the entire block.

[0030] At least some aspects of the present disclosure address the above and other deficiencies and challenges by configuring a memory sub-system to expose at least a portion of its random access memory for access by a host system. The memory space of the exposed random access memory is configured to be separate and independent from the storage space ofPCT Application Attorney Docket No. 120426-312101 / WO the memory sub-system. The host system can use storage access commands to instruct the memory sub-system to transfer data, according to the LB A block size and within the memory sub-system, between the random access memory of the memory sub-system and the storage space of the memory sub-system. Separately, the host system can use memory access instructions to load data from and / or store data to the exposed memory space of the memory sub-system at a granularity level that is smaller than the LBA block size. Thus, the host system can have the options to use a combination of memory access request and storage access request to retrieve data from and / or store data to the storage space of the memory sub-system by communicating sub blocks of data between the host system and the memory sub-system.

[0031] For example, the random access memory of the memory sub-system can be attached to the host system during a boot time as a memory device such that the host system can load data from and store data to the random access memory using a memory access protocol (e.g., a protocol of compute express link (CXL) or component interconnect express (PCIe)) and / or via executions of load instructions and store instructions. Further, the host system can send a read command to the memory sub-system to read a block of data according to the LBA block size of the memory sub-system into the random access memory of the memory sub-system using a storage access protocol (e.g., non-volatile memory express (NVMe)). During the execution of the read command, the data of the LBA block size is internally retrieved from the storage space of the memory sub-system and copied to the random access memory of the memory sub-system. As a result of the execution of the read command in the memory sub-system, the memory subsystem makes sub blocks of the data accessible to the host system in the random access memory of the memory sub-system without sending the data across the connection between the memory sub-system and the host system.

[0032] Once the data is in the random access memory of the memory sub-system, the host system has choices as to when and whether to load any portions of the data from the random access memory of the memory sub-system to the host system for processing. For example, the host system can use the memory access protocol (e.g., in accordance with CXL or PCIe) to load a selected portion of the data from the random access memory by addressing the selected portion using one or more memory addresses in the random access memory of the memory sub-system. Since the memory access protocol (e.g., CXL protocol) allows accessing the random access memory of the memory sub-system at the granularity level of byte (e.g., one byte, 8 bytes, 16 bytes, 32 bytes, or a cache line of 128 bytes), the host system can load a portion (e.g., sub block) of the block from the random access memory of the memory sub-system when the portion is about to be used in computation. Thus, the host system does not have to allocate a space in its main memory sufficient to hold the entire block of data according to the LBA block size; and thePCT Application Attorney Docket No. 120426-312101 / WO efftciency of the usage of the main memory of the host system is improved. In some cases, at least a portion of the entire block of data is not used in computations performed in the host system in a period of time. Thus, the host system can skip loading such a portion over a connection between the memory sub-system and the host system; and the efficiency of the usage of the communications bandwidth of the connection is improved.

[0033] For example, when the host system is to modify a portion of the data stored as a block according to the LBA block size in the storage space of the memory sub-system, the host system can use a read command to retrieve the block of data into the random access memory of the memory sub-system. Then, the host system can use the memory access protocol (e.g., CXL or PCIe) to store the modified portion of the block into the random access memory, without communications of the remaining portion of the block between the host system and memory sub-system. Subsequently, the host system can use a write command to cause the memory subsystem to write the block of data from the random access memory of the memory sub-system into the storage space of the memory sub-system. Thus, the efficiency of the usages of the main memory of the host system and the communications bandwidth of the connection between the memory sub-system and the host system can be improved.

[0034] For example, consider a scenario of using such a memory sub-artificial intelligence (Al) inference computations. A trained artificial neural network (ANN) model can be used to make inference / predictions. Inference / prediction computations can have many tasks running in parallel on different graphical processing unit (GPU) cores. There can be over a hundred GPUs in a cluster, where each GPU can have hundreds or more of cores. Potentially, there can be over 10,000 or so inference processes running in parallel, each running in a separate GPU core to access a different part of the memory sub-system (e.g., solid-state drive (SSD)) storing the AV ANN model. Each part being accessed can be smaller than the LBA block size. The memory sub-system can be configured to support a large number of parallel commands coming from the inference processes running in the GPU cores. After an LBA block is read from an LBA address to the random access memory of the memory sub-system, an inference / prediction process / thread running in a GPU core can load the small portion that is to be used in its computation into the high bandwidth memory (HBM) of the GPU core, eliminating the need to allocate a sufficient space in the HBM to store the entire LBA block and eliminating the transfer of unused portions of the LBA block from the memory sub-system to the HBM of the GPU core. Instead of allocating memory from HBM at the granularity of an LBA block size (e.g., 4 KB) to hold data read from the memory sub-system, the inference / prediction process / thread can allocate memory from HBM at the granularity level of a cache line (e.g., 128 bytes). HBM is an expensive, high-performance resource in GPUs. Optionally, the inference / predictionPCT Application Attorney Docket No. 120426-312101 / WO process / thread can modify, in the HBM, the portion of the LBA block that has been loaded into the HBM of the GPU core; and to store the modified LBA block back to the storage space of the memory sub-system, the inference / prediction process / thread can identify the portion of the block in the HBM via a scatter gather list (SGL) to cause the memory sub-system to combine the portion in the HBM and the unmodified portion in the random access memory of the memory sub-system to write the modified LBA block to the storage space. Avoid loading unused portions of data into HBM can improve and optimize the usages of HBM as a key resource; and the performance of the system can be greatly improved.

[0035] Such a memory sub-system can have backward compatibility with storage access protocols (e.g., NVMe protocol). When the host system is to use an entire block of data according to the LBA block size, the host system can configure and send a read command to cause the memory sub-system to send the data retrieved from the storage space of the memory sub-system to a memory location identified by the host system. For example, the read command can be configured by the host system to identify a location in the main memory of the host system as the destination of the storage access request; and in response, the memory sub-system can send the retrieved data to the main memory of the host system during the execution of the read command such that it is not necessary for the host system to further use memory access protocols to load data from the memory sub-system.

[0036] Optionally, the host system can use the random access memory of the memory subsystem as a buffer to hold data retrieved from the storage space of the memory sub-system for a period of time decided by the host system. During the period of time, the host system can load any portion of the data from the random access memory and / or modify any portion of the data in the random access memory of the memory sub-system. Accessing the random access memory of the memory sub-system using a memory access protocol (e.g., CXL protocol) is much faster than accessing the storage space of the memory sub-system using a storage access protocol (e.g., NVMe protocol). Thus, such a memory sub-system provides the host system with the option to predicatively send read commands to the memory sub-system to retrieve data from the storage space for buffering in the random access memory of the memory sub-system to reduce latency in accessing the data for the processing of the data.

[0037] Optionally, the memory sub-system can be configured to provide a host system with access to both a memory space of the random access memory of the memory sub-system and the storage space of non-volatile memory cells of the memory sub-system via a same connection. The memory space and the storage space are separately addressable by the host system using a memory access protocol and a storage access protocol over the same connection.

[0038] For example, the memory sub-system can be configured with a random accessPCT Application Attorney Docket No. 120426-312101 / WO memory addressable by a host system via a memory access protocol (e.g., compute express link (CXL) over a peripheral component interconnect express (PCIe) connection). The random access memory can be implemented using a fast memory that can be volatile (e.g., dynamic random access memory (DRAM)). The memory sub-system can offer the random access memory as a memory device attachable to the host system during the boot time; and the host system can be configured to add the memory space of the memory device offered by the memory sub-system into its memory map. Thus, the host system can access the random access memory of the memory sub-system in a same way as accessing other memory devices attached to the host system using the memory access protocol (e.g., CXL).

[0039] The memory sub-system can be further configured with a storage medium (e.g., NAND memory) addressable by a host system via a storage access protocol (e.g., non-volatile memory express (NVMe) over the peripheral component interconnect express (PCIe) connection). The storage medium is non-volatile and slower than the random access memory.

[0040] The memory sub-system allows a host system to access the memory space and the storage space independently without imposing a predefined relation between the memory space and the storage space. The memory space can be substantially smaller than the storage space. The memory sub-system can provide the host system with complete control over how the memory space is used by the host system. Optionally, the host system can use the memory space in accessing the storage space (e.g., to reduce communications over a computer bus between the memory sub-system and the host system).

[0041] For example, the memory sub-system can receive storage access commands configured to address the storage medium of the memory sub-system. The commands can be provided to the memory sub-system via submission queues configured in cyclic buffers accessible to both the host system and the memory sub-system. For example, the cyclic buffers can be configured in a portion of the main memory of the host system, or in the random access memory of the memory sub-system.

[0042] The storage medium of the memory sub-system is configured to be addressed at the granularity level of the LBA block size that is coarser than the granularity level of addressing the random access memory of the memory sub-system. For example, the storage medium can be accessed at a block level of 4096 bytes or 512 bytes per block. The random access memory can be access at a byte level (e.g., one byte, 16 bytes) or a cache line level (e.g., 128 bytes).

[0043] A storage access command (e.g., a read command or a write command) can be configured to identify a memory address for storing or retrieving data addressed by the storage access command. For example, a read command can specify a memory address as the destination to store the data to be read from the storage medium at a logical block addressingPCT Application Attorney Docket No. 120426-312101 / WO (LBA) address specified by the read command. For example, a write command can identify a memory address as the source where data can be retrieved for writing to the storage medium at a logical block addressing (LB A) address specified by the write command.

[0044] When the memory sub-system is configured to expose at least a portion of its random access memory for accessing by the host system, the host system can optionally configure the memory address, identified in the storage access command, in the random access memory of the memory sub-system. When the storage access command specifies a memory address that is in the random access memory of the memory sub-system, the execution of the storage access command does not involve communicating data over the connection between the host system and the memory sub-system.

[0045] The host system can use the random access memory of the memory sub-system as a staging ground for the data to be read from or written into the storage space of the memory subsystem. For example, the host system can assemble a block of data in the random access memory for writing into the storage medium of the memory sub-system, or prefetch a block of data from the storage medium into the random access memory for selective accessing a portion (e.g., a sub block) of the block. The availability of the staging ground within the memory subsystem can be used to reduce data traffic in the communication connection (e.g., the PCIe connection) between the memory sub-system and the host system in some applications, such as applications involving the computations of an artificial neural network.

[0046] The host system can be configured to access sub blocks of an LB A block in the storage space of the memory sub-system using a combination of storage access commands and memory access instructions. For example, the host system can be configured to allocate a block of random access memory from the memory sub-system and store data one chunk at a time into the allocated block of random access memory. When the block of data is ready in the random access memory for being stored into the storage space of the memory sub-system, the host system can enter a write command in a submission queue for the memory sub-system, where the write command is configured to cause the memory sub-system to write the data from the random access memory to the storage space of the memory sub-system.

[0047] Optionally, the host system can configure a storage access command (e.g., a read command or a write command) to specify a block of memory addresses having a capacity size that is different (e.g., smaller than) from the LBA block size. The memory sub-system can be configured to determine the size mismatch between the block of memory address identified by the storage access command and the data block being addressed via an LBA address specified in the storage access command. In response to a detected size mismatch, the memory sub-system can perform filtering operations and / or read operations accordingly.PCT Application Attorney Docket No. 120426-312101 / WO

[0048] For example, when the capacity size of the block of memory addresses identified in the storage access command is smaller than the LBA size and the storage access command includes an opcode for a write operation, the memory sub-system can perform a read-modify-write operation at the LBA address identified in the storage access command. For example, the memory sub-system can perform a read operation to retrieve the data block currently stored at the LBA address, modify the retrieved data block using the data currently at the block of memory addresses, and write the modified data block to the LBA address. Alternatively, the memory sub-system can use the data currently at the block of memory addresses to modify a block of data having a predetermined value (e.g., zero) to generate the modified data block for writing to the LBA address.

[0049] For example, when the capacity size of the block of memory addresses identified in the storage access command is smaller than the LBA size and the storage access command includes an opcode for a read operation, the memory sub-system can perform a filtering operation on the data read from the LBA address identified in the storage access command to generate the data being stored into the block of memory addresses. For example, the memory sub-system can remove the beginning portion and / or the ending portion of the data block read from the LBA address to generate the data having a size matching the capacity size of the block of memory addresses; the memory sub-system can store the generated data into the block of memory addresses to complete the execution of the storage access command.

[0050] Optionally, when the host system is to write only a portion of an LBA block into the storage space of the memory sub-system, the host system can allocate a block of the random access memory of the memory sub-system according to the LBA block size and send a read command to retrieve the data of the LBA block from the storage space into the allocated block of random access memory of the memory sub-system. Optionally, the read command can also function as a request to allocate the block of the random access memory of the memory subsystem. The host system can then store data to the portion of the block via memory access operations to modify the data of the LBA block in the random access memory. Subsequently, the host system can send a write command to cause the memory sub-system to write the modified block of data from the random access memory of the memory sub-system to the storage space of the memory sub-system. Optionally, the write command can function as a request to free the block of the random access memory allocated as the staging ground for the modified block of data.

[0051] To retrieve a sub block from the storage space of the memory sub-system, the host system can configure a read command to cause the memory sub-system to read a block (e.g., 4096 bytes or 512 bytes) of data into a block of the random access memory of the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system as a staging ground. Subsequently, the host system can execute one or more load instructions to fetch one or more portions of the block from the staging ground into its memory, such as a high bandwidth memory (HBM) in a graphics processing unit (GPU).

[0052] To write a block of data having the LBA block size to the storage space of the memory sub-system, the host system can execute store instructions to build up the block of data, one sub block a time, in the random access memory in the memory sub-system as a staging ground. After the completion of building the block of data, the host system can configure a write command to cause the memory sub-system to write the block of data from the staging ground in the memory sub-system into the storage space of the memory sub-system.

[0053] To write a sub block to the storage space of the memory sub-system, the host system can configure a read command to cause the memory sub-system to read a block (e.g., 4096 bytes or 512 bytes) of data, according to the LBA block size, into the random access memory of the memory sub-system as a staging ground. Then, the host system can execute one or more store instructions to modify one or more portions of the block in the staging ground. Then, the host system can configure a write command to cause the memory sub-system to write the modified block into the storage space of the memory sub-system.

[0054] Optionally, the memory sub-system can be configured to have multiple, separate connections to the host system such that the host system and the memory sub-system can use the connections in parallel for concurrent storage access communications and memory access communications.

[0055] For example, a first interface of the memory sub-system can provide a first connection between a host system and the memory sub-system to allow the host system to access the memory space of the memory sub-system; and a second interface of the memory subsystem can provide a second connection between the host system and the memory sub-system to allow the memory sub-system to access a memory of the host system. For example, while the first connection is being used by the host system to retrieve or modify a sub block of data in the memory space of the memory sub-system, the second connection can be used concurrently by the memory sub-system to retrieve a command from a submission queue configured in the memory of the host system, or write a completion record in a completion queue configured in the memory of the host system, or to retrieve data from (or store data to) the memory of the host system during execution of a write (or read) command that specifies a memory address in the memory of the host system as the data source (or destination).

[0056] Optionally, a random access memory external to the memory sub-system and the host processor can be used as the staging ground. For example, the memory sub-system can be configured with a first interface to access a random access memory outside of the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system. The random access memory can be provided by a memory device having random access memory cells and connected to the first interface of the memory sub-system (e.g., via a CXL connection and / or a CXL fabric). The memory sub-system can access the random access memory via a memory access protocol (e.g., compute express link (CXL)). The host processor can be configured to access the random access memory of the memory device (e.g., via another CXL connection and / or the CXL fabric) without going through any interface of the memory sub-system. The memory sub-system is configured with a storage medium (e.g., NAND memory) addressable by the host system via a storage access protocol (e.g., non-volatile memory express (NVMe)). To provide the host processor with access to the storage medium, the memory sub-system is configured with a second interface for a separate connection to the host processor.

[0057] For example, the memory sub-system can be configured to obtain, through the second interface, storage access commands from submission queues configured in cyclic buffers accessible to both the host system and the memory sub-system. For example, the cyclic buffers can be configured in a portion of the main memory of the host system, or in the random access memory of the memory device located outside of the memory sub-system, or in the memory space of the memory sub-system. The storage medium of the memory sub-system is configured to be addressed at a granularity level that is coarser than the random access memory. For example, the storage medium can be addressed at the LB A block size of 4096 bytes or 512 bytes. The random access memory is configured to be access at a byte level (e.g., one byte, 8 bytes, 16 bytes, 32 bytes), or at a cache line level (e.g., 128 bytes).

[0058] A storage access command (e.g., a read or write command) can identify a memory address for storing data to, or retrieving data from, a memory address identified by the storage access command. For example, a read command can specify the memory address as the destination to store the data to be read from the storage medium at a logical block addressing (LB A) address specified by the read command. For example, a write command can identify the memory address as the source where data can be retrieved for writing to the storage medium at a logical block addressing (LB A) address specified by the write command. The memory address identified in the storage access command can be optionally in the random access memory of the memory device located outside of the memory sub-system. While the memory sub-system is executing such a storage access command, the memory sub-system can use the first interface to store data to (or load data from) the memory device outside of the memory sub-system and concurrently using the second interface to retrieve another storage access command from a submission queue (or store a completion record for another storage access command to a completion queue) in the main memory (or another memory device located outside of thePCT Application Attorney Docket No. 120426-312101 / WO memory sub-system).

[0059] For example, a CXL or PCIe fabric can be used to connect a plurality of memory devices, the memory sub-system, and a host processor. The host processor can use the random access memory of the memory sub-system and / or the random access memory of the memory devices as a staging ground to assemble a block of data to be written into the storage medium of the memory sub-system, or to prefetch a block of data for selective accessing a portion of the block. Optionally, the host processor can also configure a submission queue and / or a completion queue for the memory sub-system in the random access memory of the memory subsystem and / or the random access memory of the memory devices. Such usages of the random access memory on a CXL or PCIe fabric can reduce the traffic to and / or from the main memory of the host processor, and / or improve the usage of the bandwidth of the main memory of the host processor (e.g., in applications involving an artificial neural network).

[0060] FIG. 1 illustrates an example computing system 100 that includes a memory subsystem 101 in accordance with some embodiments of the present disclosure. The memory subsystem 101 can include media, such as one or more volatile memory devices (e.g., memory device 104), one or more non-volatile memory devices (e.g., memory device 103), or a combination of such.

[0061] In general, a memory sub-system 101 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded multimedia controller (eMMC) drive, a universal flash storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of nonvolatile dual in-line memory module (NVDIMM).

[0062] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an internet of things (loT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes memory and a processing device.

[0063] The computing system 100 can include a host system 102 that is coupled to one or more memory sub-systems 101. FIG. 1 illustrates one example of a host system 102 coupled to one memory sub-system 101. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.PCT Application Attorney Docket No. 120426-312101 / WO

[0064] For example, the host system 102 can include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., controller 116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 102 uses the memory sub-system 101, for example, to write data to the memory sub-system 101 and read data from the memory sub-system 101.

[0065] The host system 102 can be coupled (e.g., over a computer bus 107) to the memory sub-system 101 via a physical host interface 108. Examples of a physical host interface 108 include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fibre channel, a serial attached SCSI (SAS) interface, a double data rate (DDR) memory bus interface, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), a double data rate (DDR) interface, a low power double data rate (LPDDR) interface, a compute express link (CXL) interface, or any other interface. The physical host interface 108 can be used to transmit data between the host system 102 and the memory sub-system 101. The host system 102 can further utilize an NVM express (NVMe) interface to access components (e.g., memory devices 103) when the memory sub-system 101 is coupled with the host system 102 by the PCIe interface. The physical host interface 108 can provide an interface for passing control, address, data, and other signals between the memory sub-system 101 and the host system 102. FIG. 1 illustrates a memory sub-system 101 as an example. In general, the host system 102 can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0066] The processing device 118 of the host system 102 can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some instances, the controller 116 can be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls the communications over a bus coupled between the host system 102 and the memory sub-system 101. In general, the controller 116 can send commands or requests to the memory sub-system 101 for desired access to memory devices 103, 104. The controller 116 can further include interface circuitry to communicate with the memory sub-system 101. The interface circuitry can convert responses received from the memory sub-system 101 into information for the host system 102.

[0067] The controller 116 of the host system 102 can communicate with the controller 115PCT Application Attorney Docket No. 120426-312101 / WO of the memory sub-system 101 to perform operations such as reading data, writing data, or erasing data at the memory devices 103, 104 and other such operations. In some instances, the controller 116 is integrated within the same package of the processing device 118. In other instances, the controller 116 is separate from the package of the processing device 118. The controller 116 and / or the processing device 118 can include hardware such as one or more integrated circuits (ICs) and / or discrete components, a buffer memory, a cache memory, or a combination thereof. The controller 116 and / or the processing device 118 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0068] The memory devices 103, 104 can include any combination of the different types of non-volatile memory components and / or volatile memory components. The volatile memory devices (e.g., memory device 104) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0069] Some examples of non-volatile memory components include a negative-and (or, NOT AND) (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0070] Each of the memory devices 103 can include one or more arrays of memory cells 114. One type of memory cells, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quadlevel cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell. In some embodiments, each of the memory devices 103 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, PLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells 114 of the memory devices 103 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0071] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 103 can be based onPCT Application Attorney Docket No. 120426-312101 / WO any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0072] A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 103 to perform operations such as reading data, writing data, or erasing data at the memory devices 103 and other such operations (e.g., in response to commands scheduled on a command bus by controller 116). The controller 115 can include hardware such as one or more integrated circuits (ICs) and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0073] The controller 115 can include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 101, including handling communications between the memory sub-system 101 and the host system 102.

[0074] In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system 101 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory sub-system 101 does not include a controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

[0075] In general, the controller 115 can receive commands or operations from the host system 102 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 103. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block addressPCT Application Attorney Docket No. 120426-312101 / WO (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 103. The controller 115 can further include host interface circuitry to communicate with the host system 102 via the physical host interface 108. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 103 as well as convert responses associated with the memory devices 103 into information for the host system 102.

[0076] The memory sub-system 101 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 101 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controller 115 and decode the address to access the memory devices 103.

[0077] In some embodiments, the memory devices 103 include local media controllers 105 that operate in conjunction with the memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 103. An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 103 (e.g., perform media management operations on the memory device 103). In some embodiments, a memory device 103 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 105) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0078] The controller 115 and / or a memory device 103 can include an access manager 113 configured to perform operations related to accessing a storage space of the memory sub-system 101. In some embodiments, the controller 115 in the memory sub-system 101 includes at least a portion of the access manager 113. In other embodiments, or in combination, the controller 116 and / or the processing device 118 in the host system 102 includes at least a portion of the access manager 113. For example, the controller 115, the controller 116, and / or the processing device 118 can include logic circuitry implementing the access manager 113. For example, the controller 115, or the processing device 118 (processor) of the host system 102, can be configured to execute instructions stored in memory for performing the operations of the access manager 113 described herein. In some embodiments, the access manager 113 is implemented in an integrated circuit chip disposed in the memory sub-system 101. In other embodiments, the access manager 113 can be part of firmware of the memory sub-system 101, an operating system of the host system 102, a device driver, or an application, or any combination therein.

[0079] For example, the access manager 113 implemented in the controller 115 and / or 105 of the memory sub-system 101 can be configured to expose a portion of the random accessPCT Application Attorney Docket No. 120426-312101 / WO memory (e.g., local memory 119 and / or a subset of the memory devices 103 to 104) as a memory device attachable to the host system 102 during a boot time of the computing system 100. The memory space of the exposed portion of the random access memory can be added to the memory map of the host system 102 such that the memory controller 116 can access the memory space according to a standard for memory access (e.g., compute express link (CXL)) in response to execution of memory access instructions (e.g., store instructions, load instructions) in the processing device 118. The access manager 113 implemented in the computing system 100 can be configured to facilitate the access of the storage space provided by the non-volatile memory cells (e.g., 114 in one or more of the memory devices 103 to 104) using the memory space as a staging ground, as further discussed below. Alternatively, a memory device configured outside of the memory sub-system 101 can accessible via the host interface(s) 108 of the memory sub-system 101 can be used as the staging ground and / or a buffer memory for the storage space.

[0080] FIG. 2 shows a memory sub-system having a storage space and a memory space that are both accessible to a host system according to one embodiment. For example, the memory sub-system 101 in the computing system 100 of FIG. 1 can be implemented in a way as illustrated in FIG. 2.

[0081] In FIG. 2, the memory sub-system 101 includes a memory space 121 and a storage space 131 that is separate from the memory space 121. There is no overlapping area between the memory space 121 and the storage space 131.

[0082] For example, the memory space 121 can be implemented using memory cells 114 provided in a first subset of memory devices 103, ..., 104 configured within the memory subsystem 101; and the storage space 131 can be implemented using memory cells in a second subset of the memory devices 103, ..., 104. For example, there is no overlapping between the first subset and the second subset in some implementations.

[0083] For example, the first subset of the memory devices 103, ..., 104 can have random access memory cells 123 operable and / or accessible at granularity of a smaller data size 125 (e.g., one byte, 16 bytes, or a cache line of 128 bytes). The second subset of the memory devices 103, ..., 104 can have memory cells 114 configured as memory pages (e.g., 133) operable and / or accessible at granularity of a larger data size 135 (e.g., 512 bytes, or 1024 bytes, or 4096 bytes). For example, the capacity of the memory space 121 can be a fraction of the capacity of the storage space 131.

[0084] For example, the random access memory cells (e.g., 123) used to implement the memory space 121 can be volatile and faster in access than the memory pages (e.g., 133) used to implement the storage space 131. For example, the random access memory cells (e.g., 123) canPCT Application Attorney Docket No. 120426-312101 / WO be dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), or static random access memory (SRAM), etc.

[0085] For example, the memory cells 114 used to implement the memory pages (e.g., 133) in the storage space 131 can be non-volatile and slower in access than the random access memory cells (e.g., 123). For example, the memory pages (e.g., 133) can be implemented using flash memory (e.g., NAND memory, NOR memory).

[0086] A smallest portion of the memory space 121 that can be addressed by a host system (e.g., 102) for access using a load or store instruction and a memory address (e.g., 124) can be configured to have the data size 125. A memory address (e.g., 124) represents a unit of data storage capacity of the predetermined data size 125 in the memory space 121. The memory space 121 can be physically subdivided into units of the same predetermined data size 125 for addressing using memory addresses (e.g., 124). When a memory address 124 is provided for loading data from or for storing data into the memory space 121, the memory sub-system 101 can determine the unit of random access memory cells (e.g., 123) identified by the memory address (e.g., 124) without using a look up table. The memory address 124 can be fixedly associated with a unit of random access memory cells 123 in the memory sub-system 101. An operation to store data to the memory address 124 does not result in a change in the unit of random access memory cells 123 represented by the memory address 124. A host system (e.g., 102) can use a memory access protocol (e.g., CXL) to load data from, or store data to, the unit of random access memory cells (e.g., 123) represented by the memory address (e.g., 124) over a connection 107 between the host system (e.g., 102) and the memory sub-system 101.Optionally, the memory access protocol can be cache coherent.

[0087] A smallest portion of the storage space 131 that can be addressed by a host system (e.g., 102) for access using a read or write command and a logical block address (e.g., 134) can be configured to have the data size 135. For example, the logical block address (e.g., 134) can be an LBA address as in a standard for storage access protocol (e.g., NVMe). The logical block address (e.g., 134) represents a logical unit of data storage capacity of the predetermined data size 135 in the storage space 131. The storage space 131 is logically subdivided into units of the same predetermined data size 135 for addressing using logical block addresses (e.g., 134). The memory sub-system 101 stores metadata 130 containing a look up table configured to map logical block addresses (e.g., 134) to memory page addresses (e.g., 136). When a logical block address 134 is provided for reading data from or writing data into the storage space 131, the memory sub-system 101 can use the metadata 130 to determine the physical memory page address 136 to perform the read or write operation. To write data to the logical block address 134, the memory sub-system 101 can allocate a fresh memory page that is ready to bePCT Application Attorney Docket No. 120426-312101 / WO programmed to store data (e.g., a memory page of memory cells that are in an erased state), update the metadata 130 to map the logical block address 134 to the address of the allocated memory page, and programmed the memory cells in the allocated memory page to store the data. If the logical block address 134 is previously associated with a memory page address 136, the memory sub-system 101 can update the metadata 130 such that the logical block address 134 is no longer associated with the memory page address 136; and the memory sub-system 101 can further store data indicating that the memory cells at the memory page address 136 can be erased. To read data from the logical block address 134, the memory sub-system 101 uses the metadata 130 to determine the memory page address 136 currently associated with the logical block address 134 and perform operations to sense the states of memory cells in the memory page 133 identified by the memory page address 136 to determine the data represented by the states of the memory cells. Since the mapping between logical block addresses (e.g., 134) and memory page addresses (e.g., 136), as defined in the metadata 130, can change over time (e.g., in response to deletion data from logical block addresses and overwriting data to logical block addresses), a logical block address (e.g., 134) does not always represent a same physical memory page (e.g., 133) at a memory page address (e.g., 136) in the memory sub-system 101. An operation to write data to the logical block address 134 results in a change in the page 133 of non-volatile memory cells (e.g., 114) represented by the logical block address 134.

[0088] A host system (e.g., 102 as in FIG. 1) can use a storage access protocol (e.g., NVMe) to read data from, or write data to, the unit of non-volatile memory cells (e.g., in a memory page 133) currently represented by a logical block address 134 according to the metadata 130 stored in the memory sub-system 101. For example, the host system 102 can enter a read or write command in a cyclic buffer according to an NVMe protocol; and the memory sub-system 101 can retrieve the read or write command from the cyclic buffer for execution. The read command can identify a memory address as the destination for storing the data to be read from a logical block address (e.g., 134) specified in the read command; and the write command can identify a memory address as the source for retrieving of the data to be written to a logical block address (e.g., 134) specified in the write command. The memory sub-system 101 is configured to access the memory address identified in the read or write command during the execution of the read or write command.

[0089] The memory sub-system 101 allows the host system to identify, in a read or write command, a memory address (e.g., 124) that represents a location in the memory space 121 within the memory sub-system 101. When such a read command having a memory address 124 is executed in the memory sub-system 101, the data retrieved from the logical block address 134 as identified in the read command is loaded into the memory space 121 within the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system 101; and none of the data retrieved from the logical block address 134 is communicated to outside of the memory sub-system 101 during the execution of the read command, as further discussed below in connection with FIG.3. As a result, the execution of such a read command is reduced to an internal operation within the memory sub-system 101.

[0090] Similarly, when such a write command having a memory address 124 is executed in the memory sub-system 101, the data to be written into the storage space 131 at the logical block address 134 is retrieved from the memory space 121 within the memory sub-system 101; and none of the data being written to the logical block address 134 is communicated from outside of the memory sub-system 101 during the execution of the write command, as further discussed below in connection with FIG. 3. As a result, the execution of such a write command is reduced to an internal operation within the memory sub-system 101.

[0091] FIG. 3 shows a technique of using a storage access request to transfer data between a storage space and a memory space of a memory sub-system according to one embodiment, such as the memory sub-system 101 of FIG. 2.

[0092] In FIG. 3, a storage access request 137 is sent to the memory sub-system 101 to read data 126, or write data 126 to, a logical block address 134 in the storage space 131 of the memory sub-system 101. The storage access request 137 is configured to identify not only the logical block address 134 in the storage space 131 of the memory sub-system 101, but also a memory address 124 in the memory space 121 in the memory sub-system 101.

[0093] For example, the storage access request 137 can be a read command or a write command configured in accordance with a standard of non-volatile memory express (NVMe). When the storage access request 137 includes an opcode for a read operation, the storage access request 137 represents a read command; and when the storage access request 137 includes an opcode for a write operation, the storage access request 137 represents a write command.

[0094] When the storage access request 137 is a read command, the execution of the read command in the memory sub-system 101 causes the memory sub-system 101 to determine, using the metadata 130, the memory page address 136 that is associated with the logical block address 134 in the metadata 130. Using the memory page address 136, the memory sub-system 101 performs the read operation on the memory page 133 to retrieve the data 126 programmed into the memory cells (e.g., 114) in the memory page 133. For example, the read operation can include applying read voltages to the memory cells (e.g., 114) in the memory page 133 to determine the states of the memory cells (e.g., 114). For example, when a read voltage is applied to a memory cell 114, the memory cell 114 can have a state of allowing more than a threshold amount of current to go through the memory cell 114, or a state of allowing a negligible amount of current to go through the memory cell 114. Optionally, a plurality ofPCT Application Attorney Docket No. 120426-312101 / WO different read voltages can be applied to determine the states of the memory cell 114 at the respective read voltages. The data having been programmed into the memory cell 114 can be determined based on the states of the memory cells 114 at the read voltages. In some implementations, a single memory cell can be programmed to store data having more than one bit.

[0095] After determining the data 126 stored in the memory page 133, the memory subsystem 101 can store the data into a block 120 of random access memory cells (e.g., 123) in the memory space 121. Optionally, the memory sub-system 101 can update the metadata 130 to indicate that the data of the logical block address 134 now resides (or has a cached / buffered version) in the memory space 121 at the memory address 124. The block 120 of memory cells has a plurality of units of memory cells (e.g., 123), where each unit of memory cells (e.g., 123) is represented by one memory address (e.g., 124) in the memory space 121. Thus, the data at one logical block address 134 in the storage space 131 is read internally within the memory subsystem 101 into the memory space 121 at a plurality of memory addresses (e.g., 124).

[0096] The block 120 of random access memory cells used to store the data 126 retrieved from the logical block address 134 can be identified based on the memory address 124 specified in the read command and the data size 135 of the block of data 126 stored in the memory page 133. For example, the block 120 of random access memory cells (e.g., 123) can start with the unit of memory cells 123 at the memory address 124 specified in the storage access request 137. The unit of the memory cells 123 can hold the beginning portion of the data 126 according to the data size 125. Multiple contiguous units of memory cells (e.g., 123) having consecutive memory addresses (e.g., 124) in the memory space 121 can be used to store respective portions of the data 126 retrieved from the logical block address 134.

[0097] Once the data 126 is in the block 120 of random access memory cells (e.g., 123) in the memory space 121, the host system 102 can use a memory access protocol (e.g., compute express link (CXL) or peripheral component interconnect express (PCIe)) to access any portion(s) of the data 126 using one or more of the memory addresses (e.g., 124) in the block 120, without communicating the remaining portion(s) of the block 120 across the connection 107 between the memory sub-system 101 and the host system 102. For example, the host system 102 can use the block 120 of the memory space 121 as a staging ground to buffer the data 126 from the storage space 131 and access the memory space 121 for a selected portion of the data 126 at a time when the selected portion is about to be used in computations. Since the latency of loading data from the memory space 121 is significantly lower than the latency of reading data (e.g., 126) from the storage space 131, the host system 102 can predicatively retrieve data from the storage space 131 into the memory space 121 using the storage accessPCT Application Attorney Docket No. 120426-312101 / WO request 137 and then load one or more portions of the data 126 from the memory space 121 at the time when the portions are need for computation in the host system 102 (e.g., as in FIG. 4)

[0098] Optionally, the host system 102 can use store instructions to store data to one or more portions of the block 120 of random access memory cells (e.g., 123) and thus modify the block of data 126 retrieved from the storage space 131 (e.g., as in FIG. 4). Subsequently, the host system 102 can use a write command to write the modified block of data to the storage space 131.

[0099] When the storage access request 137 is a write command, the execution of the write command in the memory sub-system 101 causes the memory sub-system 101 to program the data 126 in the block 120 of the memory space into a memory page 133 in the storage space 131. For example, if the logical block address 134 is associated with a memory page address 136 prior to the execution of the write command, the memory sub-system 101 can store data to indicate that the memory page 133 at the memory page address 136 can be erased. To execute the write command, the memory sub-system 101 allocates a fresh memory page that is ready for being programmed to store data (e.g., a memory page having memory cells in a state of being erased) and update the metadata 130 to associate the logical block address 134 with the memory page address of the allocated fresh memory page. The memory sub-system 101 can perform the write operation on the allocated fresh memory page such that during a read operation, the states of the memory cells in the memory page as programmed can be sensed to provide the same data 126 as being written via the write operation.

[0100] FIG. 4 shows a technique of using a memory access request for data transferred between a storage space and a memory space of a memory sub-system according to one embodiment.

[0101] For example, after a storage access request 137 (e.g., a read command) is executed in the memory sub-system 101 as in FIG. 3, the data 126 in a logical block address 134 is copied to a block 120 of random access memory cells (e.g., 123, 129) identified via a memory address 124 specified in the storage access request 137. The block 120 of random access memory cells contain a plurality of units of memory cells. Each unit of memory cells (e.g., 123 or 129) has a separate memory address (e.g., 124 or 128). A host system (e.g., 102 as in FIG. 1) can use one of the memory addresses (e.g., 128) in the block 120 to access a respective portion of the data 126 stored in one of the units of memory cells (e.g., 129).

[0102] For example, a processing device 118 in the host system 102 can execute a load instruction to cause a memory controller 116 in the host system 102 to generate a memory access request 127 containing a memory address 128 to load data from the block 120 of memory cells 129 in the memory space 121 to the host system 102. In response to the memory accessPCT Application Attorney Docket No. 120426-312101 / WO request 127 identifying the memory address 128, the memory sub-system 101 can provide data from a respective unit of memory cells 129 represented by the memory address 128 over the connection 107 to the host system 102.

[0103] For example, the memory access request 127 can be in accordance with a standard for compute express link (CXL) or peripheral component interconnect express (PCIe) over a PCIe connection 107 between the host system 102 and the memory sub-system 101.

[0104] In general, the memory access request 127 can specify any of the memory addresses (e.g., 124, 128) in the block 120 of memory cells to access a corresponding portion of the data 126 that is stored in a block of storage space 131 represented by a single logical block address 134. Thus, the combination of storage access request 137 and the memory access request 127 allows the host system 102 to load a sub block of the block of data 126, where the size of the sub block corresponds to the data size 125 for memory access.

[0105] Optionally, the processing device 118 in the host system 102 can execute a store instructions to cause the memory controller 116 to generate a memory access request 127 to store data to the memory address 128. Thus, a sub block of the block of data 126 as in the unit of memory cells 129 in the block 120 can be modified via the memory access request 127.Optionally, the host system 102 can use the block as a staging ground to build and / or modify the entire content in the block 120 such that a subsequent storage access request (e.g., 137 as in FIG. 3) can be used to write the content from the block 120 to a logical block address (e.g., 134) in the storage space 131 of the memory sub-system 101.

[0106] Using the techniques of FIG. 3 and FIG. 4, a host system 102 can efficiently access sub blocks of an LB A block in a storage space 131 configured in the memory sub-system 101 without a need to allocate extra memory in the host system 102 to store the entire LB A block at once and / or without communicating sub blocks of the LB A block that are not going to be used in the computations performed in the host system 102.

[0107] FIG. 5 to FIG. 7 show techniques to cause a memory sub-system to transfer data between a storage space of the memory sub-system and a memory space of the memory subsystem according to some embodiments.

[0108] In FIG. 5, a pair of a submission queue 141 and a completion queue 143 are configured in the memory space 121 of the memory sub-system 101 during a boot time of the computing system 100 containing the host system 102 and the memory sub-system 101.

[0109] For example, the submission queue 141 and the completion queue 143 can be configured as cyclic buffers according to an NVMe standard. The host system 102 can use a memory access protocol to store a storage access request 137 into the submission queue 141. The storage access request 137 can specify a memory address (e.g., 124) and a logical blockPCT Application Attorney Docket No. 120426-312101 / WO address (e.g., 134) as in FIG. 3 for execution by the memory sub-system 101. The memory subsystem 101 can retrieve the storage access request 137 for execution (e.g., as in FIG. 3). Upon completion of the execution of the storage access request 137 (e.g., a read command or a write command as discussed in connection with FIG.3), the memory sub-system 101 can generate a completion record 138 in the completion queue 143. The completion record 138 can identify the completion status of the storage access request 137. The host system 102 can retrieve the completion record 138 from the completion queue 143 using the memory access protocol.

[0110] For example, when the completion record 138 indicates that the read operation of the storage access request 137 is complete, the host system 102 knows that the data 126 is now available in the block 120 of memory cells at a location starting with the memory address 124 specified in the storage access request 137. Thus, a load instruction can be executed subsequently to load a sub block of the data 126 from a memory address (e.g., 128) in the memory space 121.[oni] For example, when the completion record 138 indicates that the write operation of the storage access request 137 is complete, the host system 102 knows that the data 126 is now stored in the logical block address 134 specified in the storage access request 137. Thus, the host system 102 can reuse the block 120 of random access memory cells for other operations, such as building up another block of data, or load data from another logical block address in the storage space 131 into the block 120 in the memory space 121.

[0112] When the submission queue 141 and the completion queue 143 are both configured in the memory sub-system 101 (e.g., as in FIG. 5), it is not necessary to configure the memory sub-system 101 with capabilities to access random access memory outside of the memory subsystem 101.

[0113] In FIG. 6, a pair of a submission queue 141 and a completion queue 143 are configured in the host memory 145 outside of the memory sub-system 101 during a boot time of the computing system 100 containing the host system 102 and the memory sub-system 101. For example, the host memory 145 can be the main memory of the host system 102 and / or the processing device 118 of the host system 102, or another random access memory that is added to the memory map of the host system 102 during the boot time of the computing system 100.

[0114] The memory sub-system 101 is configured to use a memory access protocol (e.g., in accordance with a standard for compute express link (CXL) or peripheral component interconnect express (PCIe) over a PCIe connection 107 between the host system 102 and the memory sub-system 101) to access the host memory 145. For example, the memory sub-system 101 can include a direct memory access (DMA) engine configured to retrieve data from the host memory 145, such as the storage access request 137 provided by the host system 102 in thePCT Application Attorney Docket No. 120426-312101 / WO submission queue 141 (e.g., to specify a memory address 124 and a logical block address 134 in a way as in FIG.3). As in FIG. 5, after the completion of the execution of the storage access request 137 in the memory sub-system 101, the memory sub-system 101 can use the memory access protocol to enter a completion record 138 in the completion queue 143.

[0115] In FIG. 7, the submission queue 141 for storage access requests (e.g., 137) having memory addresses (e.g., 124) in the memory space 121 and / or logical block addresses (e.g., 134) in the storage space 131 is configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5); and the completion queue 143 is configured in a host memory 145 (e.g., as in FIG. 6) When the memory sub-system 101 detects the writing of a storage access request 137 into the submission queue 141 configured in the memory space 121 of the memory subsystem 101, the memory sub-system 101 can retrieve the request 137 in response, which arrangement can reduce or eliminated the need for the memory sub-system 101 to poll the submission queue 141 regularly to determine whether there is a pending request in the submission queue 141. Similarly, when the host system 102 detects the writing of a completion record 138 in the completion queue 143, the host system 102 can retrieve the record 138 in response, which arrangement can reduce or eliminated the need for the host system 102 to poll the completion queue 143 to determine whether there is a record in the completion queue 143.

[0116] FIG. 8 shows error correction encoding and decoding for data transfers between a storage space and a memory space of the memory sub-system according to one embodiment. For example, the data transfer between a storage space 131 and a memory space 121 as discussed in connection with FIG. 3 to FIG. 7 can include the error correction operations of FIG. 8

[0117] In FIG. 8, a codeword 155 includes user data 151 and redundant data 153. The codeword 155 is stored as the data 126 in a memory page 133 that corresponds to a logical block address 134 according to metadata 130. When the memory sub-system 101 performs a read operation on the memory page 133 to determine the data 126 via sensing the states of memory cells in the memory page 133, the result of the sensing operation can have one or more random bit errors in the portion representing the user data 151 and / or the portion representing the redundant data 153.

[0118] An error correction code circuit 159 of the memory sub-system 101 can perform a decoding operation of an error correction code technique (e.g., low-density parity-check (LDPC)) to detect the random bit errors and correct the errors to recover an error-free version of the user data 151 into the block of random access memory cells 120 in the memory space 121.

[0119] The decoding operation is configured to operate the retrieved version of the data 126 or codeword 155 retrieved from the memory page 133 as a whole. The memory sub-system 101PCT Application Attorney Docket No. 120426-312101 / WO and / or the error correction code circuit 159 cannot perform the decoding operation on a portion of the data 126 or codeword 155 to recover an error-free version of only a portion of the user data 151. Thus, to determine an error-free version of any portion of the user data 151 stored in the storage space 131, the entire codeword 155 is sensed and decoded to store the error-free version of the user data 151 in the memory space 121.

[0120] The memory cells (e.g., DRAM or SDRAM cells) used to implement the memory space 121 can be more reliable in data storage and retrieval than the memory cells (e.g., NAND or NOR cells) used to implement the storage space 131. Thus, the block 120 of random access memory cells can be configured to store the user data 151 but not the redundant data 153.

[0121] Optionally, an error detection and / or correction technique can also be used to detect and / or correct random bit errors in data retrieved from the memory space 121. However, the error detection and / or correction technique can be applied separately for different portions 157, ... ., 158 of the user data 151 stored in the memory space 121, such that the decoding is not dependent on the retrieval of the user data 151 from the block 120 of the random access memory cells as a whole. Instead, the error detection and / or correction technique can be applied to any of the portions 157, ..., 158 of the user data 151. The portions 157, ..., 158 of the user data 151 at the memory addresses 124, ..., 128 respectively can be retrieved separately with error detection and / or correction. Thus, the memory sub-system 101 can retrieve a portion (e.g., 157 or 158) of the user data 151 according to a memory address (e.g., 124 or 128) without retrieving other portions of the user data 151 from the memory space 121.

[0122] To write the user data 151 in the memory space 121 to the storage space 131 at the logical block address 134, the error correction code circuit 159 can perform an encoding operation of the error correction code technique (e.g., low-density parity-check (LDPC)) to generate the codeword 155 containing both the user data 151 and the redundant data 153. The memory cells in the memory page 133 are programmed to have states representing the bits of the codewords 155.

[0123] The user data 151 can have the data size 135 representative of the capacity to store data for a user at a logical block address 134 in the storage space 131. Each portion (e.g., 157 or 158) of the user data 151 can have the data size 125 representative of the capacity to store data for a user at a memory address (e.g., 124 or 128) in the memory space 121. The data size 135 can be configured as a predetermined multiple of the data size 125. For example, the data size 135 can be 512 bytes, 1024 bytes, 2048 bytes, or 4096 bytes; and the data size 125 can be one byte, 8 bytes, 16 bytes, 32 bytes, 64 bytes, or 128 bytes.

[0124] FIG. 9 to FIG. 13 show configurations of a memory sub-system having one or more connections to a host system for storage access and memory access according to somePCT Application Attorney Docket No. 120426-312101 / WO embodiments. For example, the memory sub-system 101 in FIG. 1 to FIG. 8 can be configured with one or more host interfaces according to any of FIG. 9 to FIG. 13.

[0125] A typical host system (e.g., 102 in FIG. 1 and FIG. 9) can have a memory controller 116 configured to access memory addresses identified as being accessible in a memory map 181. For example, during a boot time, the computing system 100 can determine memory devices (e.g., the main memory of the processing devices 118, host memory 145, and / or the memory space 121 offered by the memory sub-system 101 as a memory device) that are accessible and / or attached to the processing devices 118 in the computing system 100. The memory map 181 can identify the physical memory addresses of the random access memory in the memory devices detected during the boot time of the computing system 100. The memory controller 116 can map the virtual memory addresses used in the processing devices 118 into the physical memory addresses to access memory when the processing devices 118 execute memory access instructions (e.g., load instructions, store instructions) that identify the virtual memory addresses being accessed.

[0126] In FIG. 9, the memory sub-system 101 includes a memory access interface 161 and a storage access interface 163. The memory access interface 161 is connected to the host system 102 via a connection 162; and the storage access interface 163 is connected to the host system 102 via a connection 164 that is separate from the connection 162 to the memory access interface 161.

[0127] The memory access interface 161 can be configured to allow a processing device(s) 118 in the host system 102 to access the memory space 121 efficiently with reduced latency. The processing device(s) 118 in the host system 102 can execute load instructions and store instructions to initiate communications over the connection 162 to the memory access interface 161 to load data from and store data to the memory space 121 using a memory access protocol (e.g., in compliance with a standard of compute express link (CXL), peripheral component interconnect express (PCIe), double data rate (DDR)).

[0128] The storage access interface 163 can be configured to facilitate communicate storage access communications (e.g., in compliance with standard of non-volatile memory express (NVMe)). For example, the connection 164 can be configured to allow the controller 115 (or a direct memory access (DMA) engine) of the memory sub-system 101 to access, via the connection 164, the host memory 145 to receive storage access requests (e.g., 137) from a submission queue (e.g., 141) configured in the host memory 145 (e.g., as in FIG. 6), to provide completion records (e.g., 138) into a completion queue 143 configured in the host memory 145 (e.g., as in FIG. 6 and FIG. 7), to retrieve data from memory addresses that are in the host memory 145 as specified in storage access requests having the opcode for write operations,PCT Application Attorney Docket No. 120426-312101 / WO and / or to provide data to memory addresses that are in the host memory 145 as specified in storage access requests having the opcode for read operations.

[0129] Optionally, the connections 162 and 164 are of different types. For example, in one implementation, the connection 162 is a DDR bus; and the connection 164 is a PCIe bus; and in another implementation, the connection 162 is a PCIe bus or CXL connection; and the connection 164 is a network connection. Optionally, the connection 162 can be configured to have a higher bandwidth and a lower latency in communications than the connection 164.Alternatively, the connections 162 and 164 can be of a same type (e.g., a PCIe or CXL connection) and / or can be used interchangeably for memory access and for storage access.

[0130] Alternatively, the memory access and the storage access can be made using a same interface over a same connection (e.g., a PCIe bus or CXL connection) to the host system 102, as in FIG. 10.

[0131] In FIG. 10, a host interface 108 is configured to allow the processing device(s) 118 (e.g., a CPU, a GPU, a CPU or GPU core, or a system on a chip (SoC), or an Al accelerator) to access the memory space 121 over a connection 107. The processing device(s) 118 can be configured to specify memory addresses (e.g., 124) used in storage access requests (e.g., 137) in the memory space 121. The submission queue 141 and the completion queue 143 can be both configured in the memory space 121 (e.g., as in FIG. 5). Thus, it is not necessary for the memory sub-system 101 to access the host memory 145; and the host memory 145 can be connected to the processing device(s) 118 via a connection 109 that is separate from the connection 107 between the processing device(s) 118 and the memory sub-system 101. For example, the connection 107 can be a PCIe bus, CXL connection, or a DDR bus.

[0132] Alternatively, the memory sub-system 101 can be configured to include one or more host interface(s) 108 that can be used by the processing devices 118 to load data from and store data to the memory space 121 and concurrently used by a direct memory access (DMA) engine 147 and / or the controller 115 of the memory sub-system 101 to access the host memory 145, as in FIG. 11, FIG. 12, and FIG. 13

[0133] In FIG. 11, a set of bus connections 149 can be configured to interconnect the processing device(s) 118, the host memory 145, and the host interface(s) 108 of the memory sub-system 101. Since the host interface(s) 108 allows the processing device(s) 118 to load data from and store data to the memory space 121, some submission queues can be configured for the memory sub-system 101 in the memory space 121 of the memory sub-system 101. Optionally, some submission queues and / or completion queues can be configured for the memory subsystem 101 in the host memory 145 outside of the memory sub-system 101. The processing device(s) 118 can configure storage access requests (e.g., 137) to have memory addresses (e.g.,PCT Application Attorney Docket No. 120426-312101 / WO 124) in the memory space 121 or in the host memory 145. Thus, the source of the data to be written into the storage space 131 via write commands can be in the memory space 121 or in the host memory 145 during the execution of the write commands (e.g., storage access requests 137); and the destination of the data to be retrieved from the storage space 131 via read commands can be in the memory space 121 or in the host memory 145 during the execution of the read commands (e.g., storage access requests 137).

[0134] At least one of the host interface(s) 108 in FIG. 11 can be configured to allow the direct memory access engine 147 of the memory sub-system 101 to access the host memory 145 without assistance from the processing devices 118. Thus, the processing device(s) 118 can optionally configure some storage access requests to have memory addresses in the host memory 145. For example, data to be written into the storage space 131 can be in the host memory 145 for the execution of such storage access requests having opcodes for write operations. For example, data to be retrieved from the storage space 131 can be retrieved into the host memory 145 for the execution of such storage access requests having opcodes for read operations.Further, submission queues and / or completion queues for the memory sub-system 101 can be configured in the host memory 145. The controller 115 and / or the direct memory access (DMA) engine 147 can be configured to access the submission queues and / or completion queues that are in the host memory 145.

[0135] In some implementations, the memory sub-system 101 includes multiple host interfaces 108 to allow concurrent access by the processing device(s) 118 to the memory space 121 and by the memory sub-system 101 to the host memory 145. Alternatively, the memory sub-system 101 has a single host interface 108 for a connection (e.g., PCIe or CXL connection) that allows the memory sub-system 101 to the host memory 145 during some time periods and the processing device 118 to access the memory space 121 during other time periods (but not concurrently).

[0136] Optionally, the host interface(s) 108 can be compute express link interface(s) 165 as in FIG. 12

[0137] For example, at least one of the compute express link interface(s) 165 in the memory sub-system 101 in FIG. 12 can be configured to allow the memory space 121 to be attached to the processing device 118 as a memory device; and at least one of the compute express link interface(s) 165 in the memory sub-system 101 in FIG. 12 can be configured to allow the DMA engine 147 and / or the controller 115 of the memory sub-system 101 to access at least a portion of the host memory 145. In some implementations, the memory sub-system 101 is configured with a single compute express link interface 165.

[0138] In some implementations, the compute express link interface(s) 165 can be connectedPCT Application Attorney Docket No. 120426-312101 / WO to a compute express link (CXL) fabric 169 to allow the memory sub-system 101 to access other memory devices connected to the CXL fabric 169, as in FIG. 13.

[0139] The host memory 145 in FIG. 13 can include a main memory 146 connected to the processing device(s) 118 via a memory bus 109 (e.g., DDR memory bus). The host memory 145 can further include one or more memory devices 167, ..., 168 configured outside of the memory sub-system 101 and connected to the memory sub-system 101 and the processing device(s) 118 via a compute express link (CXL) fabric 169. The CXL fabric 169 can interconnect the memory devices 167, ..., 168, the memory sub-system 101, and the processing device(s) 118 to allow both the memory sub-system 101 and the processing device(s) 118 to access the memory devices 167, ..., 168 concurrently.

[0140] For example, during the boot time of the computing system 100 containing the CXL fabric 169, the memory space 121 can be identified as one of the memory devices connected to the CXL fabric 169 and thus accessible to the processing device 118 using a memory access protocol of CXL. Thus, the physical memory addresses in the memory space 121 in the memory sub-system 101 and in the memory devices 167, ..., 168 can be added to the memory map 181 of the memory controller 116 of the processing device(s) 118. Optionally, one or more of the memory devices 167, ..., 168 can each corresponding to a memory space provided by a memory sub-system that is similar to the memory sub-system 101. Optionally, the main memory 146 is separately connected to the processing device(s) 118 (e.g., via a connection 109, such as a DDR memory bus); and the memory sub-system 101 is configured to access the main memory 146 via a memory controller 116 of the processing device(s) 118.

[0141] The CXL fabric 169 can include one or more CXL switches; and each of the memory devices 167, ..., 168 and the memory sub-system 101 can have a separate CXL connection to one of the ports of the CXL switch(es) in the CXL fabric 169. Further, each of the processing device(s) 118 can have a separate CXL connection to one of the ports of the CXL switch(es) in the CXL fabric 169 to access the memory devices on the CXL fabric 169, including the memory devices 167, ..., 168, and the memory device corresponding to the memory space 121 in the memory sub-system 101. The CXL fabric 169 can support concurrent access by different host processors (e.g., processing device(s) 118, direct memory access (DMA) engine 147, controller 115) to the memory devices on the CXL fabric 169. The memory sub-system 101 can have a plurality of parallel CXL connections 107 to the CXL fabric 169. Thus, while one or more processing devices 118 are accessing the memory space 121 of the memory sub-system 101 using a CXL memory access protocol, the DMA engine 147 of the memory sub-system 101 can use a separate CXL connection to the CXL fabric 169 to access one of the memory devices 167, ..., 168. Thus, the submission queue 141 and the completion queue 143 of the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system 101 and / or memory addresses (e.g., 124) used in storage access requests (e.g., 137) in the submission queue 141 can be distributed in the memory devices on the CXL fabric 169, including the memory devices 167, ..., 168, and the memory device corresponding to the memory space 121 of the memory sub-system 101.

[0142] For example, the processing device(s) 118 can configure a submission queue 141 for the memory sub-system 101 in the memory space 121, and / or another submission queue 141 for the memory sub-system 101 in one of the memory devices 167, ..., 168 outside of the memory sub-system 101. A storage access request 137 entered in a submission queue (e.g., 141) for execution in the memory sub-system 101 can be configured with a memory address 124 in the memory space 121, or in one of the memory devices 167, ..., 168. Thus, during the execution of the storage access request 137 having an opcode for reading from a logical block address 134, the memory sub-system 101 can retrieve data from the logical block address 134 into the memory space 121, or into the memory devices 167, ..., 168, in accordance with the memory address 124 provided in the storage access request 137. Similarly, during the execution of the storage access request 137 having an opcode for writing to a logical block address 134, the memory sub-system 101 can retrieve data using the direct memory access (DMA) engine 147, from the memory space 121, or from the memory devices 167, ..., 168, in accordance with the memory address 124 provided in the storage access request 137 for writing into a memory page 133 represented by the logical block address 134.

[0143] FIG. 14 shows communications to load a portion of data stored at a logical block address in a memory sub-system to a host system according to one embodiment. For example, communications can be implemented in a computing system 100 of FIG. 1 having a memory sub-system 101 according to FIG. 2 to FIG. 8 and connected according to FIG. 9 to FIG. 13.

[0144] As illustrated in FIG. 14, to access a portion 158 (e.g., a sub block) of data 151 stored at a logical block address 134 (e.g., an LBA address in accordance with an NVMe standard) in a storage space 131 of the memory sub-system 101, the host system 102 configures a read command 171 to have a memory address 124 in the memory space 121 of the memory sub-system 101, in addition to identifying the logical block address 134 in the storage space 131. The memory address 124 specified in the read command 171 is used to identify the destination location for the retrieval of the data 151 at the logical block address 134.

[0145] The host system 102 can send the read command 171 to the memory sub-system 101 using a storage access protocol (e.g., in accordance with an NVMe standard). For example, the host system 102 can enter the read command 171 as a storage access request 137 in a submission queue 141 for retrieval by the memory sub-system 101 (e.g., in accordance with an NVMe standard). For example, the submission queue 141 can be configured in the memory space 121PCT Application Attorney Docket No. 120426-312101 / WO of the memory sub-system 101 (e.g., as in FIG. 5 or FIG. 7), or in the host memory 145 (e.g., as in FIG. 6) For example, the submission queue 141 can be configured in a memory device (e.g., 167 or 168) connected to a portion of a CXL fabric 169 as in FIG. 13.

[0146] The execution of the read command 171 in the memory sub-system 101 causes the memory sub-system 101 to retrieve, from the logical block address 134, a codeword 155 (e.g., encoded using an error correction code technique to have redundant data 153), decode the codeword 155 to determine an error-free version of the user data 151, and store the error-free version of the user data 151 in the memory space 121 according to the memory address 124.

[0147] Since the data size 135 of the user data 151 at the logical block address 134 is a multiple of the data size 125 at each memory address (e.g., 124, ..., 128) in the memory space 121, the user data 151 occupies a plurality of memory addresses (e.g., 124, ..., 128) in the memory space 121.

[0148] After the execution of the read command 171 in the memory sub-system 101, the entire block of user data 151 retrieved from the logical block address 134 is available in the memory space 121 (e.g., as in FIG. 3 to FIG. 8). The memory sub-system 101 can send a completion record 138 to the host system 102 (e.g., in accordance with an NVMe standard) to indicate the availability of the user data 151 in the memory space 121.

[0149] For example, the host system 102 can enter the completion record 138 in a completion queue 143 for retrieval by the host system 102. For example, the completion queue 143 can be configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG.5), or in the host memory 145 (e.g., as in FIG. 6 or FIG. 7). For example, the completion queue 143 can be configured in a memory device (e.g., 167 or 168) connected to a portion of a CXL fabric 169 as in FIG. 13.

[0150] When the completion record 138 indicates a successful execution of the read command 171, any portion (e.g., 157, ..., 158) in the user data 151 can be loaded from the memory space 121 to the host system 102 via the execution of a load instruction 173 in the host system 102.

[0151] For example, in view of the completion record 138 and when the host system 102 is to use a portion 158 (e.g., a sub block) of the data 151 in computation, the host system 102 can execute a load instruction 173 to retrieve the portion 158 of the data 151 from a memory address 128 in the memory space 121. For example, the execution of the load instruction in the host system 102 can cause the memory controller 116 in the host system 102 to load the data portion 158 from the memory address 128 in the memory space 121 of the memory sub-system 101 into the host system 102 using a memory access protocol without loading the remaining portion(s) (e.g., 157) of the data 151.PCT Application Attorney Docket No. 120426-312101 / WO

[0152] Thus, the host system 102 can control which portion of the data 151 at the logical block address 134 is to be communicated from the memory sub-system 101 at a time close to when the portion is to be used in computations performed in the host system 102.

[0153] Optionally, when the host system 102 is to use the entire block of data 151 at the logical block address 134, the host system 102 can configure the read command 171 to have a memory address 124 that is in the host memory 145, such that the execution of the read command 171 in the memory sub-system 101 can result in the memory sub-system 101 delivering the block of data 151 to the host memory 145. Thus, the host system 102 has the options to configure the read command 171 to have a memory address 124 in the memory space 121 of the memory sub-system 101 or a memory address in the host memory 145 and thus outside of the memory sub-system 101. The host system 102 can select an option from the available options based on how the data 151 is to be used in the computations performed in the host system 102 for optimal performance of the computing system 100 as a whole.

[0154] Optionally, the memory space 121 is partitioned into a plurality of memory blocks, each having a size for holding the entire block of data (e.g., 151) stored at one logical block address (e.g., 134) in the storage space 131. The memory address 124 specified in the read command 171 can be used to identify which block of the plurality of predefined / pre-partitioned memory blocks in the memory space 121 is to be used to hold the data (e.g., 151) retrieved from the logical block address (e.g., 134) identified in a read command (e.g., 171). When the memory address 124 specified in the read command 171 does not align with any of the block boundaries of the memory blocks in the memory space 121, the misalignment can be detected as an indication that the beginning portion of the memory block, up to (but not including) the memory address 124, is not to be modified. Thus, the execution of such a read command (e.g., 171) in the memory sub-system 101 can include the memory sub-system 101 retrieving the entire block of data 151 at the logical block address 134, identifying the beginning portion of the data 151 having a size that is equal to the capacity of the beginning portion of the memory block that is not be modified, discarding the beginning portion of the data 151, and storing the remaining portion of the data 151 starting from the memory address 124 identified in the read command (e.g., 171).

[0155] Optionally, the read command 171 can include a count of consecutive memory addresses, starting from the memory address 124 specified in the read command 171, as the destination to store at least a portion of the data 151 retrieved from the logical block address 134 in the storage space 131. The block of consecutive memory addresses identified via the read command 171 is configured in one of the plurality of predefined / pre-partitioned memory blocks in the memory space 121. The beginning and / or the end of the consecutive memory addressesPCT Application Attorney Docket No. 120426-312101 / WO identified via the read command 171 can have a misalignment(s) with the beginning and / or the end of the predefined / pre-partitioned memory block that contains the consecutive memory addresses. The misalignment(s) can be detected as an indication that the content at the memory addresses in the predefined / pre-partitioned memory block but outside of the consecutive memory addresses identified via the read command 171 is not to be modified.

[0156] For example, when the beginning memory address of the consecutive memory addresses (e.g., the smallest memory address among the consecutive memory addresses) is not the same as the beginning memory address of the memory block (e.g., the smallest memory address in the memory block containing the consecutive memory addresses), the misalignment can cause the memory sub-system 101 to skip storing a beginning portion of the user data 151 into the memory block, where the beginning portion of the user data 151 has the size corresponding to the difference between the beginning memory address of the consecutive memory addresses and the beginning memory address of the memory block.

[0157] Similarly, when the ending memory address of the consecutive memory addresses (e.g., the largest memory address among the consecutive memory addresses) is not the same as the ending memory address of the memory block (e.g., the largest memory address in the memory block containing the consecutive memory addresses), the misalignment can cause the memory sub-system 101 to skip storing an ending portion of the user data 151 into the memory block, where the ending portion of the user data 151 has the size corresponding to the difference between the ending memory address of the consecutive memory addresses and the ending memory address of the memory block.

[0158] Thus, the consecutive memory addresses can be specified by the host system 102 to cause the memory sub-system 101 to store the user data 151 into one of a plurality of predefined / partitioned memory blocks which contains the consecutive memory addresses but only in the consecutive memory addresses by discarding the portion(s) that would be stored in the block but outside of the consecutive memory addresses.

[0159] Optionally, the read command 171 can include a field configured to identify the ending memory address of the consecutive memory addresses, in additional to a field configured to identify the beginning memory address (e.g., 124) of the consecutive memory addresses. The memory addresses specified in the fields of the read command 171 identify the consecutive memory addresses selected by the host system 102 to store at least a portion of the user data 151 retrieved from the logical block address 134, where the portion is selected in relation with predefined boundaries of memory blocks in the memory space 121.

[0160] FIG. 15 shows communications to store data from a host system to a logical block address in a memory sub-system according to one embodiment. For example, communicationsPCT Application Attorney Docket No. 120426-312101 / WO can be implemented in a computing system 100 of FIG. 1 having a memory sub-system 101 according to FIG. 2 to FIG. 8 connected according to FIG. 9 to FIG. 13.

[0161] In FIG. 15, the host system 102 is configured to use a memory space 121 in the memory sub-system 101 as a staging ground to build up a block of data 151 to be written to a logical block address 134 in the storage space 131 of the memory sub-system 101.

[0162] For example, the host system 102 can use optionally use a read command 171 as in FIG. 14 to retrieve a block of data 151 from the logical block address 134 into the memory space 121 for modification.

[0163] For example, the host system 102 can use a store instruction 175 to store a data portion 158 to a memory address 128 in the memory space 121 to modify a corresponding portion (e.g., a sub block) of the block of data 151 previously retrieved via the read command 171 (e.g., as in FIG. 14), and / or to build up the block of data 151 one portion at a time via execution of a plurality of store instructions (e.g., 175). For example, the execution of a store instruction in the host system 102 can cause the memory controller 116 in the host system 102 to store the data portion 158 (e.g., in accordance with a memory access protocol) to the memory address 128 in the memory space 121 of the memory sub-system 101 without communicating the remaining portion (e.g., 157) of the data 151 to the memory sub-system 101.

[0164] After the data to be written to the storage space 131 is stored to the memory space 121 via one or more store instructions (e.g., 175), the host system 102 can send to the memory sub-system 101 a write command 177 that specifies a memory address 128 to indicate the source location of the data 151 for writing the data 151 to the storage space 131.

[0165] Since the data size 135 of the user data 151 at the logical block address 134 is a multiple of the data size 125 at each memory address (e.g., 124, ..., 128) in the memory space 121, the user data 151 occupies a plurality of memory addresses (e.g., 124, ..., 128) in the memory space 121. Thus, the host system 102 can build up the user data 151 in the memory space 121 one portion (e.g., 157, or 158) at a time.

[0166] The host system 102 can send the write command 177 to the memory sub-system 101 using a storage access protocol (e.g., in accordance with an NVMe standard). For example, the host system 102 can enter the write command 177 as a storage access request 137 in a submission queue 141 for retrieval by the memory sub-system 101 (e.g., in accordance with an NVMe standard). For example, the submission queue 141 can be configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5 or FIG. 7), or in the host memory 145 (e.g., as in FIG. 6). For example, the submission queue 141 can be configured in a memory device (e.g., 167 or 168) connected to a portion of a CXL fabric 169 as in FIG. 13.

[0167] The execution of the write command 177 in the memory sub-system 101 causes thePCT Application Attorney Docket No. 120426-312101 / WO memory sub-system 101 to generate a codeword 155 from encoding the user data 151 in the memory space 121 (e.g., encoded using an error correction code technique to include the redundant data 153), and program a memory page in the storage space 131 to store the codeword 155.

[0168] After the execution of the write command 177 in the memory sub-system 101, the memory sub-system 101 can send a completion record 138 to the host system 102 (e.g., in accordance with an NVMe standard) to indicate the persistent storage of the user data 151 in the storage space 131. Thus, the data 151 in the memory space 121 can be discarded.

[0169] For example, the host system 102 can enter the completion record 138 in a completion queue 143 for retrieval by the host system 102. For example, the completion queue 143 can be configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG.5), or in the host memory 145 (e.g., as in FIG. 6 or FIG. 7). For example, the completion queue 143 can be configured in a memory device (e.g., 167 or 168) connected to a portion of a CXL fabric 169 as in FIG. 13.

[0170] In some implementations, the memory address 124 is configured to represent the beginning memory address of a plurality of consecutive memory addresses 124, ..., 128 used to provide at least a portion of a block of data 151 to be written to the logical block address 134.

[0171] Optionally, when the host system 102 has the entire block of data 151 to be written to the logical block address 134, the host system 102 can configure the write command 177 to have a memory address 124 that is in the host memory 145, such that the execution of the write command 177 in the memory sub-system 101 can result in the memory sub-system 101 retrieving the block of data 151 from the host memory 145. Thus, the host system 102 has the options to configure the write command 177 to have a memory address 124 in the memory space 121 of the memory sub-system 101 or a memory address in the host memory 145 and thus outside of the memory sub-system 101. The host system 102 can select an option from the available options based on how the data 151 is to be generated in the computations performed in the host system 102 for optimal performance of the computing system 100 as a whole.

[0172] Optionally, the memory space 121 is partitioned into a plurality of memory blocks, each having a size for holding the entire block of data (e.g., 151) stored at one logical block address (e.g., 134) in the storage space 131. The memory address 124 specified in the write command 177 can be used to identify which block of the plurality of predefined / pre-partitioned memory blocks in the memory space 121 is selected to provide at least a portion of the block of data 151 to be written into the logical block address 134 identified in the write command 177. When the memory address 124 specified in the write command 177 does not align with any of the block boundaries of the memory blocks in the memory space 121, the misalignment can bePCT Application Attorney Docket No. 120426-312101 / WO detected as an indication that the beginning portion of the predefined / pre-partitioned memory block, up to (but not including) the memory address 124, does not contain a corresponding portion of the block of the data 151 to be written to the logical block address 134. Thus, the execution of such a write command (e.g., 177) in the memory sub-system 101 can include the memory sub-system 101 determining the corresponding portion of the block of the data 151 that is not in the memory block identified via the memory address 124. For example, the memory sub-system 101 can determine the corresponding portion, not provided by the host system 102 for the write command 177, via reading the current codeword stored at the logical block address 134, and extracting the corresponding portion based on a difference between the memory address 124 and the beginning of the predefined / pre-partitioned memory block that contains the memory address 124. Alternatively, the corresponding portion of the block of the data 151 that is not in the memory block identified via the memory address 124 can be determined based on filling in the portion with a predetermined value (e.g., zero).

[0173] Optionally, the write command 177 can include a count of consecutive memory addresses, starting from the memory address 124 specified in the write command 177, as the source location of at least a portion of the data 151 to be written to the logical block address 134 in the storage space 131. The block of consecutive memory addresses identified via the write command 177 is configured in one of the plurality of predefined / pre-partitioned memory blocks in the memory space 121. The beginning and / or the end of the consecutive memory addresses identified via the write command 177 can have a misalignment(s) with the beginning and / or the end of the predefined / pre-partitioned memory block that contains the consecutive memory addresses. The misalignment(s) can be detected as an indication that the content at the memory addresses in the predefined / pre-partitioned memory block but outside of the consecutive memory addresses identified via the write command 177 does not contain a corresponding portion(s) of the data 151 to be written to the logical block address 134.

[0174] For example, when the beginning memory address of the consecutive memory addresses (e.g., the smallest memory address among the consecutive memory addresses) is not the same as the beginning memory address of the memory block (e.g., the smallest memory address in the memory block containing the consecutive memory addresses), the misalignment can cause the memory sub-system 101 to determine a beginning portion of the user data 151 (e.g., via reading the logical block address 134 in the storage space 131 or filling in using a predetermined value), where the beginning portion of the user data 151 has the size corresponding to the difference between the beginning memory address of the consecutive memory addresses and the beginning memory address of the memory block.

[0175] Similarly, when the ending memory address of the consecutive memory addressesPCT Application Attorney Docket No. 120426-312101 / WO (e.g., the largest memory address among the consecutive memory addresses) is not the same as the ending memory address of the memory block (e.g., the largest memory address in the memory block containing the consecutive memory addresses), the misalignment can cause the memory sub-system 101 to determine an ending portion of the user data 151 (e.g., via reading the logical block address 134 in the storage space 131 or filling in using a predetermined value), where the ending portion of the user data 151 has the size corresponding to the difference between the ending memory address of the consecutive memory addresses and the ending memory address of the memory block.

[0176] Thus, the consecutive memory addresses can be specified by the host system 102 to cause the memory sub-system 101 to determine one or more missing portions of the user data 151 (e.g., via reading the logical block address 134 in the storage space 131 or filling in using a predetermined value) and construct the entire block of data 151 from the missing portions and a portion of the user data 151 provided in the consecutive memory addresses.

[0177] Optionally, the write command 177 can include a field configured to identify the ending memory address of the consecutive memory addresses, in additional to a field configured to identify the beginning memory address (e.g., 124) of the consecutive memory addresses. The memory addresses specified in the fields of the write command 177 identify the consecutive memory addresses selected by the host system 102 to provide at least a portion of the user data 151 for writing the entire block of the data 151 to the logical block address 134 in the storage space of the memory sub-system 101. When the host system 102 uses the consecutive memory addresses in the memory space 121 to provide only a portion of the user data 151 to be written into the logical block address 134 in the storage space 131, the memory sub-system 101 can automatically determines the remaining portion of the user data 151 (e.g., by reading the current data at the logical block address 134 or filing in with a predetermined number) such that no further communications between the host system 102 and the memory sub-system 101 is necessary for specifying the data in the remaining portion of the user data 151. Alternatively, the host system 102 can use a read command 171 as in FIG. 14 to pre-load the current data at the logical block address 134 into the memory block for modification via the execution of a store instruction(s) (e.g., 175).

[0178] In at least some embodiments, the memory sub-system 101 is configured to manage the allocation, from the memory space 121 in the memory sub-system 101, of memory for use by applications running in the host system 102. For example, the memory sub-system 101 can control how memory in the memory space 121 is allocated to applications running in the host system 102.

[0179] For example, before an application running in the host system 102 reads data fromPCT Application Attorney Docket No. 120426-312101 / WO the storage space 131 of the memory sub-system 101, the application can request the operating system in the host system 102 to dynamically allocate a chunk of memory. Subsequently, the host system 102 can configure a read command (e.g., 171) with a memory address in the allocated chunk of memory to cause the memory sub-system 101 to read data from the storage space 131 into the allocated chunk of memory for further processing by the application.

[0180] Instead of the operating system in the host system 102 allocating the chunk of memory according to its memory map 181, the host system 102 can forward the memory allocation request (e.g., in response to a malloc or mmap call) to the memory sub-system 101 of one embodiment. The memory sub-system 101 can be configured to manage the allocation of memory from its memory space 121.

[0181] For example, a communication standard (e.g., NVMe) for accessing the storage space 131 of the memory sub-system 101 can be extended to implement a command to allocate (or a request for the allocation of) a chunk of memory from the memory space 121 of the memory sub-system 101. The access manager 113 in the memory sub-system 101 can track which chunks of memory in the memory space 121 are free for allocation and which chunks of memory have been allocated and thus are currently in use. The memory allocation command (or request) can specify the size of the memory chunk to be allocated from the memory space 121 of the memory sub-system 101. The host system 102 can enter the memory allocation command or request in a submission queue (e.g., 141) configured for the memory sub-system 101. During the execution of the memory allocation command or request, the memory sub-system 101 can identify a chunk of free memory in the memory space 121 and allocate the chunk in response to the memory allocation command or request. After the execution of the command, the memory sub-system 101 can provide a completion record in a completion queue (e.g., 143) to identify the starting memory address (e.g., 124) of the allocated chunk of memory.

[0182] Subsequently, the host system 102 can configure a read command (e.g., 171 and according to an NVMe standard) to identify the allocated chunk of memory as the destination of the read operation of the read command. During the execution of the read command (e.g., 171), the memory sub-system reads data identified by a logical block address (e.g., 134, such as an LB A address according to an NVMe standard) in the storage space 131 and stores the data into the memory chunk according to the starting memory address (e.g., 124) identified by the host system 102 in the read command (e.g., 171) (e.g., as discussed above in connection with FIG. 2 to FIG. 14). Since the starting memory address (e.g., 124) is provided by the memory subsystem 101 in the completion record to identify the chunk of memory allocated in response to the memory allocation command / request, the execution of the read command results in the data being read into the chunk of memory allocated according to the memory allocationPCT Application Attorney Docket No. 120426-312101 / WO command / request.

[0183] Optionally, the read command (e.g., 171) can request the retrieval of the data from a contiguous segment of logical block addresses. For example, the segment can be specified in the read command (e.g., 171) via the starting logical block address (e.g., 134) and a size of the segment (or an ending logical block address). When the memory address (e.g., 124) is specified in such a read command (e.g., 171), the data retrieved via the execution of such the read command (e.g., 171) can be stored in the memory space 121 at the destination location identified via a memory address (e.g., 124) of the allocated chunk of memory.

[0184] Optionally, the application can use the allocated chunk of memory in a read-modify-write operation. For example, the application can modify one or more portions of the data retrieved via the read command into the chunk of memory allocated from the memory space 121 of the memory sub-system 101. After the modification using a memory access protocol, the host system 102 can issue a write command (e.g., 177 and according to an NVMe standard) to write the data from the allocated chunk of memory in the memory sub-system 101 to the storage space 131 of the memory sub-system 101 (e.g., as discussed above in connection with FIG. 15).

[0185] Optionally, the application can use the allocated chunk of memory in tasks unrelated to reading data from and / or writing data to the storage space 131 of the memory sub-system 101.

[0186] When the application frees the allocated chunk of memory (e.g., via a free call), the host system 102 can forward the request to the memory sub-system 101. For example, the host system 102 can enter a memory return command / request in the submission queue (e.g., 141) configured for the memory sub-system 101. For example, the memory return command / request entered in the submission queue (e.g., 141) can identify the starting memory address (e.g., 124) of the memory chunk to be freed, such as the memory address previously identified by the memory sub-system 101 in a completion record for the execution of a memory allocation command / request. Alternatively, or in combination, the memory return command / request entered in the submission queue (e.g., 141) to free a chunk of memory can identify an identification of the memory allocation command / request previously used to allocate the chunk of memory; and the memory sub-system 101 can determine the chunk of memory to be freed based at least in part on the identification of the memory allocation command / request that causes the chunk of memory to be allocated.

[0187] Optionally, the memory sub-system 101 can impose no predetermined relation between the data in the allocated chunk of memory in the memory space 121, and the data stored at any logical block addresses in the storage space 131. For example, the host system 102 can optionally request the memory sub-system 101 to execute a read command 171 to retrieve the data from a logical block address into the allocated chunk of memory to cause the data in thePCT Application Attorney Docket No. 120426-312101 / WO allocated chunk of memory to be the same as the data at the logical block address.Subsequently, the host system 102 can optionally modify the data in the allocated chunk of memory to cause the data in the allocated chunk of memory to be different from the data at the logical block address. Optionally, the host system 102 can discard the modified content in the allocated chunk of memory (e.g., by freeing the chunk of memory without writing the content in the chunk of memory to the storage space 131). Alternatively, the host system 102 can request the memory sub-system 101 to execute a write command 177 to write the modified data in the allocated chunk of memory to the storage space 131 (e.g., at the same logical block address or another logical block address) so that the allocated chunk of memory again stores the same data as the respective logical block address identified in the write command 177.

[0188] Optionally, the memory sub-system 101 is configured to track the data that is both at a logical block address (e.g., 134) in the storage space 131 and at a memory address (e.g., 124) in the memory space 121.

[0189] Optionally, when the same data is stored both at a logical block address (e.g., 134) in the storage space 131 and at a memory address (e.g., 124) in the memory space 121, the memory sub-system 101 can update the metadata 130 to indicate that the storage medium of the logical block address (e.g., 134) is currently in the memory space 121 at the memory address (e.g., 124) and that the memory page 133 storing the same data can be optionally erased.

[0190] Optionally, the allocated memory chunk storing data for a logical block address (e.g., 134) in the storage space 131 (e.g., as a result of execution of a read command 171 or a write command 177) can be used as a cache / buffer memory allocated for the logical block address (e.g., 134). The memory sub-system 101 can be optionally configured to write the content from the allocated memory chunk to the logical block address (e.g., 134) upon freeing or reallocating the memory chunk, if the cached content in the allocated memory chunk has been modified (e.g., via memory access requests 127).

[0191] Optionally, a read command to access the storage space 131 of the memory subsystem 101 can be configured to include a request to allocate a chunk of memory, from the memory space 121 of the memory sub-system 101. During the execution of the read command, the memory sub-system 101 allocates a chunk of memory according to the size of the data being read from the storage space 131, and loads data read from the storage space 131 into the allocated chunk of memory. In a completion record for the read command, the memory subsystem 101 can identify the starting memory address of the allocated chunk of memory such that the host system 102 can use a memory access protocol to use selected portions of the data in the allocated chunk of memory.

[0192] A conventional read command (e.g., according to NVMe) is configured to specify aPCT Application Attorney Docket No. 120426-312101 / WO memory location as the destination for the read operation. During execution of the read command, a memory sub-system (e.g., solid-state drive (SSD)) is to send the data to the memory location identified via the memory address specified in the read command. Before using such a conventional read command, a host system is to perform operations to allocate a chunk of memory and then configure the read command to specify a memory address of the memory chunk as the read destination.

[0193] Optionally, such a read command can be extended to include a built-in memory allocation request. When such a read command with a built-in memory allocation request is used, the host system 102 can skip the operations and / or communications to allocate the chunk of memory before configuring the read command with a memory address of the allocated chunk of memory. As a result, the performance of the computing system 100 can be improved.

[0194] For example, a read command with a built-in memory allocation request can be configured to be functionally equivalent to entering, in a submission queue, a memory allocation request for a chunk of memory and, after obtaining the address of the allocated chunk of memory, configuring a read command to include the address of the allocated chunk of memory as the read destination, and entering the read command in the submission queue for execution by the memory sub-system. When a read command is configured with a built-in memory allocation request, the latency of the round trip communications to obtain the memory address of the allocated chunk of memory can be eliminated; and the efficiency of the usage of the communication channel between the host system and the memory sub-system can be improved.

[0195] For example, a memory allocation request can be built into a read command in the form of the lack of a valid memory location specified as the destination of the read operation. When the memory sub-system 101 detects that the memory address specified in the read command as the read destination is invalid for the memory sub-system 101 and / or the host system 102 to access over the connection 107, the memory sub-system 101 can automatically allocate a chunk of memory from the memory space 121 of the memory sub-system 101 during execution of the read command and store the data retrieved via the execution of the read command to the allocated chunk of memory. In a completion record provided for the read command, the memory sub-system 101 can identify the starting memory address of the chunk of memory storing the data retrieved via the execution of the read command. As a result, the host system 102 can skip sending a separate memory allocation request to allocate a memory block to hold the data retrieved via the execution of the read command.

[0196] Optionally and / or in combination, a predetermined memory address can be used in a read command as a request for allocation of memory to hold the data retrieved via the execution of the read command. For example, the predetermined memory address (e.g., zero) can be in aPCT Application Attorney Docket No. 120426-312101 / WO range of memory addresses that are predefined as invalid for the memory sub-system 101 to store data retrieved via execution of read commands. For example, a memory address in the segment of memory in the memory space 121 of the memory sub-system 101 to host a submission queue 141 (or a completion queue 143) can be specified as a read destination of a read command to represent a memory allocation request built in the read command.

[0197] Optionally and / or in combination, a predetermined opcode can be used in the read command to identify the memory allocation request in connection with a read operation.Optionally and / or in combination, a parameter in the read command is configured to represent a request for memory allocation to be performed during the execution of the read command.

[0198] In general, the read command specifies the size of the data to be read. When the read command has a built-in memory allocation request, the memory sub-system can use the size of the data to be read as the size of the chunk of memory to be allocated. Thus, it is not necessary to separately specify the size of the memory chunk to be allocated in the read command.

[0199] Alternatively, a field in the read command can be configured to specify the size of the memory chunk to be allocated via the execution of the read command; and the size of the memory chunk being allocated can be different from the size of the data to be read via the execution of the read command. For example, when the size of the memory chunk being allocated is smaller than the size of the data being read from the storage space 131 via the execution of the read command, the data retrieved from the storage space 131 can be truncated when being loaded into the allocated chunk of memory. For example, when the size of the memory chunk being allocated is larger than the size of the data being read from the storage space 131 via the execution of the read command, the host system 102 can use the additional memory space in the allocated chunk of memory to store data related to the processing of the data read from the storage space 131 and / or other data.

[0200] Optionally, the host system 102 can send an access completion notification to the memory sub-system 101 to indicate that the input output access associated with the execution of a storage access request (e.g., a read command or a write command) is complete such that the memory sub-system 101 can release the resources previously allocated and / or used for the storage access request. Such resources can include memory chunks allocated from the memory space 121. For example, the access completion notification can be entered in a submission queue (e.g., 141) to cause the memory sub-system 101 to free a chunk of memory previously allocated from the memory space 121 of the memory sub-system 101 and used during the execution of a read or write command in the memory sub-system 101.

[0201] For example, the access manager 113 in the memory sub-system 101 can track the memory chunks that have been allocated from the memory space 121 of the memory sub-systemPCT Application Attorney Docket No. 120426-312101 / WO and that have been used in execution of storage access requests (e.g., read commands, write commands). When the host system 102 sends an access completion notification that identifies one or more such storage access requests (e.g., via command identifications of the storage access requests), the memory sub-system 101 can deallocate the memory chunks that have been used during the execution of the storage access requests identified via the access completion notification.

[0202] For example, the host system 102 can allocate a chuck of memory via entering, in a submission queue of the memory sub-system, a memory allocation request or a read command having a built-in memory allocation request. After the execution of a read command in the memory sub-system 101 to retrieve data into the allocated chunk of memory, the host system 102 can use and / or modify the data in the chunk of memory using a memory access protocol. When the host system 102 sends an access completion notification identifying the read command, the memory sub-system 101 can identify the chunk of memory used during the execution of the read command and thus retum / free the chunk of memory.

[0203] In some implementations, a write command can include a built-in memory return request. For example, when a write command is executed to write data from the memory space 121 in the memory sub-system 101 to the storage space 131 in the memory sub-system 101, the memory sub-system 101 can retum / free the chunk of memory.

[0204] For example, a built-in memory return request can be specified in a write command in the form of a memory address of the chunk of memory allocated from the memory space 121 as the source location of the data to be written to the storage space 131. In response to a determination that the memory address is in a chunk of memory allocated from the memory space 121 and / or allocated via a read command executed in the memory sub-system 101, the memory sub-system 101 can free the chunk of memory upon completion of the execution of the write operation for the write command.

[0205] Alternatively, and / or in combination, a memory return request can be specified in a write command in the form of an opcode or another indicator specified in a predefined field in the write command.

[0206] Optionally, the memory sub-system 101 can track of a list of memory chunks that are storing the same data as certain logical block addresses in the storage space 131. When the host system 102 sends a storage access request to read the data from such a logical block address, the memory sub-system 101 can use a respective memory chunk to complete the execution of the request without reading the storage space 131 according to the logical block address.

[0207] For example, after the execution of a read command configured to retrieve data from a logical block address to a memory address in the memory space 121, the memory sub-systemPCT Application Attorney Docket No. 120426-312101 / WO 101 can update the list to indicate that the memory address stores the same data as the logical block address. When the host system 102 modifies the data in the memory space 121, the memory sub-system 101 can update the list to indicate that the memory address no longer stores the same data as the logical block address. After the execution of a write command to write the modified data from the memory address to a logical block address, the memory sub-system 101 can further update the list to indicate that the memory address stores the same data as the logical block address. When the memory chunk is freed and / or reallocated (e.g., in response to a read command or a memory allocation request), the memory sub-system 101 can erase the memory chunk and remove it from the list of memory chunks that are storing the same data as logical block addresses.

[0208] Optionally, a memory chunk can be allocated with a caching / buffering option such that the content of the memory chunk is considered the current content at a respective logical block address. In response to a request to reallocate and / or free the memory chunk, the memory sub-system 101 is configured to automatically commit the content of the memory chunk to the logical block address in the storage space 131, if the content has been modified after being read into the memory chunk from the logical block address. Thus, it is not necessary for the host system 102 to send a separate write command for the storing of the modified content from the memory chunk to the storage space 131 of the memory sub-system 101.

[0209] FIG. 16 and FIG. 17 show management of memory in a memory space of a memory sub-system according to one embodiment.

[0210] For example, an access manager 113 in the memory sub-system 101 in FIG. 16 and FIG. 17 can be configured to manage the allocation and freeing of memory chunks from the memory space 121.

[0211] For example, when an application 215 running in the host system 102 is to use a chunk of memory in the memory space 121 in the memory sub-system 101, the host system 102 can send a memory allocation request 203 to the memory sub-system 101.

[0212] For example, the memory allocation request 203 can be entered in a submission queue 141 configured for the memory sub-system 101. The submission queue 141 can be configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5 and FIG.7), or as in the host memory 145 (e.g., as in FIG. 6).

[0213] The memory allocation request 203 can include a field configured to identify the size 207 of a chunk of memory to be allocated from the memory space 121.

[0214] The access manager 113 in the memory sub-system 101 can track a list 202 of memory chunks / blocks that are free to be allocated for use by the host system 102, and a list 201 of memory chunks / block that have been allocated for use (e.g., by the host system 102 and / or byPCT Application Attorney Docket No. 120426-312101 / WO the memory sub-system 101).

[0215] In some implementations, memory blocks not in the free block list 202 are considered to have been allocated and thus in use. In other implementations, memory blocks not in the allocated block list 201 are considered free for allocation. Thus, the memory sub-system 101 can optionally maintain one of the two lists 201 and 202 without the other.

[0216] In response to the memory allocation request 203, the access manager 113 in the memory sub-system 101 can identify a free memory block 211 in the memory space 121 according to the free block list 202. The access manager 113 can move the block identifier 212 of the memory block 211 from the free block list 202 to the allocated block list 201 to indicate that the memory block 211 has been allocated for use and thus no longer free for allocation. The memory sub-system 101 can send a memory allocation response 205 to the host system 102 as a response to the memory allocation request 203. The memory allocation response 205 can include the starting memory address 124 of the memory block 211.

[0217] For example, the block identifier 212 can include the starting memory address 124 of the memory block 211 and the size 207 of the allocated memory block 211.

[0218] For example, the memory sub-system 101 can provide the memory allocation response 205 to the host system 102 via a completion record for the execution of the memory allocation request 203 retrieved from a submission queue 141. The completion record can be entered in a completion queue 143 for processing by the host system 102. The completion queue 143 can be configured in the host memory 145 (e.g., as in FIG. 6 and FIG. 7), or in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5).

[0219] Optionally, the application 215 can use the allocated memory block 211 to buffer data retrieved from the storage space 131. For example, the host system 102 can specify the memory address 124 of the allocated memory block 211 in a read command 171 to read user data 151 from the storage space 131 into the allocated memory block 211 (e.g., as in FIG. 14).

[0220] For example, the host system 102 can build up user data 151 in the allocated memory block 211 one portion (e.g., 157 or 158) at a time and then specify the memory address 124 of the allocated memory block 211 as a data source location in a write command 177 to write the user data 151 from the allocated memory block 211 to the storage space 131 (e.g., as in FIG. 15).

[0221] Optionally, the memory sub-system 101 can erase the memory block 211 before sending the memory allocation response 205 to the host system 102.

[0222] When the application 215 completes its usage of the allocated memory block 211, the host system 102 can send a memory return request 209 as in FIG. 17 to the memory sub-system 101 to free the memory block 211 such that the memory block 211 can be reallocated for use byPCT Application Attorney Docket No. 120426-312101 / WO the memory sub-system 101 or by the host system 102 (e.g., for use by the application 215, or another application or the operating system 213 running in the host system 102).

[0223] For example, the memory return request 209 can be entered in a submission queue 141 configured for the memory sub-system 101. The submission queue 141 can be configured in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5 and FIG. 7), or as in the host memory 145 (e.g., as in FIG. 6).

[0224] The memory return request 209 can include a field configured to identify the starting memory address 124 of the chunk of memory to be freed. Alternatively, or in combination, the memory return request 209 can include a field configured to identify the memory allocation request 203 (e.g., using a command ID of the memory allocation request 203) that causes the memory block 211 to be allocated; and the memory sub-system 101 can determine the identifier 212 of the memory block 211 to be freed from the command ID of the memory allocation request 203.

[0225] In response to the memory return request 209, the access manager 113 in the memory sub-system 101 can identify the memory block 211 to be freed (e.g., based on the starting memory address 124 of the memory block 211 and / or the command ID of the memory allocation request 203 that causes the memory block 211 to be allocated). The access manager 113 can move the block identifier 212 of the memory block 211 from the allocated block list 201 to the free block list 202 to indicate that the memory block 211 is now free for allocation. The memory sub-system 101 can send a memory return response 206 to the host system 102 as a response to the memory return request 209. Optionally, the memory return response 206 can include the starting memory address 124 of the memory block 211 being freed.

[0226] For example, the memory sub-system 101 can provide the memory return 206 to the host system 102 via a completion record for the execution of the memory return request 209 retrieved from a submission queue 141. The completion record can be entered in a completion queue 143 for retrieval and processing by the host system 102. The completion queue 143 can be configured in the host memory 145 (e.g., as in FIG. 6 and FIG. 7), or in the memory space 121 of the memory sub-system 101 (e.g., as in FIG. 5).

[0227] FIG. 18 shows integrating memory allocation requests in storage access requests according to some embodiments.

[0228] In FIG. 18, a storage access request 221 is configured to access a logical block address 134 and configured to include an embedded memory request 223. The execution of the storage access request 221 in the memory sub-system 101 can result in the allocation of a memory block 211, in addition to accessing at least the logical block address 134 in the storage space 131 (e.g., reading or writing at the logical block address 134 or a segment of contiguousPCT Application Attorney Docket No. 120426-312101 / WO logical block addresses starting with the logical block address 134).

[0229] For example, the memory request 223 can be specified via an opcode provided in the storage access request 221. For example, the opcode can be configured to request the allocation of a memory block in addition to a read or write operation according to the logical block address 134 in the storage space 131.

[0230] In some implementations, the size 207 of the memory block 211 to be allocated is specified in the storage access request 221 based on the data size of the storage access request 221, such as the size of data to be read from the storage space 131 (or written to the storage space 131) via the execution of the storage access request 221 in the memory sub-system 101.

[0231] Alternatively, or in combination, the storage access request 221 can be configured with a predefined field for specifying the allocation size 207 of the memory request 223.

[0232] For example, when the allocation size 207 specified in the field of the storage access request 221 is zero (or larger than a predetermined threshold), the memory sub-system 101 can execute the storage access request 221 for accessing at least the logical block address 134 without allocating a memory block. However, when the allocation size 207 specified in the field of the storage access request 221 is non-zero (and no larger than the predetermined threshold), the memory sub-system 101 can allocate, during the execution of the storage access request 221, a memory block 211 according to the allocation size 207 specified in the field of the storage access request 221.

[0233] For example, the predetermined threshold can be the capacity of the memory space 121, or a predetermined fraction of the capacity of the memory space 121. When the allocation size 207 specified in the field of the storage access request 221 is equal to (or larger than) the predetermined threshold, the memory sub-system 101 can execute the storage access request 221 without allocating a memory block 211.

[0234] For example, when the allocation size 207 specified in the field of the storage access request 221 is equal to zero (or another predetermined number), the memory sub-system 101 can allocate a memory block 211 according to the data size of the storage access request 221.

[0235] In some instances, the allocation size 207 specified in the field of the storage access request 221 is not configured to indicate the lack of a memory request (e.g., above zero and below the threshold); and the allocation size 207 can be different from the size of data to be read or written via the execution of the storage access request 221 in the memory sub-system 101. During the execution of the storage access request 221, the memory sub-system 101 can allocate a memory block 211 according to the allocation size 207 specified in the field of the storage access request 221.

[0236] Alternatively, or in combination, the memory request 223 can be specified in thePCT Application Attorney Docket No. 120426-312101 / WO storage access request 221 in the form of the lack of a valid memory address (e.g., 124) as a source location or a destination location for writing to or reading from the logical block address 134.

[0237] For example, the storage access request 221 can include an opcode configured to cause the memory sub-system 101 to at least read data from at least the logical block address 134. When an invalid memory address is specified in the storage access request 221 as the destination location of the read operation, the invalid memory address can be recognized by the memory sub-system 101 as the memory request 223 and thus can cause the memory sub-system 101 to allocate a memory block 211 to hold the data being read.

[0238] For example, a read command can be configured with a null memory address as the destination location for the reading of data from at least the logical block address 134. In response to the null memory address being specified as the read destination, the memory subsystem 101 can allocate a memory block 211 in the memory space 121 and store the data, read from the storage space 131 according to the logical block address 134, into the memory block 211 during the execution of the read command. The completion record 138 for the read command can provide the starting memory address 124 of the allocated memory block 211. Based on the starting memory address 124, the host system 102 can select a memory address (e.g., 128 in the memory block 211) to selectively load a portion of the data from the allocated memory block 211 and / or to store data to a portion of the memory block 211 (e.g., for subsequent writing to the storage space 131).

[0239] In some implementations, the null memory address is a predetermined memory address (e.g., zero, a memory address in a range of memory addresses of a submission queue 141 configured for the memory sub-system 101, or a memory address in a range of memory addresses of a completion queue 143 configured for the memory sub-system 101).

[0240] Optionally, after the data at a logical block address 134 is read into the memory block 211, the memory sub-system 101 can update the metadata 130 to indicate that the memory block 211 now stores the data for the logical block address 134.

[0241] Optionally, the block identifier 212 of the memory block 211 can be configured to identify not only the starting memory address 124 of the allocated memory block 211, but also the logical block address 134 for which the memory block 211 is allocated.

[0242] Optionally, the memory sub-system 101 can further store data configured to indicate whether the memory block 211 allocated for the access of the logical block address 134 is configured as a cache (or buffer) for the logical block address 134.

[0243] When the memory block 211 is allocated as a cache (or buffer) for the logical block address 134 (or a segment of contiguous logical block addresses starting with the logical blockPCT Application Attorney Docket No. 120426-312101 / WO address 134), the memory sub-system 101 can further store data indicating whether the content in the memory block 211 has been modified by the host system 102. If the content has been modified by the host system 102 via a memory access protocol, the memory sub-system 101 can further update the metadata 130 to indicate that the memory page (e.g., 133) previously used to store the data at the logical block address 134 can now be erased. If the cached / buffered content in the memory block 211 has been modified by the host system 102, freeing the memory block 211 can cause the memory sub-system 101 to automatically write the data from the memory block 211 to the storage space 131 according to the logical block address 134. Thus, the host system 102 does not have to send a write command via a submission queue (e.g., 141) to instruct the memory sub-system 101 to write the modified data from the memory block 211 to the storage space 131.

[0244] Optionally, the block identifier 212 can be configured to further identify the allocation size 207 of the memory block 211, the command ID of the read command that causes the allocation of the memory block 211, the size of the segment of logical block addresses for which the memory block 211 is storing data, and / or an identification of the host system 102 and / or a processing device 118 for which the memory block 211 is allocated.

[0245] Optionally, the storage access request 221 can include a scatter gather list (SGL) configured to identify one or more memory segments as a destination location for a read operation or a source location for a write operation. One or more memory segments in the scatter gather list (SGL) can be specified with a memory request 223 to cause the memory subsystem 101 to allocate a memory block and mapped the one or more memory segments to the allocated memory block.

[0246] For example, when the storage access request 221 specifies an opcode for a read operation, the memory sub-system 101 can extract portions of the data being read into memory segments identified by the scatter gather list (SGL). When the scatter gather list (SGL) includes one or more memory segments having a memory request 223, the memory sub-system 101 can allocate the memory block 211, and map the one or more memory segments into the memory block 211 via concatenation. Thus, the data to be read into the one or more memory segments are stored in the allocated memory block 211. The host system 102 can perform the same address mapping to access the corresponding data in the memory block 211 as identified via the starting memory address 124 provided in the completion record 138.

[0247] For example, when the storage access request 221 specifies an opcode for a write operation, the memory sub-system 101 can perform a read-modify -write operation by modifying the data read according to the logical block address 134 in the storage space 131. The data read from the storage space 131 can be modified using data provided at memory segments specifiedPCT Application Attorney Docket No. 120426-312101 / WO in the scatter gather list (SGL). Optionally, the scatter gather list (SGL) can include one or more first memory segments having a memory request 223 and one or more second memory segments having no memory request. During the read phase, the memory sub-system 101 can allocate a memory block 211 and read data into the one or more first memory segments in a same ways as if the opcode were for a read operation. During the modification phase, the memory sub-system 101 can retrieve data from the one or more second memory segments to modify the data obtained from reading the storage space 131 according to the logical block address 134. During the write phase, the modified data as generated during the modification phase is written back to at least the logical block address 134. As a result, the storage access request 221 with the opcode for the write operation can be used a scatter gather list (SGL) to modify one or more portions of the content in the storage space 131 starting at the logical block address 134 and retrieve one or more other portions of the content into the allocated memory block 211 for further accessing by the host system 102 using a memory access protocol (e.g., as in FIG. 4).

[0248] Optionally, when the storage access request 221 specifies an opcode for a write operation, the memory sub-system 101 can perform a read-modify -write operation by modifying the data read according to the logical block address 134 in the storage space 131. The data read from the storage space 131 can be modified using data provided at memory segments specified in the scatter gather list (SGL). The modified data is written to the storage space 131 according to the logical block address. When the storage access request 221 includes a memory request, the memory sub-system 101 allocates a memory block 211 to hold the modified data being written to the storage space 131 and provides the starting memory address 124 of the memory block 211 in the completion record 138 to allow the host system 102 to selectively access the modified data using a memory access request (e.g., 127).

[0249] In some implementations, an indication of memory return can be integrated in a storage access request.

[0250] FIG. 19 shows examples of opcodes that can be used in a storage access request according to one embodiment. For example, the storage access requests 137 (e.g., read commands 171, write commands 177) can be implemented using opcodes illustrated in FIG. 19.

[0251] In FIG. 19, a storage access request 137 includes a plurality of predefined fields, including a field for an opcode 240, a field for a memory address 124, and a field for a logical block address 134. The tasks to be performed by a memory sub-system 101 (e.g., as in FIG. 1) during the execution of the storage access request 137 are dependent on the value of the opcode 240 specified in the storage access request 137.

[0252] For example, when the opcode 240 has a predefined value associated with an operation for read 241, the storage access request 137 causes the memory sub-system 101 toPCT Application Attorney Docket No. 120426-312101 / WO read data from at least the logical block address 134 in the storage space 131 of the memory subsystem 101 to a destination location identified by the memory address 124.

[0253] Optionally, a null memory address can be used in the field of memory address 124 to represent a memory request 223, when the opcode 240 has the predefined value associated with the operation for read 241.

[0254] Optionally, the memory address 124 can be in the memory space 121 of the memory sub-system 101 to avoid the communication of the data being read from the memory sub-system 101 to outside of the memory sub-system 101. Subsequently, the host system 102 (e.g., as in FIG. 1) can use a memory access request 127 (e.g., as in FIG. 4) to access a portion of the data that has been read into the memory space 121 via the execution of the storage access request 137 having the opcode 240 for read 241.

[0255] Alternatively, the memory address 124 can be a null memory address, which cause the memory sub-system 101 to allocate a memory block 211 from the memory space 121 of the memory sub-system 101 as the destination location, as if the memory address 124 were the starting memory address 124 of the allocated memory block 211 in the memory space 121 of the memory sub-system 101.

[0256] Alternatively, the memory address 124 can be in the host memory 145, causing the memory sub-system 101 to use a memory access protocol to communicate the data retrieved from at least the logical block address 134 to the host memory 145.

[0257] Optionally, the destination location identified by the memory address 124 is provided only for part of the data being read from at least the logical block address 134. For example, a scatter gather list (SGL) can be used to specify the portion(s) to be extracted from the data to be read from the storage space 131 according to the logical block address 134. Optionally, the SGL can be configured to indicate that the memory for the portion(s) is to be allocated from the memory space 121; and in response, the memory sub-system 101 can allocate a memory block 211 and map the portion(s) to the memory block 211 via concatenation.

[0258] Alternatively, the opcode 240 can have a predefined value associated with an operation for write 242. In response, the memory sub-system 101 executing the storage access request 137 can write data from a source location identified by the memory address 124 to at least the logical block address 134 in the memory sub-system 101. For example, the memory address 124 can be in the memory space 121 of the memory sub-system 101 or in the host memory 145.

[0259] Optionally, the source location identified by the memory address 124 provides only part of the data to be written to at least the logical block address 134. For example, a scatter gather list (SGL) can be used to specify the portion(s) of the data that is provided at the sourcePCT Application Attorney Docket No. 120426-312101 / WO location; and the memory sub-system 101 is configured to perform a read-modify -write operation by reading at least the logical block address 134 for the data currently stored in the storage space 131, modifying the current data using the portion(s) from the source location, and writing the modified data back to the storage space 131 according to the logical block address 134. Optionally, the scatter gather list (SGL) can be configured to request extraction of some of the segments of the current data to be read from the storage space 131 of the memory subsystem 101, as if the opcode 240 were for the operation of read 241; and the scatter gather list (SGL) can be further configured to cause the memory sub-system 101 to allocate a memory block 211 as the destination location for providing the extracted the segments. Optionally, the storage access request 137 can include a memory request 223 to cause the memory sub-system 101 to allocate a memory block 211 to provide the entire data being written back to the storage space 131 according to the logical block address 134 (or the portion of the data that has not been modified by the data provided at the source location identified by the scatter gather list (SGL)).

[0260] Alternatively, the opcode 240 can have a predefined value associated with an operation for memory request 243. For example, the memory address 124 and / or the logical block address 134 can be used to identify the size of the data that can be read via the opcode 240 for read 241; and thus, the storage access request 137 having the opcode 240 for memory request 243 can cause the memory sub-system 101 to allocate a memory block 211 having a size that is equal to the size of the data, without causing the memory sub-system 101 to perform the operation to read from or write to the logical block address 134. For example, the memory to be allocated can be a portion of the data at the logical block address 134 identified via a scatter gather list (SGL).

[0261] Alternatively, the opcode 240 can have a predefined value associated with an operation for memory return 244. For example, the memory address 124 can be used to identify the starting memory address 124 of a memory block 211 previously allocated via the execution of a storage access request; and the memory sub-system 101 can execute the storage access request 137 having the opcode 240 for memory return 244 to free the memory block 211 from allocation. For example, the logical block address 134 can be used to identify a segment of continuous logical block addresses, starting from the logical block address 134, for which memory blocks (e.g., 211) have been previously allocated for the read and / or write access of the logical block address segment; and in response, the memory sub-system 101 is to free such memory blocks (e.g., 211).

[0262] Alternatively, the opcode 240 can have a predefined value associated with an operation for access completion 245. For example, the storage access request 137 can identify memory addresses (e.g., 124) and / or logical block addresses (e.g., 134) to indicate that the hostPCT Application Attorney Docket No. 120426-312101 / WO system 102 has completed its access to memory locations in the memory space 121 in the memory sub-system 101 and / or storage locations in the storage space 131 in the memory subsystem 101; as a result, the memory sub-system 101 can free resources allocated to provide access to the corresponding memory locations and / or storage locations, such as memory blocks (e.g., 211) allocated from the memory space 121 and used in the host system 102 accessing the memory sub-system 101.

[0263] Alternatively, the opcode 240 can have a predefined value associated with an operation for read and cache 246. In response, the memory sub-system 101 allocates a memory block 211 as the destination for the read operation and cache the data retrieved from at least the logical block address 134 in the allocated memory block 211. The starting memory address of the memory block 211 is identified in the completion record 138 for the storage access request 137. Optionally, the memory sub-system 101 can update the metadata 130 to indicate that the data of at least the logical block address 134 is now in the allocated memory block 211 such that, if the content in the allocated memory block 211 is modified, freeing the memory block 211 can cause the writing of the content back according to the logical block address 134.

[0264] Alternatively, the opcode 240 can have a predefined value associated with an operation for write and cache 247. In response, the memory sub-system 101 writes the data from the source location identified by the memory address 124 to the storage space 131 according to the logical block address 134. If the source location as identified by the memory address 124 is not in the memory space 121 in the memory sub-system 101, the memory subsystem 101 can allocate a memory block 211 to cache the data being written to at least the logical block address 134 and return the starting memory address of the allocated memory block in the completion record 138 for the storage access request 137. If the source location as identified by the memory address 124 is in the memory space 121, the memory sub-system 101 specifies the memory address 124 in the completion record 138 for the storage access request 137 as the starting memory address caching the data being written to the storage space 131. The host system 102 can continue using the memory block 211 having the starting memory address 124 identified in the completion record 138 provided for the storage access request 137 (e.g., until the memory block 211 is freed via memory return 244 or access completion 245).Optionally, the memory sub-system 101 can update the metadata 130 to indicate that the data of at least the logical block address 134 is now in the allocated memory block 211 such that, if the content in the allocated memory block 211 is modified, freeing the memory block 211 can cause the writing of the content back according to the logical block address 134.

[0265] Optionally, the memory sub-system 101 can support the use of further values for the opcode 240.PCT Application Attorney Docket No. 120426-312101 / WO

[0266] For example, an opcode 240 for write and memory return can be used to cause the memory sub-system 101 to free the memory block used in the execution of the storage access request 137 and / or any memory block(s) previously allocated to read from any of the logical block addresses (e.g., 134) currently being read during the execution of the storage access request 137.

[0267] For example, an opcode 240 for write and memory request can be used to cause the memory sub-system 101 to allocate a memory block to store the data being written to the storage space 131 according to the logical block address 134 (or a portion of the data being written that is not provided by the memory address 124 in the memory space 121, and / or not provided by the host system 102 in a read-modify -write operation).

[0268] For example, an opcode 240 for read and memory return can be used to cause the memory sub-system 101 to free any memory block(s) previously allocated to read from any of the logical block addresses (e.g., 134) currently being read during the execution of the storage access request 137.

[0269] In at least some embodiments, the memory sub-system 101 is configured to leverage the flash translation layer (FTL) to track the mapping between storage locations in the storage space 131 having data buffered or cached in the memory space 121 and the corresponding memory locations in the memory space 121 where the data is buffered or cached.

[0270] Flash translation layer (FTL) includes a logical to physical translation table that maps between logical block addresses (e.g., 134) configured in a logical storage space and addresses in a physical storage space (e.g., 131). The logical storage space is known to both the host system 102 and the memory sub-system 101. The logical block addresses (e.g., 134) are configured to represent logical storage blocks in the logical storage space such that the host system 102 can use the logical block addresses (e.g., 134) to identify storage locations of data. The logical to physical translation table maps the storage locations as identified by the logical block addresses (e.g., 134) in the logical storage space to the physical storage space (e.g., 131). The data identified to be stored in the logical storage space is actually stored in memory pages (e.g., 133) that can be addressed by the memory sub-system 101 for data storage and retrieval operations. The memory pages (e.g., 133) are allocated by the memory sub-system 101 to implement the storage locations represented by the logical block addresses (e.g., 134).

[0271] The logical to physical translation table can be configured to perform mapping at the granularity level of translation unit (TU) (also known as indirection unit (IU)). A translation unit is the smallest set of logical block addresses that can be separately mapped using the logical to physical translation table. In some implementations, such a smallest set of logical block addresses represented by a translation unit (or indirection unit) is configured to have a storagePCT Application Attorney Docket No. 120426-312101 / WO capacity size same as one logical storage block represented by one logical block address. In other implementations, such a smallest set of logical block addresses represented by a translation unit (or indirection unit) is configured to have a storage capacity size same as a predetermined number of logical storage blocks represented by a plurality of logical block addresses (e.g., four or sixteen logical block addresses).

[0272] For example, an LB A address can be configured according to a standard of NVMe to represent a storage block having a capacity size to store 4 KB of data. When a translation unit is configured to have the size of one LB A address, each translation unit of a logical to physical translation table represents a storage unit of 4 KB addressable using one LBA address.However, when a translation unit is configured to have the size of four (or sixteen) LBA addresses, each translation unit of a logical to physical translation table represents a storage unit of 16 KB (or 64 KB), with portions separately addressable using the four (or sixteen) LBA addresses represented by the translation unit.

[0273] In one embodiment, memory blocks (e.g., 211) allocated from the memory space 121 (e.g., to allow a host system 102 to access the storage space 131 using the techniques of FIG. 2 to FIG. 19) are mapped to a logical memory space for tracking. The logical memory space is partitioned into logical memory regions (or pages), each having the capacity size same as the capacity size of each translation unit used in the logical to physical translation table. Through the use of the logical memory regions (or pages), the infrastructure of logical to physical translation table of flash translation layer can be used in tracking the memory locations in the memory blocks (e.g., 211) for buffering or caching the data addressable in the logical storage space using the logical block addresses.

[0274] Typical memory blocks (e.g., 211) allocated from the memory space 121 (e.g., to allow a host system 102 to access the storage space 131 using the techniques of FIG. 2 to FIG.19) have different sizes. The memory blocks (e.g., 211) having varying sizes can be mapped to the logical memory regions (or pages) of a same size to simplify the mapping between the memory blocks (e.g., 211) and the logical storage blocks represented by logical block addresses having data buffered or cached in the respective memory blocks (e.g., 211).

[0275] The host system 102 can be configured to access the memory blocks (e.g., 211) using the physical memory addresses (e.g., 124, 128) in the memory blocks (e.g., 211). When the host system 102 accesses the memory blocks (e.g., 211) using the physical memory addresses (e.g., 124, 128), no address translation between the physical memory space 121 and the logical memory space 122 is necessary. Thus, the performance of the host system 102 accessing the memory blocks (e.g., 211) can be improved (e.g., in comparison with arrangements where the host system 102 is configured to use logical memory addresses to access the memory blocksPCT Application Attorney Docket No. 120426-312101 / WO (e.g., 211)).

[0276] For example, an entry in the logical to physical translation table of the flash translation layer (FTL) can be configured to identify (e.g., via identifiers of translation units) the logical block address(es) in the logical storage space and the corresponding memory page address(es) in the storage space 131 allocated to implement the logical block address(es).Further, the entry can be configured to include a field usable to indicate whether the data in the set of logical block address(es) is buffered or cached (e.g., as least in part) in the memory space 121.

[0277] Optionally, an entry in the logical to physical translation table can be configured to include a field usable to specify a physical memory address (e.g., 124) of a memory block (e.g., 211) allocated to buffer or cache the data for the translation unit identified by the entry. For example, the entry can be configured to indicate that “LBA 12345678 is stored on NAND device 6, channel 3, block 9876, page 13 and has a memory assignment at DRAM location 98127634”. Such an entry indicates that the data of the LBA address 12345678 is buffered or cached in the DRAM of the memory space 121 at the memory address 98127634. When the data of the LBA address 12345678 is not buffered or cached in the memory space 121, the entry can indicate that “LBA 12345678 is stored on NAND device 6, channel 3, block 9876, page 13 and has no memory assignment”. Such a technique can provide a very efficient map but can be expensive for adding, to every logical to physical translation table entry, a large field (e.g., of 5 bytes or so) to potentially store the DRAM address associated with the memory assignment. However, the capacity reserved for the field to specify an address is used sporadically, which is inefficient in the use of storage resources in the memory sub-system 101. For example, when the total NAND capacity of the storage space 131 is 1000 times the total DRAM capacity of the memory space 121, only 0.1% of translation units in the logical to physical translation table can actually be assigned addresses in DRAM. As a result, the usage rate of the total storage space reserved for storing the addresses of allocated memory for buffering / caching is no more than 0.1%.

[0278] To improve the efficiency in the usage of storage resources allocated to the logical to physical translation table, a single buffering status bit is added to each entry of the logical to physical translation table. The buffering status bit can be used to indicate whether the translation unit identified by the entry has data cached or buffered in the memory space 121, without an additional field usable to specify the memory address in the memory space 121 if the translation unit has data cached or buffered in the memory space 121. To track the memory addresses for the buffering / caching of data addressable using the logical block addresses in translation units, the memory sub-system 101 can be configured with a translation look asidePCT Application Attorney Docket No. 120426-312101 / WO table (or buffer pointer table). Each entry in the translation look aside table (or buffer pointer table) is configured to map a translation unit to a memory address in the memory space 121 for the buffering / caching data of the translation unit. When a translation unit has no data buffered / cached in the memory space 121, the translation look aside table (or buffer pointer table) contains no entry for such a translation unit. In the example where the capacity of the storage space 131 is 1000 times the capacity of the memory space 121, the number of entries in the translation look aside table (or buffer pointer table) can be 0.1%, or less, of the number of entries in the logical to physical translation table. The smaller size of the translation look aside table (or buffer pointer table) allows the tracking of the memory addresses with less resources and faster performance. The addition of the field for buffering status bit grows the logical to physical translation table marginally by one bit per entry, instead of by the size of memory addresses (e.g., 5 bytes) per entry.

[0279] A typical memory chunk allocated from the memory space 121 to access the storage space 131 can have a size that is significantly smaller than the capacity of a translation unit. Allocating memory chunks from the memory space 121 at the granularity level of translation unit can lead to inefficient usages of random access memory in the memory space 121. To improve the efficiency in the usages of the memory space 121, a logical memory space is configured to allocate logical memory regions, each having a same size as a translation unit, for tracking the buffering or caching of translation units. Thus, translation units can be mapped to memory regions / pages in the logical memory space according to the granularity level of translation unit; and each logical memory region / page has the same capacity as a translation unit. When a portion of the data of a translation unit is buffered or cached in a memory chunk having a size smaller than the translation unit, an entry in a memory allocation map is used to map the memory chunk in the corresponding logical memory region / page that is mapped to the translation unit.

[0280] For example, when a storage access request 221 is received to read data from the storage space 131 to the memory space 121, the memory sub-system 101 can determine the size of the data to be read, and allocate a memory block 211 from the memory space 121 according to the size (e.g., as in FIG. 18). The buffering status bit of the entry stored in the logical to physical translation table for the storage location being read can be updated to indicate that the data at the storage location is buffered or cached in the memory space 121. An entry can be added to the translation look aside table (or buffer pointer table) to identify, in the logical memory space, a logical memory region / page having the size equal to the size of translation unit as the location for the buffering / caching of the data. An entry is added to a memory allocation map to indicate that a portion of the logical memory region is allocated and mapped to thePCT Application Attorney Docket No. 120426-312101 / WO memory block 211 in the physical memory space 121; and the remaining portion of the logical memory region / page can be rendered inaccessible. The physical memory address 124 of the memory block 211 can be provided by the memory sub-system 101 to the host system 102 in a completion record 138. When the host system 102 uses the physical memory address (e.g., 124) in the memory block 211 to access the data cached or buffered for the storage location, no translation between the physical memory space 121 and the logical memory space is performed, which improves the access speed / latency. When a further storage access request is received in the memory sub-system 101 to access the same storage location, the memory sub-system 101 can determine, based on the entry in the logical to physical translation table, that the storage location has buffered / cached data in the memory space 121. To determine the memory address to the buffered / cached data, the memory sub-system 101 can search the translation look aside table (or buffer pointer table) to identify logical memory region / page in the logical memory space that is allocated to buffer / cache data of the storage location, and then use the memory allocation map to determine the physical memory address (e.g., 124) of the buffered / cached data.

[0281] The logical memory space can be divided into logical memory pages each having the same capacity as the size of translation unit. When a translation unit having data cached / buffered in the memory space 121, a logical memory page can be allocated for the translation unit. An entry can be added in a buffer pointer table to map the allocated logical memory page in the logical memory space to the translation unit. Typically, the host system 102 accesses the memory sub-system 101 to cause a portion of the entire data of the translation unit to be buffered or cached in the memory space 121. To improve the efficiency in the usage of the random access memory in the memory space 121, the physical memory block (e.g., 211) allocated from the memory space 121 to buffer or cache the data has a size smaller than the size of a translation unit. When the translation unit is mapped to a logical memory page, only a portion of the logical memory page has data cached or buffered in the memory space 121. The memory sub-system 101 can add an entry in a memory allocation map to implement the portion of the logical memory page and thus map the portion of the logical memory page to the memory block (e.g., 211), leaving the remaining portion of the logical memory page without physical implementation. Such a technique allows memory blocks (e.g., 211) allocated with varying sizes from the physical memory space 121 to be mapped to logical memory pages of the same size in the logical memory space.

[0282] For example, a logical pool of random access memory can be configured as memory pages having a same size as a translation unit. The content of each logical memory page may exist, not exist, or partially exist, to allow efficient mapping to physical memory blocks (e.g.,PCT Application Attorney Docket No. 120426-312101 / WO 211) allocated for use by the host system 102. Some portions of the logical pool of random access memory may not have direct physical representation and thus can be rendered inaccessible by the memory sub-system 101.

[0283] In contrast, a physical pool of random access memory (e.g., random access memory cells 123 in the physical memory space 121) can be addressed by the host system 102 over a connection 107 between the host system 102 and the memory sub-system 101. Memory blocks of different sizes can be allocated from the physical pool of random access memory in the memory space 121. For example, the host system 102 can request the allocation of a memory block 211 via a memory allocation request (e.g., 203 as in FIG. 16) for accessing a range of logical block addresses, or a storage access request (e.g., 221 as in FIG. 18) to access a portion of the data at a logical block address.

[0284] Consider, as an example, the memory sub-system 101 receives 4 commands (e.g., CMD1, CMD2, CMD3, and CMD4) in a row, each causing the memory sub-system 101 to cache or buffer data in the memory space 121. In the example, the LB A size of the storage space 131 in the memory sub-system 101 is 4 KB. CMD1 accesses a first range of LBA addresses, starting at LBA A and having a data length covering one LBA address. Thus, the size of the memory block allocated and / or used to buffer the data of LBA A is 4 KB. CMD2 accesses a second range of LBA addresses, starting at LBA B and having a data length covering two LBA addresses. Thus, the size of the memory block allocated and / or used to buffer the data of the second range of LBA addresses is 8 KB. CMD3 accesses a portion of a third range of LBA addresses, starting at LBA C and having a data length covering 128 bytes of LBA C.Thus, the size of the memory block allocated and / or us to buffer the portion of the data at LBA C is 129 bytes. CMD4 accesses a fourth range of LBA addresses, starting at LBA D and having a data length covering three LBA addresses. Thus, the size of the memory block allocated and / or used to buffer the third range of LBA addresses is 12 KB.

[0285] In the physical memory space 121, the memory blocks allocated for CMD1 to CMD4 can be from a contiguous region of physical memory addresses without gaps between adjacent memory blocks. For example, the host system 102 can access the random access memory in the physical memory space 121 at the granularity of cache line (e.g., 128 bytes).

[0286] A logical memory space can be configured to have evenly sized logical memory pages, each having a size of 16 KB. Thus, the memory block allocated to CMD1 can be mapped to the leading 4 KB of logical memory page A; the memory block allocated to CMD2 can be mapped to the leading 8 KB of logical memory page B; the memory block allocated to CMD3 can be mapped to the leading 128 bytes of logical memory page C; and the memory block allocated to CMD4 can be mapped to the leading 12 KB of logical memory page D. As a result,PCT Application Attorney Docket No. 120426-312101 / WO each memory block is mapped to a different logical memory page; and a same logical memory page is not shared by memory blocks buffering or caching data at different LBA addresses. The mapping of the memory blocks from the physical memory space 121 into the evenly sized logical memory pages in the logical memory space allows fast search and allocation operations without wasting physical memory resources in the memory space 121.

[0287] Each entry of a logical to physical translation table of the flash translation layer can be augmented to include a bit-sized field usable to indicate whether or not the LBA address to be translated via the entry has data in the memory space 121. When the capacity ratio between the memory space 121 and the storage space 131 is 1 : 1000, no more than 0.1% of the buffering status bits in the entries in the logical to physical translation table will have a set value (e.g., 1) to indicate that the respective data is cached or buffered in the memory space 121. A buffer pointer table, separate from the logical to physical translation table, is used to identify the logical memory pages allocated for the 0.1% or less of LBA addresses that have data cached or buffered in the memory space 121.

[0288] For example, the buffer pointer table can be an array containing pointers to the logical memory pages in the logical pool. The buffer pointer table contains entries for LBA addresses that have the set value (e.g., 1) in the buffering status bit of respective entries in the logical to physical translation table. The buffer pointer table contains no entries for LBA addresses that don’t have the set value (e.g., 1) in the buffering status bit of respective entries in the logical to physical translation table. For example, a pointer in the buffer pointer table can be a five-byte identification of a logical memory page in the logical memory space; and such pointers are instantiated in the buffer pointer table only for the 0.1% or less entries in the logical to physical translation table.

[0289] For example, CMD1 is used and / or executed in the memory sub-system 101 to read the data at the first range of LBA addresses into the memory space 121. During the execution of CMD1, the memory sub-system 101 can check, in the logical to physical translation table, the buffering status bit of the entry for the translation of LBA A that is addressed by CMD1.

[0290] If the buffering status bit indicates that LBA A is not yet buffered in the memory space 121, the memory sub-system 101 can identify a memory address of a memory block in the memory space 121 as the destination location of the read operation of CMD1. For example, the memory address can be specified in CMD1 in one instance; and in another instance, the CMD1 can include a built-in memory request that causes the memory sub-system 101 to allocate the memory block as the read destination. After the data is read into the memory block in the memory space 121 as the read destination, the memory sub-system 101 can update the buffering status bit to have the set value (e.g., 1) to indicate that LBA A has data buffered or cached in thePCT Application Attorney Docket No. 120426-312101 / WO memory space 121. The memory sub-system 101 can further add an entry to the buffer pointer table to indicate that LBA A is mapped to logical memory page A that is not already in use in the memory allocation map; and the memory sub-system 101 can specify in the memory allocation map that the first 4 KB of logical memory page A is mapped to the physical memory block in the memory space 121, starting with the physical memory address used as the read destination of the read operation of CMD1.

[0291] If the buffering status bit indicates that LBA A is already buffered in the memory space 121, the memory sub-system 101 can search the buffer pointer table to determine the logical memory page that is associated with LBA A and then determine, from the memory allocation map, the physical memory block that is mapped to the logical memory page. If the physical memory block as identified by the memory allocation map is buffering the entire data of LBA A, the memory sub-system 101 can skip the operation to read from the storage space 131 according to LBA A and generate a response using the physical memory block. For example, if CMD1 includes a built-in memory request (e.g., 223), the memory sub-system 101 can return the start memory address of the physical memory block currently buffering the data for LBA A without allocating another memory block to buffer the data of LBA A. For example, if CMD1 specifies a memory address in the memory space 121 (e.g., a memory address of a memory block previously allocated via a memory allocation request 203) as the read destination and the memory address is different from the memory block currently buff ering / caching the data for LBA A, the memory sub-system 101 can copy the data from the physical memory block currently buffering the data for LBA A to the read destination identified in CMD1. Optionally, the memory sub-system 101 can update the memory allocation map and the buffer pointer table to indicate that the data of LBA A is cached or buffered in both locations in the memory space 121, and perform operations to maintain data consistency across the locations and thus cache coherency.

[0292] For example, CMD2 is used and / or executed in the memory sub-system 101 to write data in the memory space 121 to the second range of LBA addresses. During the execution of CMD2 the memory sub-system 101 can check, in the logical to physical translation table, the buffering status bit of the entry for the translation of two LBA addresses starting with LBA B identified by CMD2.

[0293] If the buffering status bit indicates that two LBA addresses are not buffered in the memory space 121 before the execution of CMD2, the memory sub-system 101 can identify the memory address of the memory block in the memory space 121 provided by CMD2 to identify the source location of the write operation of CMD2. The memory sub-system 101 can update the buffering status bit to the set value (e.g., 1) that is configured to indicate the status of havingPCT Application Attorney Docket No. 120426-312101 / WO data buffered or cached in the memory space 121. The memory sub-system 101 can further add an entry to the buffer pointer table to indicate that the two LB A addresses are mapped to a logical memory page B that is not already in use in the memory allocation map and specify in the memory allocation map that the first 8 KB of the logical memory page B is mapped to the physical memory block in the memory space 121, starting with the physical memory address used to identify the source location of the write operation of CMD2.

[0294] If the buffering status bit indicates that the data at the two LBA addresses starting with LBA B is already buffered in the memory space 121, the memory sub-system 101 can search the buffer pointer table to determine the logical memory page that is associated with LBA B and then determine, from the memory allocation map, the physical memory block that is mapped to the logical memory page before the processing of CMD2. If the physical memory block is the same as the source location of the write operation of CMD2, the memory subsystem 101 can skip the operation to program memory cells in the storage space 131 in some instances. In some instances, the storage space 131 can no longer store valid data for an LBA address after the data buffered or cached in the memory space 121 has been modified by the host system 102. For example, the logical to physical translation table can be configured to indicate whether or not the data of the two LBA addresses are stored in the storage space 131. For example, when the host system 102 uses a memory access request to change the data in the physical memory block caching or buffering the data at the two LBA addresses (e.g., as in FIG.15), the memory sub-system 101 can update the logical to physical translation table to indicate that the storage space 131 no longer stores the data for the two LBA addresses. For example, to indicate that the storage space 131 no longer stores the data for the two LBA addresses, the logical to physical translation table can be updated to map the LBA addresses to an invalid address of non-volatile memory pages, a predetermined address, or the memory address in the memory space 121 caching or buffering the data of the LBA addresses. If the data at the two LBA addresses starting with LBA B is not already in the storage space 131, the memory subsystem 101 can perform the operation to write data to the storage space 131 and update the logical to physical translation table to indicate the persistent storage locations (e.g., NAND addresses) of the data at the two LBA addresses.

[0295] In some instances, at least a portion of the data at two LBA addresses starting from LBA B is buffered in a memory location different from the source location identified in CMD2; and the memory sub-system can update the portion of the buffered data according to the data provided in the source location to maintain consistency and update the buffer pointer table and the memory allocation table to indicate the data buffering at the different locations.

[0296] In some instances, the source location is configured to provide a portion of the data atPCT Application Attorney Docket No. 120426-312101 / WO the two LB A addresses starting from LB A B. In response, the memory sub-system can perform construct a complete data for the two LBA addresses, as modified by the data at the source location identified by CMD2, for the persistent storing into the storage space 131.

[0297] For example, CMD3 is used and / or executed in the memory sub-system 101 to read a portion of the data at LBA C into the memory space 121. For example, the portion of the data can be identified via a scatter gather list (SGL) according to a standard of non-volatile memory express (NVMe). During execution of CMD3, the memory sub-system 101 can check, in the logical to physical translation table, the buffering status bit of the entry for the translation of LBA C addressed by CMD3.

[0298] If the buffering status bit indicates that LBA C is not yet buffered in the memory space 121, the memory sub-system 101 can identify a memory address of a memory block in the memory space 121 as the destination of the read operation of CMD3. For example, the memory address can be specified in CMD3 in one instance; and in another instance, the CMD3 can include a built-in memory request that causes the memory sub-system 101 to allocate the memory block as the read destination. After the data is read into the memory block in the memory space 121 as the read destination, the memory sub-system 101 can update the buffering status bit to the set value (e.g., 1) to indicate that a least a portion of data at LBA C is buffered or cached in the memory space 121. The memory sub-system 101 can allocate, for LBA C, logical memory page C that is not already in use in the memory allocation map, add an entry to the buffer pointer table to indicate that LBA C is mapped to logical memory page C, and specify in the memory allocation map that the first 128 bytes of the logical memory page C is mapped to the physical memory block in the memory space 121, starting with the physical memory address used as the read destination of the read operation of CMD3. Optionally, the memory sub-system 101 can allocate a memory block to buffer the entire data of LBA C (e.g., in anticipation of the host system 102 accessing other portions of the data at LBA C, and / or to prevent fragmentation of memory resources in the memory space 121); and the memory sub-system 101 can provide the memory address of the portion of the data addressed by CMD3 via a completion record 138 (e.g., as in FIG. 18) when the CMD3 has a built-in memory request, or copy the requested data from the memory block buffering or caching the entire data of LBA C to the memory address identified by CMD3. Optionally, when the data is copied to another location in the memory space 121 as identified by CMD3 as the read destination, the memory sub-system 101 can update the buffer pointer table and the memory allocation map to identify the multiple locations in the memory space 121 used to buffer data of LBA C. The different locations in the memory space 121 can be tracked using different logical memory pages allocated from the logical pool.

[0299] An advantage of having page sized, input output independent buffer pointers is thatPCT Application Attorney Docket No. 120426-312101 / WO such buffer points can be organized in a searchable and sortable way. For example, new entries can be added and tracked via a binary tree or another technique. A binary tree can be rebalanced for improved search performance (e.g., in determination of a logical memory page mapped to a translation unit, and / or in determination of a translation unit mapped to a logical memory page). Branches can be pruned in a fast and efficient way.

[0300] FIG. 20 shows a technique to track locations in a storage space of a memory subsystem having data buffered in a memory space of the memory sub-system according to one embodiment.

[0301] For example, the technique of FIG. 20 can be implemented in the memory subsystem 101 of FIG. 1 to FIG. 13 to track data in memory blocks (e.g., 211) allocated from the memory space 121 (e.g., allocated using the techniques of FIG. 16, FIG. 18 and / or FIG. 19) for accessing the storage space 131 of the memory sub-system 101 using the techniques of FIG. 14 and FIG. 15.

[0302] In FIG. 20, the memory sub-system 101 has a logical to physical translation table 183 (e.g., configured in a flash translation layer of the memory sub-system 101). The logical to physical translation table 183 has entries, each configured to identify the mapping between a logical block address 134 in the logical storage space 132 of the memory sub-system and a memory page address 136 in the physical storage space 131 of the memory sub-system 101. For example, the logical block address 134 can be an LB A address according to a standard of NVMe. For example, the memory page address 136 can be the address to identify a set of nonvolatile memory cells, such as NAND memory cells, in the memory sub-system 101.

[0303] Further, each entry in the logical to physical translation table 183 is configured to include a field for holding a buffering status bit 189. For example, when the buffering status bit 189 has a set value (e.g., 1), the entry indicates that the data at the logical block address 134, representative of a logical storage block 193 in the logical storage space 132, is cached or buffered in the physical memory space 121 of the memory sub-system 101. Otherwise, the entry indicates that no data at the logical block address 134 is available in the physical memory space 121.

[0304] For example, each entry in the logical to physical translation table 183 has a same predetermined size, regardless of the content in the fields of the entry. When the physical storage space 131 is not storing data for the logical storage block 193 represented by the logical block address 134, the entry of the logical block address 134 can identify an invalid memory page address 136, or a predetermined memory page address 136. When the data at the logical storage block 193 is cached or buffered in the physical memory space 121 of the memory subsystem 101 but not yet committed into the physical storage space 131, the entry of the logicalPCT Application Attorney Docket No. 120426-312101 / WO block address 134 can identify a memory address buffering data in the physical memory space 121 for the logical block address 134 as the memory page address 136. The memory sub-system 101 is configured to be able to tell whether the content specified in the field for memory page address 136 is a memory address in the physical memory space 121 storing the data for the logical block address 134, or a memory page 133 in the physical storage space 131 storing the data for the logical block address 134, or an invalid address.

[0305] Optionally, the memory sub-system 101 is configured to store data of the logical block address 134 either in the physical memory space 121, or in the physical storage space 131. In such an implementation, the field for buffering status bit 189 can be eliminated; and the memory sub-system 101 can determine the buffering status of the logical block address 134 based on the type of content specified in the field of memory page address 136. In alternative implementations, the memory sub-system 101 can store data of the logical block address 134 in both the physical memory space 121 and the physical storage space 131 in some instances. For example, the physical storage space 131 can store the entire data for the logical block address 134, while the physical memory space 121 stores a portion of the entire data stored in the physical storage space 131.

[0306] In FIG. 20, the memory sub-system 101 maintains a buffer pointer table 185, separate from entries in the logical to physical translation table 183, for logical block addresses (e.g., 134) that have the set value (e.g., 1) in their fields of buffering status bit 189.

[0307] Optionally, memory blocks (e.g., 211) of varying sizes are mapped to logical memory regions (e.g., 191) having the same size. For example, the size of each memory region can be the same as the size of a logical storage block (e.g., 193) represented by a logical block address (e.g., 134), or larger.

[0308] Memory blocks (e.g., 211) allocated from the physical memory space 121 for use by the host system 102 (e.g., using the techniques of FIG. 16 to FIG. 19) and / or used to access the storage space 131 (e.g., using the techniques of FIG. 2 to FIG. 15) can be tracked using a memory allocation map 187.

[0309] For example, the memory block 211 in the physical memory space 121 has a starting memory address 124 (e.g., usable by the host system 102 in a memory access request (e.g., 127) to access the memory space 121 over a connection 107 to the memory sub-system 101). An entry in the memory allocation map 187 can associate the physical memory address 124 with a logical region identifier 195 that identifies the logical memory region 191 in the logical memory space 122 to indicate that the memory block 211 is mapped to the beginning portion of the logical memory region 191. The size of the memory block and the beginning portion of the logical memory region 191 is identified by an allocation size 207 specified in the entry for thePCT Application Attorney Docket No. 120426-312101 / WO logical region identifier 195.

[0310] Optionally, the size of each logical memory region 191 is configured to be the upper limit of a memory block (e.g., 211) that can be allocated for the host system 102 at once. Thus, each memory block (e.g., 211) allocated to the host system 102 (e.g., via a memory allocation request 203, or a storage access request 221 having a built-in memory request 223) can be mapped to one logical memory region (e.g., 191).

[0311] Alternatively, when a memory block is larger than the size of a logical memory region (e.g., 191), the memory sub-system 101 can split it into multiple blocks for mapping to multiple logical memory regions (e.g., 191).

[0312] Each logical memory region 191 is configured to host no more than one memory block (e.g., 211) allocated from the physical memory space 121. Thus, when an entry in the buffer pointer table 185 maps a logical block address 134 to a logical region identifier 195 representative of a logical memory region 191, the memory allocation map 187 can be used to further map the logical block address 134 to a memory block 211 in the physical memory space 121.

[0313] Optionally, the allocation size 207 of a memory block 211 can be smaller than the size of a logical storage block 193 represented by a logical block address 134. The memory block 211 is mapped to a beginning portion of the logical memory region 191 and thus to a beginning portion of the logical storage block 193.

[0314] Optionally, a memory block 211 can be used to buffer or cache a portion of the logical storage block 193 that does not start from the beginning of the logical storage block 193. To track the position of the buffered or cached portion relative to the beginning of the logical storage block 193, the memory allocation map 187 can be further configured to include an offset field for each entry. The offset field can be used to identify the offset of the memory block 211 relative to the beginning of the logical storage block 193 (e.g., as in FIG. 22).

[0315] When the data at the logical storage block 193, represented by the logical block address 134 defined in the logical storage space 132, is buffered / cached in a memory block 211 in the physical memory space 121, the host system 102 can execute one or more store instruction (e.g., 175) to modify the data (e.g., as in FIG. 15). In such an instance, the memory sub-system 101 can use the memory allocation map 187 to identify the logical region identifier 195 of the memory address being accessed for data modification, then use the buffer pointer table 185 to identify the logical block address 134, and then identify the entry of the logical block address 134 in the logical to physical translation table 183. The memory sub-system 101 can update the entry to indicate that the physical storage space 131 no longer stores the data for the logical block address 134, and / or the data for the logical block address 134 resides in the physicalPCT Application Attorney Docket No. 120426-312101 / WO memory space 121.

[0316] In some implementations, a portion of the data buffered in the physical memory space 121 is modified by the host system 102 via a memory access request (e.g., 127), the memory sub-system 101 can store a bit-sized status indicator in the buffer pointer table 185 or the memory allocation map 187 to indicate that the physical memory space 121 has a data portion that is more up to data than the data in the physical storage space 131. When the data at the logical block address 134 is to be committed to the physical storage space 131, the memory sub-system can check the bit-sized status indicator to determine whether to combine the data in the physical memory space 121 and in the physical storage space 131 to generate the complete, up to date data from the logical block address 134 and / or to perform a write operation to save the data of the logical block address 134 to the physical storage space 131.

[0317] Optionally, data of different portions of the logical storage block 193 can be buffered and / or cached in different memory blocks (e.g., 211). The different memory blocks are mapped to different memory regions (e.g., 191). Thus, the buffer pointer table 185 can store multiple entries to map the logical block address 134 of the logical storage block 193 to more than one logical region identifiers (e.g., 195).

[0318] In some implementations, the memory allocation map 187 and the buffer pointer table 185 are combined, where each entry identifies a logical block address (e.g., 134), a logical region identifier (e.g., 195), a physical memory address (e.g., 124), an allocation size (e.g., 207), and an offset (e.g., 227 in FIG. 25). The table can be sorted and / or indexed for fast searching according to memory address, logical memory region, and / or logical block address.

[0319] In some implementations, the logical memory space 122 and the logical storage space 132 have a fixed, predetermined relation / mapping. Thus, the logical region identifier 195 can be computed from the logical block address 134 without the need for a mapping table (e.g., as in FIG.24).

[0320] In some implementations, the offset of the memory block 211 relative to the logical storage block 193 is tracked via the buffer pointer table when the buffering status bit 189 is updated to have a set value. When a physical memory block 211 is allocated, the starting memory address 124 of the memory block 211 and its allocation size 207 are tracked via an entry in the memory allocation map 187. The memory block 211 is always mapped to the beginning portion of the logical memory region 191. When a portion of the memory block 211 is used to cache or buffer a portion of the logical storage block 193 represented by the logical block address 134, an entry is added to the buffer pointer table to identify, for the logical block address 134, the logical region identifier 195 representative of the logical memory region 191. Further, the entry can identify the offset between the logical memory region 191 and the logicalPCT Application Attorney Docket No. 120426-312101 / WO storage block 193 such that the portion of the memory block 211, as mapped into the beginning portion of the logical memory region 192, is further mapped with the offset into the corresponding portion of the logical storage block 193 that has the data being buffered in the portion of the memory block 211 (e.g., as illustrated in FIG. 26). Further, the entry can specify the size of the portion of the memory block 211 having the data buffered for the portion of the logical storage block 193.

[0321] In some implementations, a memory block 211 allocated from the physical memory space 121 is used entirely for the buffering of data from the logical block address 134. An entry in the memory allocation map 187 is configured to map the memory block 211 to a portion of the logical memory region 191 with an offset from the beginning of the logical memory region 191 (e.g., the smallest memory logical memory address in the logical memory region 191) such that, when the logical memory region 191 is mapped with the logical storage block 193, the portion of the logical memory region 191 is mapped to the portion of the logical storage block 193 having data being buffered in the memory block 211 (e.g., as illustrated in FIG. 25)

[0322] FIG. 21 shows a technique to map an allocated memory chunk to a logical memory space according to one embodiment. For example, the memory allocation map 187 of FIG. 20 can be configured to map memory blocks (e.g., 211) allocated from a physical memory space 121 in a memory sub-system 101 to a logical memory space 122 in a way as illustrated in FIG.21

[0323] In FIG. 21, a memory block 211 allocated from a memory space 121 of a memory sub-system 101 for access by a host system 102 includes a plurality of memory addresses 124, ..., 128, starting with memory address 124. The allocation size 207 of the memory block 211 identifies the storage capacity of the memory block 211 and thus the number of consecutive memory addresses 124, ..., 128 that can be addressed to access portions of the memory block 211.

[0324] The logical memory space 122 is configured to have a plurality of logical memory regions 191, 192, ..., each having a same predefined region size 197. Allocation sizes (e.g., 207) of memory blocks (e.g., 211) are configured to be no larger than the predefined region size 197. In some instances, when the host system 102 is to use a memory chunk that is larger than the predefined region size 197, the host system 102 can request for the allocation of more than one memory block (e.g., 211). Alternatively, the memory sub-system 101 can break a larger memory chunk into a plurality of memory blocks (e.g., 211), each having an allocation size 207 that is no larger than the predefined region size 197.

[0325] In FIG. 21, the memory block 211 is mapped to the beginning allocated portion 224 of the mapped logical memory region 191 according to the allocation size 207. The portion 225PCT Application Attorney Docket No. 120426-312101 / WO following the allocated portion 224 in the mapped logical memory region 191 is unused. For example, the memory addresses in the unused portion 225 of the logical memory region 191 can be rendered inaccessible.

[0326] The mapping of the memory blocks (e.g., 211) having varying allocation sizes 207 to memory regions (e.g., 191) of a predefined region size 197 can simplify the management of allocated memory resources, without wasting resources in the physical memory space 121.

[0327] For example, each allocated memory block (e.g., 211) can be represented by a separate logical memory region (e.g., 191) of a predefined region size 197. A logical memory region (e.g., 191) is not mapped to more than one allocated memory block.

[0328] In some implementations, the predefined region size 197 is configured to be the same as the size of a translation unit (e.g., 217 in FIG.22) for an entry in the logical to physical translation table 183 of the memory sub-system 101.

[0329] FIG. 22 shows a logical to physical mapping configured to facilitate tracking of buffered storage locations in a memory sub-system according to one embodiment. For example, instead of having an entry in the logical to physical translation table 183 in FIG. 20 for each logical block address (e.g., 134), a plurality of logical block addresses (e.g., 134, ...) can be grouped as a translation unit 217 to share a same entry in the logical to physical translation table 183 as in FIG. 22 to reduce the size of the logical to physical translation table 183.

[0330] In FIG. 22, a translation unit 217 can include a predetermined number of consecutive logical block addresses (e.g., 134, ...). For example, a binary representation of an identifier of the translation unit 217 can be the common leading portion of the binary representations the consecutive logical block addresses (e.g., 134, ...). Thus, the set of logical block addresses (e.g., 134, ...) of the translation unit 217 can be readily identified from the identifier of the translation unit 217; and the identifier of the translation unit 217 containing a logical block address 134 can be easily computed from the logical block address 134.

[0331] In FIG. 22, an identifier of a memory page set 219 is used to identify the addresses (e.g., 136) of memory pages (e.g., 133) used to implement the translation unit 217 in the physical storage space 131. The memory page addresses (e.g., 136) in the set 219 can be computed from the identifier of the memory page set 219; and the predetermined, fixed mapping relation is applied to the logical block addresses (e.g., 134) in the translation unit 217 and the addresses (e.g., 136) of memory pages storing data for the respective logical block addresses (e.g., 134). When the entry of the logical to physical translation table 183 is configured to map at the granularity level of a translation unit 217 having a plurality of logical block addresses (e.g., 134, ...), the number of entries used to map between the logical storage space 132 and the physical storage space 131 can be reduced.PCT Application Attorney Docket No. 120426-312101 / WO

[0332] In FIG. 22, a field of buffering status bit 189 is configured to store a bit-value.When the bit value is a set value (e.g., 1), the entry indicates that the translation unit 217 has data buffered or cached in the memory space 121 in the memory sub-system 101. When the bit value is a non-set value (e.g., 0), the entry indicates that the translation unit 217 has no data available in the memory space 121 in the memory sub-system 101.

[0333] FIG. 23 shows mapping of an allocated memory block to a logical block address in a memory sub-system according to one embodiment. For example, when the logical to physical translation table 183 is configured to perform mapping at a granularity of a translation unit 217 containing a plurality of logical block addresses (e.g., 134, ...), the mapping between the allocated memory block 211 to a logical block address 134 in FIG. 20 can be established in a way as illustrated in FIG.23.

[0334] In FIG. 23, the logical memory region 191 is configured to have a same capacity size 208 as the translation unit 217 as used in the logical to physical translation table 183. The memory block 211 is mapped to the allocated portion 224 at the beginning of the logical memory region 191; and the translation unit 217 is mapped to the logical memory region 191 (e.g., via an entry in the buffer pointer table 185 associating the identifier 195 of the logical memory region 191 with an identifier of the translation unit 217). Thus, the memory block 211 is seen storing data for the beginning portion of the set of logical storage blocks (e.g., 193) presented by the corresponding logical block addresses (e.g., 134) in the translation unit 217. Since the translation unit 217 can include a plurality of logical block addresses (e.g., 134, ...), the allocated memory block 211 can store data for more than one logical block address in the translation unit 217 (e.g., when the allocation size is larger than the size of a logical storage block 193 represented by a logical block address 134).

[0335] In some implementations, the memory block 211 is not limited to store data starting from the beginning portion of the translation unit 217. The memory allocation map 187 or the buffer pointer table 185 can store an offset to align the mapping between the allocated memory block 211 and the portion of the translation unit 217 having data stored in the memory block 211 (e.g., as in FIG. 25 and FIG. 26).

[0336] In some embodiments, the logical memory space 122 and the logical storage space 132 have a predetermined, fixed mapping relation (e.g., as illustrated in FIG. 24). In such an implementation, it is not necessary to store data mapping between a logical memory region (e.g., 191) and a translation unit (e.g., 217), as illustrated in FIG. 24.

[0337] FIG. 24 shows mapping of an allocated memory block to a logical block address through a predetermined relation between a logical memory space and a logical storage space in a memory sub-system according to one embodiment.PCT Application Attorney Docket No. 120426-312101 / WO

[0338] In FIG. 24, the logical memory regions 191, ..., 192 in the logical memory space 122 are fixedly mapped into blocks 193, ..., 194 in the logical storage space 132. For example, the identifier 195 of the logical memory region 191 can be computed, using a predetermined algorithm, from the logical block address 134 of the logical storage block 193 without using a look up table; and the logical block address 134 of the logical storage block 193 can be computed, using a predetermined algorithm, from the identifier 195 of the logical memory region 191 without using a look up table. Thus, when the memory block 211 is mapped (e.g., via the memory allocation map 187) to the beginning portion of the logical memory region 191, the memory block 211 is automatically mapped to the corresponding logical storage block 193 in the logical storage space 132 and thus its logical block address 134.

[0339] Optionally, the mapping between the logical memory space 122 and the logical storage space 132 can be established as the granularity level of each translation unit (e.g., 217) containing a plurality of logical block addresses (e.g., 134, ...).

[0340] When the memory block 211 is used to buffer or cache data for a portion of the logical storage block (e.g., 193) (or a translation unit (e.g., 217)) but starting from the beginning of the logical storage block (e.g., 193) (or the translation unit (e.g., 217)), the memory allocation map 187 can store an offset 227 to allow the mapping of the memory block 211 to the correct portion of the logical storage block (e.g., 193) (or the translation unit (e.g., 217)), as illustrated in FIG. 25.

[0341] FIG. 25 and FIG. 26 show mapping of an allocated memory block to a logical block address having misalignment with a logical memory region in a memory sub-system according to one embodiment.

[0342] In FIG. 25, an offset 227 (e.g., stored in the memory allocation map 187) identifies an allocated portion 224 of the logical memory region 191 such that when the allocated portion 224 is mapped (e.g., via a predetermined algorithm) to the translation unit 217, the allocated portion 224 corresponds to the portion of the translation unit 217 having data stored in the allocated memory block 211. The logical memory region 191 can have an unused portion 226 at the beginning and an unused portion 225 at the end of the logical memory region 191. It is not necessary to maintain a buffer pointer table 185 to map between an identifier 195 of the logical memory region 191 and an identifier of the translation unit 217, when the logical memory space 122 and the logical storage space 132 has a predetermined relation (e.g., as in FIG. 24).

[0343] Optionally, the offset 227 can be used to align the allocated portion 224 with the logical block address 134 that is not at the beginning address in the translation unit 217.

[0344] Optionally, the offset 227 can be used to align the allocated portion 224 with a portion of the logical block address 134 that is not at the beginning portion of the logical storagePCT Application Attorney Docket No. 120426-312101 / WO block 193 represented by the logical block address 134.

[0345] Alternatively, the memory allocation map 187 can be configured to always map a memory block (e.g., 211) to the beginning portion of a logical memory region (e.g., 191), as in FIG. 26. An entry in the buffer pointer table 185 can include an offset field to identify an offset between a logical memory region (e.g., 191) and a translation unit (e.g., 217) such that the beginning portion of the logical memory region 191 is mapped to a correct segment in the translation unit 217, as in FIG.26.

[0346] For example, when the technique of FIG. 26 is used, an entry in the buffer pointer table 185 can include a field to specify the identifier of the translation unit 217 in association with the identifier 195 of the logical memory region 191, and a field to specify the offset 227.

[0347] In some implementations, a portion of the allocated memory block 211 is used to buffer a portion of the translation unit 217. Thus, the offset 227 can be specified in the entry in the buffer pointer table 185 for the logical memory region with an offset 227 such that the portion of the allocated memory block 211, as in the allocated portion 224 of the logical memory region 191, is mapped to the corresponding portion of the translation unit 217 having data being buffered in the portion of the allocated memory block 211. Further, the entry can include a field to specify the size of the portion of the allocated memory block 211 used to buffer the data of the portion of the translation unit 217.

[0348] FIG. 27 to FIG. 29 show methods to track memory blocks allocated from a memory space of a memory sub-system to access a storage space of the memory sub-system according to some embodiments. The methods of FIG. 27 to FIG. 29 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software / firmware (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the methods of FIG. 27 to FIG. 29 are performed at least in part by the processing device 118 of the host system 102, the controller 115 of the memory sub-system 101, and / or the local media controller 105 of the memory sub-system 101 in FIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0349] For example, the methods of FIG. 27 to FIG. 29 can be implemented (e.g., via firmware and application specific circuits) as part of an access manager 113 in the memory sub-PCT Application Attorney Docket No. 120426-312101 / WO system 101.

[0350] FIG. 27 shows a method to map between physical memory chunks and logical storage blocks in a memory sub-system having data buffered in the physical memory chunks according to one embodiment.

[0351] For example, the memory sub-system 101 can have: a controller 115; memory cells of a first type (e.g., random access memory) to provide a memory space addressable by a host system using memory addresses according to a standard for compute express link (CXL) or component interconnect express (PCIe); and memory cells of a second type (e.g., flash memory) to provide a physical storage space addressable by the host system using logical block addressing (LB A) addresses according to a standard of non-volatile memory express (NVMe). The controller 115 of the memory sub-system 101 can be configured (e.g., via firmware and / or application specific circuits) to: store a plurality of entries in a logical to physical translation table 183, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space 132 and a portion of the physical storage space 131 of the memory sub-system 101; store, in the memory space 121, a copy of a data portion addressable in the logical storage space 132; configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space 121; and store information to identify a location, in the memory space 121, at which the data portion is cached or buffered.

[0352] At block 301, the method of FIG. 27 includes storing, in a memory sub-system 101, a plurality of entries in a logical to physical translation table 183. Each respective entry in the plurality of entries is configured to identify mapping between a portion of a logical storage space 132 (e.g., a logical storage block 193, logical storage blocks represented by logical block addresses in a translation unit 217) and a portion of a physical storage space 131 (e.g., memory page 133, a memory page set 219) of the memory sub-system 101.

[0353] For example, each of the plurality of entries as stored in the memory sub-system 101 occupies a same size of storage resources.

[0354] For example, each of the plurality of entries can have a field to specify an identifier of a portion of the logical storage space 132 (e.g., a logical block address 134 representative of a logical storage block 193, an identifier of a translation unit 217). Each of the plurality of entries can further include a field to specify an identifier of a portion of the physical storage space 131 (e.g., a memory page address 136 representative of a non-volatile memory page 133, an identifier of a memory page set 219). Each of the plurality of entries can further include a field to specify a bit value indicative of whether the portion of the logical storage space 132 has data buffered or cached in a memory space 121 of the memory sub-system 101.PCT Application Attorney Docket No. 120426-312101 / WO

[0355] For example, the respective entry can contain fields for buffering status bit 189, logical block address 134 and memory page address 136 as illustrated in FIG. 20, or contain fields for buffering status bit 189, an identifier of a translation unit 217, and an identifier of a memory page set 219 as illustrated in FIG.22. The field for buffering status bit 189 can be a bit-sized field configured to store a parameter indicative of whether or not the portion of the logical storage space 132, being mapped to the portion of the physical storage space 131, has data buffered or cached in the memory space 121.

[0356] For example, the portion of the logical storage space 132 can include a plurality of logical storage blocks (e.g., 193) addressable via a plurality of logical block addressing (LBA) addresses (e.g., 134).

[0357] At block 303, the method includes receiving, in the memory sub-system 101, a storage access request 137.

[0358] For example, the storage access request 137 can be configured in a way as illustrated in FIG. 19

[0359] For example, the storage access request 137 can include a built-in memory request 223 as in the request 221 illustrated in FIG. 18.

[0360] For example, the storage access request 137 can be configured in accordance with a standard for NVMe.

[0361] At block 305, the method includes executing, in the memory sub-system 101, the storage access request 137 to cause a data portion (e.g., 157, ..., 158) in the logical storage space 131 (e.g., addressable using logical block address 134) being buffered or cached in a memory space 121 of the memory sub-system 101.

[0362] At block 307, the method includes configuring a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space 121.

[0363] At block 309, the method includes storing, in the memory sub-system, information to identify a location (e.g., memory address 124), in the memory space 121, at which the data portion is cached or buffered.

[0364] For example, the information can include an entry in a buffer pointer table 185 and / or an entry in a memory allocation 187.

[0365] For example, the first entry is configured to map a first portion of the logical storage space 132 (e.g., logical storage block 193 or translation unit 217); and the method of FIG. 27 can further include: searching the information to identify the location (e.g., memory address 124) based on an identifier of the first portion (e.g., logical block address 134 of the logical storage block 193, or identifier of the translation unit 217).

[0366] For example, the method of FIG. 27 can further include: sorting the informationPCT Application Attorney Docket No. 120426-312101 / WO (e.g., buffer pointer table 185 and / or memory allocation map 187) to identify the location (e.g., 134) based on the identifier of the first portion (e.g., logical block address 134 of the logical storage block 193, or identifier of the translation unit 217).

[0367] For example, the data portion is a portion of data stored in the first portion of the logical storage space 131, such as a portion of the data stored in the logical storage block 193, or a portion of the data stored in the storage location represented by the translation unit 217.

[0368] For example, a size of the data portion can be smaller than a size of each of the plurality of logical storage blocks (e.g., 193) addressable respectively via the plurality of logical block addressing (LBA) addresses (e.g., 134).

[0369] FIG. 28 shows a method to map between physical memory chunks and logical memory regions of a predetermined size in a memory sub-system according to one embodiment.

[0370] For example, the memory sub-system 101 can have: random access memory cells (e.g., 123) configured to provide a memory space 121 accessible, via a memory access protocol, by a host system 102 located outside of the memory sub-system; and non-volatile memory cells (e.g., in memory page 133) configured to provide a physical storage space 131 accessible, via a storage access protocol, by the host system 102. A controller 115 of the memory sub-system 101 is configured (e.g., via firmware and / or application specific circuits) to: allocate, from the memory space 121, a plurality of memory blocks (e.g., 211) of varying sizes; establish mapping between a plurality of logical memory regions (e.g., 191, 192) of a same size 197 in a logical memory space 122 and the plurality of memory blocks (e.g., 211) respectively; buffer data (e.g., user data 151), addressable by the host system 102 via a logical block address (e.g., 134) in a logical storage space (e.g., 132) according to the storage access protocol, in a memory block 211 among the plurality of memory blocks; and establish mapping between the memory block 211 and the logical block address 134 via the logical memory space 122.

[0371] At block 321, the method of FIG. 28 includes allocating, from a physical memory space 121 of a memory sub-system 101, a plurality of memory blocks (e.g., 211) that are of varying sizes and accessible by a host system using a memory access protocol.

[0372] At block 323, the method includes providing, by the memory sub-system 101, the host system 102 with access to a physical storage space 131 of the memory sub-system 101 using logical block addresses (e.g., 134) in a logical storage space 132 configured for access according to a storage access protocol.

[0373] At block 325, the method includes establishing, by the memory sub-system 101, mapping between the plurality of memory blocks (e.g., 211) and respectively a plurality of logical memory regions (e.g., 191, 192) of a same size 197 in a logical memory space 122.

[0374] For example, each of the plurality of logical memory regions (e.g., 191, 192) has aPCT Application Attorney Docket No. 120426-312101 / WO capacity size 197 same as a translation unit 217 of a logical to physical translation table 183.

[0375] At block 327, the method includes buffering data (e.g., user data 151), addressable via a logical block address (e.g., 134) in the logical storage space 131, in a memory block 211 among the plurality of memory blocks.

[0376] At block 329, the method includes establishing, by the memory sub-system 101, mapping between the memory block 211 and the logical block address 134 via the logical memory space 122.

[0377] For example, the logical block address 134 can be mapped (e.g., directly, or via a translation unit) to a logical memory region 191 among the plurality of logical memory regions of the same size 197. For example, the memory block 211 can be mapped (e.g., via an entry in a memory allocation map 187) to a portion of the logical memory region 191. Thus, via the logical memory region 191, the logical block address 134 is mapped to the memory block 211.

[0378] For example, the controller 115 in the memory sub-system 101 can be configured to always map (e.g., via an entry in a memory allocation map 187) the memory block 211 to a beginning portion 224 of the logical memory region 191, as in FIG. 26. Alternatively, the controller 115 in the memory sub-system 101 can be operable to map (e.g., via an entry in a memory allocation map 187) the memory block 211 to a portion 224 of the logical memory region 191, with an offset 227 from the beginning portion (e.g., 226) of the logical memory region 191, as in FIG. 25.

[0379] For example, the logical block address 134 can be mapped to a logical memory region 191 via a buffer pointer table 185. Optionally, each entry in the buffer pointer table 185 can include a field to specify an offset 227 between the logical memory region 191 and the translation unit 217 (or logical block address 134) identified by the entry. Optionally, each entry in the buffer pointer table 185 can include a field to specify a size of a portion of the memory block 211 being mapped via the entry.

[0380] FIG. 29 shows a method to track memory chunks allocated to buffer data in a storage space based on a predetermined mapping between a logical memory space and a logical storage space in a memory sub-system according to one embodiment.

[0381] For example, the memory sub-system 101 can include: a random access memory (e.g., DRAM, SRAM) configured to provide a memory space 121 accessible, using a memory access protocol, by a host system 102 over a connection 107 between the host system 102 and the memory sub-system 101; and a non-volatile memory configured to provide a physical storage space accessible, via a storage access protocol, by the host system. At least one processing device 117 of the memory sub-system 101 can be configured to: allocate, from the random access memory, a memory block 211; map the memory block 211 to a logical memoryPCT Application Attorney Docket No. 120426-312101 / WO region 191 in a logical memory space 122; and establish mapping between a logical block address 134, configured in a logical storage space 132 and usable to access a portion of the nonvolatile memory using the storage access protocol, and the memory block 211 via a predetermined mapping between the logical storage space 132 and the logical memory space 122.

[0382] At block 341, the method of FIG. 29 includes allocating, from a physical memory space 121 of a memory sub-system 101, a memory block 211.

[0383] For example, the memory block 211 can be allocated in response to a memory allocation request 203 of FIG. 16, or a storage access request 221 of FIG. 18.

[0384] At block 343, the method includes identifying, by the memory sub-system 101 and to a host system 102, a physical memory address 124 in the physical memory space 121 usable by the host system 102 to access, using a memory access protocol, the memory block 211 over a connection 107 between the host system 102 and the memory sub-system 101.

[0385] For example, the method of FIG. 29 can further include: receiving, in the memory sub-system 101, a request (e.g., 203 or 221) from the host system 102; and the allocating at block 341 and the identifying at block 343 can be in response to the request (e.g., 203 or 221).

[0386] For example, the memory address 124 can be provided in a completion record 138 for the storage access request 221 of FIG. 18, or in a memory allocation response 205 to the memory allocation request 203 of FIG. 16.

[0387] At block 345, the method includes mapping, by the memory sub-system 101, the memory block 211 to a logical memory region 191 in a logical memory space 122.

[0388] For example, an entry can be added to a memory allocation map 187 to identify an identifier 195 of the logical memory region 191, the physical memory address 124 of the memory block 211, and the size 207 of the memory block 211. The entry can map the memory block 211 to the beginning portion of the logical memory region 191 according to the size 207.

[0389] In some implementations, the memory block 211 is mapped to a portion of the logical memory region 191; and the entry for the mapping of the memory block 211 can further include a field to specify an offset of the memory block 211 from the beginning portion of the logical memory region 191.

[0390] At block 347, the method includes providing, by the memory sub-system 101, the host system 102 with access to a portion of a physical storage space 131 of the memory subsystem 101 using a logical block address 134 configured in a logical storage space 132 according to a storage access protocol.

[0391] For example, the portion of the physical storage space 131 can be a logical storage block 193 represented by the logical block address 134.PCT Application Attorney Docket No. 120426-312101 / WO

[0392] At block 349, the method includes establishing, by the memory sub-system 101, mapping between the logical block address 134 and the memory block 211 via a predetermined mapping between the logical storage space 132 and the logical memory space 122, as illustrated in FIG. 24

[0393] For example, the predetermined mapping between the logical storage space 132 and the logical memory space 122 can be based on a predetermined algorithmic relation between identifiers (e.g., 195) of logical memory regions (e.g., 191, 192) in the logical memory space 122 and logical block addresses (e.g., 134) representative of logical storage blocks (e.g., 193) in the logical storage space.

[0394] For example, each respective logical memory region (e.g., 191), among the logical memory regions (e.g., 191, 192), is mapped to a respective translation unit (e.g., 217) containing a plurality of logical block addresses (e.g., 134); an identifier (e.g., 195) of the respective logical memory region (e.g., 191) is computable directly from an identifier of the respective translation unit (e.g., 217); and the identifier of the respective translation unit (e.g., 217) is computable directed from the identifier (e.g., 195) of the respective logical memory region (e.g., 191).

[0395] For example, a storage capacity size of the respective translation unit 217 in the logical storage space 132 is equal to a storage capacity size 197 of the respective logical memory region 191.

[0396] For example, the memory block 211 can be mapped, with an offset 227, to a portion 224 of the logical memory region 191, where the portion 224 is neither a beginning portion of the logical memory region 191, nor an ending portion of the logical memory region 191.

[0397] For example, the storage capacity size of the memory block can be smaller than the storage capacity size of each translation unit (e.g., 217) and / or smaller than a storage capacity size of each logical storage block (e.g., 193) represented by a logical storage address (e.g., 134) in the logical storage space 131.

[0398] A non-transitory computer storage medium can be used to store instructions programmed to implement the access managers 113 in the host system 102 and the memory subsystem 101. When the instructions are executed by the processing device 118, the controller 115, and the processing device 117, the instructions cause the host system 102 and / or the memory sub-system 101 to perform the methods discussed above.

[0399] FIG. 30 illustrates an example machine of a computer system 400 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 400 can correspond to a host system (e.g., the host system 102 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 101 of FIG. 1) or can be used toPCT Application Attorney Docket No. 120426-312101 / WO perform the operations of access managers 113 (e.g., to execute instructions to perform operations corresponding to the access managers 113 described with reference to FIGS. 1 - 29).In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0400] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0401] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430 (which can include multiple buses).

[0402] Processing device 402 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 402 can also be one or more specialpurpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 can further include a network interface device 408 to communicate over the network 420.

[0403] The data storage system 418 can include a machine-readable medium 424 (also known as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methodologies or functions described herein. The instructions 426 can also reside, completely or at least partially, within the main memory 404 and / or within the processing device 402 during execution thereof by the computer systemPCT Application Attorney Docket No. 120426-312101 / WO 400, the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable medium 424, data storage system 418, and / or main memory 404 can correspond to the memory sub-system 101 of FIG. 1.

[0404] In one embodiment, the instructions 426 include instructions to implement functionality corresponding to the access managers 113 described with reference to FIGS. 1 -29. While the machine-readable medium 424 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0405] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to convey the substance of their work most effectively to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0406] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system’s registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0407] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, andPCT Application Attorney Docket No. 120426-312101 / WO magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0408] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0409] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0410] In this description, various functions and operations are described as being performed by or caused by computer instructions to simplify description. However, those skilled in the art will recognize what is meant by such expressions is that the functions result from execution of the computer instructions by one or more controllers or processors, such as a microprocessor. Alternatively, or in combination, the functions and operations can be implemented using special purpose circuitry, with or without software instructions, such as using application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). Embodiments can be implemented using hardwired circuitry without software instructions, or in combination with software instructions. Thus, the techniques are limited neither to any specific combination of hardware circuitry and software, nor to any particular source for the instructions executed by the data processing system.

[0411] In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

PCT Application Attorney Docket No. 120426-312101 / WOCLAIMSWhat is claimed is:

1. A method, comprising:storing, in a memory sub-system, a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of a physical storage space of the memory sub-system;receiving, in the memory sub-system, a storage access request; andexecuting, in the memory sub-system, the storage access request to cause a data portion in the logical storage space being buffered or cached in a memory space of the memory sub-system.

2. The method of claim 1, wherein the method further comprises:configuring a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; andstoring, in the memory sub-system, information to identify a location, in the memory space, at which the data portion is cached or buffered;wherein each of the plurality of entries as stored in the memory sub-system occupies a same size of storage resources.

3. The method of claim 2, wherein the respective entry is configured with a bit-sized field configured to store a parameter indicative of whether or not the portion of the logical storage space, being mapped to the portion of the physical storage space, has data buffered or cached in the memory space.

4. The method of claim 3, wherein the portion of the logical storage space includes a plurality of logical storage blocks addressable via a plurality of logical block addressing (LBA) addresses.

5. The method of claim 4, wherein the first entry is configured to map a first portion of the logical storage space; and the method further comprises:searching the information to identify the location based on an identifier of the firstportion.PCT Application Attorney Docket No. 120426-312101 / WO 6. The method of claim 5, further comprising:sorting the information to identify the location based on the identifier of the first portion.

7. The method of claim 6, wherein the data portion is a portion of data stored in the first portion of the logical storage space.

8. The method of claim 7, wherein a size of the data portion is smaller than a size of each of the plurality of logical storage blocks addressable respectively via the plurality of logical block addressing (LB A) addresses.

9. A memory sub-system, comprising:memory cells of a first type to provide a memory space;memory cells of a second type to provide a physical storage space; anda controller configured to:store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; andstore, in the memory space, a copy of a data portion addressable in the logical storage space.

10. The memory sub-system of claim 9, wherein the controller if further configured to: configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; andstore information to identify a location, in the memory space, at which the data portion is cached or bufferedwherein each of the plurality of entries as stored in the memory sub-system occupies a same size of storage resources.

11. The memory sub-system of claim 10, wherein the respective entry is configured with a bit-sized field configured to store a parameter indicative of whether or not the portion of the logical storage space, being mapped to the portion of the physical storage space, has data buffered or cached in the memory space.

12. The memory sub-system of claim 11, wherein the portion of the logical storage space include a plurality of logical storage blocks addressable, by a host system outside of the memory sub-system, via a plurality of logical block addressing (LB A) addressesPCT Application Attorney Docket No. 120426-312101 / WO configured according to a standard of non-volatile memory express (NVMe).

13. The memory sub-system of claim 12, wherein the first entry is configured to map a first portion of the logical storage space; andwherein the location is addressable, by the host system, using a memory address in accordance with a standard for compute express link (CXL) or component interconnect express (PCIe).

14. The memory sub-system of claim 13, wherein the controller is further configured to: sort the information to identify the location based on an identifier of the first portion; and search the information to identify the location based on the identifier of the first portion.

15. The memory sub-system of claim 14, wherein the data portion is a portion of data stored in the first portion of the logical storage space; andwherein a size of the data portion is smaller than a size of each of the plurality of logical storage blocks addressable respectively via the plurality of logical block addressing (LBA) addresses.

16. A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, cause the memory sub-system to perform a method, comprising: maintaining a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of a physical storage space of the memory sub-system;caching or buffering, in a memory space of the memory sub-system, a data portion addressable in the logical storage space; andconfiguring a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space.

17. The non-transitory computer storage medium of claim 16, wherein the method further comprises:storing information to identify a location, in the memory space, at which the data portion is cached or buffered;wherein each of the plurality of entries, as stored in the memory sub-system, is of a same size; and the respective entry is configured with a bit-sized field configured to store a parameter indicative of whether or not the portion of the logical storage space, being mapped to the portion of the physical storage space, has dataPCT Application Attorney Docket No. 120426-312101 / WO buffered or cached in the memory space.

18. The non-transitory computer storage medium of claim 17, wherein the portion of the logical storage space include a plurality of logical storage blocks addressable via a plurality of logical block addressing (LB A) addresses; andwherein the first entry is configured to map a first portion of the logical storage space.

19. The non-transitory computer storage medium of claim 18, wherein the method further comprises:sorting the information to identify the location based on an identifier of the first portion;andsearching the information to identify the location based on the identifier of the first portion.

20. The non-transitory computer storage medium of claim 19, wherein the data portion is a portion of data stored in the first portion of the logical storage space; andwherein a size of the data portion is smaller than a size of each of the plurality of logical storage blocks addressable respectively via the plurality of logical block addressing (LBA) addresses.

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