Signal processing module, signal processing chip, active stylus chip, and touch-control device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-08
- Publication Date
- 2026-08-13
Smart Images
Figure CN2025076531_13082026_PF_FP_ABST
Abstract
Description
Signal processing module, signal processing chip, active pen chip, and touch device Technical Field
[0001] This application relates to the field of touch device technology, and in particular to a signal processing module, a signal processing chip, an active pen chip, and a touch device. Background Technology
[0002] Peripheral input components for electronic devices include passive capacitive pens and active capacitive pens. Passive capacitive pens use conductive materials at the tip to simulate a finger inputting touch commands on the electronic device's display screen. Active capacitive pens output electrical signals to the display screen through electrodes at the tip, and the display screen recognizes the touch commands based on the electrical signals output by the active capacitive pens. Because passive capacitive pens need to simulate a finger for touch, the pen tip is relatively thick and the accuracy is low. In contrast, active capacitive pens do not need to simulate a finger for touch, so the pen tip is relatively thin and the accuracy is high. In scenarios where high accuracy is required, active capacitive pens have become the main peripheral input components for electronic devices.
[0003] Currently, in order to reduce power consumption, active capacitive pens have a low-power mode for their internal signal processing chip when no touch operation is performed. When a touch operation is performed, the internal signal processing chip is woken up to perform signal processing operations.
[0004] However, the signal processing chip inside an active capacitive pen wakes up based on a low-speed clock signal in low-power mode, resulting in a longer wake-up time, higher touch latency, and a poor user experience. Summary of the Invention
[0005] In view of this, embodiments of this application provide a signal processing module, a signal processing chip, an active pen chip, and a touch device to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of the present application, a signal processing module is provided, applied to a touch device for controlling the display screen of an electronic device. The signal processing module includes: an active pen chip and a signal processing chip; the signal processing chip is electrically connected to the active pen chip; the active pen chip is configured to output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired an uplink signal output from the display screen, wherein the frequency of the first clock signal is greater than the operating clock frequency of the signal processing chip in the low-power mode; the signal processing chip is configured to switch from the low-power mode to the operating mode based on the first clock signal after receiving the wake-up signal, and after entering the operating mode, receive the uplink signal sent by the active pen chip, and control the active pen chip to output a downlink signal to the electronic device according to the uplink signal, so that the electronic device recognizes the touch command according to the downlink signal.
[0007] According to a second aspect of the embodiments of this application, an active pen chip is provided, the active pen chip being electrically connected to a signal processing chip; the active pen chip is configured to output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired an uplink signal output from the display screen, so that the signal processing chip, upon receiving the wake-up signal, switches from the low-power mode to a working mode based on the first clock signal, and after the signal processing chip switches to the working mode, sends the uplink signal to the signal processing chip, so that the signal processing chip controls the active pen chip to output a downlink signal to the electronic device based on the uplink signal.
[0008] According to a third aspect of the embodiments of this application, a signal processing chip is provided, the signal processing chip being electrically connected to an active pen chip; the signal processing chip is configured to, upon receiving a wake-up signal, switch from a low-power mode to a working mode based on a first clock signal, and after entering the working mode, receive an uplink signal sent by the active pen chip, and control the active pen chip to output a downlink signal to the electronic device according to the uplink signal, so that the electronic device can recognize touch commands according to the downlink signal, wherein the active pen chip outputs a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired the uplink signal output by the display screen.
[0009] According to a fourth aspect of the present application, a touch device is provided, including the signal processing module described in the first aspect of the present application.
[0010] According to the signal processing module provided in the embodiments of this application, the signal processing module includes an active pen chip and a signal processing chip. The active pen chip can output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired the uplink signal output from the display screen. After receiving the wake-up signal, the signal processing chip can switch from the low-power mode to the working mode based on the first clock signal. This allows the signal processing chip to control the active pen chip to output a downlink signal based on the uplink signal, enabling the electronic device to recognize touch commands based on the downlink signal and realize touch function. Since the signal processing chip switches from the low-power mode to the working mode based on the first clock signal, and the first clock signal is a high-speed clock signal, compared with the prior art, the signal processing chip can quickly wake up with a higher frequency clock signal, shortening the wake-up time, thereby reducing touch latency and improving user experience. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0012] Figure 1 is a schematic diagram of a signal processing module provided in an embodiment of this application;
[0013] Figure 2 is a schematic diagram of a clock signal provided in an embodiment of this application;
[0014] Figure 3 is a schematic diagram of an active pen chip and a signal processing chip provided in an embodiment of this application;
[0015] Figure 4 is a schematic diagram of an active pen chip provided in an embodiment of this application;
[0016] Figure 5 is a schematic diagram of a second clock source provided in an embodiment of this application;
[0017] Figure 6 is a schematic diagram of a signal processing chip provided in an embodiment of this application;
[0018] Figure 7 is a schematic diagram of another signal processing chip provided in an embodiment of this application;
[0019] Figure 8 is a schematic diagram of another signal processing chip provided in an embodiment of this application. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0021] As mentioned earlier, peripheral input components for electronic devices include passive capacitive pens and active capacitive pens. Passive capacitive pens use conductive material at the tip to simulate a finger inputting touch commands onto the screen. Active capacitive pens output electrical signals to the screen via electrodes at the tip, and the screen recognizes the touch commands based on these signals. Because passive capacitive pens require simulating a finger, their tips are relatively thick, resulting in lower accuracy. In contrast, active capacitive pens do not require simulating a finger, allowing for a finer tip and higher accuracy. In scenarios requiring high accuracy, active capacitive pens have become the primary peripheral input component for electronic devices. Currently, to reduce power consumption, active capacitive pens operate in a low-power mode when no touch operation is being performed, activating the signal processing chip to process signals during touch operations. However, in order to reduce power consumption, active capacitive pens use a low-speed clock signal as their working clock in low-power mode. The signal processing chip inside the active capacitive pen wakes up based on the low-speed clock signal in low-power mode, which results in a longer wake-up time, leading to higher touch latency and a poor user experience.
[0022] This application provides a signal processing module, which includes an active pen chip and a signal processing chip. The active pen chip, when the signal processing chip is in a low-power mode and has acquired the uplink signal output from the display screen, outputs a wake-up signal and a first clock signal to the signal processing chip. Upon receiving the wake-up signal, the signal processing chip switches from the low-power mode to the working mode based on the first clock signal. This allows the signal processing chip to control the active pen chip to output a downlink signal based on the uplink signal, enabling the electronic device to recognize touch commands and implement touch functionality. Since the signal processing chip switches from the low-power mode to the working mode based on the first clock signal, and the first clock signal is a high-speed clock signal, compared to existing technologies, the signal processing chip can quickly wake up using a higher frequency clock signal, shortening the wake-up time and thus reducing touch latency and improving user experience.
[0023] The signal processing module provided in this application is described below through embodiments.
[0024] Figure 1 is a schematic diagram of a signal processing module provided in an embodiment of this application. The signal processing module 100 is applied to a touch device that controls the display screen of an electronic device. As shown in Figure 1, the signal processing module 100 includes an active pen chip 101 and a signal processing chip 102. The signal processing chip 102 is electrically connected to the active pen chip 101. After the active pen chip 101 is in a low-power mode and has acquired the uplink signal output from the display screen, it outputs a wake-up signal and a first clock signal to the signal processing chip 102. The frequency of the first clock signal is greater than the operating clock frequency of the signal processing chip 102 in the low-power mode. After receiving the wake-up signal, the signal processing chip 102 can switch from the low-power mode to the operating mode based on the first clock signal. After entering the operating mode, it receives the uplink signal sent by the active pen chip 101 and controls the active pen chip 101 to output a downlink signal to the electronic device according to the uplink signal, so that the electronic device can recognize the touch command according to the downlink signal.
[0025] The signal processing module 100 includes an active pen chip 101 and a signal processing chip 102. The active pen chip 101 and the signal processing chip 102 are electrically connected. In one example, when the user picks up the touch device, the active pen chip 101 switches from a low-power mode to a polling mode. When the active pen chip 101 is in polling mode, it can collect the output signal of the display screen. After the active pen chip 101 collects the uplink signal output by the display screen, it outputs a wake-up signal and a first clock signal to the signal processing chip 102. The wake-up signal can be an interrupt signal.
[0026] After receiving a wake-up signal, the signal processing chip 102 switches from a low-power mode to a working mode based on a first clock signal. The frequency of the first clock signal is higher than the working clock frequency of the signal processing chip 102 in the low-power mode. The first clock signal can be a high-speed clock signal. In one example, the working clock frequency of the signal processing chip 102 in the low-power mode is 32kHz, and the frequency of the first clock signal can be 32MHz. When the signal processing chip 102 switches modes based on the first clock signal, the time required for the signal processing chip 102 to switch from the low-power mode to the working mode based on the high-speed clock signal is shorter because the frequency of the first clock signal is higher.
[0027] When the signal processing chip 102 switches to its operating mode, the active pen chip 101 sends the acquired uplink signal to the signal processing chip 102. The signal processing chip 102 then controls the active pen chip 101 to output a downlink signal based on the uplink signal. Upon receiving the downlink signal, the electronic device's display screen can recognize the touch commands from the touch device. For example, the electronic device can recognize the position of the pen tip based on the downlink signal to enable a click function, or it can recognize the pen tip trajectory to enable writing and drawing functions. In one example, the signal processing chip 102 can recognize the pressure and tilt data of the touch device during touch based on the uplink signal and output the corresponding downlink signal, enabling the electronic device to recognize the user's input pressure and the tilt degree of the touch device, providing corresponding touch feedback. It should be understood that different electronic devices may have different touch protocols. Therefore, the signal processing chip 102 can control the active pen chip 101 to output a downlink signal corresponding to the protocol based on the uplink signal, thereby enabling touch control of the electronic device. Thus, the touch device can be used to control various electronic devices with different touch protocols.
[0028] It should be noted that the active pen chip 101 in this embodiment can be an active pen driver chip, and the signal processing chip 102 can be a microcontroller unit (MCU) or Bluetooth Low Energy (BLE) chip inside the touch device, etc. The specific chip model and type are not limited in this embodiment.
[0029] In this embodiment, the signal processing module 100 includes an active pen chip 101 and a signal processing chip 102. The active pen chip 101 can output a wake-up signal and a first clock signal to the signal processing chip 102 after the signal processing chip 102 is in a low-power mode and it has acquired the uplink signal output from the display screen. Upon receiving the wake-up signal, the signal processing chip 102 can switch from the low-power mode to the working mode based on the first clock signal. This allows the signal processing chip 102 to control the active pen chip 101 to output a downlink signal based on the uplink signal, enabling the electronic device to recognize touch commands and implement touch functionality based on the downlink signal. Since the signal processing chip 102 switches from the low-power mode to the working mode based on the first clock signal, and the first clock signal is a high-speed clock signal, compared with the prior art, the signal processing chip 102 can quickly wake up using a higher frequency clock signal, shortening the wake-up time and thus reducing touch latency and improving user experience.
[0030] In one possible implementation, the active pen chip 101 can output a second clock signal to the signal processing chip 102 after the signal processing chip 102 switches from a low-power mode to a working mode, wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.
[0031] Figure 2 is a schematic diagram of a clock signal provided in an embodiment of this application. As shown in Figure 2, when the signal processing chip 102 is in low-power mode and the active pen chip 101 collects the uplink signal output by the display screen, the active pen chip 101 sends a wake-up signal and a first clock signal to the signal processing chip 102. After receiving the wake-up signal, the signal processing chip 102 switches from low-power mode to working mode according to the first clock signal. When the signal processing chip 102 switches to working mode, the active pen chip 101 outputs a second clock signal to the signal processing chip 102. The frequency of the first clock signal is greater than the frequency of the second clock signal. It should be noted that, as shown in Figure 2, the active pen chip 101 outputs the first clock signal to the signal processing chip 102 only when the signal processing chip 102 needs to be woken up, that is, when it needs to switch from low-power mode to working mode. At other times, the active pen chip 101 outputs the second clock signal to the signal processing chip 102.
[0032] It should be noted that, as shown in Figure 2, the first clock signal and the second clock signal in this application are both sine wave clock signals, and the wake-up signal is a pulse signal. The active pen chip 101 can output a high-level pulse to the signal processing chip 102 as a wake-up signal, so that the signal processing chip switches from low-power mode to working mode. When the signal processing chip 102 does not need to switch from low-power mode to working mode, the active pen chip 101 outputs a low-level pulse to the signal processing chip 102.
[0033] It should also be noted that since the signal processing chip 102 enters a low-power mode after completing its work, but the active pen chip 101 does not know when the signal processing chip 102 will switch to the low-power mode, in order to prevent the signal processing chip 102 from having no clock signal after switching to the low-power mode, the active pen chip 101 outputs a second clock signal to the signal processing chip 102 after the signal processing chip 102 switches to the working mode, so that the second clock signal can be used as the working clock after the signal processing chip 102 switches to the low-power mode.
[0034] In this embodiment, the active pen chip 101 can output a second clock signal to the signal processing chip 102 after the signal processing chip 102 switches from a low-power mode to a working mode. Thus, the active pen chip 101 can provide a second clock signal to the signal processing chip 102, so that the signal processing chip 102 has a low-speed clock signal input source.
[0035] In one possible implementation, the signal processing chip 102 can use the second clock signal as its operating clock when in a low-power mode, and use the third clock signal generated by the first clock source inside the signal processing chip 102 as its operating clock when in a working mode, wherein the frequency of the third clock signal is greater than the frequency of the second clock signal.
[0036] When the signal processing chip 102 is in low-power mode, it can use the second clock signal output by the active pen chip 101 as its working clock. At this time, the signal processing chip 102 does not need to set a clock source corresponding to the low-power mode. When the signal processing chip 102 is in working mode, it can use the third clock signal generated by the first clock source inside as its working clock. It should be understood that if a low-speed clock signal is used when the signal processing chip 102 is in working mode, its data processing capability is poor and it cannot process all uplink signals in time. Therefore, the signal processing chip 102 needs to use a high-speed clock signal for signal processing when it is in working mode. In order to reduce the power consumption of the signal processing chip 102 when it is in low-power mode, a low-speed clock signal can be used as the working clock for low-power mode. At this time, the first clock source can be in a sleep state. The frequency of the third clock signal is greater than the frequency of the second clock signal. In one example, the frequency of the third clock signal can be 32MHz and the frequency of the second clock signal can be 32kHz.
[0037] In this embodiment, the signal processing chip 102 can use the second clock signal as its operating clock when in a low-power mode. As a result, the signal processing chip 102 does not need to have a clock source to provide the clock signal used in the low-power mode, which can reduce the cost of the signal processing chip 102. Furthermore, since the signal processing chip 102 does not need to have a clock source to provide the clock signal used in the low-power mode, the power consumption of the signal processing chip 102 in the low-power mode can be reduced.
[0038] Figure 3 is a schematic diagram of an active pen chip and a signal processing chip provided in an embodiment of this application. As shown in Figure 3, the first communication pin 10111 of the active pen chip 101 is electrically connected to the second communication pin 10211 of the signal processing chip 102. The first output pin 10112 of the active pen chip 101 is electrically connected to the first input pin 10212 of the signal processing chip 102. The second output pin 10113 of the active pen chip 101 is electrically connected to the second input pin 10213 of the signal processing chip 102. The active pen chip 101 outputs a first clock signal or a second clock signal to the signal processing chip 102 through the first output pin 10112. The active pen chip 101 outputs a wake-up signal to the signal processing chip 102 through the second output pin 10113. The active pen chip 101 outputs an uplink signal to the signal processing chip 102 through the first communication pin 10111.
[0039] When the signal processing chip 102 is in low-power mode and the active pen chip 101 acquires the uplink signal output from the display screen, the active pen chip 101 outputs a first clock signal to the signal processing chip 102 through the first output pin 10112 and outputs a wake-up signal to the signal processing chip 102 through the second output pin 10113. When the signal processing chip 102 switches to working mode, the active pen chip 101 outputs a second clock signal to the signal processing chip 102 through the first output pin 10112 and outputs an uplink signal to the signal processing chip 102 through the first communication pin 10111.
[0040] Correspondingly, after receiving a wake-up signal via the second input pin 10213, the signal processing chip 102 switches from low-power mode to operating mode based on the first clock signal received via the first input pin 10212. When in operating mode, the signal processing chip 102 uses the third clock signal generated by its internal first clock source as its operating clock. It also receives the uplink signal sent by the active pen chip 101 via the second communication pin 10211, processes the uplink signal, and then controls the active pen chip 101 to send downlink signals to the electronic device. When the signal processing chip 102 is in low-power mode, it can use the second clock signal received via the first input pin 10212 as its operating clock.
[0041] In this embodiment, the first communication pin 10111 of the active pen chip 101 is electrically connected to the second communication pin 10211 of the signal processing chip 102, the first output pin 10112 of the active pen chip 101 is electrically connected to the first input pin 10212 of the signal processing chip 102, and the second output pin 10113 of the active pen chip 101 is electrically connected to the second input pin 10213 of the signal processing chip 102. Thus, the active pen chip 101 can send a first clock signal or a second clock signal to the signal processing chip 102 through the first input pin 10212, send a wake-up signal to the signal processing chip 102 through the second output pin 10113, and send an uplink signal to the signal processing chip 102 through the first communication pin 10111, enabling the signal processing chip 102 to switch from low-power mode to working mode and process the uplink signal.
[0042] Figure 4 is a schematic diagram of an active pen chip provided in an embodiment of this application. As shown in Figure 4, the active pen chip 101 includes a second clock source 1013, a third clock source 1012, a first selection unit 1014, and a control unit 1015. The second clock source 1013 and the third clock source 1012 are electrically connected to the first selection unit 1014. The control unit 1015 is electrically connected to the first selection unit 1014. The first selection unit 1014 is electrically connected to the first output pin 10112. The control unit 1015 is electrically connected to the second output pin 10113. The second clock source 1013 can output a first clock signal to the first selection unit 1014. The third clock source 1012 can output a second clock signal to the first selection unit 1014. The control unit 1015 can output a wake-up signal to the signal processing chip 102 through the second output pin 10113, and control the first selection unit 1014 to output the first clock signal or the second clock signal through the first output pin 10112.
[0043] The active pen chip 101 includes a second clock source 1013, a third clock source 1012, a first selection unit 1014, and a control unit 1015. The second clock source 1013 and the third clock source 1012 are electrically connected to the first selection unit 1014. Optionally, the second clock source 1013 can be a crystal oscillator clock circuit, and the third clock source 1012 can be an RC oscillator. The control unit 1015 is electrically connected to the first selection unit 1014 and can be a digital control unit 1015. When the signal processing chip 102 is in a low-power mode and the active pen chip 101 acquires the uplink signal output from the display screen... When the signal processing chip 102 switches to the working mode, the control unit 1015 outputs a wake-up signal to the signal processing chip 102 through the second output pin 10113, and controls the first selection unit 1014 to output the first clock signal provided by the second clock source 1013, so that the active pen chip 101 outputs the first clock signal to the signal processing chip 102 through the first output pin 10112. When the signal processing chip 102 switches to the working mode, the control unit 1015 controls the first selection unit 1014 to output the second clock signal provided by the third clock source 1012, so that the active pen chip 101 outputs the second clock signal to the signal processing chip 102 through the first output pin 10112.
[0044] In this embodiment, the active pen chip 101 includes a second clock source 1013, a third clock source 1012, a first selection unit 1014, and a control unit 1015. The second clock source 1013 and the third clock source 1012 are electrically connected to the first selection unit 1014, and the control unit 1015 is electrically connected to the first selection unit 1014. The first selection unit 1014 is electrically connected to a first output pin 10112, and the control unit 1015 is electrically connected to a second output pin 10113. Thus, a wake-up signal can be output through the control unit 1015, and the first selection unit 1014 can be controlled through the control unit 1015. The selection unit 1014 outputs a first clock signal or a second clock signal to enable the active pen chip 101 to output a wake-up signal and a first clock signal to the signal processing chip 102 when the signal processing chip 102 is in low-power mode and the active pen chip 101 has acquired an uplink signal. After the signal processing chip 102 switches to working mode, the active pen chip 101 outputs a second clock signal to the signal processing chip 102. This enables the active pen chip 101 to provide the signal processing chip 102 with a high-speed clock signal for switching from low-power mode to working mode, and a low-speed clock signal for low-power mode.
[0045] Figure 5 is a schematic diagram of a second clock source provided in an embodiment of this application. As shown in Figure 5, the second clock source 1013 includes a driving subunit 10131, a frequency multiplier subunit 10132, and a frequency divider subunit 10133. The driving subunit 10131 is electrically connected to an external crystal 201 through a first clock pin 10114 and a second clock pin 10115 on the active pen chip 101. The driving subunit 10131 is electrically connected to the frequency multiplier subunit 10132, and the frequency multiplier subunit 10132 is electrically connected to the frequency divider subunit 10133. The frequency divider subunit 10133 is electrically connected to the control unit 1015. The drive subunit 10131 can output a drive signal to the crystal 201 to drive the crystal 201 to vibrate and generate a fourth clock signal based on the vibration of the crystal 201. The frequency multiplier subunit 10132 can multiply the fourth clock signal to obtain a fifth clock signal. The frequency divider subunit 10133 can divide the fifth clock signal under the control of the control unit 1015 to obtain a first clock signal.
[0046] The second clock source 1013 includes a driving subunit 10131. The driving subunit 10131 is electrically connected to an external crystal 201 via a first clock pin 10114 and a second clock pin 10115 on the active pen chip 101. The external crystal 201 can be quartz. The driving subunit 10131 outputs a driving signal to the quartz crystal, causing it to vibrate. Based on the vibration of the quartz crystal, the driving subunit 10131 generates a fourth clock signal. In one example, the fourth clock signal is 32.768kHz. After generating the fourth clock signal, the driving subunit 10131... The fourth clock signal is transmitted to the frequency multiplier subunit 10132. The frequency multiplier subunit 10132 multiplies the fourth clock signal to obtain the fifth clock signal. The fifth clock signal can be 8MHz, 32MHz, etc. After obtaining the fifth clock signal, the frequency multiplier subunit 10132 sends the fifth clock signal to the frequency divider subunit 10133. The frequency divider subunit 10133 can perform frequency division processing on the fifth clock signal to make the frequency of the fifth clock signal higher or lower, thereby obtaining the first clock signal to be sent to the signal processing chip 102. In one example, the frequency multiplier subunit 10132 can be a phase-locked loop (PLL).
[0047] It should be noted that the frequency division subunit 10133 can determine the frequency division strategy under the control of the control unit 1015. For example, when the fifth clock signal is 32MHz, but the first clock signal to be output is 64MHz, the pulse interval of the 32MHz signal can be shortened to 1 / 2 to obtain the first clock signal of 64MHz. When the first clock signal to be output is 16MHz, the pulse interval of the 32MHz signal can be increased to 2 times to obtain the first clock signal of 16MHz.
[0048] Optionally, the fourth clock signal, the fifth clock signal, and the first clock signal can all be used as the operating clock of the active pen chip 101, and can be set as needed.
[0049] In this embodiment, the second clock source 1013 includes a driving subunit 10131, a frequency multiplier subunit 10132, and a frequency divider subunit 10133. The driving subunit 10131 can drive the crystal 201 to oscillate and generate a fourth clock signal based on the oscillating crystal 201. The frequency multiplier subunit 10132 and the frequency divider subunit 10133 can multiply and divide the fourth clock signal to obtain a first clock signal. Thus, the second clock source 1013 can provide the first clock signal to the active pen chip 101, enabling the active pen chip 101 to output a higher frequency first clock signal to the signal processing chip 102.
[0050] Figure 6 is a schematic diagram of a signal processing chip provided in an embodiment of this application. As shown in Figure 6, the signal processing chip 102 includes a fourth clock source 1022 and a fifth clock source 1023. When the signal processing chip 102 is in a low-power mode, it can use the sixth clock signal generated by the fourth clock source 1022 as the working clock, and when it is in a working mode, it can use the seventh clock signal generated by the fifth clock source 1023 as the working clock. The frequency of the sixth clock signal is greater than the frequency of the seventh clock signal.
[0051] The signal processing chip 102 may include a fourth clock source 1022 and a fifth clock source 1023. Specifically, as shown in FIG6, the structure of the fourth clock source 1022 may be similar to that of the second clock source 1013. For details, please refer to the description of the second clock source 1013. The fourth clock source 1022 can generate a high-frequency clock signal. In one example, the fourth clock source 1022 can output a 32MHz sixth clock signal as the working clock of the signal processing chip 102 in the working mode. The signal processing chip 102 may also include a fifth clock source 1023. The fifth clock source 1023 can output a low-frequency clock signal as the working clock of the signal processing chip 102 in the low-power mode. In one example, the fifth clock source 1023 can output a 32kHz seventh clock signal.
[0052] Optionally, as shown in Figure 6, the fifth clock source 1023 may include a first sub-clock source 10231 and a second sub-clock source 10232. The first sub-clock source 10231 is a crystal oscillator clock circuit. For example, it may include a driving unit driving an external crystal 201 to generate a crystal oscillator and generating a clock signal based on the external crystal 201. The second sub-clock source 10232 may be an RC oscillation circuit. In one example, the first sub-clock source 10231 may generate a 32.768kHz clock signal, and the second sub-clock source 10232 may generate a 32kHz clock signal. When the low-power mode of the signal processing chip 102 requires a high-precision clock, the clock signal output by the first sub-clock source 10231 is used as the seventh clock signal. When the low-power mode of the signal processing chip 102 does not require a high-precision clock, the clock signal output by the second sub-clock source 10232 is used as the seventh clock signal.
[0053] In this embodiment, the signal processing chip 102 includes a fourth clock source 1022 and a fifth clock source 1023. When the signal processing chip 102 is in a low-power mode, it can use the sixth clock signal generated by the fourth clock source 1022 as its working clock, and when it is in a working mode, it can use the seventh clock signal generated by the fifth clock source 1023 as its working clock. Thus, the working clock of the signal processing chip 102 can be provided by the fourth clock source 1022 and the fifth clock source 1023, ensuring the normal operation of the signal processing chip 102.
[0054] Figure 7 is a schematic diagram of another signal processing chip provided in an embodiment of this application. As shown in Figure 7, the signal processing chip 102 further includes a sixth clock source 1025 and a second selection unit 1026. The sixth clock source 1025 is electrically connected to the second selection unit 1026, and the second selection unit 1026 is electrically connected to the first input pin 10212. When the signal processing chip 102 is in a low-power mode, it can control the second selection unit 1026 to output a second clock signal as a working clock. When the second selection unit 1026 does not receive the second clock signal and does not receive a wake-up signal, it can control the second selection unit 1026 to output an eighth clock signal generated by the sixth clock source 1025 as a working clock.
[0055] As shown in Figure 7, the signal processing chip 102 includes a first clock source 1024, a sixth clock source 1025, and a second selection unit 1026. When the signal processing chip 102 is in operating mode, the first clock source 1024 can provide the operating clock for the signal processing chip 102 in operating mode. When the signal processing chip 102 is in low-power mode, the signal processing chip 102 controls the second selection unit 1026 to output the second clock signal received through the first input pin 10212, and uses the second clock signal as the operating clock for the signal processing chip 102 in low-power mode. If the second clock signal is not received normally (for example, the active pen chip 101 malfunctions and does not output the second clock signal normally), the control chip controls the second selection unit 1026 to output the eighth clock signal generated by the sixth clock source 1025, and uses the eighth clock signal as the operating clock. In one example, the eighth clock signal can be 32kHz. Optionally, the sixth clock source 1025 can be an RC oscillator, which has lower power consumption compared to a crystal oscillator clock circuit, thus reducing the power consumption of the signal processing chip 102 in low-power mode.
[0056] In this embodiment, the signal processing chip 102 further includes a sixth clock source 1025 and a second selection unit 1026. When the signal processing chip 102 does not receive the second clock signal and does not receive a wake-up signal, the signal processing chip 102 can control the second selection unit 1026 to output the eighth clock signal generated by the sixth clock source 1025 as the working clock in low-power mode. This can prevent the signal processing chip 102 from being unable to operate in low-power mode due to a fault in not receiving the second clock signal when the signal processing chip 102 uses the second clock signal output by the active pen chip 101 as the working clock in low-power mode, thereby improving the reliability of the signal processing chip 102.
[0057] Figure 8 is a schematic diagram of another signal processing chip provided in an embodiment of this application. As shown in Figure 8, the signal processing chip 102 further includes a third selection unit 1027. The third selection unit 1027 is electrically connected to the first input pin 10212 and the sixth clock source 1025 respectively. The signal processing chip 102 is used to control the third selection unit 1027 to output a first clock signal when a wake-up signal is received, and to switch from a low-power mode to a working mode based on the first clock signal. When a wake-up signal is received and the first input pin 10212 does not receive a clock signal, the third selection unit 1027 is controlled to output an eighth clock signal generated by the sixth clock source 1025, and to switch from a low-power mode to a working mode based on the eighth clock signal.
[0058] As shown in Figure 8, the signal processing chip 102 includes a third selection unit 1027. The third selection unit 1027 is electrically connected to the sixth clock source 1025 and the first input pin 10212. The sixth clock source 1025 can output an eighth clock signal to the third selection unit 1027. When the signal processing chip 102 receives a wake-up signal and the third selection unit 1027 receives a first clock signal, the signal processing chip 102 switches from the low-power mode to the working mode based on the first clock signal output by the third selection unit 1027. When the signal processing chip 102 receives a wake-up signal but does not receive a clock signal sent by the active pen chip 101, the signal processing chip 102 controls the third selection unit 1027 to output an eighth clock signal, and the signal processing unit switches from the low-power mode to the working mode based on the eighth clock signal.
[0059] Optionally, when the third selection unit 102 does not receive the first clock signal but receives the second clock signal, the signal processing chip 102 can control the third selection unit 1027 to output the second clock signal, and the signal processing chip 102 can switch from the low-power mode to the working mode based on the second clock signal.
[0060] It should be noted that the sixth clock source 1025 and the eighth clock signal can be found in the description in the above embodiments, and will not be repeated here.
[0061] In this embodiment, the signal processing chip 102 further includes a third selection unit 1027. The third selection unit 1027 is electrically connected to the first input pin 10212 and the sixth clock source 1025. When a wake-up signal is received and the first input pin 10212 does not receive a clock signal, the active pen chip 101 can control the third selection unit 1027 to output the eighth clock signal generated by the sixth clock source 1025. This allows the chip to switch from a low-power mode to a working mode based on the eighth clock signal. This prevents the signal processing chip 102 from failing to switch to a working mode due to a fault in receiving the first clock signal. This also allows the signal processing chip 102 to switch from a low-power mode to a working mode even when it does not receive the first clock signal, thus improving the reliability of the signal processing chip 102.
[0062] In one possible implementation, the frequency range of the first clock signal is [1MHz, 64MHz].
[0063] In this embodiment, the frequency range of the first clock signal is [1MHz, 64MHz], which makes the first clock signal a high-speed clock signal, allowing the signal processing unit to quickly switch from low-power mode to working mode based on the higher frequency first clock signal, thereby reducing touch latency.
[0064] In one possible implementation, the frequency range of the second clock signal is [1kHz, 64kHz].
[0065] In this embodiment of the application, the frequency range of the second clock signal is [1kHz, 64kHz], which allows the second clock signal to be a low-speed clock signal. This enables the signal processing unit to use the lower frequency second clock signal as the operating clock in low-power mode, eliminating the need for the signal processing unit to set a clock source, reducing costs, and also reducing the power consumption of the signal processing unit.
[0066] In one possible implementation, after the duration of the first clock signal output by the active pen chip 101 to the signal processing chip 102 reaches the first duration, it outputs a wake-up signal to the signal processing chip 102 for a duration of the second duration. The second duration is longer than the duration required for the signal processing chip 102 to switch from the low-power mode to the working mode. The range of the first duration is [10ns, 10μs], and the range of the second duration is [1μs, 100μs].
[0067] As shown in Figure 2, when the signal processing chip 102 is in low-power mode and the active pen chip 101 collects the uplink signal output from the display screen, the active pen chip 101 first switches the second clock signal to a high-frequency first clock signal, that is, the active pen chip 101 first outputs the first clock signal to the signal processing chip 102. When the output of the first clock signal reaches the first duration t0, the active pen chip 101 outputs a wake-up signal to the signal processing chip 102 for a duration of the second duration t1. After receiving the wake-up signal, the signal processing chip 102 switches from low-power mode to working mode based on the first clock signal. When the signal processing chip 102 switches to working mode, the active pen chip 101 outputs the second clock signal to the signal processing chip 102.
[0068] It should be understood that, regarding the clock signal shown in Figure 2, since the frequency of the first clock signal is not stable when the second clock signal just changes to the first clock signal, it is necessary to wait for a first duration t0. After the first clock signal stabilizes, a wake-up signal is sent to the signal processing chip 102. This allows the signal processing chip 102 to be woken up based on the stable first clock signal.
[0069] It should also be understood that Figure 2 is only an example and should not be construed as limiting the embodiments of this application. In one example, when the active pen chip 101 does not output the second clock signal to the signal processing chip 102, since the first clock signal is unstable when it is first generated, it is still necessary to output the first clock signal with a first duration t0 before sending the wake-up signal.
[0070] It should also be understood that the first duration is in the range of [10ns, 10μs], which can be set as needed according to the circuit conditions. The second duration is in the range of [1μs, 100μs]. Since the second duration needs to be longer than the time required for the signal processing chip 102 to switch from low power mode to working mode, the second duration is related to the frequency of the first clock signal. The second duration can be set according to the actual switching time required.
[0071] In this embodiment, after the active pen chip 101 outputs a first clock signal to the signal processing chip 102 for a duration of a first duration, it outputs a wake-up signal for a duration of a second duration to the signal processing chip 102. This allows the signal processing chip 102 to switch from a low-power mode to a working mode based on the stable frequency of the first clock signal after the frequency of the first clock signal has stabilized, improving the stability of mode switching. Furthermore, the second duration of the wake-up signal output to the active pen chip 101 is greater than or equal to the time required for mode switching by the signal processing chip 102, ensuring that the signal processing chip 102 can complete the switch from a low-power mode to a working mode based on the first clock signal and the wake-up signal, further improving the stability of mode switching.
[0072] This application embodiment also provides an active pen chip, which is electrically connected to a signal processing chip. The active pen chip is used to output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired the uplink signal output from the display screen. After receiving the wake-up signal, the signal processing chip switches from the low-power mode to the working mode based on the first clock signal. After the signal processing chip switches to the working mode, it sends an uplink signal to the signal processing chip, so that the signal processing chip controls the active pen chip to output a downlink signal to the electronic device based on the uplink signal.
[0073] In this application embodiment, the active pen chip can be the active pen chip 101 in any of the above embodiments, and the details can be found in the description of any of the above embodiments, which will not be repeated here.
[0074] This application embodiment also provides a signal processing chip electrically connected to an active pen chip. The signal processing chip is used to switch from a low-power mode to a working mode based on a first clock signal after receiving a wake-up signal, and to receive an uplink signal sent by the active pen chip after entering the working mode. The active pen chip is then controlled to output a downlink signal to the electronic device based on the uplink signal, so that the electronic device can recognize touch commands based on the downlink signal. The active pen chip outputs a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has collected the uplink signal output by the display screen.
[0075] In this application embodiment, the active pen chip can be the signal processing chip 102 in any of the above embodiments, and the details can be found in the description of any of the above embodiments, which will not be repeated here.
[0076] This application also provides a touch device, which includes the signal processing module 100 in any of the above embodiments. In one example, the touch device can be a stylus.
[0077] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.
[0078] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0079] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.
[0080] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. A signal processing module, applied to a touch device for controlling the display screen of an electronic device, characterized in that, The signal processing module includes: an active pen chip and a signal processing chip; The signal processing chip is electrically connected to the active pen chip; The active pen chip is used to output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in low power mode and the uplink signal output by the display screen is collected. The frequency of the first clock signal is greater than the operating clock frequency of the signal processing chip in low power mode. The signal processing chip is configured to switch from a low-power mode to a working mode based on the first clock signal after receiving the wake-up signal, and after entering the working mode, receive the uplink signal sent by the active pen chip, and control the active pen chip to output a downlink signal to the electronic device according to the uplink signal, so that the electronic device can recognize the touch command according to the downlink signal.
2. The signal processing module according to claim 1, characterized in that, The active pen chip is used to output a second clock signal to the signal processing chip after the signal processing chip switches from a low-power mode to a working mode, wherein the frequency of the first clock signal is greater than the frequency of the second clock signal.
3. The signal processing module according to claim 2, characterized in that, The signal processing chip is configured to use the second clock signal as the working clock when in a low-power mode, and to use the third clock signal generated by the first clock source inside the signal processing chip as the working clock when in a working mode, wherein the frequency of the third clock signal is greater than the frequency of the second clock signal.
4. The signal processing module according to claim 3, characterized in that, The first communication pin of the active pen chip is electrically connected to the second communication pin of the signal processing chip, the first output pin of the active pen chip is electrically connected to the first input pin of the signal processing chip, and the second output pin of the active pen chip is electrically connected to the second input pin of the signal processing chip. The active pen chip outputs the first clock signal and the second clock signal to the signal processing chip through the first output pin; The active pen chip outputs the wake-up signal to the signal processing chip through the second output pin; The active pen chip outputs the uplink signal to the signal processing chip through the first communication pin.
5. The signal processing module according to claim 4, characterized in that, The active pen chip includes: a second clock source, a third clock source, a first selection unit, and a control unit; The second clock source and the third clock source are electrically connected to the first selection unit, the control unit is electrically connected to the first selection unit, the first selection unit is electrically connected to the first output pin, and the control unit is electrically connected to the second output pin. The second clock source is used to output the first clock signal to the first selection unit; The third clock source is used to output the second clock signal to the first selection unit; The control unit is configured to output the wake-up signal to the signal processing chip via the second output pin, and to control the first selection unit to output the first clock signal or the second clock signal via the first output pin.
6. The signal processing module according to claim 5, characterized in that, The second clock source includes: a driver subunit, a frequency multiplier subunit, and a frequency divider subunit; The driving subunit is electrically connected to an external crystal via a first clock pin and a second clock pin on the active pen chip. The driving subunit is electrically connected to the frequency multiplier subunit, the frequency multiplier subunit is electrically connected to the frequency divider subunit, and the frequency divider subunit is electrically connected to the control unit. The driving subunit is used to output a driving signal to the crystal, drive the crystal to vibrate, and generate a fourth clock signal based on the vibration of the crystal. The frequency multiplier subunit is used to multiply the frequency of the fourth clock signal to obtain the fifth clock signal; The frequency division subunit is used to perform frequency division processing on the fifth clock signal under the control of the control unit to obtain the first clock signal.
7. The signal processing module according to claim 1, characterized in that, The signal processing chip includes a fourth clock source and a fifth clock source; The signal processing chip is configured to use the sixth clock signal generated by the fourth clock source as the working clock when in a low-power mode, and to use the seventh clock signal generated by the fifth clock source as the working clock when in a working mode, wherein the frequency of the sixth clock signal is greater than the frequency of the seventh clock signal.
8. The signal processing module according to claim 4, characterized in that, The signal processing chip further includes: a sixth clock source and a second selection unit; The sixth clock source is electrically connected to the second selection unit, and the second selection unit is electrically connected to the first input pin; The signal processing chip is configured to control the second selection unit to output the second clock signal as the working clock when in a low-power mode, and to control the second selection unit to output the eighth clock signal generated by the sixth clock source as the working clock when the second selection unit does not receive the second clock signal and does not receive the wake-up signal.
9. The signal processing module according to claim 8, characterized in that, The signal processing chip further includes: a third selection unit; The third selection unit is electrically connected to the first input pin and the sixth clock source, respectively. The signal processing chip is configured to, upon receiving the wake-up signal, control the third selection unit to output the first clock signal and switch from a low-power mode to a working mode based on the first clock signal; and, upon receiving the wake-up signal and when the first input pin does not receive a clock signal, control the third selection unit to output the eighth clock signal generated by the sixth clock source and switch from a low-power mode to a working mode based on the eighth clock signal.
10. The signal processing module according to claim 1, characterized in that, The frequency range of the first clock signal is [1MHz, 64MHz].
11. The signal processing module according to claim 3, characterized in that, The frequency range of the second clock signal is [1kHz, 64kHz].
12. The signal processing module according to claim 1, characterized in that, After the active pen chip outputs the first clock signal to the signal processing chip for a duration of a first duration, it outputs the wake-up signal to the signal processing chip for a duration of a second duration. The second duration is longer than the duration required for the signal processing chip to switch from low-power mode to working mode. The first duration is in the range of [10ns, 10μs], and the second duration is in the range of [1μs, 100μs].
13. An active pen chip, characterized in that, The active pen chip is electrically connected to the signal processing chip; The active pen chip is configured to output a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired the uplink signal output from the display screen of the electronic device. Upon receiving the wake-up signal, the signal processing chip switches from the low-power mode to the working mode based on the first clock signal. After the signal processing chip switches to the working mode, it sends the uplink signal to the signal processing chip, thereby enabling the signal processing chip to control the active pen chip to output a downlink signal to the electronic device based on the uplink signal.
14. A signal processing chip, characterized in that, The signal processing chip is electrically connected to the active pen chip; The signal processing chip is configured to switch from a low-power mode to a working mode based on a first clock signal after receiving a wake-up signal, and receive an uplink signal sent by the active pen chip after entering the working mode. The active pen chip is then configured to control the active pen chip to output a downlink signal to the electronic device based on the uplink signal, so that the electronic device can recognize touch commands based on the downlink signal. The active pen chip outputs a wake-up signal and a first clock signal to the signal processing chip after the signal processing chip is in a low-power mode and has acquired the uplink signal output by the display screen of the electronic device.
15. A touch device, characterized in that, include: The signal processing module as described in any one of claims 1-12.