Gate drive circuit and display panel
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-08-13
Smart Images
Figure CN2025089185_13082026_PF_FP_ABST
Abstract
Description
Gate driving circuit and display panel
[0001] This application claims priority to Chinese Patent Application No. 202510130776.3, filed on February 5, 2025, entitled "Gate Driving Circuit and Display Panel", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Technology
[0003] The gate drive circuit can control the display panel to have different refresh frequencies for different display areas, so as to realize the design of zoned frequency, which can reduce power consumption.
[0004] However, when displaying in a segmented frequency manner, the gate control signal output by the gate drive unit in the gate drive circuit is easily affected by the coupling of other signals, which reduces the stability of the gate control signal. Invention Overview
[0005] This application provides a gate driving circuit and a display panel to alleviate the technical problem of poor stability of the gate control signal when displaying in different frequency ranges.
[0006] In a first aspect, this application provides a gate driving circuit, which includes multiple cascaded gate driving units. Each gate driving unit includes a node control module, a first frequency divider module, a first output module, and a voltage regulation module. The node control module is electrically connected to a first clock line, a first control line, a first low-potential line, a first high-potential line, a first node, and a second node. The first frequency divider module is electrically connected to a first frequency divider control line, the first node, the second node, and a third node. The first output module is connected to the first low-potential line and the second high-potential line of the third node and the fourth node, and is configured to output at least one of the signals of the first low-potential line and the second high-potential line as a first gate control signal based on the signals of the third node and the fourth node. The voltage regulation module is electrically connected to the first node, the second node, the fourth node, the first low-potential line, and the first frequency divider control line, and is configured to select either the signal from the first low-potential line or the signal from the first frequency divider control line to be transmitted to the fourth node based on the signals of the first node and the second node.
[0007] Secondly, this application provides a display panel that includes the aforementioned gate driving circuit. Beneficial effects
[0008] The gate driving circuit and display panel provided in this application, by adding a voltage adjustment module linked to the first frequency division control line between the first node and the first output module, can select the signal in the first low potential line or the signal in the first frequency division control line to be transmitted to the fourth node according to the signal of the first node and the signal of the second node. Thus, when displaying in a segmented frequency division mode, the first frequency division control line can control the potential of the first node through the first frequency division module, and then control the first output module to output the signal of the first low potential line as the first gate control signal through the voltage adjustment module. Compared with the first low potential line not being able to output an active low potential as the first gate control signal through the first output module when displaying in a segmented frequency division mode, which makes the low potential of the first gate control signal in this case a floating state, i.e., a passive low potential, the stability of the first gate control signal when displaying in a segmented frequency division mode is improved. Attached Figure Description
[0009] Figure 1 is a circuit schematic diagram of the gate driving unit provided in an embodiment of this application.
[0010] Figure 2 is a timing diagram of the gate drive unit shown in Figure 1 when the segmentation frequency function is enabled.
[0011] Figure 3 is a timing diagram of the gate drive unit shown in Figure 1 when the segmentation and frequency division function is turned off.
[0012] Figure 4 is a circuit schematic diagram of a sub-pixel provided in an embodiment of this application.
[0013] Figure 5 is a timing diagram of the sub-pixels shown in Figure 4. Embodiments of the present invention
[0014] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description of this application is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit this application.
[0015] Please refer to Figures 1 to 3. This embodiment provides a gate driving circuit, which includes multiple cascaded gate driving units. As shown in Figure 1, the gate driving unit includes a node control module 11, a first frequency divider module 12, a first output module 13, and a voltage regulation module 14.
[0016] The node control module 11 is electrically connected to the first clock line, the first control line, the first low potential line, the first high potential line, the first node K, and the second node P[q].
[0017] The first frequency divider module 12 is electrically connected to the first frequency divider control line, the first node K, the second node P[q], and the third node W.
[0018] The first output module 13 is connected to the third node W, the fourth node G, the first low potential line and the second high potential line, and is configured to output at least one of the signals of the first low potential line and the second high potential line as a first gate control signal Nscan[q] based on the signals of the third node W and the fourth node G.
[0019] The voltage regulation module 14 is electrically connected to the first node K, the second node P[q], the fourth node G, the first low potential line, and the first frequency division control line. It is configured to select either the signal in the first low potential line or the signal in the first frequency division control line to be transmitted to the fourth node G based on the signal of the first node K and the signal of the second node P[q].
[0020] It is understood that the gate driving circuit provided in this embodiment, by adding a voltage adjustment module 14 linked to the first frequency division control line between the first node K and the first output module 13, can select the signal in the first low potential line or the signal in the first frequency division control line to be transmitted to the fourth node G according to the signal of the first node K and the signal of the second node P[q]. Thus, when displaying in a segmented frequency, the first frequency division control line can control the potential of the first node K through the first frequency division module 12, and then control the first output module 13 to output the signal of the first low potential line as the first gate control signal Nscan[q] through the voltage adjustment module 14. Compared with the first low potential line not being able to output an active low potential as the first gate control signal Nscan[q] through the first output module 13 when displaying in a segmented frequency, the low potential of the first gate control signal Nscan[q] is in a floating state, i.e., a passive low potential, which improves the stability of the first gate control signal Nscan[q] when displaying in a segmented frequency.
[0021] It should be noted that the first clock line is used to transmit the first clock signal ECK. The first control line is used to transmit the start signal STV or the signal of the second node, p[q-1], in the previous stage gate drive unit. The first low-level line is used to transmit the first low-level signal NVGL. The first high-level line is used to transmit the first high-level signal PVGH. The first frequency divider control line is used to transmit the first frequency divider control signal NLF. The second high-level line is used to transmit the second high-level signal NVGH. Nscan[q] represents the first gate control signal Nscan[q] with a positive pulse.
[0022] The node control module 11 is configured to control the transmission of a first low-level signal NVGL or a first high-level signal PVGH to the first node K based on the signal in the first control line and the first clock signal ECK, and to control the transmission of the first low-level signal NVGL or the first high-level signal PVGH to the second node P[q] based on the signal in the first node K. The potential of the first node K is opposite to the potential of the second node P[q]. For example, when the first node K is at a high potential, the second node P[q] is at a low potential; or, when the first node K is at a low potential, the second node P[q] is at a high potential.
[0023] The first frequency division module 12 is configured to control the transmission of the signal from the first node K to the third node W based on the first frequency division control signal NLF and the signal from the second node P[q].
[0024] Before the voltage regulation module 14 was added, when the frequency division and frequency distribution (MFD) function was turned off, the high and low potentials of the first gate control signal Nscan[q] were provided by active signals, and the potential was stable. After enabling the frequency division and frequency distribution (MFD) function, the first node K and the third node W are disconnected, the third node W is at a high potential, the fourth transistor T9 is disconnected, and the fourth transistor T9 cannot output the second high potential signal NVGH as the first gate control signal Nscan[q]. At this time, the first node K is at a low potential. Since the first node K is connected to the gate of the fifth transistor T10, the fifth transistor T10 is also disconnected. The first output module 13 cannot output the signal in the first low potential line as the low potential of the first gate control signal Nscan[q]. At this time, the low potential of the first gate control signal Nscan[q] is derived from the passive holding potential, which has poor stability. The first gate control signal Nscan[q] will have a micro short circuit with other signals at high potential (such as gate control signals with negative pulses or initialization signals), which will cause the low potential of the first gate control signal Nscan[q] to be unstable.
[0025] In some embodiments, the voltage regulation module 14 includes at least one of a first regulation unit 141, a second regulation unit 142, and a third regulation unit 143.
[0026] The first adjustment unit 141 is electrically connected to the first node K and the fourth node G, and is configured to control the transmission of the signal from the first node K to the fourth node G according to the signal from the first node K.
[0027] The second adjustment unit 142 is electrically connected to the first node K, the fourth node G, and the first frequency division control line, and is configured to control the transmission of the signal of the first frequency division control line to the fourth node G according to the signal of the first node K.
[0028] The third adjustment unit 143 is electrically connected to the second node P[q], the fourth node G, and the first low-potential line, and is configured to control the signal transmission of the first low-potential line to the fourth node G according to the signal of the second node P[q].
[0029] In some embodiments, the first adjustment unit 141 includes a first transistor T28, the first terminal of the first transistor T28 being electrically connected to the gate of the first transistor T28 and the first node K, and the second terminal of the first transistor T28 being electrically connected to the fourth node G.
[0030] It should be noted that the first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. For example, if the first electrode is the source, the second electrode is the drain; or if the first electrode is the drain, the second electrode is the source. The first transistor T28 is exemplarily an N-channel oxide thin-film transistor, and may also be a dual-gate oxide thin-film transistor.
[0031] In some embodiments, the second adjustment unit 142 includes a second transistor T29, the first terminal of the second transistor T29 being electrically connected to the first frequency division control line, the second terminal of the second transistor T29 being electrically connected to the fourth node G, and the gate of the second transistor T29 being electrically connected to the first node K; the channel type of the second transistor T29 is different from the channel type of the first transistor T28.
[0032] It should be noted that the second transistor T29 is, by way of example, a P-channel polysilicon thin-film transistor. The first transistor T28 and the second transistor T29 are turned on in a time-division manner.
[0033] In some embodiments, the third adjustment unit 143 includes a third transistor T30, the first terminal of the third transistor T30 is electrically connected to the first low potential line, the second terminal of the third transistor T30 is electrically connected to the fourth node G, and the gate of the third transistor T30 is electrically connected to the second node P[q]; the channel type of the third transistor T30 is the same as the channel type of the first transistor T28.
[0034] It should be noted that the third transistor T30 is, by way of example, an N-channel oxide thin-film transistor.
[0035] In some embodiments, the first output module 13 includes a fourth transistor T9 and a fifth transistor T10. The first terminal of the fourth transistor T9 is electrically connected to the third node W, and the gate of the fourth transistor T9 is electrically connected to the second high-potential line. The first terminal of the fifth transistor T10 is electrically connected to the second terminal of the fourth transistor T9 and is configured to output a first gate control signal Nscan[q]. The second terminal of the fifth transistor T10 is electrically connected to the first low-potential line, and the gate of the fifth transistor T10 is electrically connected to the fourth node G. The channel type of the fourth transistor T9 is different from that of the fifth transistor T10, and the channel type of the fourth transistor T9 is the same as that of the second transistor T29.
[0036] It should be noted that in this embodiment, the fifth transistor T10 is controlled by the fourth node G. When the frequency division function is enabled, the fifth transistor T10 can be turned on, so that the first gate control signal Nscan[q] can actively output a low potential, thereby improving the stability of the low potential.
[0037] In some embodiments, as shown in FIG1, the node control module 11 includes at least one of a sixth transistor T13, a seventh transistor T12, an eighth transistor T2, a ninth transistor T1, and a tenth transistor T3.
[0038] The control terminal of the sixth transistor T13 is configured to receive the corresponding start signal STV or the signal of the second node P[q-1] in the previous gate drive unit. The input terminal of the sixth transistor T13 is electrically connected to the first low potential line or the second low potential line.
[0039] The control terminal of the seventh transistor T12 is electrically connected to the control terminal of the sixth transistor T13, the input terminal of the seventh transistor T12 is electrically connected to the first high-potential line, and the output terminal of the seventh transistor T12 is electrically connected to the output terminal of the sixth transistor T13.
[0040] The control terminal of the eighth transistor T2 is configured to receive the first clock signal ECK. The input terminal of the eighth transistor T2 is electrically connected to the output terminal of the sixth transistor T13, and the output terminal of the eighth transistor T2 is electrically connected to the first node K.
[0041] The control terminal of the ninth transistor T1 is electrically connected to the first node K, the input terminal of the ninth transistor T1 is electrically connected to the second low potential line, and the output terminal of the ninth transistor T1 is electrically connected to the second node P[q].
[0042] The control terminal of the tenth transistor T3 is electrically connected to the first node K, the input terminal of the tenth transistor T3 is electrically connected to the first high-potential line, and the output terminal of the tenth transistor T3 is electrically connected to the second node P[q].
[0043] In some embodiments, as shown in FIG1, the node control module 11 further includes an eleventh transistor T14, the control terminal of the eleventh transistor T14 being electrically connected to the second node P[q], the input terminal of the eleventh transistor T14 being electrically connected to the first low potential line, and the output terminal of the eleventh transistor T14 being electrically connected to the first node K.
[0044] It should be noted that this embodiment can lower the potential of the first node K to the potential of the first low potential line when the second node P[q] is at a high potential, thereby improving the reliability of operation.
[0045] In some embodiments, as shown in FIG1, the first frequency divider module 12 includes a first frequency divider transistor T16, a second frequency divider transistor T11, and a first capacitor C2.
[0046] The control terminal of the first frequency divider transistor T16 is electrically connected to the second node P[q], and the input terminal of the first frequency divider transistor T16 is connected to the first frequency divider control signal NLF.
[0047] The control terminal of the second frequency divider transistor T11 is electrically connected to the output terminal of the first frequency divider transistor T16, the input terminal of the second frequency divider transistor T11 is electrically connected to the first node K, and the output terminal of the second frequency divider transistor T11 is electrically connected to the third node W.
[0048] The first terminal of the first capacitor C2 is electrically connected to the control terminal of the second frequency divider transistor T11, and the second terminal of the first capacitor C2 is electrically connected to the output terminal of the second frequency divider transistor T11.
[0049] In some embodiments, as shown in FIG1, the gate drive unit further includes a second frequency divider module 15, which is electrically connected to the second frequency divider control line, the first node K, the second node P[q], and the fifth node M, and is configured to control the transmission of the signal of the first node K to the fifth node M according to the second frequency divider control signal PLF in the second frequency divider control line and the signal of the second node P[q].
[0050] In some embodiments, the second frequency divider module 15 includes a third frequency divider transistor T20, a fourth frequency divider transistor T19, and a second capacitor C3.
[0051] The control terminal of the third frequency divider transistor T20 is electrically connected to the second node P[q], and the input terminal of the third frequency divider transistor T20 is connected to the second frequency divider control signal PLF.
[0052] The control terminal of the fourth frequency divider transistor T19 is electrically connected to the output terminal of the third frequency divider transistor T20, the input terminal of the fourth frequency divider transistor T19 is electrically connected to the first node K, and the output terminal of the fourth frequency divider transistor T19 is electrically connected to the fifth node M.
[0053] The first terminal of the second capacitor C3 is electrically connected to the control terminal of the fourth frequency divider transistor T19, and the second terminal of the second capacitor C3 is electrically connected to the output terminal of the fourth frequency divider transistor T19.
[0054] Please continue to refer to Figure 1. In some embodiments, the gate driving unit further includes a second output module 16. The second output module 16 is electrically connected to the second node P[q], the fifth node M, the second node P[q-2] of the (q-2)th stage gate driving unit, the second clock line, the first high potential line, and the second gate control line. It is configured to output the second gate control signal Pscan[q] in the second gate control line according to the signal of the second node P[q], the signal of the fifth node M, the signal of the second node P[q-2] of the (q-2)th stage gate driving unit, the second clock signal CK1 in the second clock line, and the first high potential signal PVGH in the first high potential line.
[0055] In some embodiments, as shown in FIG1, the second output module 16 includes a first switching transistor T8, a first output transistor T6, a second output transistor T7, and a third capacitor C1.
[0056] The control terminal of the first switching transistor T8 is electrically connected to the second node P[q-2] of the (q-2)th stage gate drive unit, the input terminal of the first switching transistor T8 is electrically connected to the fifth node M, and the output terminal of the first switching transistor T8 is electrically connected to the sixth node Q1.
[0057] The control terminal of the first output transistor T6 is electrically connected to the sixth node Q1. The input terminal of the first output transistor T6 is configured to receive the second clock signal CK1, and the output terminal of the first output transistor T6 is configured to output the second gate control signal Pscan[q].
[0058] The control terminal of the second output transistor T7 is electrically connected to the second node P[q], the input terminal of the second output transistor T7 is electrically connected to the first high potential line, and the output terminal of the second output transistor T7 is electrically connected to the output terminal of the first output transistor T6.
[0059] The first terminal of the third capacitor C1 is electrically connected to the control terminal of the first output transistor T6, and the second terminal of the third capacitor C1 is electrically connected to the output terminal of the first output transistor T6.
[0060] Please continue to refer to Figure 1. In some embodiments, the gate driving unit further includes a third output module 17. The third output module 17 is electrically connected to the second node P[q], the fifth node M, the second node P[q-2] of the (q-2)th stage gate driving unit, the third clock line, the first high potential line, and the third gate control line. It is configured to output the third gate control signal Pscan[q+1] in the third gate control line according to the signal of the second node P[q], the signal of the fifth node M, the signal of the second node P[q-2] of the (q-2)th stage gate driving unit, the third clock signal CK2 in the third clock line, and the first high potential signal PVGH in the first high potential line.
[0061] In some embodiments, the third output module 17 includes a second switching transistor T23, a third output transistor T24, a fourth output transistor T25, and a fourth capacitor C4.
[0062] The control terminal of the second switching transistor T23 is electrically connected to the second node P[q-2] of the q-2th stage gate drive unit, the input terminal of the second switching transistor T23 is electrically connected to the fifth node M, and the output terminal of the second switching transistor T23 is electrically connected to the seventh node Q2.
[0063] The control terminal of the third output transistor T24 is electrically connected to the seventh node Q2. The input terminal of the third output transistor T24 is configured to receive the third clock signal CK2, and the output terminal of the third output transistor T24 is configured to output the third gate control signal Pscan[q+1].
[0064] The control terminal of the fourth output transistor T25 is electrically connected to the second node P[q], the input terminal of the fourth output transistor T25 is electrically connected to the first high-potential line, and the output terminal of the fourth output transistor T25 is electrically connected to the output terminal of the third output transistor T24.
[0065] The first terminal of the fourth capacitor C4 is electrically connected to the control terminal of the third output transistor T24, and the second terminal of the fourth capacitor C4 is electrically connected to the output terminal of the third output transistor T24.
[0066] In some embodiments, the gate driving unit further includes a first control module 18, which is electrically connected to the first node K, the second node P[q], the first high potential line and the fourth clock line, and is configured to control the signal transmission between the first high potential line and the first node K according to the fourth clock signal CK3 in the fourth clock line and the signal of the second node P[q].
[0067] In some embodiments, the first control module 18 includes a twelfth transistor T4 and a thirteenth transistor T5. The first terminal of the twelfth transistor T4 is electrically connected to the first node K, and the gate of the twelfth transistor T4 is connected to the fourth clock signal CK3. The first terminal of the thirteenth transistor T5 is electrically connected to the second terminal of the twelfth transistor T4, the gate of the thirteenth transistor T5 is electrically connected to the second node P[q], and the second terminal of the thirteenth transistor T5 is electrically connected to the first high-potential line.
[0068] It should be noted that in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the twelfth transistor T4 and the thirteenth transistor T5 can be turned on simultaneously to pull the potential of the first node K to the potential of the first high potential line, which improves the reliability of operation.
[0069] In some embodiments, the gate drive unit further includes a second control module 19, which is electrically connected to the third node W, the second node P[q], the first high-potential line and the fourth clock line, and is configured to control the signal transmission between the first high-potential line and the third node W according to the fourth clock signal CK3 in the fourth clock line and the signal of the second node P[q].
[0070] In some embodiments, the second control module 19 includes a fourteenth transistor T17 and a fifteenth transistor T18. The first terminal of the fourteenth transistor T17 is electrically connected to the third node W, and the gate of the fourteenth transistor T17 is connected to the fourth clock signal CK3. The first terminal of the fifteenth transistor T18 is electrically connected to the second terminal of the fourteenth transistor T17, the gate of the fifteenth transistor T18 is electrically connected to the second node P[q], and the second terminal of the fifteenth transistor T18 is electrically connected to the first high-potential line.
[0071] It should be noted that in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the fourteenth transistor T17 and the fifteenth transistor T18 can be turned on simultaneously to pull the potential of the third node W to the potential of the first high potential line, which improves the reliability of operation.
[0072] In some embodiments, the gate drive unit further includes a third control module 20, which is electrically connected to the fifth node M, the second node P[q], the first high-potential line and the fourth clock line, and is configured to control the signal transmission between the first high-potential line and the fifth node M according to the fourth clock signal CK3 in the fourth clock line and the signal of the second node P[q].
[0073] In some embodiments, the third control module 20 includes a sixteenth transistor T21 and a seventeenth transistor T22. The first terminal of the sixteenth transistor T21 is electrically connected to the fifth node M, and the gate of the sixteenth transistor T21 is connected to the fourth clock signal CK3. The first terminal of the seventeenth transistor T22 is electrically connected to the second terminal of the sixteenth transistor T21, the gate of the seventeenth transistor T22 is electrically connected to the second node P[q], and the second terminal of the seventeenth transistor T22 is electrically connected to the first high-potential line.
[0074] It should be noted that in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the sixteenth transistor T21 and the seventeenth transistor T22 can be turned on simultaneously to pull the potential of the fifth node M to the potential of the first high potential line, which improves the reliability of operation.
[0075] Please refer to Figure 1. The gate drive unit also includes a reset transistor T15. The control terminal of the reset transistor T15 is configured to receive a reset control signal Ctr. The input terminal of the reset transistor T15 is electrically connected to the first high-potential line, and the output terminal of the reset transistor T15 is electrically connected to the first node K.
[0076] Optionally, the reset transistor T15 is configured to be enabled when the display device is powered on and / or during the blanking interval.
[0077] Optionally, each of the above transistors can be an N-channel transistor or a P-channel transistor. The semiconductor of each of the above transistors can be a silicon semiconductor or an oxide semiconductor.
[0078] Optionally, in some embodiments, the first transistor T28, the third transistor T30, the fifth transistor T10, the sixth transistor T13, the ninth transistor T1, the eleventh transistor T14, the twelfth transistor T4, the fourteenth transistor T17, and the sixteenth transistor T21 are N-channel transistors, and the other transistors are P-channel transistors.
[0079] In some embodiments, as shown in Figure 2, when the first frequency division control signal NLF is at a high potential, the signal of the first node K is at a low potential to turn on the second transistor T29 and turn off the first transistor T28. The signal of the second node P[q] is at a high potential to turn off the third transistor T30. The signal of the third node W is at a high potential to turn off the fourth transistor T9. The signal of the fourth node G is at a high potential to turn on the fifth transistor T10. The fifth transistor T10 outputs the signal in the first low potential line as the first gate control signal Nscan[q], so that the first gate control signal Nscan[q] is at an active low potential, i.e., VGL.
[0080] It should be noted that the high potential of the first frequency division control signal NLF, i.e., VGH, is used to indicate the activation of the frequency division function. Since the gate of the third transistor T30 is at the high potential of the second node P[q] and the source of the third transistor T30 is at the high potential of the fourth node G, the gate-source voltage difference of the third transistor T30, i.e., Vgs, does not exceed its threshold voltage. Therefore, the third transistor T30 is turned off.
[0081] In some embodiments, as shown in Figure 3, when the first frequency division control signal NLF is at a low potential (VGL), the signal of the first node K is at a low potential to turn on the second transistor T29 and turn off the first transistor T28. The signal of the second node P[q] is at a high potential to turn on the third transistor T30. The signal of the fourth node G is at a low potential to turn off the fifth transistor T10. The signal of the third node W is at a low potential to turn on the fourth transistor T9. The signal in the second high potential line output by the fourth transistor T9 is the first gate control signal Nscan[q], which makes the first gate control signal Nscan[q] at an active high potential (VGH).
[0082] The second gate control signal Pscan[q] outputs a negative pulse during the period when the signal at the first node K is at a low potential.
[0083] It should be noted that the first frequency division control signal NLF being at a low potential, i.e., VGL, is used to characterize the frequency division function being turned off. Since the gate of the third transistor T30 is at a high potential of the second node P[q] and the source of the third transistor T30 is at a low potential of the fourth node G, the gate-source voltage difference of the third transistor T30, i.e., Vgs, is greater than its threshold voltage. Therefore, the third transistor T30 is turned on.
[0084] In some embodiments, as shown in Figures 2 and 3, the signal of the first node K is at a high potential to turn on the first transistor T28 and turn off the second transistor T29; the second node P[q] is at a low potential to turn off the third transistor T30; the fourth node G is at a high potential to turn on the fifth transistor T10, and the signal in the first low potential line output by the fifth transistor T10 is the first gate control signal Nscan[q], so that the first gate control signal Nscan[q] is at an active low potential, i.e., VGL.
[0085] It should be noted that when the signal of the first node K is at a high potential, the fifth transistor T10 can be controlled by the first transistor T28 to output an active low potential, namely VGL.
[0086] In some embodiments, this embodiment provides a display panel that includes the gate driving circuit described above.
[0087] It is understood that, since the display panel provided in this embodiment includes the gate driving circuit described above, it is also possible to add a voltage adjustment module 14 linked to the first frequency division control line between the first node K and the first output module 13. The voltage adjustment module 14 can select the signal in the first low potential line or the signal in the first frequency division control line to be transmitted to the fourth node G according to the signal of the first node K and the signal of the second node P[q]. Thus, when displaying in a frequency division mode, the first frequency division control line can control the potential of the first node K through the first frequency division module 12, and then control the first output module 13 to output the signal of the first low potential line as the first gate control signal Nscan[q] through the voltage adjustment module 14. Compared with the first low potential line not being able to output an active low potential as the first gate control signal Nscan[q] through the first output module 13 when displaying in a frequency division mode, the low potential of the first gate control signal Nscan[q] is in a floating state, i.e., a passive low potential, which improves the stability of the first gate control signal Nscan[q] when displaying in a frequency division mode.
[0088] In some embodiments, the display panel also includes a plurality of sub-pixels distributed in an array.
[0089] As shown in Figure 4, each sub-pixel includes a light-emitting device Di and a pixel driving circuit that drives the light-emitting device Di to emit light. The pixel driving circuit includes a driving transistor Tdr and a writing transistor Tda.
[0090] Optionally, the light-emitting device Di can be an organic light-emitting diode, a sub-millimeter light-emitting diode, a micro light-emitting diode, etc.
[0091] The driving transistor Tdr is electrically connected to the light-emitting device Di between the first voltage terminal Vdd and the second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current to drive the light-emitting device Di to emit light.
[0092] Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di, the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.
[0093] The write transistor Tda is configured to transmit a data signal to the control terminal of the drive transistor Tdr. Specifically, the input terminal of the write transistor Tda is configured to receive the corresponding data signal DS, the output terminal of the write transistor Tda is electrically connected to the input terminal of the drive transistor Tdr, and the control terminal of the write transistor Tda is connected to the second gate control signal Pscan[q] output by the q-th stage gate drive unit. This allows control over the frequency at which multiple sub-pixels refresh the display data, enabling a segmented frequency display design for the display panel.
[0094] The sub-pixel also includes a compensation transistor Tc, the input terminal of which is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of which is electrically connected to the control terminal of the driving transistor Tdr. The control terminal of the compensation transistor Tc is configured to receive the first gate control signal Nscan[q] output by the q-th level gate driving unit.
[0095] The sub-pixel includes a reset transistor Tr, the input terminal of which is electrically connected to the reset line VLr, and the output terminal of which is electrically connected to the control terminal of the drive transistor Tdr. The control terminal of the reset transistor Tr is configured to receive the first gate control signal Nscan[q-3] output by the (q-3)th gate drive unit.
[0096] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and are either P-type or q-type transistors. Optionally, to reduce leakage current from the control terminal of the driving transistor Tdr to its output terminal and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. For compatibility with existing manufacturing processes, the compensation transistor Tc and the reset transistor Tr are q-type transistors. It is understood that the active layer of the oxide transistor includes indium gallium zinc oxide, etc.
[0097] Please refer to Figure 4. The sub-pixel also includes a first initial transistor Ti1, a second initial transistor Ti2, a first light-emitting control transistor Te1, a second light-emitting control transistor Te2, and a storage capacitor Cst.
[0098] The input terminal of the first initial transistor Ti1 is configured to receive the first initial signal transmitted by the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting device Di, and the control terminal of the first initial transistor Ti1 is configured to receive the gate drive signal Pscan2.
[0099] The input terminal of the first light-emitting control transistor Te1 is electrically connected to the first voltage terminal Vdd, and the output terminal of the first light-emitting control transistor Te1 is electrically connected to the input terminal of the driving transistor Tdr.
[0100] The input terminal of the second light-emitting control transistor Te2 is electrically connected to the output terminal of the driving transistor Tdr. The output terminal of the second light-emitting control transistor Te2 is electrically connected to the anode of the light-emitting device Di. The control terminal of the second light-emitting control transistor Te2 is electrically connected to the control terminal of the first light-emitting control transistor Te1 and is connected to the light-emitting control signal EM.
[0101] The input terminal of the second initial transistor Ti2 is configured to receive the second initial signal transmitted by the second initial line VL2. The output terminal of the second initial transistor Ti2 is electrically connected to the output terminal of the first light-emitting control transistor Te1 and the input terminal of the driving transistor Tdr. The control terminal of the second initial transistor Ti2 is configured to receive the gate driving signal Pscan2.
[0102] The first terminal of the storage capacitor Cst is electrically connected to the first voltage terminal Vdd, and the second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor Tdr.
[0103] Optionally, the sub-pixel also includes a bootstrap capacitor Cboost, the first terminal of which is electrically connected to the control terminal of the data transistor Tda, and the second terminal of which is electrically connected to the control terminal of the driving transistor Tdr.
[0104] Figure 5 is a timing diagram of the sub-pixel shown in Figure 4. The working stages of this sub-pixel in each frame include:
[0105] Phase 1: The light emission control signal EM is at a high potential, and both the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned off; the gate drive signal Pscan2 is at a low potential, turning on the first initial transistor Ti1 and the second initial transistor Ti2. The first initial signal transmitted by the first initial line VL1 initializes the anode potential of the light emission device Di, and the second initial signal transmitted by the second initial line VL2 initializes the input potential of the drive transistor Tdr.
[0106] Second stage: When the light emission control signal EM is at a high potential, both the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned off; when Nscan[q-3] is at a high potential, the reset transistor Tr is turned on, and the signal in the reset line VLr resets the gate potential of the driving transistor Tdr; when Nscan[q] is at a low potential, the compensation transistor Tc is turned off.
[0107] Third stage: When the light emission control signal EM is at a high potential, both the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned off; when Nscan[q-3] is at a high potential, the reset transistor Tr is turned on, and the signal in the reset line VLr resets the gate potential of the driving transistor Tdr; when Nscan[q] is at a high potential, the compensation transistor Tc is turned on, and the signal in the reset line VLr synchronously resets the potential of the source and / or drain of the driving transistor Tdr.
[0108] Fourth stage: The light emission control signal EM is at a high potential, and the first light emission control transistor Te1 and the second light emission control transistor Te2 are both turned off; Nscan[q-3] is at a low potential, and the reset transistor Tr is turned off; Nscan[q] is at a high potential, and the compensation transistor Tc is turned on; Pscan[q] is at a low potential, in which the write transistor Tda in the nth row of sub-pixels is turned on. Subsequently, Pscan[q+1] is at a low potential, in which the write transistor Tda in the (n+1)th row of sub-pixels is turned on. The data signal DS passes through the write transistor Tda, the drive transistor Tdr, and the compensation transistor Tc to the gate of the drive transistor Tdr.
[0109] Fifth stage: The light emission control signal EM is at a high potential, and both the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned off; the gate drive signal Pscan2 is at a low potential, turning on the first initial transistor Ti1 and the second initial transistor Ti2. The first initial signal transmitted by the first initial line VL1 initializes the anode potential of the light emission device Di, and the second initial signal transmitted by the second initial line VL2 initializes the input potential of the drive transistor Tdr.
[0110] Stage 6: The light emission control signal EM is at a low potential, and both the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned on; Nscan[q-3] is at a low potential, and the reset transistor Tr is turned off; Nscan[q] is at a low potential, and the compensation transistor Tc is turned off; Pscan[q] is at a high potential, and the write transistor Tda is turned off; the light emission device Di starts to emit light.
[0111] It is understood that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all such substitutions or changes should fall within the protection scope of the appended claims.
Claims
1. A gate driving circuit, wherein, The gate driving circuit includes multiple cascaded gate driving units, each gate driving unit comprising: A node control module, which is electrically connected to a first clock line, a first control line, a first low-potential line, a first high-potential line, a first node, and a second node; The first frequency divider module is electrically connected to the first frequency divider control line, the first node, the second node, and the third node. A first output module, which is connected to the first low-potential line and the second high-potential line of the third node and the fourth node, is configured to output at least one of the signals of the first low-potential line and the second high-potential line as a first gate control signal according to the signals of the third node and the fourth node. A voltage regulation module is electrically connected to the first node, the second node, the fourth node, the first low-potential line, and the first frequency division control line, and is configured to select either a signal from the first low-potential line or a signal from the first frequency division control line to transmit to the fourth node based on the signals from the first node and the second node.
2. The gate driving circuit according to claim 1, wherein, The voltage regulation module includes: A first adjustment unit is electrically connected to the first node and the fourth node, and is configured to control the transmission of the signal from the first node to the fourth node according to the signal from the first node. The second adjustment unit is electrically connected to the first node, the fourth node and the first frequency division control line, and is configured to control the transmission of the signal of the first frequency division control line to the fourth node according to the signal of the first node. The third adjustment unit is electrically connected to the second node, the fourth node, and the first low-potential line, and is configured to control the transmission of the signal from the first low-potential line to the fourth node based on the signal from the second node.
3. The gate driving circuit according to claim 2, wherein, The first adjustment unit includes a first transistor, the first electrode of the first transistor being electrically connected to the gate of the first transistor and the first node, and the second electrode of the first transistor being electrically connected to the fourth node.
4. The gate driving circuit according to claim 3, wherein, The second adjustment unit includes a second transistor, the first terminal of the second transistor is electrically connected to the first frequency division control line, the second terminal of the second transistor is electrically connected to the fourth node, and the gate of the second transistor is electrically connected to the first node; The channel type of the second transistor is different from that of the first transistor.
5. The gate driving circuit according to claim 4, wherein, The third adjustment unit includes a third transistor, the first terminal of which is electrically connected to the first low potential line, the second terminal of which is electrically connected to the fourth node, and the gate of which is electrically connected to the second node. The channel type of the third transistor is the same as that of the first transistor.
6. The gate driving circuit according to claim 5, wherein, The first output module includes: The fourth transistor has its first terminal electrically connected to the third node and its gate electrically connected to the second high-potential line. The fifth transistor has its first terminal electrically connected to the second terminal of the fourth transistor and configured to output the first gate control signal, the second terminal of the fifth transistor being electrically connected to the first low-potential line, and the gate of the fifth transistor being electrically connected to the fourth node. The fourth transistor has a different channel type than the fifth transistor, but the fourth transistor has the same channel type as the second transistor.
7. The gate driving circuit according to claim 6, wherein, When the signal of the first frequency division control line is at a high potential, the signal of the first node is at a low potential to turn on the second transistor, the signal of the fourth node is at a high potential to turn on the fifth transistor, the signal of the third node is at a high potential to turn off the fourth transistor, and the fifth transistor outputs the signal in the first low potential line as the first gate control signal.
8. The gate driving circuit according to claim 7, wherein, The signal of the first node is at a low potential to turn off the first transistor, and the signal of the second node is at a high potential to turn off the third transistor.
9. The gate driving circuit according to claim 6, wherein, When the signal of the first frequency division control line is at a low potential, the signal of the first node is at a low potential to turn on the second transistor, the signal of the fourth node is at a low potential to turn off the fifth transistor, the signal of the third node is at a low potential to turn on the fourth transistor, and the signal in the second high potential line output by the fourth transistor is the first gate control signal.
10. The gate driving circuit according to claim 9, wherein, The signal of the first node is at a low potential to turn off the first transistor, and the signal of the second node is at a high potential to turn on the third transistor.
11. The gate driving circuit according to claim 6, wherein, The first node is at a high potential to turn on the first transistor and turn off the second transistor; the second node is at a low potential to turn off the third transistor; the fourth node is at a high potential to turn on the fifth transistor, and the fifth transistor outputs the signal in the first low potential line as the first gate control signal.
12. The gate drive circuit according to any one of claims 1-11, wherein, The gate driving circuit further includes: The second frequency divider module is electrically connected to the second frequency divider control line, the first node, the second node, and the fifth node, and is configured to control the transmission of the signal from the first node to the fifth node according to the second frequency divider control signal in the second frequency divider control line and the signal from the second node; The second output module is electrically connected to the second node, the fifth node, the second node of the (q-2)th stage gate drive unit, the second clock line, the first high potential line, and the second gate control line. It is configured to output the second gate control signal in the second gate control line based on the signal of the second node, the signal of the fifth node, the signal of the second node of the (q-2)th stage gate drive unit, the second clock signal in the second clock line, and the first high potential signal in the first high potential line.
13. The gate driving circuit according to claim 12, wherein, The gate drive circuit further includes a third output module, which is electrically connected to the second node, the fifth node, the second node of the (q-2)th stage gate drive unit, the third clock line, the first high potential line, and the third gate control line. The third output module is configured to output a third gate control signal in the third gate control line based on the signal of the second node, the signal of the fifth node, the signal of the second node of the (q-2)th stage gate drive unit, the third clock signal in the third clock line, and the first high potential signal in the first high potential line.
14. A display panel, wherein, The display panel includes a gate driving circuit, which includes multiple cascaded gate driving units, each gate driving unit comprising: A node control module, which is electrically connected to a first clock line, a first control line, a first low-potential line, a first high-potential line, a first node, and a second node; The first frequency divider module is electrically connected to the first frequency divider control line, the first node, the second node, and the third node. A first output module, which is connected to the first low-potential line and the second high-potential line of the third node and the fourth node, is configured to output at least one of the signals of the first low-potential line and the second high-potential line as a first gate control signal according to the signals of the third node and the fourth node. A voltage regulation module is electrically connected to the first node, the second node, the fourth node, the first low-potential line, and the first frequency division control line, and is configured to select either a signal from the first low-potential line or a signal from the first frequency division control line to transmit to the fourth node based on the signals from the first node and the second node.
15. The display panel according to claim 14, wherein, The voltage regulation module includes: A first adjustment unit is electrically connected to the first node and the fourth node, and is configured to control the transmission of the signal from the first node to the fourth node according to the signal from the first node. The second adjustment unit is electrically connected to the first node, the fourth node and the first frequency division control line, and is configured to control the transmission of the signal of the first frequency division control line to the fourth node according to the signal of the first node. The third adjustment unit is electrically connected to the second node, the fourth node, and the first low-potential line, and is configured to control the transmission of the signal from the first low-potential line to the fourth node based on the signal from the second node.
16. The display panel according to claim 15, wherein, The first adjustment unit includes a first transistor, the first electrode of the first transistor being electrically connected to the gate of the first transistor and the first node, and the second electrode of the first transistor being electrically connected to the fourth node.
17. The display panel according to claim 16, wherein, The second adjustment unit includes a second transistor, the first terminal of the second transistor is electrically connected to the first frequency division control line, the second terminal of the second transistor is electrically connected to the fourth node, and the gate of the second transistor is electrically connected to the first node; The channel type of the second transistor is different from that of the first transistor.
18. The display panel according to claim 17, wherein, The third adjustment unit includes a third transistor, the first terminal of which is electrically connected to the first low potential line, the second terminal of which is electrically connected to the fourth node, and the gate of which is electrically connected to the second node. The channel type of the third transistor is the same as that of the first transistor.
19. The display panel according to claim 18, wherein, The first output module includes: The fourth transistor has its first terminal electrically connected to the third node and its gate electrically connected to the second high-potential line. The fifth transistor has its first terminal electrically connected to the second terminal of the fourth transistor and configured to output the first gate control signal, the second terminal of the fifth transistor being electrically connected to the first low-potential line, and the gate of the fifth transistor being electrically connected to the fourth node. The fourth transistor has a different channel type than the fifth transistor, but the fourth transistor has the same channel type as the second transistor.
20. The display panel according to claim 19, wherein, When the signal of the first frequency division control line is at a high potential, the signal of the first node is at a low potential to turn on the second transistor, the signal of the fourth node is at a high potential to turn on the fifth transistor, the signal of the third node is at a high potential to turn off the fourth transistor, and the fifth transistor outputs the signal in the first low potential line as the first gate control signal.