Display panel and display device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-08-13
Smart Images
Figure CN2025089195_13082026_PF_FP_ABST
Abstract
Description
Display panel and display device Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] Organic light-emitting diode (OLED) displays feature low power consumption, fast response speed, and wide viewing angle, making them promising for future applications. Currently, OLED display technology is widely used in various electronic products, from small items like smart bracelets, smartwatches, smartphones, and tablets to large devices such as laptops, desktop computers, and televisions.
[0003] Display technology is a significant chapter in the history of human civilization. With the rapid popularization of OLED, in addition to the excellent performance of the screen when it is on, the visual effect when the screen is off has also attracted much attention from users. Especially in the field of smart wearables, lower screen reflectivity and a better all-around black effect are strong demands from consumers. However, the reflectivity of OLED display panels is currently relatively high, which affects the all-around black display effect of OLED display panels. Invention Overview
[0004] This application provides a display panel and a display device to reduce the reflectivity of the display panel and improve the integrated black display effect.
[0005] The technical solution provided in this application is as follows:
[0006] In a first aspect, embodiments of this application provide a display panel, which includes:
[0007] Substrate;
[0008] A driving circuit layer is disposed on the substrate;
[0009] A first planarization layer is disposed on the side of the driving circuit layer away from the substrate;
[0010] A first electrode layer is disposed on the side of the first planarization layer away from the driving circuit layer. The first electrode layer includes a plurality of spaced first sub-electrodes, with a first gap between two adjacent first sub-electrodes. The first sub-electrodes are connected to the driving circuit layer.
[0011] The first planarization layer includes a light-shielding sub-layer, which is disposed at least corresponding to the first gap, and the light-shielding sub-layer has light-absorbing properties.
[0012] Secondly, embodiments of this application also provide a display device, which includes the display panel described in one of the foregoing embodiments. Attached Figure Description
[0013] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 is a cross-sectional structural diagram of a display panel provided in an embodiment of this application.
[0015] Figure 2 is a schematic diagram of the light path of ambient light passing through the display panel provided in an embodiment of this application.
[0016] Figure 3 is a schematic diagram of another cross-sectional structure of the display panel provided in an embodiment of this application.
[0017] Figure 4 is a schematic cross-sectional view of another display panel provided in an embodiment of this application. Embodiments of the present invention
[0018] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.
[0019] To address the issue of high reflectivity in current OLED display panels, which affects the seamless black display effect, the inventors of this application discovered in their research that a polarizer can reduce the reflectivity of the display panel. The polarizer includes a linear polarization layer and a quarter-wave plate layer. Ideally, the polarized light after passing through the linear polarization layer and the quarter-wave plate layer is completely circularly polarized. Under this condition, the reflected light from the display panel can be almost completely absorbed, resulting in extremely low reflectivity and excellent seamless black effect. However, in reality, due to factors such as the phase difference of the quarter-wave plate layer and the change in the relative axis angle between the quarter-wave plate layer and the linear polarization layer, the polarized light after passing through the linear polarization layer and the quarter-wave plate layer is elliptically polarized. Some of the polarized components do not completely change their polarization state after being reflected by the display panel and cannot be absorbed, resulting in light leakage and thus increasing reflectivity. Meanwhile, ambient light contains light of various wavelengths. Different wavelengths of light exhibit different polarization states after passing through the linear polarization layer and the quarter-wave plate layer. Along with light leakage, color changes also occur, resulting in a uniform black effect. While uniform black is generally well-maintained at a normal viewing angle, different color shifts appear at wider viewing angles. Therefore, although placing a polarizer on the display panel can reduce reflectivity, the effect is limited, leaving the display panel with relatively high reflectivity, thus affecting the uniform black display effect of the OLED display panel.
[0020] Therefore, this application provides a display panel and a display device to absorb ambient light transmitted through the display panel, reduce the reflectivity of the display panel, and improve the integrated black display effect.
[0021] Please refer to Figures 1 and 2. Figure 1 is a cross-sectional structural diagram of a display panel provided in an embodiment of this application, and Figure 2 is a light path diagram of ambient light passing through the display panel provided in an embodiment of this application. Referring to Figure 1, the display panel 100 includes a substrate 10 and a driving circuit layer 20, a first planarization layer, and a first electrode layer 40 disposed on the substrate 10. The first planarization layer is disposed on the side of the driving circuit layer 20 away from the substrate 10. The first electrode layer 40 is disposed on the side of the first planarization layer away from the driving circuit layer 20. The first electrode layer 40 includes a plurality of spaced-apart first sub-electrodes 41, with a first gap between adjacent first sub-electrodes 41, and the first sub-electrodes 41 are connected to the driving circuit layer 20.
[0022] The first planarization layer includes a light-shielding sub-layer 31, which is disposed at least corresponding to the gap of the first sub-electrode 41 and has light-absorbing properties. Thus, by disposing a light-absorbing sub-layer 31 between the driving circuit layer 20 and the first electrode layer 40, and by disposing the light-shielding sub-layer 31 at least corresponding to the first gap, the light-shielding sub-layer 31 can absorb ambient light transmitted through the display panel 100, reducing the reflection of ambient light by the driving circuit layer 20, thereby reducing the reflectivity of the display panel 100 and improving the integrated black display effect.
[0023] In some embodiments, referring to FIG1, the substrate 10 includes a first polyimide layer 11, a first barrier layer 12, a second polyimide layer 13, and a second barrier layer 14 stacked together. The materials of the first barrier layer 12 and the second barrier layer 14 include inorganic materials such as silicon oxide and silicon nitride.
[0024] The driving circuit layer 20 is disposed on the substrate 10. The driving circuit layer 20 includes a plurality of transistors 21. The plurality of transistors 21 include a first transistor T1 and a second transistor T2 connected to the first transistor T1. The first transistor T1 includes a first active layer AS1, a first gate G1, a first source S1, a first drain D1, and a first electrode C1. The second transistor T2 includes a second active layer AS2, a second gate G2, a third gate G3, a second source S2, and a second drain D2. The material of the first active layer AS1 includes a silicon semiconductor material, such as low-temperature polycrystalline silicon; the material of the second active layer AS2 is a metal oxide semiconductor material, such as IGZO.
[0025] Optionally, the substrate 10 further includes a first buffer layer 15, a second buffer layer 16, and a light-shielding layer 17 located between the first buffer layer 15 and the second buffer layer 16. The light-shielding layer 17 is disposed at least corresponding to the channel portion of the first active layer AS1. The second buffer layer 16 is located on the side of the first buffer layer 15 away from the second barrier layer 14. The materials of the first buffer layer 15 and the second buffer layer 16 include inorganic materials such as silicon oxide and silicon nitride. The material of the light-shielding layer 17 includes a metallic material with light-shielding properties.
[0026] The driving circuit layer 20 further includes a plurality of insulating layers disposed between the structures of the first transistor T1 and the second transistor T2. The plurality of insulating layers includes a first gate insulating layer 221 located between the first active layer AS1 and the first gate G1. The first gate G1 is located on the side of the first active layer AS1 away from the substrate 10.
[0027] The plurality of insulating layers also includes a first interlayer insulating layer 222 located between the first gate G1 and the first electrode C1. The first electrode C1 is located on the side of the first gate G1 away from the first active layer AS1. The first electrode C1 is disposed corresponding to the first gate G1. The second gate G2 is disposed in the same layer as the first electrode C1.
[0028] It should be noted that, in this application, "co-layer arrangement" refers to the process in which at least two different structures are obtained by patterning a film layer formed of the same material during the fabrication process, and the at least two different structures are arranged in the same layer. For example, in this embodiment, the second gate G2 and the second electrode plate are obtained by patterning the same conductive film layer, and therefore the second gate G2 and the second electrode plate are arranged in the same layer.
[0029] The plurality of insulating layers also includes a second gate insulating layer 223 located between the second gate G2 and the second active layer AS2. The second active layer AS2 is located on the side of the second gate G2 away from the substrate 10. The second gate G2 and the second active layer AS2 are correspondingly disposed.
[0030] The plurality of insulating layers also includes a third gate insulating layer 224 located between the second active layer AS2 and the third gate G3. The third gate G3 is located on the side of the second active layer AS2 away from the substrate 10. The third gate G3 is disposed corresponding to the channel portion of the second active layer AS2.
[0031] The plurality of insulating layers also includes a second interlayer insulating layer 225 located between the third gate G3 and the second source S2 and the second drain D2. The second source S2 and the second drain D2 are located on the side of the third gate G3 away from the substrate 10. The first source S1, the first drain D1, the second source S2, and the second drain D2 are disposed in the same layer.
[0032] The first gate G1, the second gate G2, the third gate G3, and the first electrode C1 are all made of conductive materials, such as copper, aluminum, titanium, or other metals. The first gate insulating layer 221, the second gate insulating layer 223, the third gate insulating layer 224, the first interlayer insulating layer 222, and the second interlayer insulating layer 225 are all made of inorganic materials such as silicon oxide and silicon nitride.
[0033] In some embodiments, the driving circuit layer 20 further includes a shielding signal line 231 located on the side of the transistor 21 away from the substrate 10. The shielding signal line 231 is connected to the light-shielding layer 17 to provide a shielding signal to the light-shielding layer 17.
[0034] Optionally, the driving circuit layer 20 further includes a first bridging electrode 232, and the shielded signal line 231 is connected to the light-shielding layer 17 through the first bridging electrode 232. The first bridging electrode 232 is disposed on the same layer as the first source S1 and the first drain D1.
[0035] The driving circuit layer 20 further includes a passivation layer 226 and a second planarization layer 227 located between the transistor 21 and the shielded signal line 231. The second planarization layer 227 is located on the side of the passivation layer 226 away from the substrate 10.
[0036] The first planarization layer 30 is located on the side of the shielded signal line 231 away from the substrate 10. The first planarization layer 30 covers the shielded signal line 231 and the second planarization layer 227. The first planarization layer 30 includes a light-shielding sublayer 31 and a planarization sublayer 32, both of which are integrally disposed, with the planarization sublayer 32 located on the side of the light-shielding sublayer 31 away from the driving circuit layer 20.
[0037] The material of the light-shielding sublayer 31 includes an organic material doped with a light-absorbing factor, which includes at least one of black pigment, black dye, and carbon black. For example, the material of the light-shielding sublayer 31 includes a thermosetting resin doped with a black pigment. The material of the planarization sublayer 32 may be the same as the material of the second planarization layer 227, such as both being organic materials like resin.
[0038] The first electrode layer 40 is located on the side of the first planarization layer 30 away from the substrate 10. The first electrode layer 40 includes a plurality of first sub-electrodes 41, each of which is connected to a corresponding transistor 21. For example, the first sub-electrode 41 is connected to the first drain D1 of the first transistor T1, and the first drain D1 of the first transistor T1 is connected to the second drain D2 of the second transistor T2. The shielded signal line 231 is located between adjacent first sub-electrodes 41.
[0039] Optionally, the driving circuit layer 20 further includes a second bridging electrode 211 disposed on the same layer as the shielded signal line 231. The first sub-electrode 41 is connected to the first drain D1 of the first transistor T1 through the second bridging electrode 211. The materials of the second bridging electrode 211 and the shielded signal line 231 are the same as the material of the first source S1.
[0040] The display panel 100 further includes a light-emitting functional layer 50 and a second electrode layer 60. The light-emitting functional layer 50 is located between the first sub-electrode 41 and the second electrode layer 60. The light-emitting functional layer 50 may include a hole-containing organic layer, a light-emitting material layer, and an electronic organic layer stacked sequentially.
[0041] The hole-injecting organic layer may include a hole injection layer and a hole transport layer. The hole injection layer is in direct contact with the first sub-electrode 41, and the hole transport layer is located between the hole injection layer and the light-emitting material layer. The hole-injecting organic layer may also include an electron blocking layer located between the hole transport layer and the light-emitting material layer.
[0042] The electronically functional organic layer may include an electron injection layer and an electron transport layer. The electron injection layer is in direct contact with the second electrode layer 60, and the electron transport layer is located between the electron injection layer and the luminescent material layer. The electronically functional organic layer may also include a hole blocking layer located between the electron transport layer and the luminescent material layer.
[0043] Wherein, the first sub-electrode 41 is the anode, the second electrode layer 60 is the cathode, the first sub-electrode 41 is a patterned electrode, and the second electrode layer 60 is a planar electrode formed entirely in one layer.
[0044] The display panel 100 further includes a pixel definition layer 33 and a support pillar 34. The pixel definition layer 33 is disposed on the side of the first planarization layer 30 away from the driving circuit layer 20, and includes pixel definition portions and openings located between the pixel definition portions. The openings expose a portion of the first sub-electrode 41, and the pixel definition layer 33 covers the edge of the first sub-electrode 41 and the first planarization layer 30. The support pillar 34 is located on the pixel definition layer 33 and is used to support the mask plate during the deposition of the light-emitting functional layer 50.
[0045] Referring to Figures 1 and 2, ambient light rays A and B enter the display panel 100. Ray A strikes the first sub-electrode 41, and ray B strikes the first gap. Ray A is reflected by the first sub-electrode 41, while ray B is absorbed by the light-shielding sub-layer 31 of the first planarization layer 30. This prevents ray B from being reflected out of the display panel 100 by the metal layer on the driving circuit layer 20; for example, ray B is not reflected by the shielded signal line 231 on the driving circuit layer 20. This reduces the reflection of ambient light by the driving circuit layer 20, thereby lowering the reflectivity of the display panel 100 and improving the integrated black display effect.
[0046] In some embodiments, the sum of the thickness of the light-shielding sub-layer 31 and the thickness of the planarization sub-layer 32 is less than or equal to 4 micrometers, such as 4 micrometers, 3 micrometers, 2.8 micrometers, 2.5 micrometers, 2.2 micrometers, 2 micrometers, 1.9 micrometers, 1.7 micrometers, 1.5 micrometers, etc. That is, the thickness of the first planarization layer 30 is less than or equal to 4 micrometers to avoid the first sub-electrode 41 being unfavorable for film formation in the contact holes of the first planarization layer 30 and to prevent the uniformity of the film thickness of the first sub-electrode 41 from deteriorating if the thickness of the first planarization layer 30 is too thick.
[0047] The thickness of the light-shielding sub-layer 31 is greater than or equal to the thickness of the flattening sub-layer 32. A thicker light-shielding sub-layer 31 allows for better absorption of ambient light transmitted through the display panel 100, which is beneficial for reducing the reflectivity of the display panel 100 and improving overall black levels. Optionally, the thickness ratio of the flattening sub-layer 32 to the light-shielding sub-layer 31 is 1 / 9 to 1 / 2, such as 1 / 9, 2 / 9, 4 / 9, 1 / 8, 3 / 8, 1 / 7, 2 / 7, 3 / 7, 1 / 6, 1 / 5, 2 / 5, 1 / 4, 1 / 3, 1 / 2, etc. For example, the thickness of the light-shielding sub-layer 31 is 1.5 micrometers, and the thickness of the flattening sub-layer 32 is 0.5 micrometers.
[0048] Optionally, the resolution of the material of the light-shielding sub-layer 31 is greater than that of the material of the planarization sub-layer 32, so that while the light-shielding sub-layer 31 absorbs ambient light, it can also better planarize the surface topography of the driving circuit layer 20. It should also be noted that the first sub-electrode 41 is connected to the corresponding transistor through the contact hole of the first planarization layer 30. The contact hole of the first planarization layer 30 includes a first sub-hole formed by the light-shielding sub-layer 31 and a second sub-hole formed by the planarization sub-layer 32, and the first sub-hole and the second sub-hole are interconnected to form the contact hole of the first planarization layer 30. The material resolution of the light-shielding sub-layer 31 is greater than that of the planarization sub-layer 32. Under the same patterning process, the aperture of the first sub-hole formed by the light-shielding sub-layer 31 is smaller than the aperture of the second sub-hole formed by the planarization sub-layer 32. That is, in the contact holes formed by the first planarization layer 30, the aperture of the contact hole portion closer to the transistor is smaller than the aperture of the contact hole portion farther from the transistor. This facilitates the formation of the first sub-electrode 41 within the contact holes of the first planarization layer 30 and simplifies the process of forming the contact holes in the first planarization layer 30. Higher material resolution allows for more accurate etching to form the desired pattern during the patterning process, reducing the likelihood of material residue. For example, higher material resolution allows for the formation of smaller and finer contact holes during the patterning process.
[0049] In some embodiments, the display panel 100 further includes a polarizer 70, which is located on the side of the second electrode layer 60 away from the driving circuit layer 20. The polarizer 70 includes a linear polarizing layer and a quarter-wave plate layer, with the linear polarizing layer located on the side of the quarter-wave plate layer away from the light-emitting functional layer 50. Of course, the polarizer 70 may also include a compensation film or other film layer. The ratio of the thickness of the light-shielding sub-layer 31 to the thickness of the polarizer 70 is 0.4 / 50 to 4 / 50, for example, 0.4 / 50, 0.6 / 50, 0.9 / 50, 1 / 50, 1.5 / 50, 1.8 / 50, 2 / 50, 2.5 / 50, 3 / 50, 3.5 / 50, 4 / 50, etc.
[0050] In this embodiment, by configuring the light-shielding sub-layer 31 and the polarizer 70 in combination, and controlling the thickness ratio of the light-shielding sub-layer 31 to the polarizer 70, the reflectivity of the display panel 100 can be significantly reduced, resulting in a substantial improvement in the integrated black display effect. Furthermore, by combining the light-shielding sub-layer 31 and the polarizer 70, while achieving a significant improvement in the integrated black display effect, the thickness of the polarizer 70 can also be reduced; for example, the thickness of the polarizer 70 can be less than or equal to 50 micrometers, thereby reducing the overall thickness of the display panel 100.
[0051] The light-shielding sub-layer 31 absorbs ambient light B in Figure 2, and the polarizer 70 absorbs ambient light A reflected by the first sub-electrode 41. Specifically, the incident ambient light is natural light, unpolarized; after passing through the linear polarization layer of the polarizer 70, it is converted into linearly polarized light; after passing through the quarter-wave plate layer, it is converted into left-handed circularly polarized light (or right-handed circularly polarized light). This light is incident on the first sub-electrode 41, and after being reflected by the first sub-electrode 41, it is converted into right-handed circularly polarized light (or left-handed circularly polarized light). After passing through the quarter-wave plate layer again, it is converted into linearly polarized light. The vibration direction of this light is perpendicular to the transmission axis of the linear polarization layer, so the light cannot pass through the linear polarization layer, thus achieving an extinction effect.
[0052] In some embodiments, continuing to refer to FIG1, the display panel 100 further includes an encapsulation layer 80 located on the side of the light-emitting functional layer 50 away from the first electrode layer 40, and the second electrode layer 60 is located between the light-emitting functional layer 50 and the encapsulation layer 80. The encapsulation layer 80 is used to protect the light-emitting functional layer 50 and the second electrode layer 60, preventing water and oxygen intrusion that could cause the light-emitting functional layer 50 to fail.
[0053] Optionally, the encapsulation layer 80 can be formed by alternately laminating one or more organic layers and one or more inorganic layers. Multiple inorganic or organic layers can be provided. The organic layers are formed of polymers and can be, for example, laminates or monolayers formed from polyethylene terephthalate, polyimide, polycarbonate, epoxy resin, polyethylene, and polyacrylate. The organic layers can be formed from polyacrylates, specifically including substances obtained by polymerizing monomer compositions comprising diacrylate-based monomers and triacrylate-based monomers. The monomer composition may also include monoacrylate-based monomers. Furthermore, the monomer composition may include known photoinitiators such as TPO, but the monomer composition is not limited thereto. The inorganic layers can be laminates or monolayers comprising metal oxides or metal nitrides. For example, the inorganic layers may include any one of SiNx, Al2O3, SiO2, and TiO2. Optionally, along the direction from the substrate 10 to the driving circuit layer 20, the encapsulation layer 80 includes a first inorganic encapsulation sublayer 81, a first organic encapsulation sublayer 82, and a second inorganic encapsulation sublayer 83.
[0054] In some embodiments, the display panel 100 further includes a touch function layer 90 located on the side of the encapsulation layer 80 away from the light-emitting functional layer 50. The touch function layer 90 is located between the encapsulation layer 80 and the polarizer 70. The touch function layer 90 can implement touch functionality in a self-capacitive touch or a mutual-capacitive touch manner. When the touch function layer 90 implements touch functionality in a self-capacitive touch manner, the touch function layer 90 may have only one touch metal layer.
[0055] When the touch function layer 90 implements the touch function using capacitive touch, the touch function layer 90 includes a first touch metal layer, a touch insulating layer, and a second touch metal layer. The touch insulating layer is located on the side of the first touch metal layer away from the encapsulation layer 80, and the second touch metal layer is located on the side of the touch insulating layer away from the encapsulation layer 80. The first touch metal layer can be directly disposed on the encapsulation layer 80, or a spacer layer can be disposed between the first touch function layer 90 and the encapsulation layer 80. The spacer layer can include an inorganic spacer layer and / or an organic spacer layer. The first touch metal layer includes a first touch electrode, a second touch electrode, and a first bridging wire; the second touch metal layer includes a second bridging wire; both the first and second touch electrodes are metal networks. Alternatively, the second touch metal layer includes a first touch electrode, a second touch electrode, and a first bridging wire; the first touch metal layer includes a second bridging wire. Optionally, the touch function layer 90 includes a touch electrode layer 91, an interlayer spacer layer 92 located between the touch electrode layer 91 and the encapsulation layer 80, and a protective layer 93 located between the touch electrode layer 91 and the polarizer 70.
[0056] In some embodiments, referring to FIG3, FIG3 is a schematic cross-sectional view of another display panel 100 provided in an embodiment of the present application. The difference from the display panel 100 exemplified in FIG1 is that the light-shielding sub-layer 31 is located on the side of the flat sub-layer 32 away from the driving circuit layer 20.
[0057] In some embodiments, the sum of the thickness of the light-shielding sub-layer 31 and the thickness of the planarization sub-layer 32 is less than or equal to 4 micrometers, such as 4 micrometers, 3 micrometers, 2.8 micrometers, 2.5 micrometers, 2.2 micrometers, 2 micrometers, 1.9 micrometers, 1.7 micrometers, 1.5 micrometers, etc. That is, the thickness of the first planarization layer 30 is less than or equal to 4 micrometers to avoid the first sub-electrode 41 being unfavorable for film formation in the contact holes of the first planarization layer 30 and to prevent the uniformity of the film thickness of the first sub-electrode 41 from deteriorating if the thickness of the first planarization layer 30 is too thick.
[0058] The thickness of the light-shielding sub-layer 31 is greater than or equal to the thickness of the flattening sub-layer 32. A thicker light-shielding sub-layer 31 allows for better absorption of ambient light transmitted through the display panel 100, which is beneficial for reducing the reflectivity of the display panel 100 and improving overall black levels. Optionally, the thickness ratio of the flattening sub-layer 32 to the light-shielding sub-layer 31 is 1 / 9 to 1 / 2, such as 1 / 9, 2 / 9, 4 / 9, 1 / 8, 3 / 8, 1 / 7, 2 / 7, 3 / 7, 1 / 6, 1 / 5, 2 / 5, 1 / 4, 1 / 3, 1 / 2, etc. For example, the thickness of the light-shielding sub-layer 31 is 1.5 micrometers, and the thickness of the flattening sub-layer 32 is 0.5 micrometers.
[0059] Optionally, the material resolution of the planarization sublayer 32 is greater than that of the light-shielding sublayer 31, so that while the light-shielding sublayer 31 absorbs ambient light, it can also better planarize the surface topography of the driving circuit layer 20. It should also be noted that the first sub-electrode 41 is connected to the corresponding transistor through the contact hole of the first planarization layer 30. The contact hole of the first planarization layer 30 includes a first sub-hole formed by the light-shielding sublayer 31 and a second sub-hole formed by the planarization sublayer 32, and the first sub-hole and the second sub-hole are interconnected to form the contact hole of the first planarization layer 30. The material resolution of the planarization sublayer 32 is greater than that of the light-shielding sublayer 31. Under the same patterning process, the aperture of the first sub-hole formed by the light-shielding sublayer 31 can be larger than the aperture of the second sub-hole formed by the planarization sublayer 32. That is, in the contact holes formed by the first planarization layer 30, the aperture of the contact hole portion near the transistor is smaller than the aperture of the contact hole portion away from the transistor. This facilitates the formation of the first sub-electrode 41 within the contact holes of the first planarization layer 30 and simplifies the process of forming the contact holes in the first planarization layer 30. Other explanations are provided in the above embodiments and will not be repeated here.
[0060] In some embodiments, referring to FIG4, FIG4 is another cross-sectional structural schematic diagram of the display panel 100 provided in the embodiments of this application. The difference from the display panel 100 exemplified in FIG1 is that the first planarization layer 30 includes a light-shielding sublayer 31 but does not include a planarization sublayer 32. The thickness of the light-shielding sublayer 31 is less than or equal to 4 micrometers, such as 4 micrometers, 3 micrometers, 2.8 micrometers, 2.5 micrometers, 2.2 micrometers, 2 micrometers, 1.9 micrometers, 1.7 micrometers, 1.5 micrometers, etc. Other descriptions are provided in the above embodiments and will not be repeated here.
[0061] Based on the same inventive concept, this application also provides a display device, which includes the display panel 100 described in one of the foregoing embodiments. The display device can be an electronic product such as a smart bracelet, smartwatch, smartphone, tablet computer, laptop computer, desktop computer, or television.
[0062] As can be seen from the above embodiments:
[0063] This application provides a display panel and display device. The display panel includes a substrate and a driving circuit layer, a first planarization layer, and a first electrode layer disposed on the substrate. The first electrode layer includes a plurality of spaced-apart first sub-electrodes with a first gap between adjacent first sub-electrodes. The first sub-electrodes are connected to the driving circuit layer. The first planarization layer includes a light-shielding sub-layer, which is disposed at least corresponding to the first gap and has light-absorbing properties. Thus, by disposing a light-absorbing sub-layer between the driving circuit layer and the first electrode layer, and with the light-shielding sub-layer being disposed at least corresponding to the gap of the first sub-electrodes, the light-shielding sub-layer can absorb ambient light transmitted through the display panel, reduce the reflection of ambient light by the driving circuit layer, thereby reducing the reflectivity of the display panel and improving the integrated black display effect.
[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0065] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A display panel comprising: Substrate; A driving circuit layer is disposed on the substrate; A first planarization layer is disposed on the side of the driving circuit layer away from the substrate; A first electrode layer is disposed on the side of the first planarization layer away from the driving circuit layer. The first electrode layer includes a plurality of spaced first sub-electrodes, with a first gap between two adjacent first sub-electrodes. The first sub-electrodes are connected to the driving circuit layer. The first planarization layer includes a light-shielding sub-layer, which is disposed at least corresponding to the first gap, and the light-shielding sub-layer has light-absorbing properties.
2. The display panel according to claim 1, wherein, The material of the light-shielding sublayer includes an organic material doped with a light-absorbing factor, which includes at least one of black pigment, black dye, and carbon black.
3. The display panel according to claim 2, wherein, The first planarization layer further includes a planarization sublayer, and the planarization sublayer and the light-shielding sublayer are integrally disposed, wherein the thickness of the light-shielding sublayer is greater than or equal to the thickness of the planarization sublayer.
4. The display panel according to claim 3, wherein, The ratio of the thickness of the flat sublayer to the thickness of the light-shielding sublayer is 1 / 9 to 1 / 2.
5. The display panel according to claim 3, wherein, The flat sublayer is located on the side of the light-shielding sublayer away from the driving circuit layer.
6. The display panel according to claim 5, wherein, The resolution of the material in the flat sublayer is less than that of the material in the light-shielding sublayer.
7. The display panel according to claim 3, wherein, The light-shielding sublayer is located on the side of the flat sublayer away from the driving circuit layer.
8. The display panel according to claim 7, wherein, The resolution of the material in the flat sublayer is greater than that of the material in the light-shielding sublayer.
9. The display panel according to any one of claims 1 to 8, wherein, The display panel also includes: A light-emitting functional layer is disposed on the side of the first electrode layer away from the driving circuit layer. The driving circuit layer includes a plurality of transistors, and the first sub-electrode of the first electrode layer is connected to the corresponding transistor. An encapsulation layer is disposed on the side of the light-emitting functional layer away from the first electrode layer; A polarizer is disposed on the side of the encapsulation layer away from the light-emitting functional layer; The ratio of the thickness of the light-shielding sub-layer to the thickness of the polarizer is 0.4 / 50 to 4 / 50.
10. The display panel according to claim 9, wherein, The polarizer includes a linear polarizing layer and a quarter-wave plate layer, wherein the linear polarizing layer is located on the side of the quarter-wave plate layer away from the light-emitting functional layer; the thickness of the polarizer is less than or equal to 50 micrometers.
11. A display device comprising a display panel, the display panel comprising: Substrate; A driving circuit layer is disposed on the substrate; A first planarization layer is disposed on the side of the driving circuit layer away from the substrate; A first electrode layer is disposed on the side of the first planarization layer away from the driving circuit layer. The first electrode layer includes a plurality of spaced first sub-electrodes, with a first gap between two adjacent first sub-electrodes. The first sub-electrodes are connected to the driving circuit layer. The first planarization layer includes a light-shielding sub-layer, which is disposed at least corresponding to the first gap, and the light-shielding sub-layer has light-absorbing properties.
12. The display device according to claim 11, wherein, The material of the light-shielding sublayer includes an organic material doped with a light-absorbing factor, which includes at least one of black pigment, black dye, and carbon black.
13. The display device according to claim 12, wherein, The first planarization layer further includes a planarization sublayer, and the planarization sublayer and the light-shielding sublayer are integrally disposed, wherein the thickness of the light-shielding sublayer is greater than or equal to the thickness of the planarization sublayer.
14. The display device according to claim 13, wherein, The ratio of the thickness of the flat sublayer to the thickness of the light-shielding sublayer is 1 / 9 to 1 / 2.
15. The display device according to claim 13, wherein, The flat sublayer is located on the side of the light-shielding sublayer away from the driving circuit layer.
16. The display device according to claim 15, wherein, The resolution of the material in the flat sublayer is less than that of the material in the light-shielding sublayer.
17. The display device according to claim 13, wherein, The light-shielding sublayer is located on the side of the flat sublayer away from the driving circuit layer.
18. The display device according to claim 17, wherein, The resolution of the material in the flat sublayer is greater than that of the material in the light-shielding sublayer.
19. The display device according to any one of claims 11 to 18, wherein, The display panel also includes: A light-emitting functional layer is disposed on the side of the first electrode layer away from the driving circuit layer. The driving circuit layer includes a plurality of transistors, and the first sub-electrode of the first electrode layer is connected to the corresponding transistor. An encapsulation layer is disposed on the side of the light-emitting functional layer away from the first electrode layer; A polarizer is disposed on the side of the encapsulation layer away from the light-emitting functional layer; The ratio of the thickness of the light-shielding sub-layer to the thickness of the polarizer is 0.4 / 50 to 4 / 50.
20. The display device according to claim 19, wherein, The polarizer includes a linear polarizing layer and a quarter-wave plate layer, wherein the linear polarizing layer is located on the side of the quarter-wave plate layer away from the light-emitting functional layer; the thickness of the polarizer is less than or equal to 50 micrometers.