Chip, stack structure, package structure, circuit board assembly, and electronic device

Abstract

The present application provides a chip, a stack structure, a package structure, a circuit board assembly, and an electronic device. The chip comprises: a substrate; a device layer, the device layer being arranged on one side of the substrate; a wiring layer, the wiring layer being arranged on the side of the device layer facing away from the substrate, and the wiring layer comprising a conductive structure; and a pad, the pad being electrically connected to the conductive structure, and the pad being exposed from a side surface of the chip. The present application can increase the number of stacked layers of a chip.

Description

Chips, stacked structures, packaging structures, circuit board assemblies and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510138399.8, filed on February 7, 2025, entitled "Chip, Stacked Structure, Packaging Structure, Circuit Board Assembly and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a chip, a stacked structure, a packaging structure, a circuit board assembly, and an electronic device. Background Technology

[0003] Complex scenarios such as big data and cloud computing require the processing and storage of massive amounts of data, necessitating higher read / write speeds and larger storage capacities for memory chips. To increase storage capacity, one related technology involves stacking multiple memory chips sequentially on a substrate along its thickness. Each chip is electrically connected to the next layer via bonding wires. To provide fixed positions for the bonding wires of each chip layer, the multiple layers are staggered along the length or width of the substrate. However, due to limitations in the bonding wire connection method, the number of stacked chip layers in this related technology is relatively small. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip, a stacking structure, a packaging structure, a circuit board assembly, and an electronic device that can increase the number of stacked layers of the chip.

[0005] A first aspect of this application provides a chip, comprising: a substrate, a device layer, a wiring layer, and pads. The device layer is disposed on one side of the substrate. The wiring layer is disposed on the side of the device layer opposite to the substrate, and the wiring layer includes conductive structures. The pads are electrically connected to the conductive structures and are exposed from the side of the chip. The side of the chip can refer to the outer surface located between the top and bottom surfaces of the chip and extending along the thickness direction of the chip. In practical applications, multiple chips are usually packaged together for use. In this way, each chip can be placed upright on a functional chip, and the pads of each chip can be soldered to the functional chip. That is, multiple chips are stacked along the length or width direction of the functional chip. Each chip can be fixed to the functional chip by the pads disposed on its side. Compared with the connection method using wire bonding, each chip layer does not need to reserve a fixed position corresponding to the bonding wire. Compared with the connection method using through-silicon vias (TSVs), each chip layer does not need to reserve a fixed position for the TSV. Therefore, the number of stacked layers is unlimited, thereby increasing the number of stacked chip layers.

[0006] In some embodiments of this application, a first hole is provided inwardly on the surface of the device layer facing the wiring layer and on the side connected to the surface, and at least a portion of the pad is located within the first hole. This allows the pad to be exposed from the surface of the device layer facing the wiring layer for contact and electrical connection with conductive structures in the wiring layer. Furthermore, the pad can be exposed from the side of the device layer for easy soldering to a functional chip. Moreover, since the pad is essentially embedded within the device layer and exposed on its surface, the pad arrangement does not additionally increase the chip's footprint. Therefore, when the chip is fixed to the substrate, the total thickness of the chip and substrate is not additionally increased.

[0007] In some embodiments of this application, the first hole is a through hole, and a second hole is provided on the side of the substrate facing inward. The second hole communicates with the through hole, and a portion of the pad is located within the second hole. That is, a portion of the pad is located within the through hole on the device layer, and another portion is located within the second hole in the substrate. This increases the size of the pad, thereby improving the stability of the electrical connection between the chip and the substrate, adapter board, or functional chip.

[0008] In some embodiments of this application, the pad includes a conductive body structure and a seed layer that at least surrounds the sidewalls of the conductive body structure. When the pad includes a conductive body structure and a seed layer, the seed layer can be deposited first during the pad fabrication process, and then the conductive body structure can be fabricated by electroplating. The seed layer is typically made of stainless steel, TiN, or Ti, and the conductive body structure is typically made of copper or aluminum, thereby facilitating the attachment of the conductive body structure to the first hole of the device layer and the second hole of the substrate.

[0009] In some embodiments of this application, the chip further includes a thermally conductive layer. In one embodiment, the thermally conductive layer is disposed on the side of the wiring layer away from the substrate. The chip generates heat during operation. The thermally conductive layer disposed on the side of the wiring layer away from the substrate can dissipate the generated heat outwards in a timely and effective manner, preventing overheating inside the chip and thus avoiding impact on chip performance or even chip damage.

[0010] Therefore, the chip also includes a passivation layer, which is located between the thermally conductive layer and the wiring layer. The material of the thermally conductive layer can include metals, metal-graphene composites, diamond, and other inorganic or organic materials. When the material of the thermally conductive layer is conductive, the passivation layer placed between the thermally conductive layer and the wiring layer can provide electrical isolation, preventing short circuits between the thermally conductive layer and the wiring layer, since the wiring layer includes conductive structures.

[0011] In another embodiment, the thermally conductive layer is disposed on the side of the substrate away from the device layer. The chip generates heat during operation, and the thermally conductive layer disposed on the side of the substrate away from the device layer can dissipate this heat outwards in a timely and effective manner, preventing overheating inside the chip and thus avoiding impact on chip performance or even chip damage.

[0012] In a specific implementation, the heat-conducting layer includes a first heat sink. In one possible implementation, the first heat sink has a flat plate structure and no internal microchannels.

[0013] In another possible implementation, the first heat sink has a first microchannel. This allows heat to be dissipated from the chip by introducing a medium through the first microchannel.

[0014] In one example, the first microchannel is a closed structure, and a medium is disposed within the first microchannel. Therefore, heat dissipation can be achieved through the medium within the first microchannel.

[0015] In another example, the first heat sink has an inlet and an outlet, both of which are connected to a first microchannel. A second heat sink is typically included in the package structure, with its inlet and outlet connected to microchannels within the second heat sink. This allows the first and second heat sinks to form a liquid transport channel, enabling heat to be transferred to the second heat sink and diffused outwards via convection heat transfer, thereby improving the chip's heat dissipation efficiency.

[0016] A second aspect of this application provides a stacked structure comprising multiple chips according to any of the above embodiments, wherein the chips are stacked sequentially along the thickness direction, and the pads of each chip are located on the same side. In application, the stacked structure can be placed upright on a functional chip, and the pads of each chip can be soldered to the functional chip. That is, multiple chips are stacked along the length or width direction of the functional chip, and each chip can be fixed to the functional chip by pads provided on its side. Compared with the connection method using wire bonding, each chip layer does not need to reserve a fixed position corresponding to the wire; compared with the connection method using through-silicon vias (TSVs), each chip layer also does not need to reserve a fixed position for the TSV. Therefore, the number of stacked layers is unlimited, thereby increasing the number of chip stacked layers. This enables the achievement of ultra-high capacity and ultra-high bandwidth. Furthermore, with the increase in the number of stacked layers, a higher integration density per unit volume can be obtained.

[0017] In addition, each chip can be fixed to a substrate, adapter board or functional chip via pads on its side. Therefore, on the one hand, it can achieve a higher interconnection density than leaded structures, and on the other hand, it is also conducive to achieving structural integration and improving structural stability.

[0018] In some embodiments of this application, the stacked structure further includes a second heat sink, which is located on one side of the multiple chips along the thickness direction; that is, the second heat sink is located on the side of the multiple chips. The second heat sink has a second microchannel, and the inlet and outlet of the chips are connected to the second microchannel. Thus, the first heat sink and the second heat sink can form a liquid transport channel, thereby conducting heat to the second heat sink and diffusing it outwards through convection heat transfer and other methods, thereby improving the heat dissipation efficiency of the chips.

[0019] In some embodiments of this application, the stacked structure further includes a third heat sink with a third microchannel, which is disposed on the multilayer chip, and the third microchannel passes through each chip. Thus, the third heat sink can also provide auxiliary heat dissipation for each chip, further improving the heat dissipation efficiency of the stacked structure.

[0020] In some embodiments of this application, a medium is disposed within the third microchannel, and the third microchannel is a closed structure. Alternatively, the third microchannel is connected to the second microchannel. Thus, the third heat sink and the second heat sink can form a liquid transport channel, thereby transferring heat to the second heat sink and diffusing it outwards through convection heat transfer, thereby improving the chip's heat dissipation efficiency.

[0021] In some embodiments of this application, the stacked structure further includes a first molding compound layer that wraps around a portion of the multiple chips from one side where the pads of the multiple chips are located. This increases the stability of the connections between the multiple chips.

[0022] Regarding the number of thermally conductive layers in the stacked structure, in one possible implementation, when the heat dissipation efficiency of the thermally conductive layers is low, a thermally conductive layer is provided between every two chips. Therefore, by providing a thermally conductive layer between every two chips, the heat dissipation efficiency of each chip is increased, thereby improving the overall heat dissipation efficiency of the stacked structure.

[0023] In another possible implementation, when the heat dissipation efficiency of the thermal conductive layer is high, there is a thermal conductive layer between at least two adjacent chips, and at least two adjacent chips without a thermal conductive layer. That is, in this case, the number of thermal conductive layers is less. Because the thermal conductive layer has high heat dissipation efficiency, it still provides high heat dissipation efficiency for the entire stacked structure. Furthermore, it can reduce the size of the stacked structure and lower costs.

[0024] Furthermore, the thermal conductive layers can be uniformly arranged, for example, one thermal conductive layer every N chips. Alternatively, the thermal conductive layers can be non-uniformly arranged. For example, the number of chips between two adjacent thermal conductive layers in the first group may differ from the number of chips between two adjacent thermal conductive layers in the second group.

[0025] A third aspect of this application also provides a packaging structure, including a carrier structure and a stacked structure according to any of the above embodiments, wherein the stacked structure is disposed on the carrier structure, and the pads of each chip in the stacked structure face the carrier structure. The packaging structure can achieve all the effects of the stacked structure.

[0026] In some embodiments of this application, the carrier structure includes at least one of a substrate, an adapter board, and a functional chip. That is, the specific structure of the carrier structure can be selected according to actual needs.

[0027] In some embodiments of this application, the supporting structure includes a body and a welding structure, with the welding structure located between the body and the stacked structure. The encapsulation structure further includes a second molding compound layer, located between the stacked structure and the body, and encapsulating the welding structure. Thus, the second molding compound layer protects the welding structure from oxidation or corrosion. Furthermore, the second molding compound layer is connected to the first molding compound layer of the stacked structure. This further increases the stability of the stacked structure and enhances the mechanical strength of the encapsulation structure.

[0028] A fourth aspect of this application also provides a circuit board assembly, including a circuit board and a stacked structure according to any of the above embodiments, the stacked structure being disposed on the circuit board. The circuit board assembly can achieve all the effects of the stacked structure. Alternatively, the circuit board assembly includes a circuit board and a package structure according to any of the above embodiments, the package structure being disposed on the circuit board. The circuit board assembly can achieve all the effects of the package structure.

[0029] A fifth aspect of this application also provides an electronic device, including a housing and the aforementioned circuit board assembly, the circuit board assembly being disposed within the housing. The electronic device is capable of achieving all the effects of the circuit board assembly.

[0030] A sixth aspect of this application also provides a method for fabricating a chip. The method includes: fabricating a device layer structure on a wafer; fabricating pads, at least a portion of which are located within the wafer; fabricating a wiring layer structure on the device layer structure to obtain a chip structure; and cutting the chip structure along the locations of the pads to obtain multiple chips. Each chip includes pads located on its side surface. The side surface of the chip can refer to the outer surface located between the top and bottom surfaces of the chip and extending along the thickness direction of the chip. In practical applications, multiple chips are typically packaged together for use. This allows each chip to be placed upright on a functional chip, and the pads of each chip to be soldered to the functional chip. In other words, multiple chips are stacked along the length or width direction of the functional chip. Each chip can be fixed to the functional chip by the pads located on its side. Compared to wire bonding, each chip layer does not need to reserve a fixed position corresponding to the wires. Compared to through-silicon vias (TSVs), each chip layer also does not need to reserve a fixed position for the TSVs. Therefore, the number of stacked layers is unlimited, thereby increasing the number of chip stacked layers.

[0031] In some embodiments of this application, after fabricating the wiring layer structure on the device layer structure, the fabrication method further includes: fabricating a thermally conductive layer structure on the side of the wiring layer structure facing away from the wafer. The chip generates heat during operation. The thermally conductive layer disposed on the side of the substrate facing away from the device layer can dissipate the generated heat outward in a timely and effective manner, preventing overheating inside the chip and thus avoiding impact on chip performance or even chip damage.

[0032] A seventh aspect of this application also provides a method for fabricating a stacked structure. The method includes: sequentially flipping multiple chips and fixing their side pads to a third substrate. The chips are fabricated using the chip fabrication method described in any of the above embodiments. The multiple chips are stacked sequentially along their thickness direction, with the pads of all chips facing the third substrate. The third substrate is then removed to obtain the stacked structure. In application, the stacked structure can be placed upright on a functional chip, and the pads of each chip can be soldered to the functional chip. That is, multiple chips are stacked along the length or width direction of the functional chip, and each chip can be fixed to the functional chip by pads located on its side. Compared to wire bonding, each chip layer does not need to reserve a fixed position corresponding to the wire. Compared to through-silicon via (TSV) connections, each chip layer also does not need to reserve a fixed position for the TSV. Therefore, the number of stacked layers is unlimited, thereby increasing the number of chip stacked layers. This enables ultra-high capacity and ultra-high bandwidth. Furthermore, increasing the number of stacked layers results in higher integration density per unit volume.

[0033] In some embodiments of this application, after the steps of sequentially flipping multiple chips and fixing the side pads to a third substrate, the manufacturing method further includes: fabricating a first molding compound on the third substrate, the first molding compound covering a portion of the multiple chips. This increases the stability of the connection between the multiple chips.

[0034] In some embodiments of this application, sequentially flipping multiple chips and fixing their side pads to a third carrier board includes: sequentially flipping one or at least two first chips and fixing their side pads to the third carrier board; fixing a first heat sink to the third carrier board, wherein the first heat sink is fixed to the front or back of one or at least two first chips; and sequentially flipping one or at least two second chips and fixing their side pads to the third carrier board. In other words, chips and first heat sinks are sequentially fixed to the third carrier board.

[0035] An eighth aspect of this application also provides a method for fabricating a stacked structure. The method includes: fabricating multiple wafer structures, each wafer structure comprising sequentially stacked wafers, device layer structures, and wiring layer structures, and each wafer structure also including pads, at least a portion of which are located within the wafers; stacking the multiple wafer structures sequentially to obtain an initial stacked structure; and cutting the initial stacked structure along the locations of the pads to obtain the final stacked structure. In application, the stacked structure can be placed upright on a functional chip, and the pads of each chip can be soldered to the functional chip. That is, multiple chips can be stacked along the length or width of the functional chip, and each chip can be fixed to the functional chip by pads located on its side. Compared to wire bonding, each chip layer does not need a pre-reserved fixed position for the wires; compared to through-silicon vias (TSVs), each chip layer does not need a pre-reserved fixed position for the TSVs. Therefore, the number of stacked layers is unlimited, thereby increasing the number of chip stacked layers. This enables ultra-high capacity and ultra-high bandwidth. Furthermore, increasing the number of stacked layers results in higher integration density per unit volume.

[0036] A ninth aspect of this application also provides a method for manufacturing a packaging structure. The method includes: flipping a stacked structure and fixing the side pads to a support structure. The stacked structure is manufactured using the above-described method. The support structure includes a body and a soldering structure, with the soldering structure located between the body and the stacked structure. A second molding compound is then fabricated, located between the stacked structure and the body, and encapsulating the soldering structure. The packaging structure achieves all the effects of the stacked structure. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 is a schematic diagram of a packaging structure in a related technology;

[0039] Figure 2 is a schematic diagram of the packaging structure in another related technology;

[0040] Figure 3 is a schematic diagram of the first type of encapsulation structure in the embodiments of this application;

[0041] Figure 4 is a top view of Figure 3;

[0042] Figure 5 is a schematic diagram of the second type of encapsulation structure in an embodiment of this application;

[0043] Figure 6 is a top view of Figure 5;

[0044] Figure 7 is a schematic diagram of the third type of encapsulation structure in the embodiments of this application;

[0045] Figure 8 is a top view of Figure 7;

[0046] Figure 9 is a schematic diagram of the packaging structure shown in Figure 3;

[0047] Figure 10 is a cross-sectional view of section AA in Figure 9;

[0048] Figure 11 is a lateral cross-sectional view of Figure 9;

[0049] Figure 12a is a schematic diagram of one structure of the chip in the packaging structure shown in Figure 9;

[0050] Figure 12b is a schematic diagram of another chip structure in the packaging structure shown in Figure 9;

[0051] Figure 13 is a cross-sectional view of the section at CC in Figure 12a;

[0052] Figure 14 is a cross-sectional view of the section at DD in Figure 12a;

[0053] Figure 15a is a schematic diagram of a thermal conductive layer in the chip shown in Figure 12a;

[0054] Figure 15b is a schematic diagram of another structure of the thermal conductive layer in the chip shown in Figure 12a;

[0055] Figure 16 is a schematic flowchart of a method for manufacturing the packaging structure shown in Figure 9;

[0056] Figure 17 is a schematic diagram of the first part of the manufacturing process shown in Figure 16;

[0057] Figure 18 is a schematic diagram of the second part of the manufacturing method shown in Figure 16;

[0058] Figure 19 is a schematic diagram of the third part of the manufacturing process shown in Figure 16;

[0059] Figure 20 is a schematic diagram of the fourth part of the manufacturing method shown in Figure 16;

[0060] Figure 21 is a schematic diagram of another process for manufacturing the packaging structure shown in Figure 9;

[0061] Figure 22 is a schematic diagram of a part of the manufacturing process shown in Figure 21;

[0062] Figure 23 is a schematic diagram of another part of the manufacturing process shown in Figure 21.

[0063] Icons: 100 - Package structure; 10 - Substrate; 20 - Stacked structure; 21 - Chip; 211 - Substrate; 2110 - Wafer; 2111 - Second via; 212 - Device layer; 2120 - Device layer structure; 2121 - First via; 213 - Wiring layer; 2130 - Wiring layer structure; 2131 - Dielectric structure; 2132 - Conductive structure; 214 - Pad; 2141 - Seed layer; 2142 - Conductive body structure; 215 - Thermally conductive layer; 2150 - Thermally conductive layer structure; 2151 - First microchannel; 21511 - First subchannel; 21512 - Second subchannel; 2152 - Inlet; 2153 - Outlet; 216 - Passivation layer; 2160 - Passivation Layer structure; 217-side surface; 30-functional chip; 31-substrate; 310-wafer; 311-TSV; 32-device layer; 33-first bonding structure; 34-wiring layer; 35-second bonding structure; 40-interface board; 50-bonding wire; 60-second heat sink; 61-second microchannel; 70-third heat sink; 71-third microchannel; 80-molding structure; 81-first molding layer; 82-second molding layer; 201-first carrier board; 202-second carrier board; 203-third carrier board; 2031-adhesive layer; 204-fourth carrier board; 2041-first buffer layer; 205-fifth carrier board; 2051-second buffer layer; 206-sixth carrier board. Detailed Implementation

[0064] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, while "more" refers to two or more. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0066] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0067] Terms such as “connected” and “linked” are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses. Terms such as “upper,” “lower,” “left,” and “right” are used only relative to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and may vary accordingly depending on the orientation of the components in the drawings.

[0068] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0069] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0070] Complex scenarios such as big data and cloud computing require the processing and storage of massive amounts of data, demanding higher read / write speeds and larger storage capacities from memory chips. However, as the pace of Moore's Law slows, shrinking the size of memory chips becomes increasingly difficult, hindering further improvements in density on a 2D plane. Furthermore, as manufacturing nodes shrink, challenges related to process integrity, cost, capacitor leakage and interference, and sensing margin become more pronounced, making it challenging to achieve stable charge storage and read / write operations within a smaller space.

[0071] Vertically stacking multiple memory chips can increase storage capacity. Common structures include stacked double data rate synchronous dynamic random access memory (DDR SDRAM) and high bandwidth memory (HBM). Here, HBM specifically refers to dynamic random access memory (DRAM).

[0072] As shown in Figure 1, the stacked DDR SDRAM structure includes a substrate 10 and multiple chips 21, each of which can be a DDR memory chip. Each chip 21 is placed horizontally, and the multiple chips 21 are stacked vertically. Each layer of chips 21 is connected to the lower layer via wire bonding. For example, the top layer chip 21 is electrically connected to the next-top layer chip 21 via bonding wire 50, the next-top layer chip 21 is electrically connected to the chip 21 below it via bonding wire 50, and so on. The bottom layer chips 21 are electrically connected to the substrate 10 via bonding wire 50. Thus, the bonding wires 50 achieve interconnection between chips 21 and between chips 21 and the substrate 10. Furthermore, to provide a fixed position for the bonding wires 50 on the upper layer chips 21, each layer of chips 21 is horizontally staggered. Therefore, if the number of stacked layers of chips 21 is too high, the lower layer chips 21 will not be able to provide a large fixed area for the upper layer chips 21, resulting in insufficient stability of the upper layer chips 21. Therefore, using wire bonding limits the number of stacked layers of chip 21. For example, it is typically required that the number of stacked layers not exceed 20, and in related technologies, the maximum number of layers is usually 16.

[0073] As shown in Figure 2, the HBM includes a substrate 10 and multiple chips 21, each of which is a DDR memory chip. Each chip 21 is placed horizontally and stacked in multiple layers vertically. Each layer of chips 21 is interconnected through through-silicon vias (TSVs) 311. However, the TSVs 311 occupy a large area on the chips 21 and the substrate 10, sacrificing the area of ​​the HBM structure and thus increasing the cost.

[0074] Based on this, embodiments of this application provide an electronic device. The electronic device can be, for example, a server, consumer electronics, home electronics, in-vehicle electronics, financial terminal products, communication electronic products, etc., and this application embodiment does not limit the scope of these. Indicatively, the aforementioned consumer electronics can be mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics can be smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronic products can be in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can be automated teller machines (ATMs), self-service electronic devices, etc. Communication electronic products can be servers, storage devices, radar, base stations, and other communication equipment.

[0075] The electronic device may include a housing and a circuit board assembly, the circuit board assembly being disposed within the housing. Regarding the structure of the circuit board assembly, in one possible embodiment, the circuit board assembly may include a circuit board and a package structure 100, the package structure 100 being disposed on the circuit board. Here, the package structure 100 may be a system-in-package (SISP) structure or other type of package structure 100. In another possible embodiment, the circuit board assembly may include a circuit board and a stack structure 20, the stack structure 20 being disposed on the circuit board. The package structure 100 may include the stack structure 20.

[0076] For ease of description, in this embodiment, three directions can be defined: X-axis, Y-axis, and Z-axis. X-axis represents the length direction of the packaging structure 100, Y-axis represents the width direction of the packaging structure 100, and Z-axis represents the thickness direction of the packaging structure 100. Furthermore, the X, Y, and Z axes are perpendicular to each other.

[0077] Regarding the specific structure of the package structure 100, in one possible implementation, as shown in Figures 3 and 4, the package structure 100 includes a functional chip 30 and a plurality of stacked structures 20, which are laid out in a rectangular array on the functional chip 30. The stacked structures 20 may include a plurality of chips 21 (not shown in Figures 3 and 4) stacked sequentially along the X direction.

[0078] Chip 21 and functional chip 30 may be the same or different. Both chip 21 and functional chip 30 can be unpackaged chips, i.e., bare chips; or they can be packaged functional modules. For example, chip 21 and functional chip 30 can be system-on-chips (SOCs), dummy chips, computing chips, memory chips, input / output (I / O) chips, integrated passive devices (IPDs), etc. For instance, chip 21 can be a memory chip, and functional chip 30 can be a computing chip. A computing chip can be, for example, a central processing unit (CPU) or a graphics processing unit (GPU).

[0079] In another possible implementation, as shown in Figures 5 and 6, the package structure 100 includes a substrate 10, a plurality of stacked structures 20, and a functional chip 30. The plurality of stacked structures 20 and the functional chip 30 are laid flat on the substrate 10. The plurality of stacked structures 20 are respectively located on both sides of the functional chip 30.

[0080] In another possible embodiment, as shown in Figures 7 and 8, the package structure 100 includes a substrate 10, an adapter plate 40, a plurality of stacked structures 20, a functional chip 30a, and a functional chip 30b. The plurality of stacked structures 20 and the functional chip 30a are fixed to the adapter plate 40, and the adapter plate 40 is fixed to the substrate 10. The functional chip 30b is fixed to the substrate 10.

[0081] The technical solution of this embodiment will be described in detail below, taking the stacked structure 20 shown in Figure 3 as an example of the functional chip 30.

[0082] As shown in Figure 9, the functional chip 30 includes a substrate 31, a device layer 32 (body), a first bonding structure 33, a wiring layer 34, and a second bonding structure 35. The first bonding structure 33 and the device layer 32 are located on one side of the substrate 31, with the device layer 32 situated between the substrate 31 and the first bonding structure 33. The wiring layer 34 and the second bonding structure 35 are located on the other side of the substrate 31, with the wiring layer 34 situated between the second bonding structure 35 and the substrate 31. A through-hole TSV 311 is provided on the substrate 31, thereby allowing the first bonding structure 33 to be electrically connected to the second bonding structure 35 via the device layer 32, the TSV 311, and the wiring layer 34.

[0083] As shown in Figures 9, 10, and 11, the stacked structure 20 includes a plurality of chips 21 stacked sequentially along the X direction. The X direction is the length direction of the packaging structure 100, but the thickness direction of the chips 21.

[0084] As shown in Figures 12a and 13, chip 21 includes a substrate 211, a device layer 212, a wiring layer 213, and pads 214. The device layer 212 is disposed on one side of the substrate 211. The device layer 212 includes multiple active regions and isolation regions, with an isolation region between every two active regions.

[0085] As shown in Figure 12a, a wiring layer 213 is disposed on the side of the device layer 212 facing away from the substrate 211. The wiring layer 213 includes a dielectric structure 2131 and a conductive structure 2132. The conductive structure 2132 is located within the dielectric structure 2131 and is exposed from the wiring layer 213 toward the surface of the device layer 212. The conductive structure 2132 of the wiring layer 213 is also in contact with the device layer 212, thus the conductive structure 2132 can be electrically connected to the device layer 212.

[0086] The material of the dielectric structure 2131 can be a dielectric material, specifically polyimide (PI) or SiO2, etc. The material of the conductive structure 2132 can be Cu or Al, etc.

[0087] As shown in Figure 12a, the pad 214 is electrically connected to the conductive structure 2132. Specifically, the pad 214 contacts the conductive structure 2132, thereby achieving the electrical connection. As shown in Figures 13 and 14, the chip 21 typically includes multiple pads 214, each of which is electrically connected to a portion of the conductive structure 2132 in the wiring layer 213. Since the conductive structure 2132 is also electrically connected to the active region of the device layer 212, signals from the device layer 212 can be transmitted to the pad 214 through the conductive structure 2132.

[0088] As shown in Figure 12a, the pads 214 are exposed from the side surface 217 of the chip 21. When the chip 21 includes multiple pads 214, each pad 214 is located on the same side surface 217 of the chip 21 and is exposed from the same side surface 217. In this embodiment, the side surface 2147 of the chip 21 can refer to the outer surface located between the top and bottom surfaces of the chip 21 and extending along the X direction.

[0089] In practical applications, as shown in Figures 9, 10, and 11, multiple chips 21 are typically packaged together for use. The pads 214 of each chip 21 are located on the same side 217. This allows each chip 21 to be placed upright on the functional chip 30, and the pads 214 of each chip 21 to be soldered to the functional chip 30. In other words, multiple chips 21 are stacked along the length or width of the functional chip 30. Each chip 21 can be fixed to the functional chip 30 by the pads 214 on its side. Compared to wire bonding, each layer of chips 21 does not require a pre-reserved fixed position for the bonding wire 50. Similarly, compared to TSV311 connections, each layer of chips 21 does not require a pre-reserved fixed position for the TSV311. Therefore, the number of stacked layers is unlimited, allowing for an increase in the number of stacked chip layers. This enables the achievement of ultra-high capacity and ultra-high bandwidth. Furthermore, increasing the number of stacked layers results in higher integration density per unit volume.

[0090] Furthermore, each chip 21 can be fixed to the substrate 10, the adapter board 40, or the functional chip 30 via pads 214 on its side 217. Therefore, on the one hand, a higher interconnect density than the bonding wire 50 structure can be achieved; on the other hand, it is also beneficial to achieve structural integration and improve structural stability. Moreover, each chip 21 does not need to reserve TSVs for transmitting signals from that chip 21 to other chips, which saves surface area of ​​the functional chip 30 and thus reduces costs.

[0091] In this embodiment, the thickness (dimension along the Z direction) of the packaging structure 100 is mainly determined by the length or width of the chip 21, and is typically greater than 1 mm.

[0092] As shown in Figure 12a, a first hole 2121 is provided inwardly on the surface of the device layer 212 facing the wiring layer 213 and the side connected to the surface thereto. At least a portion of the pad 214 is located within the first hole 2121. Thus, on the one hand, the pad 214 can be exposed from the surface of the device layer 212 facing the wiring layer 213 to contact and electrically connect with the conductive structure 2132 in the wiring layer 213. On the other hand, the pad 214 can be exposed from the side 217 of the device layer 212 for soldering to the functional chip 30 shown in Figure 9. Furthermore, the pad 214 is essentially embedded within the device layer 212 and exposed on its surface, thereby not increasing the area occupied by the chip 21. When the chip 21 is fixed to the functional chip 30, the total thickness of the chip 21 and the functional chip 30 is not increased.

[0093] As shown in Figure 12a, the first hole 2121 is a through hole, and a second hole 2111 is provided on the side of the substrate 211 facing inward. The second hole 2111 communicates with the through hole, and part of the pad 214 is also located within the second hole 2111. That is, part of the pad 214 is located within the through hole on the device layer 212, and another part is located within the second hole 2111 on the substrate 211. In this way, the size of the pad 214 can be increased, thereby improving the electrical connection stability between the chip 21 and the functional chip 30 as shown in Figure 9.

[0094] As shown in Figure 12a, the pad 214 includes a conductive body structure 2142 and a seed layer 2141 that at least covers the sidewalls of the conductive body structure 2142. In one example, the seed layer 2141 only covers the sidewalls of the conductive body structure 2142. In another example, the seed layer 2141 may cover both the sidewalls and the bottom of the conductive body structure 2142. When the pad 214 includes the conductive body structure 2142 and the seed layer 2141, during the fabrication of the pad 214, the seed layer 2141 can be deposited first, and then the conductive body structure 2142 can be fabricated by electroplating or deposition. The material of the seed layer 2141 can typically be stainless steel, TiN, or Ti, and the material of the conductive body structure 2142 can typically include Cu or Al. This facilitates the attachment of the conductive body structure 2142 to the first hole 2121 of the device layer 212 and the second hole 2111 of the substrate 211.

[0095] In addition, as the number of stacked layers of chip 21 increases, the heat generated by the entire package structure 100 also increases. Excessive temperature will lead to a decrease in the performance of chip 21 and a shortened lifespan. Therefore, in order to improve the heat dissipation efficiency of chip 21, as shown in Figure 12a, chip 21 also includes a thermally conductive layer 215.

[0096] Regarding the placement of the thermal conductive layer 215, in one possible implementation, as shown in FIG12a, the thermal conductive layer 215 is disposed on the side of the wiring layer 213 facing away from the substrate 211. Since the chip 21 generates heat during operation, the thermal conductive layer 215 disposed on the side of the wiring layer 213 facing away from the substrate 211 can dissipate the generated heat in a timely and effective manner, preventing overheating inside the chip 21 from affecting the performance of the chip 21 or even causing damage to the chip 21.

[0097] Based on this, as shown in Figure 12a, chip 21 further includes a passivation layer 216, which is located between the thermally conductive layer 215 and the wiring layer 213. The material of the thermally conductive layer 215 may include metal, metal-graphene composite, diamond, other inorganic or organic materials, etc. When the material of the thermally conductive layer 215 is a conductive material, since the wiring layer 213 includes a conductive structure 2132, the passivation layer 216 disposed between the thermally conductive layer 215 and the wiring layer 213 can play an electrical isolation role, preventing short circuits between the thermally conductive layer 215 and the wiring layer 213.

[0098] Regarding the placement of the thermal conductive layer 215, in another possible embodiment, as shown in FIG12b, the thermal conductive layer 215 is disposed on the side of the substrate 211 away from the device layer 212. Since the chip 21 generates heat during operation, the thermal conductive layer 215 disposed on the side of the substrate 211 away from the device layer 212 can dissipate the generated heat outward in a timely and effective manner, preventing overheating inside the chip 21 from affecting the performance of the chip 21 or even causing damage to the chip 21.

[0099] In this embodiment, a passivation layer 216 may also be provided on the side of the wiring layer 213 away from the substrate 211. In this way, when multiple chips 21 are stacked, a passivation layer 216 is provided between the wiring layer 213 of each chip 21 and the thermal conductive layer 215 of the adjacent chip 21, thereby achieving electrical isolation.

[0100] In a specific implementation, the thermally conductive layer 215 includes a first heat sink. In one possible implementation, the first heat sink has a flat plate structure and no internal microchannels.

[0101] In another possible implementation, the first heat sink is provided with a first microchannel 2151 as shown in Figures 15a and 15b. This allows heat to be dissipated from the chip 21 by introducing a medium into the first microchannel 2151. The medium can be a single-phase liquid, a two-phase flow medium, or a phase-change medium. A two-phase flow medium can refer to a medium composed of two substances in two different phases. Common two-phase flow media include gas and water, or water and ice, etc.

[0102] As shown in Figure 15a, the first microchannel 2151 includes a plurality of parallel first subchannels 21511 and a second subchannel 21512 connecting two adjacent first subchannels 21511, with the two adjacent second subchannels 21512 located on different sides. Thus, the second subchannels 21512 located on different sides can dissipate heat to their respective vicinity without affecting each other.

[0103] In one example, as shown in Figure 15a, the first microchannel 2151 is a closed structure, and a medium is disposed within the first microchannel 2151. Therefore, the chip 21 can dissipate heat through the medium within the first microchannel 2151.

[0104] In another example, as shown in Figure 15b, the first heat sink has an inlet 2152 and an outlet 2153, both of which are connected to the first microchannel 2151. As shown in Figure 9, the package structure 100 also includes a second heat sink 60, which is located on one side of the plurality of chips 21 along the thickness direction. That is, the second heat sink 60 is located on the side of the plurality of chips 21, specifically, on the side of the plurality of chips 21 away from the functional chip 30. The second heat sink 60 has a second microchannel 61, and the inlet 2152 and outlet 2153 of the chip 21 are both connected to the second microchannel 61. Thus, the first heat sink and the second heat sink 60 can form a liquid transport channel, thereby conducting heat to the second heat sink 60 and diffusing it outward through convection heat transfer and other means, thereby improving the heat dissipation efficiency of the chip 21.

[0105] Regarding the number of thermal conductive layers 215 in the stacked structure 20, in one possible implementation, when the heat dissipation efficiency of the thermal conductive layers 215 is low, a thermal conductive layer 215 is provided between every two chips 21. Thus, by providing a thermal conductive layer 215 between every two chips 21, the heat dissipation efficiency of each chip 21 is increased, thereby improving the overall heat dissipation efficiency of the stacked structure 20.

[0106] In another possible implementation, when the heat dissipation efficiency of the thermal conductive layer 215 is high, there is at least one thermal conductive layer 215 between two adjacent chips 21, and at least two adjacent chips 21 without a thermal conductive layer 215 between them. That is, in this case, the number of thermal conductive layers 215 is reduced. Because the thermal conductive layer 215 has high heat dissipation efficiency, it still provides high heat dissipation efficiency for the entire stacked structure 20. Furthermore, it can reduce the size of the stacked structure 20 and lower the cost.

[0107] Furthermore, the thermal conductive layers 215 can be uniformly arranged, for example, one thermal conductive layer 215 is provided every N chips 21. Alternatively, the thermal conductive layers 215 can be non-uniformly arranged. For example, the number of chips 21 between two adjacent thermal conductive layers 215 in the first group is different from the number of chips 21 between two adjacent thermal conductive layers 215 in the second group.

[0108] As shown in Figure 9, the packaging structure 100 also includes a third heat sink 70, which has a third microchannel 71 inside. The third heat sink 70 is disposed on the multilayer chip 21, and the third microchannel 71 passes through each chip 21. Thus, the third heat sink 70 can also provide auxiliary heat dissipation for each chip 21, thereby further improving the heat dissipation efficiency of the stacked structure 20.

[0109] Similar to the structure of the first heat sink, in one example, the third microchannel 71 contains a medium and is a closed structure. In another example, the third microchannel 71 is connected to the second microchannel 61. Thus, the third heat sink 70 and the second heat sink 60 can form a liquid transport channel, thereby transferring heat to the second heat sink 60 and diffusing it outwards through convection heat transfer, thereby improving the heat dissipation efficiency of the chip 21.

[0110] As shown in Figure 9, the packaging structure 100 also includes a molding compound structure 80, which includes a first molding compound layer 81 and a second molding compound layer 82. The first molding compound layer 81 wraps around a portion of the multiple chips 21 from the side where the pads 214 of the multiple chips 21 are located. This increases the stability of the connection between the multiple chips 21. The second molding compound layer 82 is located between the stacked structure 20 and the device layer 32, and wraps around the first solder structure 33. Thus, the second molding compound layer 82 protects the first solder structure 33 from oxidation or corrosion. Moreover, the second molding compound layer 82 is connected to the first molding compound layer 81 of the stacked structure 20. This further increases the stability of the stacked structure 20 and enhances the mechanical strength of the packaging structure 100. The solder structure can specifically be a solder ball layer.

[0111] The material of the encapsulated structure 80 can be resin, PI, or silicon dioxide.

[0112] This application embodiment also provides a method for manufacturing a packaging structure 100, which can be applied to the packaging structure 100 shown in FIG9. As shown in FIG16, the manufacturing method includes:

[0113] S161, fabricating device layer structures on a wafer.

[0114] As shown in Figure 17(a), a device layer structure 2120 can be fabricated on a wafer 2110 using techniques such as photolithography, electroplating, and chemical mechanical polishing. The device layer structure 2120 includes multiple active regions (not shown in Figure 17(a)) and isolation regions (not shown in Figure 17(a)), with an isolation region between each pair of active regions.

[0115] S162, Create solder pads.

[0116] As shown in Figure 17(b), a portion of pad 214 is located within device layer structure 2120, and another portion is located within wafer 2110. Pad 214 is situated in an isolation region outside the active region of device layer structure 2120. Specifically, during fabrication, blind vias can be etched from device layer structure 2120 using TSV technology, penetrating device layer structure 2120 and extending into wafer 2110. Next, a thin seed layer 2141 is deposited within the blind vias, and a conductive body structure 2142 is fabricated within the seed layer 2141 by electroplating or deposition. The surface of the conductive body structure 2142 is chemically and mechanically polished, retaining only the conductive body structure 2142 located within the blind vias. The material of seed layer 2141 is typically stainless steel, TiN, or Ti, while the material of conductive body structure 2142 typically includes Cu or Al.

[0117] S163, Create the wiring layer structure.

[0118] As shown in Figure 17(c), a wiring layer structure 2130 is fabricated on the side of the device layer structure 2120 facing away from the wafer 2110. The wiring layer structure includes a dielectric structure 2131 and a conductive structure 2132. The conductive structure 2132 is located within and exposed above the dielectric structure 2131. The dielectric structure 2131 can be made of a dielectric material, specifically PI or SiO2. The conductive structure 2132 can be made of Cu or Al. A passivation layer structure 2160 is fabricated on the wiring layer structure 2130.

[0119] S164, initial temporary bond.

[0120] As shown in Figure 17(d), a first release layer (not shown) is deposited on a first carrier substrate 201, and a wafer 2110, on which a device layer structure 2120, a wiring layer structure 2130, and a passivation layer 216 are fabricated, is bonded to the first release layer, with the passivation layer 216 facing the first release layer. The material of the first carrier substrate 201 can be Si or glass. The first release layer can be, for example, an adhesive layer.

[0121] S165, thinned wafer.

[0122] The wafer 2110 is thinned from the side away from the passivation layer 216, reducing the wafer 2110 from more than 700 μm to less than 200 μm, to obtain the structure shown in Figure 17(e).

[0123] S166, secondary temporary bonding.

[0124] As shown in Figure 17(f), a second release layer (not shown) is deposited on the second carrier 202, and the structure with the first carrier 201 is bonded to the second release layer, and the wafer 2110 is fixed to the second release layer. The second release layer can be, for example, an adhesive layer.

[0125] S167, Remove the first carrier board and the first release layer to obtain the chip structure.

[0126] The first carrier 201 and the first release layer shown in Figure 17(f) can be removed by means of laser debonding, thermal debonding or mechanical debonding to obtain the chip structure shown in Figure 18(a).

[0127] When the thermal conductive layer 215 shown in Figure 12a is a flat plate structure without microchannels, the thermal conductive layer structure 2150 can then be fabricated on the side of the wiring layer structure 2130 away from the wafer 2110.

[0128] S168, chip structure cutting.

[0129] As shown in Figure 18(b), the chip structure is cut along the location of the pad 214. Specifically, laser cutting, rotary cutting, or etching can be used to cut the chip structure to obtain multiple chips 21, which are then fixed onto the second carrier board 202. Next, the second carrier board 202 and the second release layer are removed to obtain multiple independent chips. Finally, each chip is polished and cleaned.

[0130] S169, multiple chips are flipped sequentially and the side pads are fixed to the third carrier board, and the first molding compound is fabricated.

[0131] As shown in Figure 18(c), an adhesive layer is applied to the third substrate 203, and a 90° flip chip bonding tool is used for chip-to-wafer (C2W) processing to fix the chip 21 onto the third substrate 203 with a spacing of <30µm. The adhesive layer can be an organic adhesive with a certain degree of stickiness, and the third substrate 203 can be made of materials such as Si or glass.

[0132] For each chip 21 that is fixed, an adhesive layer is provided on one side of the chip 21, so that every two adjacent chips 21 are also fixed together by the adhesive layer.

[0133] A first molding compound 81 is obtained by filling the gaps between the Z-direction upright and X-direction aligned chips 21 on the adhesive layer with a dam, filler, or other adhesive. The material of the first molding compound 81 may include resin, PI, silicon oxide, etc. The first molding compound 81 encapsulates a portion of the multiple chips. This increases the stability of the connection between the multiple chips 21.

[0134] In other embodiments, if the thermal conductive layer 215 in the chip 21 has a first microchannel 2151, the thermal conductive layer can be pre-fabricated. During the process of fixing the chip 21 to the third carrier 203, one or at least two of the multiple chips 21 can be flipped sequentially and the side pads 214 can be fixed to the third carrier 203; the thermal conductive layer can be fixed to the third carrier 203, and the thermal conductive layer can be fixed to the front or back of one or at least two of the first chips 21; one or at least two of the multiple chips 21 can be flipped sequentially and the side pads 214 can be fixed to the third carrier 203, and so on. That is, the chip 21 and the thermal conductive layer are fixed to the third carrier 203 sequentially.

[0135] S1610, remove the third carrier board.

[0136] The third carrier plate 203 and the adhesive layer 2031 can be removed by means of laser debonding, thermal debonding or mechanical debonding to obtain the structure shown in Figure 18(d).

[0137] S1611, fabricating device layers on a wafer.

[0138] As shown in Figure 19(a), TSV311 can be fabricated on the front side of wafer 210 first, and then device layer 32 can be fabricated using photolithography, electroplating, chemical mechanical polishing and other techniques.

[0139] S1612, fabricate the first solder structure on the device layer.

[0140] The first welding structure 33, as shown in Figure 19(b), can be fabricated on the device layer 32 by means of photolithography, electroplating or etching.

[0141] S1613, fabricate the first buffer layer and attach it to the fourth carrier plate.

[0142] As shown in Figure 19(c), a first buffer layer 2041 can be fabricated on the device layer 32, and the first buffer layer 2041 wraps around the first solder structure 33. Next, the fourth carrier board 204 is attached to the first buffer layer 2041. This avoids direct contact between the first solder structure 33 and the fourth carrier board 204, preventing damage to the solder balls in the first solder structure 33.

[0143] S1614, fabricate the wiring layer and the second solder structure.

[0144] As shown in Figure 19(d), wafer 310 is thinned from the side (back side) away from device layer 32, and wiring layer 34 and second bonding structure 35 are sequentially fabricated on the back side of wafer 310. The second bonding structure 35 can be electrically connected to the first bonding structure 33 sequentially through wiring layer 34, TSV 311 and device layer 32.

[0145] S1615, fabricate the second buffer layer and attach it to the fifth carrier plate.

[0146] As shown in Figure 19(e), a second buffer layer 2051 can be fabricated on the wiring layer 34, and the second buffer layer 2051 wraps around the second solder structure 35. Next, the fifth carrier board 205 is attached to the second buffer layer 2051. This prevents the second solder structure 35 from directly contacting the fifth carrier board 205, thus avoiding damage to the solder balls in the second solder structure 35.

[0147] S1616, Remove the fourth carrier plate and the first buffer layer.

[0148] The fourth carrier plate 204 and the first buffer layer 2041 shown in Figure 19(e) can be removed by means of laser debonding, thermal debonding or mechanical debonding to obtain the structure shown in Figure 19(f).

[0149] S1617 bonds the stacked structure to the functional chip.

[0150] As shown in Figure 20(a), the pads 214 of each chip 21 in the stacked structure 20 can be soldered to the first soldering structure 33 of the functional chip 30.

[0151] S1618, Create the second molding layer.

[0152] As shown in Figure 20(b), the gap between chip 21 and functional chip 30 can be filled with materials such as resin, PI, and silicon oxide to obtain a second molding compound 82 that encapsulates the first welding structure 33. This avoids oxidation or corrosion of the solder balls in the bottom first welding structure 33 and enhances the mechanical strength of the package structure 100.

[0153] S1619, remove the fifth carrier plate and the second buffer layer.

[0154] The fifth carrier 205 and the second buffer layer 2051 shown in Figure 20(b) can be removed by means of laser debonding, thermal debonding, or mechanical debonding to obtain the structure shown in Figure 20(c). In this structure, the second welding structure 35 is exposed, which facilitates electrical connection with the circuit board.

[0155] In other embodiments of this application, a method for manufacturing a stacked encapsulation structure 100 is also provided, which can be applied to the encapsulation structure 100 shown in FIG. 9. As shown in FIG. 21, the manufacturing method includes:

[0156] S211, fabricating device layer structures on a wafer.

[0157] Refer to step S161 shown in Figure 16.

[0158] S212, for creating solder pads.

[0159] Refer to step S162 shown in Figure 16.

[0160] S213, Create the wiring layer structure.

[0161] Refer to step S163 shown in Figure 16.

[0162] S214, initial temporary bond.

[0163] Refer to step S164 shown in Figure 16.

[0164] S215, thinned wafer.

[0165] Refer to step S165 shown in Figure 16.

[0166] S216, secondary temporary bonding.

[0167] As shown in Figure 22(a), the wafer 2110 is flipped onto the underside of the second carrier 202 to obtain a wafer structure, wherein the second carrier 202 is located on the side of the wafer 2110 away from the device layer structure 2120.

[0168] S217 involves stacking multiple wafer structures sequentially.

[0169] For the bottommost wafer structure 21a, the second carrier 202 on wafer structure 21a can be removed to obtain the structure shown in Figure 22(b). For the remaining wafer structures 21b, the first carrier 201 and the first release layer on wafer structure 21b can be removed to obtain the structure shown in Figure 22(c). As shown in Figure 22(d), the wafer structure 21b with the first carrier 201 and the first release layer removed is stacked on the back side of wafer structure 21a. After each layer of wafer structure 21b is stacked, the second carrier 202 on wafer structure 21b can be removed. This process is repeated until the stacking process of all wafer structures 21a and wafer structures 20b is completed to obtain the structure shown in Figure 22(e).

[0170] S218, bonding the multilayer wafer structure to the sixth substrate and removing the first substrate.

[0171] As shown in Figure 23(a), the multilayer stacked wafer structures 21a and 21b are bonded to the sixth carrier 206 on the side away from the device layer structure 2120, and the first carrier 201 shown in Figure 22(e) is removed.

[0172] S219, cutting.

[0173] As shown in Figure 23(b), cutting is performed along the location of pad 214. Specifically, laser cutting, blade cutting, or etching can be used to cut, resulting in multiple stacked structures 20, which are then fixed to the sixth carrier board 206.

[0174] S210, remove the sixth carrier board.

[0175] The sixth carrier plate 206 is removed to obtain the stacked structure 20 shown in Figure 23(c). Finally, the stacked structure 20 is polished and cleaned.

[0176] S2111, fabricating device layers on a wafer.

[0177] Refer to step S1611 shown in Figure 16.

[0178] S2112, fabricate the first solder structure on the device layer.

[0179] Refer to step S1612 shown in Figure 16.

[0180] S2113, fabricate the first buffer layer and attach it to the fourth carrier plate.

[0181] Refer to step S1613 shown in Figure 16.

[0182] S2114, fabricate the wiring layer and the second soldering structure.

[0183] Refer to step S1614 shown in Figure 16.

[0184] S2115, fabricate the second buffer layer and attach it to the fifth carrier plate.

[0185] Refer to step S1615 shown in Figure 16.

[0186] S2116, Remove the fourth carrier plate and the first buffer layer.

[0187] Refer to step S1616 shown in Figure 16.

[0188] S2117 flips the stacked structure and bonds the sides to the functional chip.

[0189] A 90° flip chip bonding tool can be used for chip to wafer (C2W) operations, which flips the stacked structure 20 by 90° and fixes the sides to the functional chip.

[0190] S1618, Create the second molding layer.

[0191] Refer to step S1618 shown in Figure 16.

[0192] S1619, remove the fifth carrier plate and the second buffer layer.

[0193] Refer to step S1619 shown in Figure 16.

[0194] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

A chip characterized in that, include: Substrate; A device layer, wherein the device layer is disposed on one side of the substrate; A wiring layer is disposed on the side of the device layer opposite to the substrate, and the wiring layer includes a conductive structure; The pads are electrically connected to the conductive structure and are exposed from the side of the chip. The chip according to claim 1, characterized in that, The device layer has a first hole on its surface facing the wiring layer and on its side connected to the surface, and at least a portion of the pad is located within the first hole. The chip according to claim 2 is characterized in that, The first hole is a through hole, and a second hole is provided on the side of the substrate facing inward. The second hole communicates with the through hole, and part of the pad is located inside the second hole. The chip according to any one of claims 1-3 is characterized in that, The pad includes a conductive body structure and a seed layer that at least surrounds the sidewalls of the conductive body structure. The chip according to any one of claims 1-3 is characterized in that, The chip further includes a thermally conductive layer, which is disposed on the side of the wiring layer away from the substrate, or the thermally conductive layer is disposed on the side of the substrate away from the device layer. The chip according to claim 5 is characterized in that, The chip also includes a passivation layer located between the thermal conductive layer and the wiring layer. The chip according to claim 5 or 6 is characterized in that, The thermally conductive layer includes a first heat sink. The chip according to claim 7 is characterized in that, The first heat sink has a first microchannel inside. The chip according to claim 8 is characterized in that, The first microchannel is a closed structure, and a medium is provided inside the first microchannel; Alternatively, the first radiator has an inlet and an outlet, both of which are connected to the first microchannel. A stacked structure, characterized in that, The invention includes a plurality of chips as described in any one of claims 1-9, wherein the plurality of chips are stacked sequentially along the thickness direction, and the pads of each chip are located on the same side. The stacking structure according to claim 10 is characterized in that, The stacked structure also includes a second heat sink, which is located on one side of the plurality of chips along the thickness direction. The second heat sink has a second microchannel, and the inlet and outlet of the chips are connected to the second microchannel. The stacking structure according to claim 11 is characterized in that, The stacked structure also includes a third heat sink with a third microchannel, the third heat sink being disposed on multiple layers of the chip, and the third microchannel passing through each of the chip. The stacking structure according to claim 12 is characterized in that, The third microchannel contains a medium and is a closed structure; or, the third microchannel is connected to the second microchannel. The stacking structure according to any one of claims 11-13 is characterized in that, The stacked structure also includes a first molding compound layer that wraps around a portion of the plurality of chips from one side where the pads of the plurality of chips are located. The stacking structure according to any one of claims 11-14 is characterized in that, The stacked structure also includes multiple thermal conductive layers, with at least two adjacent chips having a thermal conductive layer between them, and at least two adjacent chips not having a thermal conductive layer between them. A packaging structure, characterized in that, It includes a carrier structure and a stacking structure as described in any one of claims 10-15, wherein the stacking structure is disposed on the carrier structure and the pads of each chip in the stacking structure face the carrier structure. The packaging structure according to claim 16 is characterized in that, The supporting structure includes at least one of a substrate, an adapter board, and a functional chip. The packaging structure according to claim 16 or 17 is characterized in that, The supporting structure includes a body and a welded structure, wherein the welded structure is located between the body and the stacked structure; The encapsulation structure further includes a second molding layer, which is located between the stacked structure and the body and wraps the welding structure. The second molding layer is connected to the first molding layer of the stacked structure. A circuit board assembly, characterized in that, Includes a circuit board and the stacking structure according to any one of claims 10-15, wherein the stacking structure is disposed on the circuit board; Alternatively, the circuit board assembly includes a circuit board and a packaging structure as described in any one of claims 16-18, the packaging structure being disposed on the circuit board. An electronic device, characterized in that, It includes a housing and the circuit board assembly of claim 19, the circuit board assembly being disposed within the housing. A method for manufacturing a chip, characterized in that, The manufacturing method includes: Fabricating device layer structures on wafers; Fabricate pads, at least a portion of which are located within the wafer; A wiring layer structure is fabricated on the device layer structure to obtain a chip structure; The chip structure is cut along the location of the pads to obtain multiple chips, each chip including pads located on the side of the chip. The manufacturing method according to claim 21 is characterized in that, After fabricating the wiring layer structure on the device layer structure, the fabrication method further includes: A thermally conductive layer structure is fabricated on the side of the wiring layer structure opposite to the wafer. A method for fabricating a stacked structure, characterized in that, The manufacturing method includes: Multiple chips are flipped sequentially and the side pads are fixed to a third carrier board. The chips are manufactured using the chip manufacturing method described in claim 21 or 22, and the multiple chips are stacked sequentially along the thickness direction of the chips. Remove the third carrier plate to obtain the stacked structure. The manufacturing method according to claim 23 is characterized in that, After the step of sequentially flipping multiple chips and fixing the side pads to the third carrier board, the fabrication method further includes: A first molding compound is formed on the third substrate, the first molding compound covering a portion of the plurality of chips. The manufacturing method according to claim 23 or 24 is characterized in that, The step of sequentially flipping multiple chips and fixing the side pads to the third carrier board includes: One or at least two of the plurality of chips are flipped in sequence and the side pads are fixed to the third carrier board; The first heat sink is fixed to the third carrier board, and the first heat sink is fixed to the front or back of the one or at least two first chips; One or at least two of the plurality of chips are flipped in sequence and the side pads are fixed to the third carrier board. A method for fabricating a stacked structure, characterized in that, The manufacturing method includes: Multiple wafer structures are fabricated, each wafer structure comprising sequentially stacked wafers, device layer structures, and wiring layer structures, and each wafer structure further comprising pads, at least a portion of which is located within the wafers; The multiple wafer structures are stacked sequentially to obtain an initial stacked structure; The initial stack structure is cut along the location of the pads to obtain the stack structure. A method for fabricating an encapsulation structure, characterized in that, The manufacturing method includes: The stacked structure is flipped over and the side pads are fixed to the support structure. The stacked structure is obtained by the method of manufacturing the stacked structure according to claim 25. The support structure includes a body and a welding structure, and the welding structure is located between the body and the stacked structure. A second molding layer is fabricated, which is located between the stacked structure and the body and encapsulates the welded structure.

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