Interposer structure and manufacturing method therefor, chip packaging structure, and electronic device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-08-18
- Publication Date
- 2026-08-13
Smart Images
Figure CN2025115340_13082026_PF_FP_ABST
Abstract
Description
Adapter structure and its manufacturing method, chip packaging structure, electronic equipment Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to an adapter structure and its manufacturing method, a chip packaging structure, and an electronic device. Background Technology
[0002] Interposer technology is an intermediate layer technology used to connect chips, playing a crucial role in advanced packaging technologies, especially in 2.5D and 3D chip packaging. Interposers are primarily used to connect multiple chips to the underlying substrate, achieving higher I / O (input / output) density, lower transmission latency, and lower power consumption.
[0003] Current interposers are mainly divided into passive interposers and active interposers. Passive interposers contain only a few redistribution layers (RDLs) for interconnection and passive components such as capacitors. Active interposers contain active components such as field-effect transistors (FETs), which not only connect chips but also have certain functions, and are mostly used in some high-end products.
[0004] Referring to Figure 1, in a current 2.5D packaging structure, the SOC (System-on-Chip) and HMB (High-Bandwidth Memory) are connected via an active adapter board 1. The active adapter board 1 houses SRAM (Static Random-Access Memory) to meet storage requirements. However, with continuous technological advancements, chip performance demands are increasing, while the area of the active adapter board 1 is limited. This leads to limitations in the interconnect bandwidth and speed between the memory devices (HBM, SRAM) and the SOC, as well as limitations in the area and capacity of the SRAM, resulting in the current product structure being unable to meet these requirements. Summary of the Invention
[0005] This application provides an adapter structure and its manufacturing method, a chip packaging structure, and an electronic device, which can solve various problems caused by the limited area of existing adapter boards.
[0006] This application provides an interposer structure including a first interposer and a second interposer. The first interposer includes a first substrate and a first wiring structure disposed on the front side of the first substrate. A first through-silicon via (TSV) is disposed in the first substrate and connected to the first wiring structure. The second interposer includes a second substrate and a second wiring structure disposed on the front side of the second substrate. A second TSV is disposed in the second substrate and connected to the second wiring structure. The back sides of the first substrate and the back sides of the second substrate are connected via a bonding surface, and the first TSV and the second TSV are connected at the bonding surface.
[0007] In the aforementioned adapter structure, two adapter boards (a first adapter board and a second adapter board) are bonded back-to-back to form a new adapter structure. The use of two adapter boards increases the area capacity, and wiring layers can be fabricated on both adapter boards, thereby increasing the number of wiring layers and ultimately improving interconnect bandwidth and speed. The two adapter boards can be active or passive. Active adapter boards, through internally placed active devices (such as field-effect transistors) and multiple wiring layers, can improve bandwidth and speed. Passive adapter boards increase area capacity and can additionally incorporate passive devices, such as capacitors, thereby improving the electrical performance of the device.
[0008] In some possible implementations, the first routing structure includes active devices. In this case, the first adapter board is an active adapter board, which, through the internally arranged active devices (such as field-effect transistors) and multiple wiring layers, can further improve interconnect bandwidth and speed.
[0009] In some possible implementations, the second wiring structure includes active devices. In this case, the second adapter board is an active adapter board, which, through the internally arranged active devices (such as field-effect transistors) and multiple wiring layers, can further improve interconnect bandwidth and speed.
[0010] In some possible implementations, the first adapter board has multiple active regions, and the area of each active region is less than or equal to 1R; where R is a photomask area. Two adjacent active regions in the first adapter board are connected through a second adapter board. That is, multiple active regions in the first adapter board can be connected through the second adapter board, thereby overcoming the 1R limitation and making the total area of the active regions greater than 1R.
[0011] In some possible implementations, the second adapter board has multiple active regions, and the area of each active region is less than or equal to 1R; where R is the area of a photomask; two adjacent active regions in the second adapter board are connected through the first adapter board. That is, multiple active regions in the second adapter board can be connected through the first adapter board, thereby overcoming the 1R limitation and making the total area of the active regions greater than 1R.
[0012] In some possible implementations, the first adapter board includes a first active area, a second active area, and a third active area; the second active area is located between the first and third active areas, and its area is 1R, while the areas of the first and third active areas are both 0.5R. The second adapter board includes a fourth and a fifth active area; both the fourth and fifth active areas have an area of 1R; the fourth active area overlaps with both the first and second active areas, and the first active area is connected to the second active area through the fourth active area; the fifth active area overlaps with both the second and third active areas, and the third active area is connected to the second active area through the fifth active area; the fourth active area is connected to the fifth active area through the second active area. In this configuration, interaction between the multiple active areas within the two adapter boards is possible.
[0013] In some possible implementations, the first adapter board includes a sixth and a seventh active area; both the sixth and seventh active areas have an area of 1R. The second adapter board includes an eighth, a ninth, and a tenth active area. The ninth active area is located between the eighth and tenth active areas, and its area is 1R. The areas of the eighth and tenth active areas are both 0.5R. The sixth active area overlaps with both the eighth and ninth active areas, and the eighth active area is connected to the ninth active area through the sixth. The seventh active area overlaps with both the ninth and tenth active areas, and the ninth active area is connected to the tenth active area through the seventh. The sixth active area is connected to the seventh active area through the ninth. In this configuration, interaction between the multiple active areas within the two adapter boards is possible.
[0014] In some possible implementations, the first routing structure includes static random access memory (SRAM). That is, by incorporating SRAM in the first adapter board, the area capacity of the SRAM can be increased, thereby improving bandwidth and speed.
[0015] In some possible implementations, the second wiring structure includes at least one of a serializer / deserializer (SERDES) and a power management module. The power management module can be an integrated voltage regulator (IVR), a low dropout regulator (LDO), or the like.
[0016] In some possible implementations, both the first and second trace structures include capacitor components. By incorporating capacitor components in both the first and second adapter boards, the number of capacitor components can be increased, thereby improving the performance of the package structure, such as reducing noise and enhancing signal integrity. The capacitor components can be one or more of the following: deep trench capacitor (DTC), metal-insulator-metal capacitor (MIM cap), etc.
[0017] In some possible implementations, the back sides of the first substrate and the back sides of the second substrate are connected by a hybrid bonding method. In this case, the bonding surfaces can employ a combination of dielectric-dielectric bonding and direct metal-to-metal bonding (such as direct copper-to-copper bonding), without the need for additional adhesives or materials, thereby enabling high-density interconnection to meet the interconnection requirements between the first and second adapter boards.
[0018] In some possible implementations, a first groove is provided on the back side of the first substrate, and a second groove is provided on the back side of the second substrate; the first groove and the second groove are joined at the bonding surface to form a microchannel. Coolant is transported within the microchannel to achieve heat dissipation, thereby improving heat dissipation efficiency.
[0019] This application also provides a method for fabricating an adapter structure, which may include: providing a first adapter plate; wherein the first adapter plate includes a first substrate and a first wiring structure formed on the front side of the first substrate, and a first through-silicon via (TSV) connected to the first wiring structure is formed in the first substrate. Providing a second adapter plate; wherein the second adapter plate includes a second substrate and a second wiring structure formed on the front side of the second substrate, and a second TSV connected to the second wiring structure is formed in the second substrate. Bonding the first adapter plate and the second adapter plate through the back side of the first substrate and the back side of the second substrate, wherein the first TSV and the second TSV are connected at the bonding surface.
[0020] Using this fabrication method, the first and second adapter boards are bonded together through the back sides of the first and second substrates to form a novel adapter structure. The area capacity can be increased by using two adapter boards. Furthermore, wiring layers can be fabricated on both adapter boards, thereby increasing the number of wiring layers and thus improving interconnect bandwidth and speed.
[0021] In some possible implementations, the bonding of the first and second adapter plates via the back sides of the first and second substrates can include: employing a hybrid bonding process to bond the first and second adapter plates via the back sides of the first and second substrates. In this bonding process, the bonding surfaces can employ a combination of dielectric-dielectric bonding and direct metal-to-metal bonding (such as direct copper-to-copper bonding), eliminating the need for additional adhesives or materials, thereby achieving high-density interconnection to meet the interconnection requirements between the first and second adapter plates.
[0022] In some possible implementations, the aforementioned provision of the first adapter board may include: providing a first substrate, forming a first wiring structure including active devices on the front side of the first substrate, and forming a first through-silicon via (TSV) in the first substrate that connects to the first wiring structure. In this case, the interconnect bandwidth and speed can be further improved.
[0023] In some possible implementations, the provision of the second adapter board described above may include: providing a second substrate, forming a second wiring structure including active devices on the front side of the second substrate, and forming a second through-silicon via (TSV) in the second substrate that connects to the second wiring structure. In this case, the interconnect bandwidth and speed can be further improved.
[0024] This application also provides a chip packaging structure, which includes at least one chip and an adapter structure as provided in any of the aforementioned possible implementations; the chip is disposed on one side of a first adapter board and connected to the first adapter board.
[0025] In some possible implementations, the aforementioned chip may include a system-on-chip (SOC) and double data rate synchronous dynamic random access memory (DDR). The SOC includes an internal adapter board and multiple logic chips disposed on the internal adapter board, the multiple logic chips being connected to the internal adapter board; the internal adapter board contains SRAM.
[0026] In some possible implementations, the chip package structure also includes a substrate, input / output chips, and memory chips. The adapter structure, input / output chips, and memory chips are located on the same side of the substrate and connected to it; the adapter structure is connected to the substrate via a second adapter plate. Independently mounting the memory chip on the substrate can reduce the latency between the memory chip and other chips; independently mounting the input / output chips on the substrate can increase the bandwidth of the input / output chips.
[0027] In some possible implementations, the chip package structure also includes at least one electronic device disposed on one side of the second adapter board and connected to the second adapter board. In this case, the package structure serves as a package system, and the adapter structure can meet the double-sided device setup requirements of the package system. Furthermore, this adapter structure can overcome the 1R limitation, allowing for the selection of a larger adapter structure according to the needs of the package system, thus better accommodating the setup of multiple systems.
[0028] In some possible implementations, the chip package structure also includes a redistribution layer disposed on the side of the second adapter board facing the electronic device, through which the electronic device connects to the second adapter board. This simplifies the connection between the electronic device and the second adapter board, reduces connection difficulty, and simplifies the manufacturing process.
[0029] This application also provides an electronic device that includes a circuit board and a chip package structure as provided in any of the aforementioned possible implementations, wherein the chip package structure is electrically connected to the circuit board. Attached Figure Description
[0030] Figure 1 is a schematic diagram of a chip packaging structure provided in the prior art;
[0031] Figure 2 is a schematic diagram of a partial structure in an electronic device provided in an embodiment of this application;
[0032] Figure 3 is a schematic diagram of a transition structure provided in an embodiment of this application;
[0033] Figure 4 is a schematic diagram of the distribution of the active region in a transition structure provided in an embodiment of this application;
[0034] Figure 5 is a schematic diagram of the distribution of the active region in a transition structure provided in an embodiment of this application;
[0035] Figure 6 is a schematic diagram of the distribution of the active region in a transition structure provided in an embodiment of this application;
[0036] Figure 7 is a schematic diagram of a transition structure provided in an embodiment of this application;
[0037] Figure 8 is a schematic diagram of the microchannel structure in a transition structure provided in an embodiment of this application;
[0038] Figure 9 is a flowchart of a method for manufacturing a transition structure provided in an embodiment of this application;
[0039] Figure 10 is a schematic diagram of the manufacturing process of a transition structure provided in the embodiment of this application;
[0040] Figure 11 is a schematic diagram of the manufacturing process of a transition structure provided in the embodiment of this application;
[0041] Figure 12 is a schematic diagram of the manufacturing process of a transition structure provided in the embodiment of this application;
[0042] Figure 13 is a schematic diagram of a chip packaging structure provided in an embodiment of this application;
[0043] Figure 14 is a schematic diagram of a chip packaging structure provided in an embodiment of this application;
[0044] Figure 15 is a planar schematic diagram of a chip packaging structure provided in an embodiment of this application;
[0045] Figure 16 is a schematic diagram of a chip packaging structure provided in an embodiment of this application. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0047] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, they can refer to electrical connections or mechanical connections; fixed connections or detachable connections or integral connections; direct connections or indirect connections through an intermediate medium; or internal communication between two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as “up,” “down,” “left,” and “right” are used only in relation to the orientation of the components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly depending on the orientation of the components in the accompanying drawings.
[0048] First, let me explain some of the technical terms used in this application.
[0049] A printed circuit board (PCB) is a base plate that connects electronic components together via wires and connectors, providing electrical connections and support. Widely used in electronic products, PCBs offer stable electrical connections, enabling electronic components to operate reliably and communicate with other components. Furthermore, PCBs provide mechanical support and protection for electronic components, making them easier to install and maintain. A PCB consists of a non-conductive substrate (usually made of insulating material) and conductive layers covering its surface. The conductive layers are typically made of copper foil, with circuit patterns formed through chemical etching or mechanical processing. These patterns define the connections and layout between electronic components.
[0050] An interposer (also known as a dielectric layer) is an intermediate dielectric layer added between a chip and a PCB in integrated circuit packaging technology. This dielectric layer is used to connect chips and is commonly used in distributed systems. It facilitates information exchange between upper-layer or lower-layer nodes (such as connecting two chips). Interposers can electrically interconnect with chips and the substrate, enabling information exchange between them. Interposers allow for short-distance, high-density interconnections between chips, improving chip performance and bandwidth, and making chips more compact.
[0051] An adapter board includes a substrate (such as a silicon wafer) and wiring structures on the substrate. Adapter boards typically have through-holes, such as through-silicon vias (TSVs), used to transmit data between different chips to the connected circuit board. Therefore, an adapter board acts as a bridge connecting multiple chips to the same circuit board, enabling smaller, more power-efficient, and higher bandwidth systems.
[0052] Interposers can be classified into passive interposers and active interposers based on whether their routing structure contains active components (such as field-effect transistors). An interposer is an active interposer if its routing structure includes active components; it is a passive interposer if its routing structure does not contain active components, but only routing layers and passive components (such as capacitors and resistors).
[0053] This application provides an electronic device with a chip packaging structure. The chip packaging structure employs a novel interposer structure (interposer board). This interposer structure is formed by bonding two interposers back to back, which increases the interposer area and solves various problems caused by the limited area of the interposer board in the prior art. This, in turn, can improve interconnect bandwidth and speed.
[0054] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product equipped with a storage device, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc.
[0055] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.
[0056] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip packaging structure, such as circuit boards, controllers, input / output devices, etc. This application does not impose any restrictions on this, and it can be set as needed in practice.
[0057] As illustrated in Figure 2, this application embodiment provides an electronic device that may include a PCB and a chip package structure 01 disposed on the PCB, with the chip package structure 01 connected to the PCB. The chip package structure 01 employs a novel adapter structure 10, which is formed by bonding two adapter boards (101 and 102) back-to-back, thereby increasing the area capacity and meeting the device's requirements for high bandwidth and high speed.
[0058] Referring to Figure 2, the chip package structure 01 described above may also include a substrate Sub and multiple chips D disposed on the adapter structure 10. The multiple chips D are connected to the substrate Sub via the adapter structure 10, and the substrate Sub is used to connect to the PCB. Of course, in some chip package structures 01, the substrate Sub may not be provided; it can be included as needed in practice, and this application does not impose any restrictions on this. For the application of the adapter structure 10 in the chip package structure 01, please refer to the relevant description below.
[0059] This application does not restrict the types of multiple chips D set on the adapter board 10; in practice, they can be set as needed.
[0060] As illustrated, the multiple chips that can be configured in the adapter structure 10 may include one or more of the following chips: system on chip (SOC), multiple double data rate synchronous dynamic random access memory (DDR), high bandwidth memory (HMB), central processing unit (CPU), graphics processing unit (GPU), etc., but are not limited to these.
[0061] The following provides a further description of the specific structure of the novel adapter structure 10 provided in the embodiments of this application.
[0062] Schematic, referring to Figure 3, this application embodiment provides an interposer structure 10, which includes a first interposer plate 101 and a second interposer plate 102. The first interposer plate 101 includes a first substrate Sub1 and a first wiring structure A1 disposed on the front side of the first substrate Sub1. The first substrate Sub1 has a plurality of first through silicon vias (TSVs1) connected to the first wiring structure A1. The second interposer plate 102 includes a second substrate Sub2 and a second wiring structure A2 disposed on the front side of the second substrate Sub2. The second substrate Sub2 has a plurality of second through silicon vias (TSVs2) connected to the second wiring structure A2.
[0063] Referring again to Figure 3, the back side of the first substrate Sub1 is bonded to the back side of the second substrate Sub2, and multiple first through-silicon vias TSV1 and multiple second through-silicon vias TSV2 are connected at the bonding surface M, thereby forming multiple data channels between the first adapter plate 101 and the second adapter plate 102 to meet the interaction between the first adapter plate 101 and the second adapter plate 102.
[0064] This application does not impose any restrictions on the bonding method between the back side of the first substrate Sub1 and the back side of the second substrate Sub2; in practice, it can be set as needed.
[0065] Schematic, in some possible implementations, the back side of the first substrate Sub1 and the back side of the second substrate Sub2 can be connected using a hybrid bonding method. In this case, the bonding surface M can employ a combination of dielectric-dielectric bonding and direct copper-to-copper bonding, eliminating the need for additional adhesives or materials, thereby achieving high-density interconnection to meet the interconnection requirements between the first adapter plate 101 and the second adapter plate 102.
[0066] Furthermore, this application does not impose any restrictions on the connection method between the first through-silicon via (TSV1) and the second through-silicon via (TSV2) at the bonding surface M.
[0067] For example, in some possible implementations, the back side of the first substrate Sub1 may be provided with a first bonding pad (PAD) connected to the first through-silicon via (TSV1), and the back side of the second substrate Sub2 may be provided with a second bonding pad (PAD) connected to the second through-silicon via (TSV2). The first bonding pad and the second bonding pad are connected at the bonding surface M. Both the first bonding pad (PAD) and the second bonding pad (PAD) may be copper bonding pads (Cu PAD).
[0068] For example, in some possible implementations, the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be nano-through silicon vias (nTSVs). In this case, the first through-silicon via (TSV1) and the second through-silicon via (TSV2) can be directly bonded together at the bonding surface M without the need for a bonding pad.
[0069] It should be noted that the first interposer 101 mentioned above can be an active interposer or a passive interposer; similarly, the second interposer 102 can be an active interposer or a passive interposer. This application does not impose any restrictions on this, and it can be configured as needed in practice.
[0070] As explained above, passive adapter boards do not contain active components, only multiple routing layers (such as layers 3 and 4) and passive components (such as capacitors and resistors); while active adapter boards contain active components, more routing layers (such as layers 10), and can also contain passive components as needed. Because active adapter boards contain active components and have more routing layers, they can meet higher bandwidth and speed requirements compared to passive adapter boards.
[0071] Schematic, referring to Figure 3, when the first interposer 101 is an active interposer, the first wiring structure A1 may include active devices such as field-effect transistors t1, as well as passive devices such as multiple wiring layers (or redistribution layers) and capacitor structures. When the first interposer 101 is a passive interposer, the first wiring structure A1 does not contain active devices, but only passive devices such as multiple redistribution layers and capacitor structures.
[0072] Schematic, referring to Figure 3, when the second interposer 102 is an active interposer, the second wiring structure A2 may include active devices such as a field-effect transistor t2, as well as passive devices such as multiple wiring layers and capacitor structures. When the second interposer 102 is a passive interposer, the second wiring structure A2 does not contain active devices, but only passive devices such as multiple redistribution layers (RDLs) and capacitor structures.
[0073] The following description, based on the configuration types of the first adapter plate 101 and the second adapter plate 102, explains the configuration of the adapter structure 10.
[0074] For example, in some possible implementations, both the first adapter board 101 and the second adapter board 102 in the adapter structure 10 can be passive adapter boards, and both the first adapter board 101 (or the first wiring structure A1) and the second adapter board 102 (or the second wiring structure A1) can be provided with capacitors. In this case, on the one hand, by increasing the area of the first adapter board 101 and the second adapter board 102, the number of wiring layers can be increased, thereby improving bandwidth and speed. On the other hand, by providing capacitors in the first adapter board 101 and the second adapter board 102, the number of capacitors can be increased, thereby improving the performance of the package structure, such as reducing noise and improving signal integrity.
[0075] It should be noted that this application does not limit the form of the capacitors provided in the first adapter plate 101 and the second adapter plate 102; in practice, they can be set as needed.
[0076] Indicatively, in some possible implementations, the capacitors disposed in the first adapter plate 101 and the second adapter plate 102 may be one or more of the following capacitors: deep trench capacitor (DTC), metal-insulator-metal capacitor (MIM cap).
[0077] For example, referring to Figure 3, both the first interposer 101 and the second interposer 102 in the interposer structure 10 can be active interposers. In this case, the first interposer 101 (or the first wiring structure A1) can include multiple field-effect transistors t1 (also called transistors) and multiple wiring layers located above the multiple field-effect transistors t1 (i.e., away from the first substrate), thereby forming multiple circuit modules. The second interposer 102 (or the second wiring structure A2) can include multiple field-effect transistors t2 and multiple wiring layers located below the multiple field-effect transistors t2 (i.e., away from the second substrate), thereby forming multiple circuit modules.
[0078] This application does not impose any restrictions on the type, function, or quantity of circuit modules formed on the first adapter board 101 and the second adapter board 102; in practice, they can be set as needed.
[0079] As illustrated, in some possible implementations, the circuit modules formed on the first adapter board 101 may include static random access memory (SRAM), physical layer interface circuitry (PHY), etc. The circuit modules formed on the second adapter board 102 may include serializers / deserializers (SERDES), power management modules, etc. The power management module may be an integrated voltage regulator (IVR), a low dropout regulator (LDO), etc.
[0080] By placing SRAM on the first adapter board 101, the area capacity of the SRAM in the package structure can be increased. Externally connected circuit modules such as serializers / deserializers (SERDES) and power management modules are placed on the second adapter board 102. Compared to placing these circuit modules on the front side (i.e., the side facing the chip), placing them on the back side of the second adapter board 102 reduces insertion loss of data signals due to passing through silicon vias (TSV1, TSV2).
[0081] Furthermore, when both the first adapter board 101 and the second adapter board 102 are active adapter boards, both adapter boards are equipped with active devices and a large number of redistribution layers, which can further improve the data interconnect bandwidth and speed.
[0082] For example, in some other possible implementations, the first adapter board 101 and the second adapter board 102 in the adapter structure 10 can be an active adapter board and a passive adapter board, respectively. For instance, the first adapter board 101 can be an active adapter board and the second adapter board 102 can be a passive adapter board; or, the first adapter board 101 can be a passive adapter board and the second adapter board 102 can be an active adapter board.
[0083] In addition, it should be noted that due to the limitations of existing process conditions, the maximum area of the active region in existing active adapter boards does not exceed one photomask size R (retical), that is, the area of the active region is less than or equal to 1R, which greatly limits its application.
[0084] In contrast, the active adapter structure 10 provided in this application (i.e., at least one of the first adapter board 101 and the second adapter board 102 is an active adapter board) can, under existing process conditions, allow the overall area of the active region in the active adapter board to exceed the 1R limitation, such as 1.5R, 2R, 2.5R, 3R, etc. Illustrated, a photomask size 1R can be 33mm × 26mm, but is not limited to this.
[0085] The active region in the aforementioned adapter board refers to the area on the adapter board where active devices (such as field-effect transistors) are formed. An active region is formed using a single photomask process, so the area of an active region will not exceed the area R of a photomask.
[0086] As illustrated, in the adapter structure 10 provided in this application, when the first adapter board 101 is an active adapter board, the first adapter board 101 may include multiple active regions, and two adjacent active regions can be connected through the second adapter board 102. In this way, the multiple active regions in the first adapter board 101 can be formed using multiple photomask processes, thereby breaking through the 1R limitation and making the total area of the active regions in the first adapter board 101 greater than 1R.
[0087] Similarly, when the second adapter board 102 is an active adapter board, it can include multiple active regions, and two adjacent active regions can be connected through the first adapter board 101. In this way, the multiple active regions in the second adapter board 102 can be formed using multiple photomask processes, thereby breaking through the 1R limitation and making the total area of the active regions in the second adapter board 102 greater than 1R.
[0088] It should be understood that multiple active areas on an adapter board are fabricated using multiple photomask processes, and cut tracks (i.e. blank areas where no components or traces are installed) are left between adjacent active areas.
[0089] Taking the example that both the first adapter board 101 and the second adapter board 102 are active adapter boards, the specific settings of the active areas in the first adapter board 101 and the second adapter board 102 are illustrated.
[0090] For example, in some possible implementations, referring to Figure 4, the first adapter plate 101 includes a first active region a1, a second active region a2, and a third active region a3 arranged sequentially along the horizontal direction X. The first active region a1 and the third active region a3 are distributed on both sides of the second active region a2. The first active region a1 and the second active region a2 are adjacent to each other, and there is a blank cutting channel d between the first active region a1 and the second active region a2. The second active region a2 and the third active region a3 are adjacent to each other, and there is a blank cutting channel d between the second active region a2 and the third active region a3. The area of the second active region a2 is 1R, and the areas of the first active region a1 and the third active region a3 are both 0.5R. That is, the total area of the multiple active regions (a1, a2, a3) in the first adapter plate 101 is 2R. The second adapter plate 102 includes a fourth active region a4 and a fifth active region a5 arranged sequentially along the horizontal direction X. The fourth active region a4 and the fifth active region a5 are arranged adjacent to each other, with a blank cutting channel d between them. The area of the fourth active region a4 and the fifth active region a5 is 1R, that is, the total area of the multiple active regions (a4, a5) in the second adapter plate 102 is 2R.
[0091] Referring again to Figure 4, the areas of the multiple active regions in the first adapter plate 101 and the multiple active regions in the second adapter plate 102 are approximately the same (2R) and are arranged opposite to each other. That is, the projections of the first active region a1, the second active region a2, and the third active region a3 onto the substrate (Sub1, Sub2) overlap with the projections of the fourth active region a4 and the fifth active region a5 onto the substrate. Specifically, the projection of the fourth active region a4 onto the substrate overlaps with the projections of the first active region a1 and the left portion of the second active region a2 onto the substrate; thus, the first active region a1 and the second active region a2 can be connected through the fourth active region a4 to achieve interaction. The projection of the fifth active region a5 onto the substrate (Sub1, Sub2) overlaps with the projections of the third active region a3 and the right portion of the second active region a2 onto the substrate; thus, the third active region a3 and the second active region a2 can be connected through the fifth active region a5 to achieve interaction. Both the fourth active region a4 and the fifth active region a5 overlap with the second active region a2; thus, the fourth active region a4 and the fifth active region a5 can be connected through the second active region a2 to achieve interaction. In other words, in this transition structure 10, multiple active regions within the two transition boards (101 and 102) can interact with each other.
[0092] For example, in some other possible implementations, referring to Figure 5, the first adapter plate 101 includes a sixth active region a6 and a seventh active region a7 arranged sequentially along the horizontal direction X. The sixth active region a6 and the seventh active region a7 are arranged adjacent to each other, with a blank cutting channel d between them. The area of the sixth active region a6 and the seventh active region a7 is 1R, that is, the total area of the multiple active regions (a6, a7) in the first adapter plate 101 is 2R. The second adapter plate 102 includes an eighth active region a8, a ninth active region a9, and a tenth active region a10 arranged sequentially along the horizontal direction X. The eighth active region a8 and the tenth active region a10 are distributed on both sides of the ninth active region a9. The eighth active region a8 and the ninth active region a9 are arranged adjacent to each other, with a blank cutting channel d between them. The ninth active region a9 and the tenth active region a10 are arranged adjacent to each other, with a blank cutting channel d between them. The area of the ninth active region a9 is 1R, and the areas of the eighth active region a8 and the tenth active region a10 are both 0.5R. That is, the total area of the multiple active regions (a8, a9, a10) in the second adapter plate 102 is 2R.
[0093] Based on this, continuing to refer to Figure 5, the areas of multiple active regions in the first adapter plate 101 and the multiple active regions in the second adapter plate 102 are approximately the same (2R) and are arranged opposite to each other. That is, the projections of the sixth active region a6 and the seventh active region a7 on the substrate (Sub1, Sub2) overlap with the projections of the eighth active region a8, the ninth active region a9, and the tenth active region a10 on the substrate. Specifically, the projection of the sixth active region a6 on the substrate overlaps with the projections of the eighth active region a8 and the left portion of the ninth active region a9 on the substrate; thus, the eighth active region a8 and the ninth active region a9 can be connected through the sixth active region a6 to achieve interaction. The projection of the seventh active region a7 on the substrate (Sub1, Sub2) overlaps with the projections of the tenth active region a0 and the right portion of the ninth active region a9 on the substrate; thus, the ninth active region a9 and the tenth active region a10 can be connected through the seventh active region a7 to achieve interaction. The sixth active region a6 and the seventh active region a7 both overlap with the ninth active region a9; thus, the sixth active region a6 and the seventh active region a7 can be connected through the ninth active region a9 to achieve interaction. In other words, in this transition structure 10, multiple active regions within the two transition boards (101 and 102) can interact with each other.
[0094] Depending on actual needs, the distribution of the active areas of the two adapter boards (101, 102) in the horizontal X and vertical Y directions in the plane can be flexibly designed. As long as it is ensured that two adjacent active areas in one adapter board can be connected through the other adapter board to achieve interconnection.
[0095] For example, referring to Figure 6, some transition structures 10 may include a first region C1 and a second region C2 in the longitudinal direction Y of the plane. In the first region C1, the active regions in the first transition plate 101 and the second transition plate 102 may adopt the distribution shown in Figure 4 above. In the second region C2, the active regions in the first transition plate 101 and the second transition plate 102 may adopt the distribution shown in Figure 5 above. For details, please refer to the relevant descriptions above, which will not be repeated here.
[0096] Additionally, referring to Figure 7, in order to improve heat dissipation efficiency, in some possible implementations, a microchannel b can be provided in the bonding region between the back side of the first substrate Sub1 and the back side of the second substrate Sub2 in the transition structure 10. Coolant is transported in the microchannel b to achieve heat dissipation, thereby improving heat dissipation efficiency.
[0097] Figure 8 is an exploded and enlarged schematic diagram of the microchannel b in Figure 7. Referring to Figure 8(a) and (b), the microchannel b can be configured as follows: a first groove b1 is provided on the back side of the first substrate Sub1, and a second groove b2 is provided on the back side of the second substrate Sub2. After the back side of the first substrate Sub1 and the back side of the second substrate Sub2 are bonded together, the groove opening of the first groove b1 and the groove opening of the second groove b2 are joined (or matched) to form the microchannel b.
[0098] Of course, this application does not limit the shape of the first groove b1 and the second groove b2 in the plane. For example, they can be S-shaped, square-shaped, mesh-shaped, etc., as long as they can meet the heat dissipation requirements.
[0099] The following description, in conjunction with the manufacturing method of the adapter structure 10, further illustrates the adapter structure 10 provided in the embodiments of this application.
[0100] As illustrated in FIG9, this application provides a method for manufacturing a transition structure, which may include:
[0101] Step S1, referring to FIG10, a first adapter board 101 is provided; wherein, the first adapter board 101 includes a first substrate Sub1 and a first wiring structure A1 formed on the front side of the first substrate Sub1, and a first through silicon via TSV1 connected to the first wiring structure A1 is formed in the first substrate Sub1.
[0102] Schematic, referring to Figure 10, in some possible implementations, step S1 may include: providing a silicon substrate (Sub1), fabricating multiple field-effect transistors t1 and other active devices on the front side of the silicon substrate (Sub1), and fabricating multiple wiring layers on the active device layers to form a first wiring structure A1 containing multiple circuit modules on the front side of the silicon substrate (Sub1). Step S1 also includes forming a first through-silicon via (TSV1) in the silicon substrate (Sub1) to connect with the multiple circuit modules. The first TSV1 may be fabricated using a via-first process or a via-last process; this application does not impose any limitation on this.
[0103] Multiple interconnect pads (PADs) are formed on the top of the first wiring structure A1, and the first adapter board 101 achieves interconnection and communication with the chip through the top interconnect pads. Multiple interconnect pads (PADs), such as copper interconnect pads (Cu PADs), are formed on the back side of the silicon substrate (Sub1), but are not limited to this. The first adapter board 101 achieves connection with the second adapter board 102 through the interconnect pads (PADs) on the back side of the substrate.
[0104] Step S2, referring to Figure 11, a second adapter board 102 is provided; wherein, the second adapter board 102 includes a second substrate Sub2 and a second wiring structure A2 formed on the front side of the second substrate Sub2, and a second through silicon via TSV2 connected to the second wiring structure A2 is formed in the second substrate Sub2.
[0105] Schematic, referring to Figure 11, in some possible implementations, step S2 may include: providing a silicon substrate (Sub2), fabricating multiple field-effect transistors t2 and other active devices on the front side of the silicon substrate (Sub2), and fabricating multiple wiring layers on the active device layers to form a second wiring structure A2 containing multiple circuit modules on the front side of the silicon substrate (Sub2). Step S2 also includes forming a second through-silicon via (TSV2) on the silicon substrate (Sub2) to connect with the multiple circuit modules. The second TSV2 may be fabricated using either a via-first or via-last process; this application does not impose any limitations on this.
[0106] Multiple connection pads (PADs) are formed on the top of the second wiring structure A2, and the second adapter plate 102 achieves interconnection with the substrate through the top connection pads. Multiple connection pads (PADs), such as copper connection pads (Cu PADs), are formed on the back side of the silicon substrate (Sub2) and are respectively connected to multiple second through-silicon vias (TSV2), but are not limited to this. The second adapter plate 102 achieves connection with the first adapter plate 101 through the connection pads on the back side of the substrate.
[0107] Step S3, referring to Figure 12, the first adapter plate 101 and the second adapter plate 102 are bonded through the back side of the first substrate Sub1 and the back side of the second substrate Sub2, and the first through silicon via TSV1 and the second through silicon via TSV2 are connected at the bonding surface M.
[0108] Schematic, referring to Figure 12, in some possible implementations, step S3 may include: using a hybrid bonding (HB) process to bond the first adapter plate 101 and the second adapter plate 102 through the back side of the first substrate Sub1 and the back side of the second substrate Sub1. In this case, the connection pad on the back side of the first substrate Sub1 is bonded to the connection pad on the back side of the second substrate Sub1, thereby forming a connection between the first through-silicon via TSV1 and the second through-silicon via TSV2 at the bonding surface M.
[0109] By employing a hybrid bonding technology to bond the back sides of the first substrate Sub1 and the second substrate Sub1, a combination of dielectric-dielectric bonding and direct copper-to-copper bonding is used at the bonding surface M. This eliminates the need for additional adhesives or materials, thereby enabling high-density interconnection and meeting the interconnection requirements between the first adapter board 101 and the second adapter board 102.
[0110] It should be understood that, in the embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0111] For other related content in the above manufacturing method, please refer to the corresponding parts in the aforementioned structural embodiments, which will not be repeated here; for other settings in the aforementioned structural embodiments, please refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.
[0112] The application of the adapter structure 10 provided in the embodiments of this application will be illustrated below with reference to a specific chip packaging structure 01.
[0113] Application 1
[0114] Schematic, referring to Figure 13, some chip package structures 01 may include a substrate Sub and a chip module U, an input / output chip IO, and a memory chip MEM disposed on the substrate Sub. The chip module U, the input / output chip IO, and the memory chip MEM are connected through the substrate Sub. The chip module U includes a transition structure 10, a System-on-a-Chip (SOC) disposed on the transition structure 10, and multiple DDRs distributed around the SOC. The SOC and DDRs are disposed on one side of a first transition board 101 and connected to the first transition board 101. The transition structure 10 is connected to the substrate Sub through a second transition board 102. This chip package structure 01 is connected to a PCB in an electronic device through the substrate Sub (see Figure 2).
[0115] Referring again to Figure 13, in some possible implementations, the aforementioned SOC may include an internal interposer 201, multiple logic chips D1, and a heat sink 202. The multiple logic chips D1 are mounted on the internal interposer 201, which contains SRAM. The multiple logic chips D1 are interconnected via the internal interposer 201, and the SOC is connected to the first interposer 101 in the interposer structure 10 via the internal interposer 201. The heat sink 202 is positioned above the multiple logic chips D1. The heat sink 202 can be made of silicon (but is not limited to this), and is used to form heat dissipation channels on top of the multiple logic chips D1, improving the heat dissipation efficiency of the package structure.
[0116] In this packaging structure, an SRAM can be provided on the first adapter board 101, which can maximize the area capacity of the SRAM and thus improve the data interconnect bandwidth and speed.
[0117] It should be understood that SOCs require more advanced manufacturing processes, while DDRs can be manufactured using conventional processes. In the aforementioned chip packaging structure 01, separating the DDR from the SOC and setting it up independently improves product yield and thus reduces costs.
[0118] In addition, in the chip packaging structure 01 described above, the memory chip MEM is independently mounted on the substrate Sub, which can reduce the latency between the memory chip MEM and the chip module U (SOC, DDR); the input / output chip IO is independently mounted on the substrate Sub, which can increase the bandwidth of the input / output chip IO to the outside world.
[0119] Application 2
[0120] Figure 14 is a cross-sectional view of a chip packaging structure provided in an embodiment of this application, and Figure 15 is a plan view of Figure 14.
[0121] As illustrated in Figures 14 and 15, in some chip packaging structures 01, which can also be called a system on wafer (SOW), the packaging system may include an adapter structure 10, multiple chips such as SOC and HBM disposed on one side of the first adapter board 101 and connected to the first adapter board 101, and electronic devices disposed on one side of the second adapter board 102 and connected to the second adapter board 102. The electronic devices may be one or more of devices such as a power module 30 and a connector 31.
[0122] The SOC settings are similar to those in Application 1, and will not be repeated here.
[0123] No substrate is required in this packaging system.
[0124] Of course, in order to simplify the connection between multiple electronic devices (30, 31) and the second adapter board 102, as shown in Figure 16, in some possible implementations, a redistribution layer RDL1 can be provided on the lower surface of the second adapter board 102. Multiple electronic devices (30, 31) can be connected to the second adapter board 102 through the redistribution layer RDL1, thereby reducing the connection difficulty and simplifying the manufacturing process.
[0125] On the one hand, the adapter structure 10 provided in this application can meet the packaging system's requirements for double-sided devices. On the other hand, the adapter structure 10 provided in this application can overcome the 1R limitation, thereby allowing for the selection of a larger adapter structure 10 according to the needs of the packaging system, thus better meeting the requirements of multiple system setups.
[0126] In addition, as shown in Figures 13 and 15, the packaging system may also include a heat sink 40, a fixing structure 50, etc. This application does not limit this, and it can be set as needed in practice.
[0127] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A transition structure, characterized in that, It includes a first interposer and a second interposer; The first adapter plate includes a first substrate and a first trace structure disposed on the front side of the first substrate; The second adapter plate includes a second substrate and a second wiring structure disposed on the front side of the second substrate; The first substrate has a first through-silicon via (TSV) and the first TSV is connected to the first wiring structure; the second substrate has a second TSV and the second TSV is connected to the second wiring structure. The back side of the first substrate is connected to the back side of the second substrate through a bonding surface, and the first through-silicon via and the second through-silicon via are connected at the bonding surface.
2. The adapter structure according to claim 2, characterized in that, The first wiring structure includes active devices.
3. The adapter structure according to claim 1 or 2, characterized in that, The second wiring structure includes active devices.
4. The adapter structure according to any one of claims 1-3, characterized in that, The first adapter board has multiple active areas, and the area of each active area is less than or equal to 1R; where R is the area of a photomask. Two adjacent active regions in the first adapter board are connected through the second adapter board.
5. The adapter structure according to any one of claims 1-4, characterized in that, The second adapter board has multiple active areas, and the area of each active area is less than or equal to 1R; where R is the area of a photomask. Two adjacent active regions in the second adapter board are connected through the first adapter board.
6. The adapter structure according to claim 4 or 5, characterized in that, The first adapter board includes a first active area, a second active area, and a third active area; the second active area is located between the first active area and the third active area, the area of the second active area is 1R, and the areas of the first active area and the third active area are both 0.5R; The second adapter board includes a fourth active region and a fifth active region; the area of the fourth active region and the fifth active region is 1R. The fourth active region overlaps with both the first active region and the second active region, and the first active region is connected to the second active region through the fourth active region. The fifth active region overlaps with the second active region and the third active region, and the third active region is connected to the second active region through the fifth active region; The fourth active region is connected to the fifth active region through the second active region.
7. The adapter structure according to any one of claims 4-6, characterized in that, The first adapter board includes a sixth active region and a seventh active region; the area of the sixth active region and the seventh active region is 1R; The second adapter board includes an eighth active area, a ninth active area, and a tenth active area; the ninth active area is located between the eighth active area and the tenth active area, the area of the ninth active area is 1R, and the areas of the eighth active area and the tenth active area are both 0.5R; The sixth active region, the eighth active region, and the ninth active region all have overlapping areas, and the eighth active region is connected to the ninth active region through the sixth active region; The seventh active region overlaps with the ninth and tenth active regions, and the ninth active region is connected to the tenth active region through the seventh active region. The sixth active region is connected to the seventh active region through the ninth active region.
8. The adapter structure according to any one of claims 1-7, characterized in that, The first routing structure includes a static random access memory (SRAM).
9. The adapter structure according to any one of claims 1-8, characterized in that, The second wiring structure includes at least one of a serializer / deserializer SERDES and a power management module.
10. The adapter structure according to any one of claims 1-9, characterized in that, The first wiring structure includes a capacitor; the second wiring structure includes a capacitor.
11. The adapter structure according to any one of claims 1-10, characterized in that, The back side of the first substrate is connected to the back side of the second substrate by a hybrid bonding method.
12. The adapter structure according to any one of claims 1-11, characterized in that, The back side of the first substrate is provided with a first groove, and the back side of the second substrate is provided with a second groove; The first groove and the second groove are joined at the bonding surface to form a microchannel.
13. A method for manufacturing a transition structure, characterized in that, include: A first adapter board is provided; wherein the first adapter board includes a first substrate and a first wiring structure formed on the front side of the first substrate, and a first through-silicon via is formed in the first substrate to connect with the first wiring structure. A second adapter board is provided; wherein the second adapter board includes a second substrate and a second wiring structure formed on the front side of the second substrate, and a second through-silicon via is formed in the second substrate to connect with the second wiring structure; The first adapter plate and the second adapter plate are bonded together through the back side of the first substrate and the back side of the second substrate, and the first through-silicon via and the second through-silicon via are connected at the bonding surface.
14. The method for manufacturing the adapter structure according to claim 13, characterized in that, The bonding of the first adapter plate and the second adapter plate through the back sides of the first substrate and the back sides of the second substrate includes: A hybrid bonding process is used to bond the first adapter plate and the second adapter plate through the back side of the first substrate and the back side of the second substrate.
15. The method for manufacturing the adapter structure according to claim 13 or 14, characterized in that, The provision of the first adapter board includes: A first substrate is provided, a first wiring structure including an active device is formed on the front side of the first substrate, and a first through-silicon via (TSV) connected to the first wiring structure is formed in the first substrate.
16. The method for manufacturing the adapter structure according to any one of claims 13-15, characterized in that, The provision of the second adapter board includes: A second substrate is provided, a second wiring structure including an active device is formed on the front side of the second substrate, and a second through-silicon via (TSV) connected to the second wiring structure is formed in the second substrate.
17. A chip packaging structure, characterized in that, It includes at least one chip and an adapter structure as described in any one of claims 1-12; the chip is disposed on one side of the first adapter board and connected to the first adapter board.
18. The chip packaging structure according to claim 17, characterized in that, The at least one chip includes a system-on-a-chip (SoC); the SoC includes an internal adapter board and a plurality of logic chips disposed on the internal adapter board, the plurality of logic chips being connected to the internal adapter board; the internal adapter board is provided with SRAM.
19. The chip packaging structure according to claim 17 or 18, characterized in that, The chip packaging structure also includes a substrate, input / output chips, and a memory chip; The adapter structure, the input / output chip, and the memory chip are located on the same side of the substrate and are connected to the substrate. The adapter structure is connected to the substrate via the second adapter plate.
20. The chip packaging structure according to claim 17 or 18, characterized in that, The chip packaging structure also includes at least one electronic device disposed on one side of the second adapter board and connected to the second adapter board.
21. The chip packaging structure according to claim 20, characterized in that, The chip packaging structure also includes a redistribution layer disposed on the side of the second adapter board facing the electronic device, and the electronic device is connected to the second adapter board through the redistribution layer.
22. An electronic device, characterized in that, It includes a circuit board and a chip package structure as described in any one of claims 17-21; the circuit board is connected to the chip package structure.