Asymmetric OTP memory and data writing method
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2026-08-13
Smart Images
Figure CN2025118159_13082026_PF_FP_ABST
Abstract
Description
Asymmetric OTP memory and data writing method Technical Field
[0001] This invention relates to integrated circuit technology, and more particularly to memory technology. Background Technology
[0002] Patent documents CN2021112205 and US10510427B2 disclose antifuse memory technology based on MOSFETs. Figure 3 shows the existing MOSFET structure. The GIDL breakdown voltage of conventional MOSFETs is relatively low. GIDL, or gate-induced drain current, occurs below the gate-drain overlap region. In conventional CMOS transistors, LDD provides a short connection path under the sidewall between the gate under-drain channel and the drain. Because the LDD region is very close to the gate region, even overlapping when projected, at large GD reverse voltages, although the gate region and source-drain must be aligned in the device structure, there is actual overlap. When a negative bias is applied to the gate or a strong positive bias is applied to the drain, holes, which are the majority carriers of the substrate, accumulate near the drain LDD on the surface, depleting / deeply depleting the original N-type silicon, tending to invert this region. As a result, the depletion region of the drain LDD extends towards the drain, similar to p+ doping, and strong band bending occurs due to the induced electric field. At this point, when the bandgap becomes greater than the band gap, i.e., when the valence band Ev becomes higher than the conduction band Ec, electrons flow into the drain through the tunneling effect, generating leakage current. Furthermore, due to thermally generated EHP, holes flow into the substrate, and electrons flow into the drain, increasing the leakage current. In addition, if the device deteriorates due to NBTI, PBTI, or HCI stress, traps in the interface will generate trap-assisted tunneling currents, further increasing the GIDL current. These multiple factors contribute to GIDL leakage.
[0003] On the other hand, during programming, the WL (word line) must use a high Vpp (6~7V, for <0.11um processes). With the BL (bit line) at 0V, leakage at the GIDL (given junction) and junction is easily caused. When programming the NMOS gate cap, if the gate breakdown point is not on the source side, a voltage drop (Vt drop) may occur, leading to changes in the minimum read voltage and current. Furthermore, the charge pump (CP) needs to pump from Vdd or Vcc to Vpp in stages, resulting in a larger required charge pump size and higher power consumption. More importantly, the high-voltage Vpp WL decoder circuit must be precisely designed to avoid Vpp leakage, which also increases the size of the WL decoder.
[0004] US Patent document US20090090980A1 discloses an asymmetric LDD-type MOSFET that is compatible with standard CMOS technology and requires no additional mask. To create a large voltage drop region on the drain side, the drain LDD is removed by blocking LDD / Halo injection. Forming LDD / Halo injection using a mask tool requires only one logic operation layer, thus eliminating the need for additional process steps. The significant improvement of BVdss is due to the design of a wide depletion region below the sidewall region and between the drain and the substrate, reducing the peak electric field on the drain side and enabling a larger reverse-biased drain voltage than in conventional cases. Technical issues
[0005] The technical problem to be solved by the present invention is to provide an OTP memory with low power consumption, small area and less leakage current, as well as a data writing method. Technical solutions
[0006] The technical solution adopted by the present invention to solve the aforementioned technical problem is an asymmetric OTP memory, comprising an array formed by arranging a preset number of memory cells, wherein the memory cells include:
[0007] An antifuse storage MOSFET, the gate of which is connected to the first row line WP.
[0008] A select MOSFET has its gate connected to the third row line WS, its first current terminal connected to the second current terminal of the antifuse storage MOSFET, and its second current terminal connected to the first column line BL.
[0009] The antifuse storage MOS transistor is a PMOS transistor, and the selection MOS transistor is an asymmetric PMOS transistor. The source region of the asymmetric PMOS transistor includes a P-type region and a lightly doped P-type region, and the drain region consists only of a P-type region. The doping concentrations of the P-type regions in the source and drain regions are the same, and the doping concentration of the lightly doped P-type region is lower than that in the P-type region.
[0010] Furthermore, the storage unit also includes a detection MOS transistor, the connection point of the selection MOS transistor and the antifuse storage transistor is connected to the gate of the detection MOS transistor, the first current terminal of the detection MOS transistor is connected to the first column line BL, and the second current terminal is connected to the second column line BR.
[0011] Furthermore, the first current terminal of the selected MOS transistor is connected to the second current terminal of the antifuse storage MOS transistor through a voltage divider MOS transistor; the gate of the voltage divider MOS transistor is connected to the second row line WB; the voltage divider MOS transistor is an asymmetric PMOS transistor.
[0012] Furthermore, the antifuse storage MOS transistor is an asymmetric PMOS transistor.
[0013] The present invention also provides a data writing method for an asymmetric OTP memory, comprising the following steps:
[0014] (1) Apply a positive voltage to the first column line BL;
[0015] (2) Apply 0 voltage to the third line WS;
[0016] (3) A negative voltage is applied to the first row line WP;
[0017] The voltage difference between the first column line BL and the first row line WP is 6.5V.
[0018] The present invention also provides a data writing method for an asymmetric OTP memory, the asymmetric OTP memory including a detection MOS transistor, comprising the following steps:
[0019] (1) Apply a positive voltage to the first column line BL;
[0020] (2) Apply 0 voltage to the third line WS;
[0021] (3) A negative voltage is applied to the first row line WP;
[0022] The voltage difference between the first column line BL and the first row line WP is 6.5V.
[0023] The present invention also provides a data writing method for an asymmetric OTP memory, the asymmetric OTP memory including a detection MOSFET and a voltage divider MOSFET, comprising the following steps:
[0024] (1) Apply a positive voltage to the first column line BL;
[0025] (2) Apply 0 voltage to the second row line WB and the third row line WS;
[0026] (3) A negative voltage is applied to the first row line WP;
[0027] The voltage difference between the first column line BL and the first row line WP is 6.5V. Beneficial effects
[0028] The beneficial effects of this invention are as follows: Using the technology of this invention, the high programming voltage can be split during the programming process, allowing the use of a lower negative Vpp (-4V, <0.11um process) and a bit line voltage of 2.5V, significantly reducing GIDL and junction leakage. When programming the gate capacitance of the PMOS, the gate is at 0V, and its gate breakdown point is far from the source edge, eliminating Vt drop, reducing the minimum read voltage, and resulting in a more uniform read current. Compared with NMOS-type antifuse memory arrays, PMOS-type antifuse memory arrays can use split programming Vpp (-4V) and Vbl (2.5V), thus requiring fewer charge pump stages, saving area and reducing charge pump power consumption. Lowering Vpp (from 6V to 4V) simplifies the WL (Vpp) decoder circuit, resulting in a smaller area and less leakage. Attached Figure Description
[0029] Figure 1 shows the drain breakdown Ids-Vds curves of asymmetric MOS and conventional MOS (Vgs=0V).
[0030] Figure 2 shows the Ids-Vds curves of an asymmetric MOS and a conventional MOS at 1.2V.
[0031] Figure 3 is a schematic diagram of the PMOS transistor structure.
[0032] Figure 4 is a schematic diagram of the asymmetric PMOS transistor used in this invention.
[0033] Figure 5 is a circuit diagram of Embodiment 1 of the present invention.
[0034] Figure 6 is a circuit diagram of Embodiment 2 of the present invention.
[0035] Figure 7 is a circuit diagram of Embodiment 3 of the present invention. Embodiments of the present invention
[0036] Referring to Figures 1 and 2, Figure 1 shows the drain breakdown behavior of NLDD and conventional devices. The results show that the BVdss of the 65nm NLDD device can be increased from 2V to 6V. The significant improvement in BVdss is due to the reduction in drain-side LDD, which creates a larger depletion space for the voltage drop.
[0037] Figure 2 shows a comparison of the I / V ratio of NLDD (N-type asymmetric MOSFET) and conventional devices. The measured I of the NLDD device decreases significantly in the transistor region due to its large series resistance R. As the channel voltage (v) increases, it reaches the pinch-off point, indicating that the device enters the saturation region, and eventually approaches the I of a conventional device. This means that if the NLDD device is always biased in saturation, its DC performance will not be significantly affected. Note that the traditional device model (symmetric LDD device) is provided by the IC foundry.
[0038] Figure 3 shows the structure of a conventional MOS transistor (symmetric PMOS transistor). The region indicated by P+ is the P-type region, and the region indicated by P- is the lightly doped P-type region.
[0039] Referring to Figure 4, the source region of an asymmetric PMOS transistor (PLDD) includes a P-type region and a lightly doped P-type region, while the drain region consists only of a P-type region. The doping concentrations of the P-type regions in the source and drain regions are the same, while the doping concentration of the lightly doped P-type region is lower than that in the P-type region. halo represents localized n+ heavy doping, and RSX is the source-side sheet resistance.
[0040] The following table compares N-type asymmetric MOSFETs (NLDD) and P-type asymmetric MOSFETs (PLDD):
[0041]
[0042] Because the doping concentration of the lightly doped P-type region (P-) is typically lower than that of the lightly doped N-type region (N-), the depletion region is wider and the electric field distribution is smoother. Hole mobility is lower than electron mobility, resulting in a lower tunneling probability; from a circuit performance perspective, this significantly reduces static power consumption. Therefore, PLDD performs better than NLDD in GIDL leakage current.
[0043] Referring to Figure 5, the asymmetric OTP memory of the present invention includes an array formed by arranging a predetermined number of memory cells, wherein the memory cells include:
[0044] An antifuse storage MOSFET, the gate of which is connected to the first row line WP.
[0045] A select MOSFET has its gate connected to the third row line WS, its first current terminal connected to the second current terminal of the antifuse memory transistor, and its second current terminal connected to the first column line BL.
[0046] The antifuse storage MOS transistor is a PMOS transistor, and the selection MOS transistor is an asymmetric PMOS transistor. Example
[0047] As an example 1, referring to Figure 5, the asymmetric OTP memory of this embodiment includes an array formed by arranging a preset number of memory cells, wherein the memory cells include:
[0048] An antifuse storage MOSFET, the gate of which is connected to the first row line WP.
[0049] A select MOSFET has its gate connected to the third row line WS, its first current terminal connected to the second current terminal of the antifuse memory transistor, and its second current terminal connected to the first column line BL.
[0050] Its features are,
[0051] The antifuse storage MOS transistor is a PMOS transistor.
[0052] The selected MOS transistor is an asymmetric PMOS transistor (shown by the dashed coil).
[0053] The source region of the asymmetric PMOS transistor includes a P-type region and a lightly doped P-type region, while the drain region consists only of a P-type region. The doping concentrations of the P-type regions in the source and drain regions are the same, and the doping concentration of the lightly doped P-type region is lower than that in the P-type region.
[0054] In this embodiment, the high programming voltage can be split during programming, allowing the use of a lower negative Vpp (-4V, <0.11um process) and BL of 2.5V, significantly reducing GIDL and Junction leakage. When programming the PMOS gate cap, the gate is at 0V, and its gate breakdown point is far from the source edge, with no Vt drop, thus reducing the minimum read voltage and making the read current more uniform. Compared to NMOS XPM, PMOS XPM can use split programming Vpp (-4V) and Vbl (2.5V), thus requiring fewer charge pump stages, saving area and reducing charge pump power consumption. Reducing Vpp (from 6V to 4V) makes the WL (Vpp) decoder circuit simpler, smaller in area, and with less leakage.
[0055] Using an N-type asymmetric MOS (NLDD) can increase the Vdg of the GIDL leakage current in the WS drain region by 2-3V. However, during programming, WL must use a relatively high Vpp (6-7V for <0.11µm processes). At 0V, BL can easily lead to leakage in the GIDL and junction. When programming the NMOS gate cap, if the gate breakdown point is not at the source side, Vtdrop may occur, causing changes in the minimum read voltage and current. Furthermore, the charge pump needs to pump from Vdd or Vcc to Vpp in stages, resulting in a larger required charge pump size and higher power consumption. More importantly, the high-voltage Vpp WL decoder circuit must be precisely designed to avoid Vpp leakage, which also increases the size of the WL decoder. Example
[0056] As an embodiment 2, referring to Figure 6, the asymmetric OTP memory of this embodiment includes an array formed by arranging a preset number of memory cells, wherein the memory cells include:
[0057] An antifuse storage MOSFET, the gate of which is connected to the first row line WP.
[0058] A select MOSFET has its gate connected to the third row line WS, its first current terminal connected to the second current terminal of the antifuse memory transistor, and its second current terminal connected to the first column line BL.
[0059] The antifuse storage MOS transistor is a PMOS transistor, and the selection MOS transistor is an asymmetric PMOS transistor. The source region of the asymmetric PMOS transistor includes a P-type region and a lightly doped P-type region, and the drain region consists only of a P-type region. The doping concentrations of the P-type regions in the source and drain regions are the same, while the doping concentration of the lightly doped P-type region is lower than that in the P-type region.
[0060] The memory cell also includes a detection MOS transistor. The connection point of the select transistor and the antifuse memory transistor is connected to the gate of the detection MOS transistor. The first current terminal of the detection MOS transistor is connected to the first column line BL, and the second current terminal is connected to the second column line BR.
[0061] This embodiment requires fewer stages, has a smaller size, and consumes less power, which is crucial for ultra-low power applications such as UHF RFID chips. Reducing Vpp simplifies the WL decoder circuit design, thereby reducing the size of the WL decoder. When programming the PMOS gate edge region, its gate is at 0V, and even if the breakpoint is far from the source edge, there is no Vt drop (PMOS fully turned on), thus lowering the minimum read voltage and making the read current more uniform. During the read process, the floating point (FN) after being charged by the WS pulse reaches Vdd. For a programmed PMOS capacitor, this becomes a resistor, rapidly discharging to FN at 0V, thus fully turning on the detection MOS transistor. For an unprogrammed PMOS capacitor, FN remains at Vdd and is insensitive to any voltage interference, thus avoiding read errors.
[0062] If an asymmetric NMOS transistor is used, the logic Vdd (1.8, 1.1V) can be directly applied to the WS gate and BL without needing a levelshifter. By shielding the lightly doped drain implantation and P-type pocket ion implantation of the WS MOS transistor to form an asymmetric NLDD MOS, the Vdg that generates GIDL leakage on the WS drain can be increased by 2-3V. However, during programming, the WL must use an excessively high Vpp (6-7V, for <0.11µm processes). At 0V on the BL, this easily leads to GIDL and junction leakage. Furthermore, the charge pump needs to pump from Vdd or Vcc to Vpp in stages, resulting in a larger charge pump size and higher power consumption. More importantly, the high-voltage Vpp WL decoder circuit must be precisely designed to avoid Vpp leakage, which also increases the size of the WL decoder. When programming the NMOS gate cap, if the gate breakdown point is not on the source side, a Vt drop may occur, potentially causing changes in the minimum read voltage and current. To address this, a native NMOS capacitor must be used. During the read operation, the floating point (FN, connected to the gate of the sense MOS transistor) is highly sensitive to voltage interference from WL, WS, BL, and BR, which can lead to data read errors. To solve this problem, an additional read control NMOS is typically used in series with the local sense NMOS, which increases the size of the XLPM array, or a very complex read voltage timing operation is employed. Example
[0063] As an example 3, see Figure 7. This example adds a voltage divider tube (shown by the dashed circle in Figure 6) to the basic example 2; the specific structure will not be described in detail.
[0064] In this embodiment, the programming high voltage is split during programming, using a lower negative Vpp (-4V, <0.11um process) and 2.5V BL, which significantly reduces GIDL and junction leakage. Compared to NMOS XLPM, the charge pump requires fewer stages, is smaller, and consumes less power, which is crucial for ultra-low power applications such as UHF RFID chips. Lowering Vpp simplifies the WL decoder circuit design, thereby reducing the size of the WL decoder. When programming the PMOS gate edge region, its gate is at 0V, and even if the breakpoint is far from the source edge, there is no Vt drop (PMOS fully turned on), thus reducing the minimum read voltage and making the read current more uniform. During reading, the floating point (FN) after being charged by the WS pulse reaches Vdd, which acts as a resistor for the programmed PMOS capacitor, rapidly discharging to FN at 0V, thus fully turning on the detection MOS transistor. For the unprogrammed PMOS capacitor, FN will remain at Vdd and is insensitive to any voltage interference, thus avoiding read errors.
[0065] If an asymmetric NMOS is used for the voltage divider MOSFET, the WL must use an excessively high Vpp (6~7V, for <0.11um process) during programming. At 0V, BL can easily cause leakage in GIDL and Junction. Furthermore, the charge pump needs to pump from Vdd or Vcc to Vpp in stages, resulting in a larger charge pump size and higher power consumption. More importantly, the high Vpp WL decoder circuit must be precisely designed to avoid Vpp leakage, which also increases the size of the WL decoder. When programming the NMOS gate Cap, if the gate breakdown point is not on the source side, Vt drop may occur, potentially causing changes in the minimum read voltage and current. To solve this, a native NMOS capacitor must be used. During reading, the floating point (FN, connected to the gate of the sense MOSFET) is very sensitive to voltage interference from WL, WS, BL, and BR, which can lead to data read errors. To address this, an additional read control NMOS is typically used in series with the local sense NMOS, which increases the size of the XLPM array. Alternatively, a very complex read voltage timing operation can be employed.
[0066] To further reduce the area, the antifuse storage MOS transistor, select MOS transistor, and voltage divider MOS transistor in this embodiment can all be asymmetric PMOS transistors.
Claims
1. An asymmetric OTP memory, comprising an array formed by arranging a predetermined number of memory cells, wherein the memory cells include: An antifuse storage MOSFET, the gate of which is connected to the first row line WP; A select MOSFET has its gate connected to the third row line WS, its first current terminal connected to the second current terminal of the antifuse storage MOSFET, and its second current terminal connected to the first column line BL. Its features are, The antifuse storage MOS transistor is a PMOS transistor. The selected MOS transistor is an asymmetric PMOS transistor. The source region of the asymmetric PMOS transistor includes a P-type region and a lightly doped P-type region, while the drain region consists only of a P-type region. The doping concentrations of the P-type regions in the source and drain regions are the same, and the doping concentration of the lightly doped P-type region is lower than that in the P-type region.
2. The asymmetric OTP memory as described in claim 1, characterized in that, The storage cell also includes a detection MOS transistor, the connection point of the selection MOS transistor and the antifuse storage transistor is connected to the gate of the detection MOS transistor, the first current terminal of the detection transistor is connected to the first column line BL, and the second current terminal is connected to the second column line BR.
3. The asymmetric OTP memory as described in claim 2, characterized in that, The first current terminal of the selected MOSFET is connected to the second current terminal of the antifuse storage MOSFET through a voltage divider MOSFET; the gate of the voltage divider MOSFET is connected to the second row line WB; the voltage divider MOSFET is an asymmetric PMOS transistor.
4. The asymmetric OTP memory as described in claim 3, characterized in that, The antifuse storage MOS transistor is an asymmetric PMOS transistor.
5. The data writing method of the asymmetric OTP memory according to claim 1, characterized in that, Includes the following steps: (1) Apply a positive voltage to the first column line BL; (2) Apply 0 voltage to the third line WS; (3) A negative voltage is applied to the first row line WP; The voltage difference between the first column line BL and the first row line WP is 6.5V.
6. The data writing method of the asymmetric OTP memory according to claim 2, characterized in that, Includes the following steps: (1) Apply a positive voltage to the first column line BL; (2) Apply 0 voltage to the third line WS; (3) A negative voltage is applied to the first row line WP; The voltage difference between the first column line BL and the first row line WP is 6.5V.
7. The data writing method of the asymmetric OTP memory according to claim 3, characterized in that, Includes the following steps: (1) Apply a positive voltage to the first column line BL; (2) Apply 0 voltage to the second row line WB and the third row line WS; (3) A negative voltage is applied to the first row line WP; The voltage difference between the first column line BL and the first row line WP is 6.5V.