Method and apparatus for manufacturing HDI circuit board, and printed circuit board

Abstract

The present application relates to a method and apparatus for manufacturing an HDI circuit board, and a printed circuit board (PCB). In the present application, the steps of blind-hole drilling, first copper formation, first copper reduction, first through-hole drilling, second copper formation, resin plugging, second copper reduction, third copper formation, etc., are sequentially performed on a multi-layer PCB, so as to form high-aspect-ratio blind holes and through-holes in the multi-layer PCB, thereby achieving a relatively good hole-filling effect and through-hole copper thickness uniformity with relatively good throwing power, and effectively avoiding the problem of a copper thickness being not uniform due to insufficient throwing power during hole-filling copper plating and through-hole plating.

Description

HDI circuit board manufacturing method, apparatus and printed circuit board

[0001] The application claims priority to Chinese patent application filed on February 6, 2025, with application number 202510132937.2 and title "Infrared Light Transmission Structure, Infrared Control Circuit and Infrared Control Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of PCB manufacturing technology, specifically to HDI circuit board manufacturing methods, apparatus, and printed circuit boards. Background Technology

[0003] HDI (High-Density Interconnect) circuit boards are high-density circuit boards that utilize micro-blind via technology. Designed specifically for small-capacity applications, these compact products feature high density, high precision, and high performance. As electronic products become more multifunctional, complex, and miniaturized, the application of HDI circuit boards is becoming increasingly widespread.

[0004] With the development of integrated circuits, high aspect ratio circuit boards are increasingly used. In the circuit board manufacturing industry, a high aspect ratio refers to products with an aperture ≤ 0.2mm and an aspect ratio ≥ 15:1. The metallization plating process for these holes presents significant challenges, primarily due to the substantial difference in copper plating rates between the hole opening and the hole's interior. The plating rate is faster at the opening and slower in the interior, resulting in a large difference in copper thickness between the two areas. This affects the reliability of the copper quality, leading to issues such as uneven copper ductility, uneven copper thickness causing problems with resistance and signal impedance. Furthermore, the small hole diameter complicates the resin plugging process, potentially causing poor plugging quality.

[0005] In high aspect ratio HDI circuit boards, through-holes and blind vias are also co-plated. This often leads to quality issues during production, such as poor copper uniformity, small hole diameter, uneven copper ductility, and poor resin plugging. The higher the aspect ratio, the more severe the problems become. Summary of the Invention

[0006] In view of the above problems, this application provides an HDI circuit board manufacturing method, apparatus, and printed circuit board to solve the problem that in the prior art, even high aspect ratio HDI circuit boards are often co-plated with through-holes and blind vias, which frequently leads to quality problems during the production process, such as poor copper uniformity in the holes, small hole diameter, uneven copper ductility, and poor resin plugging. The higher the aspect ratio, the more serious the problems become in the circuit board with co-plated through-holes and blind vias.

[0007] According to one aspect of the embodiments of this application, a method for manufacturing an HDI circuit board is provided, the method comprising:

[0008] Drill blind holes to obtain a multilayer PCB board and create blind holes in the multilayer PCB board;

[0009] The first copper production involves sequentially creating the first copper layer on the PCB multilayer board using a copper immersion method and a copper plating method. The copper plating solution used in the copper plating method is a hole-filling solution.

[0010] The first copper reduction involves reducing the copper content on the first surface.

[0011] The first through-hole is drilled to create the first through-hole on the PCB multilayer board.

[0012] The second copper production involves sequentially creating a second copper layer on a PCB multilayer board using three methods: copper plating, flash plating, and pulse plating. The copper plating solutions used in the flash plating and pulse plating methods are non-hole-filling solutions.

[0013] Resin plugs are used to fill the first through hole;

[0014] The second copper reduction involves reducing the copper in the cover hole area of ​​the PCB multilayer board, wherein the cover hole area is the area connected to the first through hole;

[0015] The third copper preparation involves sequentially creating a capping copper layer in the capping area using three methods: immersion copper plating, flash copper plating, and pulse electroplating. The copper plating solutions used in the flash copper plating and pulse electroplating methods are non-filling solutions.

[0016] In some optional embodiments, the first copper reduction specifically includes:

[0017] The first grinding process reduced the copper thickness of the first surface by 2μm-4μm. The second grinding process was carried out using a 1.8A current, a 5mm±2mm grinding mark width, and a 2-second brush mark time.

[0018] The first micro-etching process involves micro-etching the copper on the first surface to reduce the copper thickness by 22 μm.

[0019] In some optional embodiments, the second copper reduction specifically includes:

[0020] The second grinding process involves smoothing out excess resin in the resin plug hole and grinding the copper on the second surface of the cap hole area to reduce the copper thickness by 2μm-4μm. The grinding is performed three times using a current of 1.8A, a grinding mark width of 5mm±2mm, and a brush mark time of 2 seconds.

[0021] The second micro-etching process involves micro-etching the cap hole area to reduce copper thickness by 10μm-20μm.

[0022] The third grinding process involves smoothing the resin protruding after the second micro-etching by using a 1.8A current, a grinding mark width of 5mm ± 2mm, and a brush mark time of 2 seconds.

[0023] In some optional embodiments, drilling a blind hole specifically includes:

[0024] Laser-etched blind vias are created by laser etching on a multilayer PCB board.

[0025] The first plasma degumming process removes excess resin from the blind holes.

[0026] In some alternative embodiments, after the second copper reduction and before the third copper production, the process further includes:

[0027] A second through hole is drilled to create a second through hole on the PCB multilayer board.

[0028] The second plasma degumming process removes excess resin from the second through-hole.

[0029] In some optional embodiments, the pore-filling solution consists of 9%-11% H2SO4 and 5.75%-6.25% Cu. 2+ 1.125%-1.575% leveling agent, 1.125%-1.575% brightener, 50-70 PPM CL - composition.

[0030] In some optional embodiments, the non-pore-filling solution consists of 22.5%-27% H2SO4 and 3.375%-4.15% Cu. 2+ 0.85%-1.15% leveling agent, 0.055%-0.105% gloss agent, 0.75-1.25% leveling agent, 50-70 PPM CL - composition.

[0031] In some optional embodiments, the pulse electroplating process for the second and third copper preparations includes six stages, specifically:

[0032] The first stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating.

[0033] The second stage, which accounts for 30% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 20:1.

[0034] The third stage, which accounts for 25% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 18:9.

[0035] The fourth stage, accounting for 10% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 16:8.

[0036] The fifth stage, accounting for 15% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 14:7.

[0037] The sixth stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating.

[0038] According to another aspect of the present application, an HDI circuit board manufacturing apparatus is provided, the apparatus being used to perform the above-described HDI circuit board manufacturing method to manufacture a printed circuit board.

[0039] According to another aspect of the embodiments of this application, a printed circuit board is provided, which is manufactured by performing an HDI circuit board manufacturing method as described above using the HDI circuit board manufacturing apparatus described above.

[0040] The HDI circuit board manufacturing method, apparatus, and printed circuit board of this application have the following advantages: By sequentially performing blind hole drilling, first copper plating, first copper reduction, first through hole drilling, second copper plating, resin plugging, second copper reduction, and third copper plating on a multilayer PCB, high vertical and horizontal blind holes and through holes are manufactured in the multilayer PCB; better hole filling effect and better through hole copper uniformity with good deep plating capability are obtained, effectively avoiding the problem of uneven copper thickness caused by insufficient deep plating capability of hole filling, copper plating, and through hole plating.

[0041] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0042] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0043] Figure 1 shows a flowchart of the HDI circuit board manufacturing method according to Embodiment 1 of this application;

[0044] Figure 2 shows a schematic diagram of the first copper reduction process of Embodiment 1 provided in this application;

[0045] Figure 3 shows a schematic diagram of the second copper reduction process of Embodiment 1 provided in this application. Embodiments of the present invention

[0046] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein.

[0047] Example 1,

[0048] Referring to Figure 1, this application embodiment provides a method for manufacturing an HDI circuit board, which includes:

[0049] 110. Drill blind holes to obtain a PCB multilayer board and create blind holes in the PCB multilayer board; In step 110, drilling blind holes specifically includes: laser blind hole drilling, which uses a laser to laser-drill blind holes in the PCB multilayer board; and first plasma desmearing to remove excess resin from the blind holes.

[0050] 120. First copper fabrication: The first copper layer is fabricated on the PCB multilayer board sequentially using copper immersion and copper plating methods. The copper plating solution used in the copper plating process is a via-filling solution. In step 120, the via-filling solution consists of 9%-11% H2SO4 and 5.75%-6.25% Cu. 2+ 1.125%-1.575% leveling agent, 1.125%-1.575% brightener, 50-70 PPM CL - Composition. The filling solution can achieve good filling quality and high filling efficiency for blind holes.

[0051] 130, First copper reduction: copper reduction is performed on the first copper surface; in step 130, the first copper reduction specifically includes: first grinding: grinding the first copper surface to reduce copper by 2μm-4μm, and performing two grindings with a current of 1.8A, a grinding mark width of 5mm±2mm, and a brush mark time of 2 seconds; first micro-etching: micro-etching the first copper surface to reduce copper by 22μm.

[0052] 140. First through hole drilling: Create the first through hole in the PCB multilayer board. In step 140, the through hole can be drilled in the PCB multilayer board by mechanical drilling or laser drilling. The first through hole connects the upper and lower surfaces of the PCB multilayer board.

[0053] Step 150 involves the second copper plating process, which involves sequentially applying copper plating to the second side of the PCB multilayer board using three methods: immersion copper plating, flash copper plating, and pulse electroplating. The copper plating solutions used in the flash copper plating and pulse electroplating methods are non-orifice-filling solutions. In step 150, the non-orifice-filling solution consists of 22.5%-27% H₂SO₄ and 3.375%-4.15% Cu. 2+ 0.85%-1.15% leveling agent, 0.055%-0.105% gloss agent, 0.75-1.25% leveling agent, 50-70 PPM CL -Composition. In this step, a low copper ratio is used to reduce the copper plating speed in high-current areas and to reduce uneven copper plating between high and low current areas. This is combined with the reverse current in the pulse plating process to reduce the thickness of the thicker copper in high-potential areas. This step is used to create a second copper layer outside the first copper layer, increasing the copper thickness of the PCB multilayer board.

[0054] 160. Resin plugging: Filling the first through hole with epoxy resin; In step 160, epoxy resin is used to fill the first through hole to protect the inner circuit of the first through hole.

[0055] 170. Second copper reduction: Copper reduction is performed on the cover hole area of ​​the PCB multilayer board, where the cover hole area is the area connected to the first through hole. In step 170, the second copper reduction specifically includes: second grinding: smoothing the excess resin of the resin plug and grinding the second copper of the cover hole area to reduce the copper thickness to 2μm-4μm, and performing three grindings with a current of 1.8A, a grinding mark width of 5mm±2mm, and a brush mark time of 2 seconds; second micro-etching: micro-etching the cover hole area to reduce the copper thickness to 10μm-20μm; third grinding: smoothing the resin protruding after the second micro-etching, and performing one grinding with a current of 1.8A, a grinding mark width of 5mm±2mm, and a brush mark time of 2 seconds.

[0056] 180. The third copper preparation involves sequentially creating a caphole copper layer in the caphole area using three methods: immersion copper plating, flash copper plating, and pulse electroplating. The copper plating solutions used in the flash copper plating and pulse electroplating methods are non-filling solutions. In step 180, the non-filling solution consists of 22.5%-27% H₂SO₄ and 3.375%-4.15% Cu. 2+ 0.85%-1.15% leveling agent, 0.055%-0.105% gloss agent, 0.75-1.25% leveling agent, 50-70 PPM CL - Composition. In this step, a low copper ratio is used to reduce the copper plating speed in high-current areas and minimize uneven copper plating between high and low potential current areas. This is combined with the reverse current in the pulse plating process to reduce the thickness of the copper in high-potential areas. This step is used to create a capping copper layer in the capping area to cover the location of the first through-hole.

[0057] This application involves sequentially drilling blind holes, performing a first copper plating, a first copper reduction, drilling through holes, performing a second copper plating, resin plugging, a second copper reduction, and a third copper plating on a multilayer PCB board. This process creates high-dimensional and horizontally oriented blind holes and through holes, achieving better hole filling effect and better through-hole copper uniformity with good deep plating capability. It effectively avoids the problem of uneven copper thickness caused by insufficient deep plating capability in hole filling and through-hole plating.

[0058] In some optional embodiments, referring to Figure 2, the first copper reduction specifically includes:

[0059] 210. The first grinding process reduces the copper thickness of the first surface by 2μm-4μm. This is achieved by grinding twice using a 1.8A current, a 5mm±2mm grinding mark width, and a 2-second brush mark time. The grinding can be performed using a grinding equipment. The first grinding process includes the following steps: Based on the high current distribution characteristics of the through-hole plating, the thicker copper areas are all clamping points. Therefore, during the grinding stage, the side of the product with the clamping point is placed against the ceramic grinding wheel. The grinding pressure is greatest at this thicker copper area, resulting in a greater copper reduction effect and ensuring a reduction in the copper thickness difference across the entire PCB multilayer board.

[0060] 220, First micro-etching: Micro-etching to reduce copper thickness on the first copper surface by 22μm. In this embodiment, the first micro-etching can be performed using a micro-etching solution composed of sulfuric acid, hydrogen peroxide, water-soluble metal salts, and micro-etching stabilizers. Specifically, the micro-etching is performed through the following steps: the product with the pinched end is brought along a horizontal production line, and then the pressure of the micro-etching nozzle is increased based on the thicker copper plating area, increasing the micro-etching rate at that location to achieve a greater copper reduction effect, thereby reducing the overall copper thickness variation across the board surface.

[0061] In some optional embodiments, referring to Figure 3, the second copper reduction specifically includes:

[0062] 310. The second grinding process involves smoothing out excess resin from the resin-filled vias and grinding the copper on the second surface of the via area to reduce the copper thickness by 2μm-4μm. This is done three times using a 1.8A current, a 5mm±2mm grinding mark width, and a 2-second brush mark time. The grinding can be performed using a grinding machine. The second grinding process includes the following steps: Based on the high current distribution characteristics of the via-filling electroplating, the thicker copper areas are all at the clamping points. Therefore, during the grinding stage, the side of the product with the clamping point is placed against the ceramic grinding wheel. The grinding pressure is greatest at this thicker copper area, resulting in a greater copper reduction effect and ensuring a reduction in the copper thickness difference across the entire PCB multilayer board.

[0063] 320. The second micro-etching process involves micro-etching the capping area to reduce copper thickness by 10μm-20μm. This second micro-etching can be performed using a micro-etching solution composed of sulfuric acid, hydrogen peroxide, water-soluble metal salts, and micro-etching stabilizers. Specifically, the micro-etching process involves the following steps: the product with the pinched end is electroplated along a horizontal production line. Then, based on the thicker copper plating area, the pressure of the micro-etching nozzle is increased to increase the micro-etching rate at that location, achieving a greater copper reduction effect and thus reducing the overall copper thickness variation across the board.

[0064] 330, the third grinding step, smooths out the resin protruding after the second micro-etching. This is done with a 1.8A current, a 5mm ± 2mm grinding mark width, and a 2-second brush mark time. The third grinding removes excess resin from the capping area, making the surface smooth and facilitating the third electroplating.

[0065] In this embodiment, the product is electroplated along a horizontal production line at the end with the pinch point. Then, the pressure of the micro-etching nozzle is increased for areas with thicker copper plating, increasing the micro-etching rate at those areas to achieve a greater copper reduction effect, thereby reducing the overall copper thickness variation across the board. The first micro-etching is used to reduce the copper thickness added by the through-hole plating, from approximately 25μm~30μm to 8~10μm. The copper thickness variation is controlled to ≤5μm during the first plating. The second micro-etching is used to reduce the copper thickness for through-hole plating, from approximately 30μm~35μm to 15~20μm. Through the two-stage grinding and micro-etching process, the copper thickness variation in thick copper areas is controlled to within 10μm, ensuring that fine lines meet the etching process requirements. Large copper thickness deviations, or deviations exceeding 10μm, will result in incomplete etching, short circuits, or over-etching leading to undersized lines.

[0066] In the above embodiments, through the first, second and third grinding, based on the high current distribution characteristics of through-hole electroplating or through-hole electroplating, the thicker copper areas are all clamping points. Therefore, during the grinding stage, the side of the product with clamping points is placed against the ceramic grinding wheel. The grinding pressure is greatest at this copper-thicker position, resulting in a greater copper reduction effect and ensuring a reduction in the overall copper thickness difference of the board surface.

[0067] In some alternative embodiments, blind vias are drilled, specifically including: laser-drilled blind vias, which are created by laser drilling into a multilayer PCB board; alternatively, blind vias can be made by mechanical drilling.

[0068] The first step is plasma desmearing to remove excess resin from blind vias. Resin residue after drilling on PCB multilayer boards can be removed using any of the following methods: vacuum plasma cleaning, chemical dissolution, mechanical removal, thermal stripping, or potassium permanganate method. In this solution, organic solvents such as acetone, acetic acid, and methanol can be used to chemically dissolve the epoxy resin, thereby cleaning it. Before desmearing, target PTH holes need to be drilled on the PCB multilayer board. The initial drilling process can be mechanical drilling or laser drilling based on drilling data.

[0069] In some alternative embodiments, after the second copper reduction and before the third copper reduction, the process further includes:

[0070] The second through-hole is drilled to create a second through-hole on the PCB multilayer board. This step is used to create through-holes that do not require a cover hole. The second through-hole can be created by mechanical drilling or laser drilling.

[0071] The second plasma desmear removes excess resin from the second through-hole. Resin residue after drilling on a PCB multilayer board can be removed using any of the following methods: vacuum plasma cleaning, chemical dissolution, mechanical removal, thermal stripping, or potassium permanganate method. In this solution, organic solvents such as acetone, acetic acid, and methanol can be used to chemically dissolve the epoxy resin, thereby cleaning it. Before desmearing, the target PTH holes need to be drilled on the PCB multilayer board. The initial drilling process can be mechanical drilling or laser drilling according to the drilling data.

[0072] In some optional embodiments, the pore-filling solution consists of 9%-11% H2SO4 and 5.75%-6.25% Cu. 2+ 1.125%-1.575% leveling agent, 1.125%-1.575% brightener, 50-70 PPM CL - Composition. In this embodiment, the filling electroplating solution ratio is H2SO4: 90-110 g / L, Cu 2+ 57.5–62.5 g / L, CL - Chloride ions: 50-70 ppm; leveling agent: 11.25-15.75 ml / L; brightener: 11.25-15.75 ml / L. Chloride ions stabilize the copper plating lattice quality and enhance the ductility of the copper plating.

[0073] In some optional embodiments, the non-pore-filling solution consists of 22.5%-27% H2SO4 and 3.375%-4.15% Cu. 2+ 0.85%-1.15% leveling agent, 0.055%-0.105% gloss agent, 0.75-1.25% leveling agent, 50-70 PPM CL - Composition. In this embodiment, the non-filling solution, i.e., the through-hole plating solution, contains H2SO4: 250-270 g / L and Cu. 2+ 33.75—41.5 g / L, CL - The concentrations of various plating agents are as follows: H₂SO₄: 50-70 ppm; leveling agent: 8.5-11.5 ml / L; brightener: 0.55-1.05 ml / L; wetting agent: 7.5-12.5 ml / L. The high acidity of H₂SO₄ provides a more uniform current distribution. A low copper ratio reduces the copper plating speed in high-current areas and minimizes uneven copper plating between high and low potential areas. Furthermore, the reverse current in the pulse plating process helps reduce the thickness of copper in high-potential areas. Chloride ions stabilize the copper plating lattice quality and enhance the ductility of the copper plating.

[0074] In some optional embodiments, the pulse electroplating process for the second and third copper deposits includes six stages. The primary function of PTH (Pulse-Through Plating) is to chemically deposit a thin layer of metallic copper on the non-conductive hole wall substrate of the drilled via, serving as the base for subsequent copper electroplating. Flash plating coats the copper deposited in the via with a base copper layer approximately 5-10 μm thick, allowing for pretreatment oiling, micro-etching, and pickling during VCP (Vacuum-Cured Pore Plating) to ensure the integrity of the deposited copper. Specifically, it includes:

[0075] The first stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating.

[0076] The second stage, which accounts for 30% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 20:1.

[0077] The third stage, which accounts for 25% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 18:9.

[0078] The fourth stage, accounting for 10% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 16:8.

[0079] The fifth stage, accounting for 15% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 14:7.

[0080] The sixth stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating.

[0081] [Revised according to Rule 26, 20.10.2025] See Table 1 below. Table 1 shows the pulse electroplating parameters, which can ensure uniform copper plating and meet the requirements for copper plating thickness in the second or third copper plating process.

[0082] [Revised according to Rule 26, October 20, 2025]

[0083] Table 1

[0084] Example 2:

[0085] According to another aspect of the embodiments of this application, an HDI circuit board manufacturing apparatus is provided, which is used to perform the above-described HDI circuit board manufacturing method to manufacture a printed circuit board.

[0086] The following steps can be performed using the apparatus of this application:

[0087] Drill blind holes to obtain a multilayer PCB board and create blind holes in the multilayer PCB board;

[0088] The first copper production involves sequentially creating the first copper layer on the PCB multilayer board using a copper immersion method and a copper plating method. The copper plating solution used in the copper plating method is a hole-filling solution.

[0089] The first copper reduction involves reducing the copper content on the first surface.

[0090] The first through-hole is drilled to create the first through-hole on the PCB multilayer board.

[0091] The second copper production involves sequentially creating a second copper layer on a PCB multilayer board using three methods: copper plating, flash plating, and pulse plating. The copper plating solutions used in the flash plating and pulse plating methods are non-hole-filling solutions.

[0092] Resin plugs are used to fill the first through hole;

[0093] The second copper reduction involves reducing the copper in the cover hole area of ​​the PCB multilayer board, wherein the cover hole area is the area connected to the first through hole;

[0094] The third copper preparation involves sequentially creating a capping copper layer in the capping area using three methods: immersion copper plating, flash copper plating, and pulse electroplating. The copper plating solutions used in the flash copper plating and pulse electroplating methods are non-filling solutions.

[0095] This application separates the fabrication steps of blind vias and through vias, performing copper plating on both in a filler plating solution with a high aspect ratio copper plating solution and pulse electroplating process. This avoids the problem of uneven copper thickness caused by insufficient depth plating in filler and through-hole plating. Furthermore, if multiple copper plating processes result in copper thickness exceeding control requirements on the board surface, a special grinding and micro-etching copper reduction process is used to remove the excess copper, achieving a surface copper thickness within the allowable range for subsequent etching processes.

[0096] Example 3:

[0097] According to another aspect of the embodiments of this application, a printed circuit board is provided. The printed circuit board is manufactured by performing the HDI circuit board manufacturing method described above using the HDI circuit board manufacturing apparatus. The beneficial effects of the HDI circuit board manufacturing method, apparatus and printed circuit board of this application are as follows: By sequentially performing blind hole drilling, first copper plating, first copper reduction, first through hole drilling, second copper plating, resin plugging, second copper reduction and third copper plating on the PCB multilayer board, high vertical and horizontal blind holes and through holes are created in the PCB multilayer board; better hole filling effect and better through hole copper uniformity with good deep plating ability are obtained, effectively avoiding the problem of uneven copper thickness caused by insufficient deep plating ability of hole filling copper plating and through hole plating.

[0098] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. Similarly, for the purpose of simplification and aiding understanding of one or more aspects of the invention, in the above description of exemplary embodiments of this application, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0099] Those skilled in the art will understand that the modules in the device of the embodiment can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiment can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components, except that at least some of such features and / or processes or units are mutually exclusive.

[0100] It should be noted that the above embodiments are illustrative of this application and not restrictive, and those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A method for manufacturing an HDI circuit board, characterized in that, The method includes: Drill blind holes to obtain a multilayer PCB board and create blind holes in the multilayer PCB board; The first copper production involves sequentially creating the first copper layer on the PCB multilayer board using a copper immersion method and a copper plating method. The copper plating solution used in the copper plating method is a hole-filling solution. The first copper reduction involves reducing the copper content on the first surface. The first through-hole is drilled to create the first through-hole on the PCB multilayer board. The second copper production involves sequentially creating a second copper layer on a PCB multilayer board using three methods: copper plating, flash plating, and pulse plating. The copper plating solutions used in the flash plating and pulse plating methods are non-hole-filling solutions. Resin plugs are used to fill the first through hole; The second copper reduction involves reducing the copper in the cover hole area of ​​the PCB multilayer board, wherein the cover hole area is the area connected to the first through hole; The third copper preparation involves sequentially creating a capping copper layer in the capping area using three methods: immersion copper plating, flash copper plating, and pulse electroplating. The copper plating solutions used in the flash copper plating and pulse electroplating methods are non-filling solutions.

2. The method for manufacturing an HDI circuit board according to claim 1, characterized in that, The first copper reduction specifically includes: The first grinding process reduced the copper thickness of the first surface by 2μm-4μm. The second grinding process was carried out using a 1.8A current, a 5mm±2mm grinding mark width, and a 2-second brush mark time. The first micro-etching process involves micro-etching the copper on the first surface to reduce the copper thickness by 22 μm.

3. The method for manufacturing an HDI circuit board according to claim 1, characterized in that, The second copper reduction specifically includes: The second grinding process involves smoothing out excess resin in the resin plug hole and grinding the copper on the second surface of the cap hole area to reduce the copper thickness by 2μm-4μm. The grinding is performed three times using a current of 1.8A, a grinding mark width of 5mm±2mm, and a brush mark time of 2 seconds. The second micro-etching process involves micro-etching the cap hole area to reduce copper thickness by 10μm-20μm. The third grinding process involves smoothing the resin protruding after the second micro-etching by using a 1.8A current, a grinding mark width of 5mm ± 2mm, and a brush mark time of 2 seconds.

4. The method for manufacturing an HDI circuit board according to claim 2 or 3, characterized in that, The drilling of blind holes specifically includes: Laser-etched blind vias are created by laser etching on a multilayer PCB board. The first plasma degumming process removes excess resin from the blind holes.

5. The method for manufacturing an HDI circuit board according to claim 4, characterized in that, Following the second copper reduction and before the third copper production, the process also includes: A second through hole is drilled to create a second through hole on the PCB multilayer board. The second plasma degumming process removes excess resin from the second through-hole.

6. The method for manufacturing an HDI circuit board according to claim 1, characterized in that, The pore-filling solution consists of 9%-11% H2SO4 and 5.75%-6.25% Cu. 2+ 1.125%-1.575% leveling agent, 1.125%-1.575% brightener, 50-70 PPM CL - composition.

7. The method for manufacturing an HDI circuit board according to claim 1, characterized in that, The non-filling solution consists of 22.5%-27% H2SO4 and 3.375%-4.15% Cu. 2+ 0.85%-1.15% leveling agent, 0.055%-0.105% gloss agent, 0.75-1.25% leveling agent, 50-70 PPM CL - composition.

8. The method for manufacturing an HDI circuit board according to claim 1, characterized in that, The pulse electroplating process for the second and third copper preparations includes six stages, specifically: The first stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating. The second stage, which accounts for 30% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 20:

1. The third stage, which accounts for 25% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:3 and a positive-to-negative current time ratio of 18:

9. The fourth stage, accounting for 10% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 16:

8. The fifth stage, accounting for 15% of the entire pulse electroplating cycle, adopts a positive-to-negative current ratio of 1:2 and a positive-to-negative current time ratio of 14:

7. The sixth stage, accounting for 15% of the entire pulse electroplating cycle, uses 100% positive current for pulse electroplating.

9. An HDI circuit board manufacturing apparatus, characterized in that, The apparatus is used to perform the HDI circuit board manufacturing method according to any one of claims 1-8 to manufacture a printed circuit board.

10. A printed circuit board, characterized in that, The printed circuit board is manufactured by performing an HDI circuit board manufacturing method as described in any one of claims 1-8 using the HDI circuit board manufacturing apparatus as described in claim 9.

Images