Semiconductor device and manufacturing method therefor, integrated circuit, and electronic apparatus

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and disclosed are a semiconductor device and a manufacturing method therefor, an integrated circuit, and an electronic apparatus. The semiconductor device comprises a first chip and a second chip that are bonded to each other, a via, a conductive pillar located in the via, a first insulating protective layer, and a buffer layer. The first chip comprises a first substrate and a redistribution layer located between the first substrate and the second chip. The via passes through the first substrate and a plurality of dielectric layers of the redistribution layer from the side of the first substrate distant from the second chip. The first insulating protective layer is located in the via, and is annularly arranged between the first substrate and the conductive pillar. The buffer layer is annularly arranged between the first insulating protective layer and the conductive pillar, and between each dielectric layer and the conductive pillar. The mechanical strength of the buffer layer is greater than the mechanical strength of each dielectric layer. The first insulating protective layer can not only protect the side wall of the first substrate, but also insulate the first substrate from the conductive pillar. The buffer layer can relieve stress on the dielectric layers, thereby preventing cracking of the dielectric layers.

Description

Semiconductor devices and their fabrication methods, integrated circuits, electronic devices

[0001] This application claims priority to Chinese patent application filed on February 5, 2025, with application number 202510130832.3 and entitled "Semiconductor device and preparation method thereof, integrated circuit, electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, integrated circuits, and electronic devices. Background Technology

[0003] Through silicon via (TSV) technology is a high-density packaging technology that enables vertical electrical interconnection between chips by filling conductive materials such as copper, tungsten, and polysilicon. It has advantages such as reducing package size and increasing the integration density of integrated circuits, and can therefore be applied to integrated circuits, such as three-dimensional integrated circuits (3D-ICs).

[0004] In the process of fabricating integrated circuits, the TSV process can be divided into three stages: front-end TSV (TSV-first), middle-end TSV (TSV-middle), and back-end TSV (TSV-last). Taking TSV-last as an example, TSVs are usually fabricated after the front-end and back-end stages of the wafer are completed. At this stage, an etching process is required to form a via through the low-k dielectric material in the redistribution layer (RDL), and then conductive material is filled into the via.

[0005] However, during the subsequent annealing and / or hot loading processes of TSV, cracking of materials with low dielectric constants is likely to occur, affecting the structural and electrical integrity of the device and reducing its reliability. Summary of the Invention

[0006] This application provides a semiconductor device and its fabrication method, an integrated circuit, and an electronic device, which are used to reduce the risk of damage to the dielectric layer in the semiconductor device and improve the reliability of the semiconductor device.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, a semiconductor device is provided, comprising: a first chip and a second chip bonded together, a via, conductive pillars, a first insulating protective layer, and a buffer layer. The first chip includes a first substrate and a redistribution layer, the redistribution layer being located between the first substrate and the second chip, and including a plurality of stacked dielectric layers. The via extends from the side of the first substrate away from the second chip, penetrating the first substrate and the plurality of dielectric layers. The conductive pillars are located within the via. The first insulating protective layer is located within the via and is circumferentially disposed between the first substrate and the conductive pillars. The buffer layer is located within the via and is circumferentially disposed between the first insulating protective layer and the conductive pillars, and between each dielectric layer and the conductive pillars. The mechanical strength of the buffer layer is greater than the mechanical strength of each dielectric layer.

[0009] The semiconductor device provided in some embodiments of this application, by setting a first chip and a second chip bonded to each other, can utilize the second chip to provide a carrier and support for the first chip, which facilitates etching of the first substrate and redistribution layer in the first chip from the back side of the first chip (that is, the side of the first substrate away from the second chip) to form a via through multiple dielectric layers in the first substrate and redistribution layer.

[0010] Furthermore, by providing a first insulating protective layer that is arranged in a ring between the first substrate and the conductive post within the via, the first substrate and the conductive post can be separated. This not only achieves insulation between the first substrate and the conductive post, preventing short circuits between them, but also protects the sidewalls of the first substrate used to form the via, preventing damage to the first substrate during the etching of the redistribution layer to form the via.

[0011] Furthermore, by setting a buffer layer within the via, placing the buffer layer between each dielectric layer and the conductive pillar, and setting the mechanical strength of the buffer layer to be greater than that of each dielectric layer, the stress resistance of the buffer layer is superior to that of each dielectric layer. This avoids direct contact between the conductive pillar and the dielectric layer during the fabrication of the semiconductor device. The buffer layer with good stress resistance effectively blocks the stress generated by the conductive pillar and the stress generated between the conductive pillar and the first substrate, alleviating and reducing the stress transmitted to the dielectric layer. This provides better protection for the dielectric layer, reduces or even eliminates the risk of cracking in the dielectric layer itself, ensures the structural and electrical integrity of the semiconductor device, and improves the reliability of the semiconductor device.

[0012] In addition, the buffer layer can fill and repair the abnormal morphology of the sidewalls corresponding to the vias in the redistribution layer, providing a smoother surface for the formation of the subsequent conductive pillars. This is beneficial for forming a structurally complete conductive pillar and reducing the risk of stress concentration.

[0013] In one possible implementation of the first aspect, the buffer layer is made of at least one of silicon oxide, silicon nitride, or silicon carbonitride. Using at least one of these materials to form the buffer layer ensures that the mechanical strength of the buffer layer is greater than that of each dielectric layer, thereby ensuring that the buffer layer provides good protection to the dielectric layers.

[0014] In a second aspect, a semiconductor device is provided, comprising: a first chip and a second chip bonded together, a via, conductive pillars, a first insulating protective layer, and a buffer layer. The first chip includes a first substrate and a redistribution layer, the redistribution layer being located between the first substrate and the second chip, and including a plurality of stacked dielectric layers. The via extends through the first substrate and the plurality of dielectric layers from a side of the first substrate away from the second chip. The conductive pillars are located within the via. The first insulating protective layer is located within the via and is circumferentially disposed between the first substrate and the conductive pillars. The buffer layer is located within the via and is circumferentially disposed between the first insulating protective layer and the conductive pillars, and between each dielectric layer and the conductive pillars. The material of the buffer layer includes at least one of silicon oxide, silicon nitride, or silicon carbonitride.

[0015] The semiconductor device provided in some embodiments of this application, by setting a first chip and a second chip bonded to each other, can utilize the second chip to provide a carrier and support for the first chip, which facilitates etching of the first substrate and redistribution layer in the first chip from the back side of the first chip (that is, the side of the first substrate away from the second chip) to form a via through multiple dielectric layers in the first substrate and redistribution layer.

[0016] Furthermore, by providing a first insulating protective layer that is arranged in a ring between the first substrate and the conductive post within the via, the first substrate and the conductive post can be separated. This not only achieves insulation between the first substrate and the conductive post, preventing short circuits between them, but also protects the sidewalls of the first substrate used to form the via, preventing damage to the first substrate during the etching of the redistribution layer to form the via.

[0017] Furthermore, by setting a buffer layer within the via, positioned between each dielectric layer and the conductive pillar, and using a material including at least one of silicon oxide, silicon nitride, or silicon carbonitride, the mechanical strength of the buffer layer can be greater than that of each dielectric layer. This avoids direct contact between the conductive pillars and the dielectric layer during the fabrication of the semiconductor device. The buffer layer, with its excellent stress resistance, effectively blocks the stress generated by the conductive pillars and the stress between the conductive pillars and the first substrate, mitigating and reducing the stress transmitted to the dielectric layer. This provides better protection for the dielectric layer, reducing or even eliminating the risk of cracking, ensuring the structural and electrical integrity of the semiconductor device, and improving its reliability.

[0018] In one possible implementation of the first or second aspect, the buffer layer comprises a first buffer sublayer and a second buffer sublayer stacked together, along the radial direction of the conductive post and in the direction from the conductive post to the redistribution layer. The mechanical strength of the first buffer sublayer is greater than or equal to the mechanical strength of the second buffer sublayer. This not only allows for adjustment of the overall thickness of the buffer layer but also reduces the risk of cracking in the dielectric layer itself to a greater extent.

[0019] In one possible implementation of the first or second aspect, the adhesion force between the buffer layer and the conductive pillar is greater than the adhesion force between each dielectric layer and the conductive pillar. This reduces or even eliminates the risk of cracking at the interface between the buffer layer and the conductive pillar during thermal expansion of the conductive pillar.

[0020] In one possible implementation of the first or second aspect, the buffer layer comprises a first buffer sublayer and a second buffer sublayer stacked together, along the radial direction of the conductive post and in the direction from the conductive post to the redistribution layer. The adhesion force between the first buffer sublayer and the conductive post is greater than or equal to the adhesion force between the second buffer sublayer and the conductive post. This not only allows for adjustment of the overall thickness of the buffer layer but also significantly reduces the risk of cracking at the interface where the dielectric layer and the buffer layer contact.

[0021] In one possible implementation of the first or second aspect, the outer diameter of the first insulating protective layer is larger than the outer diameter of the buffer layer.

[0022] In one possible implementation of the first or second aspect, the first insulating protective layer is located on the side of the redistribution layer away from the second chip. The outer surface of the first insulating protective layer is connected to the outer surface of the buffer layer, forming a first stepped surface.

[0023] In one possible implementation of the first or second aspect, under the same etching conditions, the etching rate of each dielectric layer is greater than the etching rate of the first insulating protective layer. That is, during the etching of the dielectric layers, it is difficult to etch the first insulating protective layer. This improves the protective effect of the first insulating protective layer on the first substrate during the etching of the dielectric layers to form vias, preventing damage to the sidewalls of the first substrate used to form the vias. Furthermore, it also improves the dimensional uniformity of the portion of the via corresponding to the first substrate.

[0024] In one possible implementation of the first or second aspect, the first chip further includes an etch stop layer located between the second chip and the redistribution layer. The via also penetrates the etch stop layer, and a buffer layer extends into the etch stop layer. Accordingly, during the formation of the via, the first substrate and multiple dielectric layers are first etched into the etch stop layer, then the buffer layer is formed, and finally the buffer layer above the via interconnect layer and the remaining portion of the etch stop layer are etched away. This arrangement reduces the risk of material from the interconnect pattern splashing onto the sides of the dielectric layer when etching the via to the interconnect layer, avoiding interference with the filling of the conductive pillars and reducing the risk of material diffusion in the dielectric layer. Furthermore, it reduces the difficulty of controlling etching uniformity during a one-step etching to the via interconnect layer.

[0025] In one possible implementation of the first or second aspect, the surface of the etch stop layer closest to the first substrate and the portion of the etch stop layer in contact with the buffer layer constitute a second step surface. The second step surface effectively demonstrates that the buffer layer does not completely penetrate the etch stop layer, thus reducing the amount of interconnect pattern material splashed onto the inner surface of the dielectric layer.

[0026] In one possible implementation of the first or second aspect, the first chip further includes a via interconnect layer located between the second chip and the etch stop layer. Vias extend into interconnect patterns within the via interconnect layer, and conductive pillars contact the interconnect patterns. The conductive pillars enable interconnection between themselves and external structures.

[0027] In one possible implementation of the first or second aspect, the second chip further includes a via interconnect layer. The vias also penetrate the bonding surfaces of the first and second chips and extend to the interconnect pattern in the via interconnect layer, with conductive posts contacting the interconnect pattern. In this case, the second chip can form a shorter vertical electrical interconnect with the first chip via the conductive posts.

[0028] In one possible implementation of the first or second aspect, the semiconductor device further includes a second insulating protective layer located within the via and extending from the first substrate to the via interconnect layer. The second insulating protective layer surrounds the conductive pillar and is located between the buffer layer and the conductive pillar. The mechanical strength of the second insulating protective layer is greater than or equal to the mechanical strength of the buffer layer. The provision of the second insulating protective layer prevents other structures between the via interconnect layer and the etch stop layer (e.g., the second substrate in the second chip) from directly contacting the conductive pillar, thereby avoiding short circuits in the conductive pillars. Furthermore, the second insulating protective layer provides good protection for the buffer layer; it prevents the transfer of cracking phenomena from the dielectric layer itself to the second insulating protective layer, thus helping to ensure the structural integrity of the second insulating protective layer.

[0029] In one possible implementation of the first or second aspect, the adhesion force between the second insulating protective layer and the conductive pillar is greater than or equal to the adhesion force between the buffer layer and the conductive pillar. This allows for better adhesion between the second insulating protective layer and the conductive pillar, thereby reducing the risk of cracking at the interface where the dielectric layer and the buffer layer contact.

[0030] In one possible implementation of the first or second aspect, the first insulating protective layer also covers the surface of the first substrate away from the second chip. This provides more comprehensive protection for the first substrate and avoids damage to the surface of the first substrate away from the second chip during the formation of the via.

[0031] In one possible implementation of the first or second aspect, the material of the first insulating protective layer includes at least one of silicon oxide or silicon nitride.

[0032] In one possible implementation of the first or second aspect, the material of the first insulating protective layer and the buffer layer are the same. This allows the first insulating protective layer and the buffer layer to be formed using the same process parameters, which helps to simplify the fabrication process of the semiconductor device.

[0033] Thirdly, a method for fabricating a semiconductor device is provided, the method comprising: bonding a first chip and a second chip, the first chip including a first substrate and a redistribution layer, the redistribution layer being located between the first substrate and the second chip, and including a plurality of dielectric layers stacked thereon; forming a via penetrating the first substrate and the plurality of dielectric layers from the side of the first substrate away from the second chip; forming a first insulating protective layer, a buffer layer, and a conductive pillar within the via; the first insulating protective layer being disposed in a ring between the first substrate and the conductive pillar; the buffer layer being disposed in a ring between the first insulating protective layer and the conductive pillar, and between the plurality of dielectric layers and the conductive pillar; the mechanical strength of the buffer layer being greater than the mechanical strength of the plurality of dielectric layers.

[0034] The semiconductor device fabrication method provided in some embodiments of this application, by bonding a first chip and a second chip together, can utilize the second chip to provide a carrier and support for the first chip, facilitating the etching of the first substrate and redistribution layer in the first chip from the back side of the first chip (i.e., the side surface of the first substrate away from the second chip), forming vias that penetrate multiple dielectric layers in the first substrate and redistribution layer.

[0035] Furthermore, by forming a first insulating protective layer, a buffer layer, and a conductive pillar within the via, and by having the first insulating protective layer encircle between the first substrate and the conductive pillar, the first substrate and the conductive pillar can be separated. This achieves insulation between the first substrate and the conductive pillar, preventing short circuits between them, and also protects the sidewalls of the first substrate used to form the via, preventing damage to the first substrate during the etching of the redistribution layer to form the via.

[0036] By forming a buffer layer between each dielectric layer and the conductive pillar, and ensuring that the mechanical strength of the buffer layer is greater than that of each dielectric layer, the stress resistance of the buffer layer is superior to that of each dielectric layer. This allows for the avoidance of direct contact between the conductive pillar and the dielectric layer during the fabrication of semiconductor devices. The buffer layer, with its excellent stress resistance, effectively blocks the stress generated by the conductive pillar and the stress generated between the conductive pillar and the first substrate, thus alleviating and reducing the stress transmitted to the dielectric layer. This provides better protection for the dielectric layer, reduces or even eliminates the risk of cracking in the dielectric layer itself, ensures the structural and electrical integrity of the semiconductor device, and improves the reliability of the semiconductor device.

[0037] In addition, the buffer layer can fill and repair the abnormal morphology of the sidewalls corresponding to the vias in the redistribution layer, providing a smoother surface for the formation of the subsequent conductive pillars. This is beneficial for forming a structurally complete conductive pillar and reducing the risk of stress concentration.

[0038] In one possible implementation of the third aspect, forming a via and a first insulating protective layer includes: forming a first sub-via penetrating a first substrate; forming a first insulating protective film covering the sidewalls and bottom wall of the first substrate and the first sub-via; and etching, based on the first sub-via, a portion of the first insulating protective film covering the bottom wall of the first sub-via and a plurality of dielectric layers to form a second sub-via communicating with the first sub-via.

[0039] By dividing the etching of the via into etching of the first substrate and etching of multiple dielectric layers in the redistribution layer, and forming a first insulating protective film before etching the redistribution layer, on the one hand, the first substrate can be protected to prevent damage to the sidewalls of the first substrate used to form the first sub-via; on the other hand, insulation can be provided between the first substrate and the subsequently formed conductive pillars to avoid short circuit between the first substrate and the conductive pillars.

[0040] In one possible implementation of the third aspect, the first chip further includes an etch stop layer located between the second chip and the redistribution layer. During the formation of the second sub-via based on the first sub-via, a portion of the etch stop layer is also etched to extend the second sub-via into the etch stop layer.

[0041] This allows the portion of the etch stop layer not penetrated by the second sub-via to shield the interconnect layer on the side of the etch stop layer away from the first substrate, preventing premature exposure of the interconnect layer on that side and avoiding material backsplattering of the interconnect pattern in the interconnect layer. Furthermore, etching the second sub-via in stages, rather than directly etching to the interconnect layer in one step, reduces the difficulty of controlling etching uniformity in a single etching step.

[0042] In one possible implementation of the third aspect, forming a buffer layer and a conductive pillar includes: forming a buffer film covering the sidewalls and bottom wall of the first insulating protective layer and the second sub-via; removing a portion of the buffer film covering the bottom wall of the second sub-via and etching the remaining portion of the aforementioned etch stop layer; and filling the via with a conductive material to form a conductive pillar.

[0043] In one possible implementation of the third aspect, the second chip further includes an interconnect layer; before removing the portion of the buffer film covering the bottom wall of the second sub-via and etching the remaining portion of the etch stop layer, the fabrication method further includes: etching the portion of the buffer film covering the bottom wall of the second sub-via, the remaining portion of the etch stop layer, and the bonding surface of the first and second chips based on the first and second sub-vias to form a third sub-via extending into the interconnect layer. A second insulating protective layer is formed covering the sidewalls of the first, second, and third sub-vias, exposing the interconnect pattern.

[0044] Fourthly, an integrated circuit is provided, comprising: a semiconductor device and a packaging structure as described in any of the design embodiments of the first aspect. The semiconductor device is packaged within the packaging structure.

[0045] Fifthly, an electronic device is provided, comprising: an integrated circuit and a circuit board as described in any of the design embodiments of the fourth aspect. The circuit board is electrically connected to the integrated circuit.

[0046] The technical effects of any of the design methods in the fourth or fifth aspects can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0047] Figure 1 is an architectural diagram of an electronic device provided in an embodiment of this application;

[0048] Figure 2 is a partial structural diagram of an electronic device provided in an embodiment of this application;

[0049] Figure 3 is a structural diagram of an integrated circuit provided in an embodiment of this application;

[0050] Figure 4 is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of this application;

[0051] Figure 5a is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0052] Figure 5b is a top view of the structure corresponding to the semiconductor device shown in Figure 5a;

[0053] Figure 6 is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0054] Figure 7a is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0055] Figure 7b is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0056] Figure 8 is a cross-sectional view of another semiconductor device provided in an embodiment of this application;

[0057] Figure 9 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0058] Figures 10a-10g are cross-sectional structural diagrams corresponding to each step in a method for fabricating a semiconductor device according to an embodiment of this application;

[0059] Figures 11a-11b are cross-sectional structural diagrams corresponding to each step in another method for fabricating a semiconductor device provided by an embodiment of this application;

[0060] Figures 12a-12b are cross-sectional structural diagrams corresponding to each step in another method for fabricating a semiconductor device provided by an embodiment of this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0062] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. "a and / or b" includes the following three combinations: only a, only b, and a combination of a and b. "Spacing" refers, for example, to the minimum distance between two adjacent structures.

[0063] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply difference. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0064] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0065] In this application embodiment, the terms "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can vary accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the illustrations do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the areas shown in this application, but rather include shape deviations due to, for example, manufacturing. For example, an etched area shown as rectangular would typically have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0066] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0067] This application provides an electronic device. This electronic device can be applied to various communication systems or protocols, such as Bluetooth (BT) communication technology, Global Positioning System (GPS) communication technology, Global System for Mobile Communication (GSM) communication technology, Wireless Fidelity (WiFi) communication technology, Wideband Code Division Multiple Access (WCDMA) communication technology, Long Term Evolution (LTE) technology, 5G communication technology, and other future communication technologies.

[0068] The electronic devices in this application embodiment can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. Electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc., and this application embodiment is not limited in this regard.

[0069] Figure 1 is an architectural diagram of an electronic device provided in an embodiment of this application. As shown in Figure 1, the electronic device 1000 includes components such as a memory 100, a processor 200, an input device 300, and an output device 400. Those skilled in the art will understand that the structure of the electronic device shown in Figure 1 does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in Figure 1, or may combine some of the components shown in Figure 1, or may have a different component arrangement than that shown in Figure 1.

[0070] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area can store data created based on the use of the electronic device (such as audio data, image data, phonebook, etc.). Furthermore, the memory 100 includes external memory 110 and internal memory 120. Data stored in external memory 110 and internal memory 120 can be transferred between each other. External memory 110 includes, for example, a hard disk, USB flash drive, floppy disk, etc. Internal memory 120 includes, for example, static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory, etc.

[0071] The processor 200 is the control center of the aforementioned electronic device 1000. It connects to various parts of the electronic device 1000 via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 100, and by calling data stored in the memory 100, it performs various functions and processes data of the electronic device 1000, thereby providing overall monitoring of the electronic device 1000. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, or other application-specific integrated circuits (ASICs). In Figure 1, the processor 200 is taken as a CPU. The CPU may include an arithmetic logic unit (ALU) 210 and a control unit 220. The ALU 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and the processed results are typically sent back to the internal memory 120. The controller 220 can control the arithmetic logic unit 210 to process data, and the controller 220 can also control the external memory 110 and the internal memory 120 to store or retrieve data. The memory 100 can store data generated by the processor 200.

[0072] Input device 300 is used to receive input digital or character information and generate key signal inputs related to user settings and function control of electronic device 1000. For example, input device 300 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. Optionally, the touchscreen may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, transmitting the signal to the touch controller. The touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to processor 200, and can receive and execute commands from processor 200. Furthermore, touchscreens can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control buttons, power switch buttons, etc.), trackballs, mice, and joysticks. The controller 220 in the processor 200 can also control the input device 300 to receive or not receive input signals. Furthermore, the input digital or character information received by the input device 300, as well as key signal inputs related to user settings and function control of the electronic device, can be stored in the internal memory 120.

[0073] Output device 400 is used to output signals corresponding to data input by input device 300 and stored in internal memory 120. For example, output device 400 outputs audio signals or video signals. The controller 220 in the processor 200 can also control output device 400 to output signals or not output signals.

[0074] It should be noted that the thick arrows in Figure 1 represent data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a one-way arrow between input device 300 and internal memory 120 indicates that data received by input device 300 is transmitted to internal memory 120. As another example, a two-way arrow between arithmetic logic unit 210 and internal memory 120 indicates that data stored in internal memory 120 can be transmitted to arithmetic logic unit 210, and data processed by arithmetic logic unit 210 can be transmitted to internal memory 120. The thin arrows in Figure 1 represent components that controller 220 can control. For example, controller 220 can control external memory 110, internal memory 120, arithmetic logic unit 210, input device 300, and output device 400.

[0075] Optionally, the electronic device 1000 shown in Figure 1 may also include various sensors, such as gyroscope sensors, hygrometer sensors, infrared sensors, magnetometer sensors, etc., which will not be described in detail here. Optionally, the electronic device 1000 may also include wireless fidelity (WiFi) modules, Bluetooth modules, etc., which will not be described in detail here.

[0076] Figure 2 illustrates a partial structure of the electronic device 1000. As shown in Figure 2, the electronic device 1000 may further include a circuit board 500 and an integrated circuit 600, which is disposed on the circuit board 500 and electrically connected to the circuit board 500. The circuit board 500 includes, but is not limited to, a printed circuit board (PCB).

[0077] As shown in Figure 2, the electronic device 1000 further includes a connector disposed between the circuit board 500 and the integrated circuit 600, with the integrated circuit 600 electrically connected to the circuit board 500 via the connector. The connector can be, for example, a ball grid array (BGA). The integrated circuit 600 can be a 3D IC.

[0078] The number of integrated circuits 600 can be one or more. When there are multiple integrated circuits 600, they can be laid flat on the circuit board 500 or stacked along the thickness direction of the circuit board 500. The integrated circuits 600 can be applied to logic devices (such as the arithmetic unit 210, controller 220, sensor, etc. in the processor 200) or to memory devices (such as the external memory 110, internal memory 120, etc. in the memory 100). This application embodiment does not limit this.

[0079] Figure 3 illustrates the structure of an integrated circuit 600. The integrated circuit 600 may include a semiconductor device 610 and a package structure 620. The semiconductor device 610 is packaged inside the package structure 620, and the number of semiconductor devices 610 may be one or more. Figure 3 illustrates two semiconductor devices 610.

[0080] It is understood that the structure illustrated in the embodiments of this application does not constitute a specific limitation on the integrated circuit 600. In other embodiments of this application, the integrated circuit 600 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements.

[0081] In some examples, as shown in FIG3, the above-mentioned packaging structure 620 may include a packaging substrate 621 and a heat sink 622, wherein the heat sink 622 is connected to the packaging substrate 621 through an adhesive layer or a solder layer.

[0082] For example, the packaging substrate 621 has high heat dissipation and conductivity. The material of the packaging substrate 621 may include composite materials, and the structure of the packaging substrate 621 may be a stacked structure. Optionally, the material of the packaging substrate 621 may include copper and molybdenum, and the packaging substrate 621 is composed of sequentially stacked copper layers / molybdenum layers / copper layers.

[0083] For example, the semiconductor device 610 can be electrically connected to the packaging substrate 621 and encapsulated within the space formed by the heat sink 622 and the packaging substrate 621. The semiconductor device 610 can be flip-chip bonded to the packaging substrate 621, thereby enabling electrical communication with the circuit board 500 through the packaging substrate 621.

[0084] In some embodiments, as shown in FIG4, the semiconductor device 610 may include: a first substrate 11, a redistribution layer 12, and conductive pillars 14.

[0085] The material of the first substrate 11 may include, for example, silicon or some other suitable semiconductor material. Optionally, the first substrate 11 may be a silicon substrate, which may be a fabricated wafer or a bare die. For example, multiple field-effect transistors or similar structures may be integrated into the first substrate 11.

[0086] The aforementioned redistribution layer 12 is located on one side of the first substrate 11. For example, the redistribution layer 12 includes a plurality of dielectric layers 121, which are stacked along the thickness direction of the first substrate 11. Optionally, the number of dielectric layers 121 can be two, three, four, or even more. Further, as shown in FIG4, the redistribution layer 12 may also include metal wiring 122 in the same layer as each dielectric layer 121. Here, "in the same layer" means that the dielectric layer 121 has a plurality of openings penetrating it, and the metal wiring 122 disposed in the same layer as the dielectric layer 121 fills the plurality of openings. FIG4 only schematically shows the metal wiring 122 and does not limit its specific structure.

[0087] For example, the material of each dielectric layer 121 includes a dielectric material with a low dielectric constant, which may be less than the dielectric constant of undoped silicon oxide. For example, the dielectric layer 121 has a large number of micropores or voids. The material of the dielectric layer 121 includes, but is not limited to, at least one of the following: porous carbon-doped silicon oxide (CDO), porous methyl silsesquioxane (MSQ), porous hydrogen silsesquioxane (HSQ), and porous organosilicate glass (OSG). Of course, the material of the dielectric layer 121 may also include other porous materials, which is not limited in this embodiment. The dielectric materials included in different dielectric layers 121 may be the same or different; correspondingly, the dielectric constants of different dielectric layers 121 may be the same or different.

[0088] Here, the dielectric layer 121 is formed using a dielectric material with a low dielectric constant, which helps to reduce the in-layer capacitance in the metal interconnect and improve the operating speed of the integrated circuit 600 that uses the aforementioned semiconductor device 610.

[0089] Referring again to Figure 4, the semiconductor device 610 has a via H, which may be a through-silicon via (TSV). The via H penetrates multiple dielectric layers 121 in the redistribution layer 12 and extends into the first substrate 11. The aforementioned conductive pillars 14 fill the via H. The material of the conductive pillars 14 includes, for example, conductive materials such as metals; optionally, the material of the conductive pillars 14 includes, but is not limited to, copper.

[0090] Understandably, the dielectric material comprising the dielectric layer 121, with its low dielectric constant, has a low elastic modulus. Furthermore, the coefficients of thermal expansion (CTE) of the materials of the first substrate 11 and the conductive pillar 14 differ. During subsequent TSV annealing and / or hot-loading processes, the conductive pillar 14 is prone to expansion, potentially compressing the dielectric layer 121. Additionally, the stress generated between the first substrate 11 and the conductive pillar 14 can easily be transferred to the dielectric layer 121, leading to cracking within the dielectric layer 121 itself (as shown by dashed circle A in Figure 4), or cracking at the interface where the dielectric layer 121 contacts the conductive pillar 14 (as shown by dashed circle B in Figure 4). This can affect the structural and electrical integrity of the semiconductor device, reducing its reliability.

[0091] Based on this, the present application embodiments have improved the structure of the semiconductor device 610 and the method for fabricating the semiconductor device 610. The following is a schematic description with reference to the accompanying drawings.

[0092] In some examples, as shown in Figures 5a and 6-8, the semiconductor device 610 may include: a first chip 1 and a second chip 2.

[0093] For example, the first chip 1 can be a wafer with circuit functionality, or it can refer to a bare chip (die) obtained by dicing a wafer with circuit functionality. A bare chip can also be called a die or particle. The second chip 2 can be a wafer with circuit functionality, or it can be a bare chip obtained by dicing a wafer with circuit functionality. In some scenarios, the second chip 2 can also be a wafer or glass substrate without circuit functionality, serving only a supporting function.

[0094] The first chip 1 and the second chip 2 are bonded together. In Figures 5a and 6-8, the dashed line between the first chip 1 and the second chip 2 refers, for example, to the bonding surfaces of the first chip 1 and the second chip 2. Various bonding methods are available between the first chip 1 and the second chip 2, and the specific method can be selected according to actual needs. For example, bonding methods between the first chip 1 and the second chip 2 include, but are not limited to, fusion bonding, hybrid bonding, and temporary bonding.

[0095] Referring again to Figures 5a and 6-8, the first chip 1 includes a first substrate 11 and a redistribution layer 12. The redistribution layer 12 is located between the first substrate 11 and the second chip 2, that is, the second chip 2, the redistribution layer 12, and the first substrate 11 are stacked sequentially along the thickness direction of the first substrate 11. The redistribution layer 12 includes multiple stacked dielectric layers 121. Furthermore, the redistribution layer 12 may also include metal wiring 122 disposed on the same layer as each dielectric layer 121. For details regarding the first substrate 11, dielectric layer 121, and metal wiring 122, please refer to the relevant descriptions above; they will not be repeated here.

[0096] For example, as shown in FIG5a, the redistribution layer 12 may further include a plurality of metal diffusion barrier layers 123, each metal diffusion barrier layer 123 being located between two adjacent dielectric layers 121. Along the thickness direction of the first substrate 11, the metal diffusion barrier layers 123 and dielectric layers 121 are alternately disposed. The material of the metal diffusion barrier layer 123 includes a dielectric material, optionally including, but not limited to, at least one of silicon nitride or silicon carbonitride. The dielectric constant of the material of the metal diffusion barrier layer 123 is, for example, higher than the dielectric constant of the material of the dielectric layer 121.

[0097] The aforementioned metal diffusion barrier layer 123 can block metal diffusion between two adjacent dielectric layers 121.

[0098] In some examples, as shown in Figures 5a and 6-8, the semiconductor device 610 may further include a via H. The via H extends along the thickness direction of the first substrate 11, from the side of the first substrate 11 away from the second chip 2, and penetrates the first substrate 11 and the aforementioned plurality of dielectric layers 121. Depending on the location of the interconnect layer, the via H may penetrate a portion or all of the dielectric layers 121 included in the redistribution layer 12. The accompanying figures illustrate via H penetrating all of the dielectric layers 121 as an example.

[0099] In the case where the redistribution layer 12 also includes a metal diffusion barrier layer 123, the via H may also penetrate each metal diffusion barrier layer 123.

[0100] Here, during the formation of the through hole H, the second chip 2 can provide support and load-bearing capacity for the first chip 1.

[0101] In some examples, as shown in Figures 5a and 6-8, the semiconductor device 610 may further include a conductive post 3. The conductive post 3 is located within a via H and extends along the thickness direction of the first substrate 11. For example, the depth of the via H along the thickness direction of the first substrate 11 is equal to or approximately equal to the length of the conductive post 3.

[0102] Optionally, the material of the conductive post 3 includes, but is not limited to, metallic materials such as copper. The end of the conductive post 3 furthest from the second chip 2 is used, for example, to connect to other wiring layers; the end of the conductive post 3 closest to the second chip 2 is used, for example, to connect to the interconnect pattern in the via interconnect layer, so as to electrically connect the conductive post 3 to the external structure through the interconnect pattern, thereby achieving vertical electrical interconnection. For details regarding the via interconnect layer and interconnect pattern, please refer to the relevant description below, which will not be repeated here.

[0103] Here, the first substrate 11 is located on the side of the second chip 2 away from the second chip 2, for example, referred to as the back side of the first chip 1, and the via H is formed by etching the back side of the first chip 1.

[0104] In some examples, as shown in Figures 5a and 6-8, the semiconductor device 610 may further include a first insulating protective layer 4. The first insulating protective layer 4 is located within the via H, and is arranged in a ring between the first substrate 11 and the conductive pillar 3.

[0105] For example, along the thickness direction of the first substrate 11, the size of the first insulating protective layer 4 is smaller than the depth of the via H, and the size of the first insulating protective layer 4 is greater than or equal to the thickness of the first substrate 11. Furthermore, the first insulating protective layer 4 is located on the side of the redistribution layer 12 away from the second chip 2. The first insulating protective layer 4 may cover the portion of the sidewall in the via H corresponding to the first substrate 11, while not covering or only slightly covering the portion of the sidewall in the via H corresponding to the redistribution layer 12. Optionally, as shown in FIG5a, the first insulating protective layer 4 may be located only within the via H; or, as shown in FIG6-8, a portion of the first insulating protective layer 4 may be located within the via H, and another portion may also cover the surface of the first substrate 11 on the side away from the second chip 2.

[0106] The material of the first insulating protective layer 4 includes, for example, an insulating dielectric material. The first insulating protective layer 4 separates the first substrate 11 and the conductive pillar 3, preventing direct contact between them and achieving insulation between them, thus preventing short circuits. Furthermore, the first insulating protective layer 4 also protects the first substrate 11, preventing damage to the sidewalls of the via H opposite to the first substrate 11 during the etching of the redistribution layer 12 to form the via H.

[0107] Optionally, under the same etching conditions, the etching rate of each dielectric layer 121 is greater than the etching rate of the first insulating protective layer 4. That is, under the same etching conditions, it is easier to etch the dielectric layer 121, but more difficult to etch the first insulating protective layer 4. In this way, during the etching of the dielectric layer 121 to form the via H, the etching of the first insulating protective layer 4 can be reduced. On the one hand, this is beneficial to improving the protective effect of the first insulating protective layer 4 on the first substrate 11, preventing damage to the sidewalls of the first substrate 11 used to form the via H; on the other hand, it can improve the dimensional uniformity of the portion of the via H corresponding to the first substrate 11.

[0108] In some examples, as shown in Figures 5a and 6-8, the semiconductor device 610 may further include a buffer layer 5. The buffer layer 5 is located within the via H, and is arranged in a ring between the first insulating protective layer 4 and the conductive pillars 3, and between the plurality of dielectric layers 121 and the conductive pillars 3 in the redistribution layer 12.

[0109] The buffer layer 5 covers the portion of the first insulating protective layer 4 located within the via H, and also covers the portion of the sidewall of the via H opposite to the redistribution layer 12. Correspondingly, the buffer layer 5 may cover the portions of the dielectric layers 121 exposed by the via H. If the redistribution layer 12 further includes a metal diffusion barrier layer 123, the buffer layer 5 may also cover, for example, the portions of the metal diffusion barrier layer 123 exposed by the via H.

[0110] As shown in Figure 5b, for example, the orthographic projection of the buffer layer 5 onto the first substrate 11 is annular, the orthographic projection of the first insulating protective layer 4 onto the first substrate 11 is annular, the orthographic projection of the buffer layer 5 onto the first substrate 11 surrounds the orthographic projection of the conductive post 3 onto the first substrate 11, and the orthographic projection of the first insulating protective layer 4 onto the first substrate 11 surrounds the orthographic projection of the buffer layer 5 onto the first substrate 11. The buffer layer 5 can separate the conductive post 3 from the first insulating protective layer 4, and also separate the conductive post 3 from each dielectric layer 121 in the redistribution layer 12, preventing direct contact between the conductive post 3 and each dielectric layer 121.

[0111] For example, the mechanical strength of the buffer layer 5 is greater than the mechanical strength of each of the dielectric layers 121.

[0112] It is understandable that when the mechanical strength of the buffer layer 5 is greater than that of each dielectric layer 121, the stress resistance of the buffer layer 5 will be superior to that of each dielectric layer 121. Accordingly, during the fabrication of the semiconductor device and the thermal expansion of the conductive pillar 3, the buffer layer 5, with its good stress resistance, can effectively block the stress generated by the conductive pillar 3 and the stress generated between the conductive pillar 3 and the first substrate 11, thereby alleviating and reducing the stress transmitted to the dielectric layer 121. This provides better protection for the dielectric layer 121, reducing or even eliminating the risk of cracking in the dielectric layer 121 itself. Consequently, it avoids the cracking phenomenon shown by the dashed circle A in Figure 4, ensuring the structural and electrical integrity of the semiconductor device 610 and improving its reliability.

[0113] For example, the material of the buffer layer 5 includes, but is not limited to, at least one of silicon oxide, silicon nitride, or silicon carbonitride.

[0114] When the buffer layer 5 is formed using at least one of silicon oxide, silicon nitride, or silicon carbonitride, the performance requirements of the buffer layer 5 can be met, and the mechanical strength of the buffer layer 5 can be greater than that of each dielectric layer 121. Similarly, this ensures that the buffer layer 5 has a good protective effect on the dielectric layer 121, reduces or even eliminates the risk of cracking of the dielectric layer 121 itself, and correspondingly avoids the cracking phenomenon shown by the dashed circle A in Figure 4, ensuring the structural and electrical integrity of the semiconductor device 610 and improving the reliability of the semiconductor device 610.

[0115] Furthermore, the sidewalls of the redistribution layer 12 corresponding to the via H may have a rough morphology due to etching. By setting the buffer layer 5, the abnormal morphology of the sidewalls of the redistribution layer 12 corresponding to the via H can be filled and repaired, providing a smoother surface for the subsequent formation of the conductive pillar 3. This is beneficial for forming a structurally complete conductive pillar 3 and reducing the risk of stress concentration.

[0116] In some embodiments, the adhesion between the buffer layer 5 and the conductive pillar 3 is greater than the adhesion between each dielectric layer 121 and the conductive pillar 3. Accordingly, the buffer layer 5 and the conductive pillar 3 have better adhesion, and the peel resistance between the buffer layer 5 and the conductive pillar 3 is greater than the peel resistance between the dielectric layer 121 and the conductive pillar 3.

[0117] It is understandable that in the annealing and / or heat loading processes for fabricating semiconductor devices, the closer the location is to the conductive pillar 3, the greater the thermal stress it experiences. By providing better adhesion between the buffer layer 5 and the conductive pillar 3, the risk of cracking at the interface between the buffer layer 5 and the conductive pillar 3 can be reduced or even avoided, as can the risk of cracking at the interface between the buffer layer 5 and each dielectric layer 121, thus preventing cracking at the interface shown by the dashed circle B in Figure 4.

[0118] With the buffer layer 5 having high mechanical strength and the buffer layer 5 having high adhesion to the conductive pillar 3, the cracking phenomenon of the dielectric layer 121 in different aspects can be comprehensively improved, which is conducive to further ensuring the structural and electrical integrity of the semiconductor device 610 and improving the reliability of the semiconductor device 610.

[0119] The structure of the aforementioned buffer layer 5 includes various options, which can be selected and configured according to actual needs.

[0120] In some embodiments, as shown in FIG5a, the buffer layer 5 is a structure composed of a single film layer.

[0121] In this case, the structure of the buffer layer 5 is relatively simple and easy to prepare, which helps to simplify the preparation process of the semiconductor device 610 and avoid significantly increasing the cost of the semiconductor device 610.

[0122] In other embodiments, the buffer layer 5 is a structure composed of multiple buffer sublayers. These multiple buffer sublayers are stacked sequentially along the radial direction of the conductive pillars 3 and in the direction from the conductive pillars 3 towards the redistribution layer 12. The materials used in different buffer sublayers may be the same or different.

[0123] Optionally, the buffer layer 5 may include two, three, or even more buffer sub-layers. Figures 6-8 illustrate the case where the buffer layer 5 includes two buffer sub-layers. As shown in Figures 6-8, the buffer layer 5 includes a first buffer sub-layer 51 and a second buffer sub-layer 52, which are stacked sequentially along the radial direction of the conductive post 3 and in the direction from the conductive post 3 to the redistribution layer 12. That is, the first buffer sub-layer 51 is closer to the conductive post 3 than the second buffer sub-layer 52.

[0124] For example, the adhesion between the first buffer sublayer 51 and the conductive post 3 is greater than or equal to the adhesion between the second buffer sublayer 52 and the conductive post 3. That is, along the radial direction of the conductive post 3 and in the direction from the conductive post 3 to the redistribution layer 12, the adhesion between the multiple buffer sublayers in the buffer layer 5 and the conductive post 3 decreases sequentially, and the adhesion between the buffer sublayer closer to the conductive post 3 is better.

[0125] In this way, not only can the overall thickness of the buffer layer 5 be adjusted using the first buffer sub-layer 51 and the second buffer sub-layer 52, but the risk of cracking at the interface where the dielectric layer 121 and the buffer layer 5 meet can also be reduced to a greater extent.

[0126] Furthermore, the mechanical strength of the first buffer sublayer 51 is greater than or equal to the mechanical strength of the second buffer sublayer 52. That is, along the radial direction of the conductive post 3 and in the direction from the conductive post 3 to the redistribution layer 12, the mechanical strength of the multiple buffer sublayers in the buffer layer 5 decreases sequentially, and the buffer sublayers closer to the conductive post 3 have better mechanical strength.

[0127] In this way, not only can the overall thickness of the buffer layer 5 be adjusted using the first buffer sub-layer 51 and the second buffer sub-layer 52, but the risk of cracking of the dielectric layer 121 itself can also be reduced to a greater extent.

[0128] For example, compared to the first buffer sublayer 51, the second buffer sublayer 52 has better process compatibility with the dielectric layer 121. Compared to the second buffer sublayer 52, the first buffer sublayer 51 has better density, moisture resistance, and other properties.

[0129] Other structures may also be provided in the first chip 1 mentioned above, which will be illustrated below with reference to the accompanying drawings.

[0130] In some embodiments, as shown in FIG5a and FIG6-8, the first chip 1 may further include an etch stop layer 13. The etch stop layer 13 is located between the second chip 2 and the redistribution layer 12. For example, the etch stop layer 13 is in contact with the redistribution layer 12. Optionally, the material of the etch stop layer 13 may include at least one of the following materials: silicon oxide (SiO), silicon nitride (SiN), silicon carbide nitride (SiCN), silicon carbide oxynitride (SiCNO), etc., and the embodiments of this application do not specifically limit this.

[0131] Furthermore, the via H also penetrates the etch stop layer 13, and the buffer layer 5 extends into the interior of the etch stop layer 13. The aforementioned via interconnect layer is located on the side of the etch stop layer 13 away from the first substrate 11. This means that the conductive pillar 3 also penetrates the etch stop layer 13, for example, extending into the interconnect pattern in the via interconnect layer; while the buffer layer 5 penetrates only a portion of the etch stop layer 13, but not completely.

[0132] Correspondingly, in the process of forming the via H, the first substrate 11 and multiple dielectric layers 121 are first etched into the inside of the etch stop layer 13, and then the buffer layer 5 is prepared. Then the buffer layer 5 above the via interconnect layer and the remaining part of the etch stop layer 13 are etched apart.

[0133] This configuration reduces the risk of interconnect pattern material splashing onto the inner surface of dielectric layer 121 during the etching process from via H to the interconnect layer, thus preventing interference with the filling of conductive pillars 3 and reducing the risk of interconnect pattern material diffusion within the dielectric layer. Furthermore, it also reduces the difficulty of controlling etching uniformity during the one-step etching process to the interconnect layer.

[0134] In some examples, as shown in FIG5a, when the buffer layer 5 extends into the etch stop layer 13, the orthographic projection of the buffer layer 5 onto the first substrate 11 and the orthographic projection of the etch stop layer 13 onto the first substrate 11 may partially overlap, for example. Furthermore, there is a gap between the surface of the buffer layer 5 away from the first substrate 11 and the surface of the etch stop layer 13 away from the first substrate 11. Relative to the first substrate 11, there is a height difference between the portion of the etch stop layer 13 in contact with the buffer layer 5 and the portion of the etch stop layer 13 near the first substrate 11. Correspondingly, the surface of the etch stop layer 13 near the first substrate 11 and the portion of the etch stop layer 13 in contact with the buffer layer 5 constitute a second stepped surface (as shown by the dashed coil D near the second chip 2 in FIG5a).

[0135] The second step surface setting can more clearly show that the buffer layer 5 does not completely penetrate the etch stop layer 13, ensuring the effect of reducing the material splashing of the interconnect pattern onto the inner surface of the dielectric layer 121.

[0136] As can be understood, as shown in Figures 5a and 6-8, the interconnect layer 6 includes, for example, an interconnect dielectric layer 61 and an interconnect pattern 62 disposed on the same layer as the interconnect dielectric layer 61. The material of the interconnect pattern 62 includes, but is not limited to, metallic materials such as copper and tungsten. The material of the interconnect dielectric layer 61 includes, but is not limited to, dielectric materials with low dielectric constants. Optionally, the material of the interconnect dielectric layer 61 and the material of the aforementioned dielectric layer 121 can be the same or different. The dielectric constant of the interconnect dielectric layer 61 is, for example, higher than that of the dielectric layer 121.

[0137] The aforementioned via interconnect layer 6 can also be called a via interconnect wiring layer or landing metal. The via interconnect layer 6 can serve as a stop layer for vias H. After the via H penetrates multiple dielectric layers 121 in the redistribution layer 12, it stops at the via interconnect layer 6. The conductive pillars in the via H form an interconnect with the interconnect pattern 62 in the via interconnect layer 6.

[0138] Here, the location of the interconnect layer 6 can be varied, depending on the stacking architecture of the first chip 1 and the second chip 2 in the semiconductor device 610. The specific location can be selected according to the actual design requirements.

[0139] In some embodiments, as shown in Figures 5a and 6, the via interconnect layer 6 is located within the first chip 1, as part of the first chip 1. Specifically, the via interconnect layer 6 is located between the second chip 2 and the etch stop layer 13.

[0140] Referring again to Figures 5a and 6, the via H extends into the interconnect pattern 62 in the via interconnect layer 6, and the conductive post 3 contacts the interconnect pattern 62 to form an electrical connection. The via interconnect layer 6 and the etch stop layer 13 are in direct contact, for example, without any other structure between them. The portion of the etch stop layer 13 not penetrated by the buffer layer 5 separates the buffer layer 5 from the interconnect pattern 62. Furthermore, the etch stop layer 13 and the redistribution layer 12 are in direct contact, for example, without any other structure between them.

[0141] In this case, the second chip 2 can be used as a bottom carrier, for example. The second chip 2 can be a wafer with circuit functions (or other functional devices), or a wafer or glass substrate without circuit functions (or other functional devices).

[0142] In other embodiments, as shown in Figures 7a, 7b, and 8, the via interconnect layer 6 is located within the second chip 2, as part of the second chip 2. Specifically, the via interconnect layer 6 is located on the side of the bonding surface of the first chip 1 and the second chip 2 away from the first substrate 11.

[0143] Referring again to Figures 7a, 7b, and 8, the via H also penetrates the bonding surface of the first chip 1 and the second chip 2, and extends to the interconnect pattern 62 in the via interconnect layer 6. The conductive pillar 3 contacts the interconnect pattern 62 to form an electrical connection. The etch stop layer 13 and the redistribution layer 12 are in direct contact, for example, without any other structure between them.

[0144] In this case, the second chip 2 can form a shorter vertical electrical interconnect with the first chip 1 through the conductive post 3.

[0145] Optionally, the first chip 1 and the second chip 2 can, for example, form a face-to-face (F2F) three-dimensional (3D) stacked wafer architecture. In this case, as shown in Figures 7a and 7b, the second chip 2 further includes a second substrate 21 located on the side of the interconnect layer 6 away from the first chip 1. The surface of the interconnect layer 6 closest to the first chip 1 can serve as the front side of the second chip 2 for bonding with the first chip 1. The via H, after penetrating the bonding surface of the first chip 1 and the second chip 2, can stop on the surface of the interconnect pattern 62.

[0146] Alternatively, the first chip 1 and the second chip 2 can, for example, form a face-to-back (F2B) 3D stacked wafer architecture. In this case, as shown in FIG8, the second chip 2 further includes a second substrate 21, with the via interconnect layer 6 located on the side of the second substrate 21 away from the first chip 1. The surface of the second substrate 21 closest to the first chip 1 can serve as the back surface of the second chip 2 for bonding with the first chip 1. Furthermore, the via H extends through the second substrate 21 and then stops on the surface of the interconnect pattern 62.

[0147] The second substrate 21 described above is, for example, the same as the first substrate 11, as can be seen in the above description, and will not be repeated here.

[0148] It is understandable that, when the interconnect layer 6 is located within the second chip 2, other structures may be provided between the interconnect layer 6 and the redistribution layer 12 (or etch stop layer 13). For example, in Figures 7a and 7b, an insulating layer, a bonding layer, etc., are provided between the interconnect layer 6 and the etch stop layer 13; in Figure 8, an insulating layer, a bonding layer, a second substrate 21, etc., are provided between the interconnect layer 6 and the etch stop layer 13. Since the buffer layer 5 does not completely penetrate the etch stop layer 13 and is located on the side of the etch stop layer 13 away from the second chip 2, other structures (materials including but not limited to silicon) between the interconnect layer 6 and the etch stop layer 13 may be in direct contact with the conductive pillar 3.

[0149] In some embodiments, as shown in Figures 7a, 7b, and 8, the semiconductor device 610 may further include a second insulating protective layer 7 located within the via H. The second insulating protective layer 7 extends from the first substrate 11 to the via interconnect layer 6 along the thickness direction of the first substrate 11. Furthermore, the second insulating protective layer 7 surrounds the conductive pillar 3 and is located between the buffer layer 5 and the conductive pillar 3. Accordingly, the second insulating protective layer 7 may isolate the conductive pillar 3 from other structures between the via interconnect layer 6 and the etch stop layer 13. For example, in Figure 8, the second insulating protective layer 7 may isolate the second substrate 21 and the conductive pillar 3.

[0150] The material of the second insulating protective layer 7 includes, for example, an insulating dielectric material. The provision of the second insulating protective layer 7 can prevent other structures between the via interconnect layer 6 and the etch stop layer 13 (such as the second substrate 21 mentioned above) from directly contacting the conductive pillar 3, thereby avoiding short circuits in the conductive pillar 3 and ensuring that the semiconductor device 610 has good electrical reliability.

[0151] For example, the mechanical strength of the second insulating protective layer 7 is greater than or equal to the mechanical strength of the buffer layer 5. Accordingly, the stress resistance of the second insulating protective layer 7 is greater than or equal to the stress resistance of the buffer layer 5.

[0152] This design allows the second insulating protective layer 7 to provide good protection for the buffer layer 5. On the other hand, it avoids transferring the cracking phenomenon of the dielectric layer 121 itself to the second insulating protective layer 7, which helps to ensure the structural integrity of the second insulating protective layer 7.

[0153] Furthermore, the adhesion force between the second insulating protective layer 7 and the conductive pillar 3 is greater than or equal to the adhesion force between the buffer layer 5 and the conductive pillar 3.

[0154] Since the second insulating protective layer 7 also separates the buffer layer 5 and the conductive pillar 3, by setting the second insulating protective layer 7 and the conductive pillar 3 to have a large adhesion force, the second insulating protective layer 7 and the conductive pillar 3 can have better adhesion, which reduces the risk of cracking at the interface where the dielectric layer 121 and the buffer layer 5 come into contact to a greater extent.

[0155] Here, the second chip 2 may also include a redistribution layer, the structure of which may differ from that of the redistribution layer in the first chip 1. In the structure shown in FIG7a, the redistribution layer in the second chip 2 may be located between the via interconnect layer 6 and the bonding layer, or between the via interconnect layer 6 and the second substrate 21. In the structure shown in FIG8, the redistribution layer in the second chip 2 may be located between the via interconnect layer 6 and the second substrate 21, or on the side of the via interconnect layer 6 away from the second substrate 21.

[0156] As shown in Figure 7b, when the redistribution layer in the second chip 2 is located on the side of the via interconnect layer 6 close to the first chip 1, and the via also penetrates the redistribution layer, the second insulating protective layer 7 can have the performance of a buffer layer and can act as a buffer sub-layer to protect the dielectric layer of the redistribution layer in the second chip 2. Furthermore, the redistribution layer and the via interconnect layer 6 in the second chip 2 can also be provided with an etch stop layer, similar to the second stepped surface shown in Figure 5a (as indicated by the dashed circle D). The second insulating protective layer 7 and the etch stop layer in the second chip 2 can also form a stepped surface; the preparation method of the second insulating protective layer 7 is, for example, the same as the preparation method of the buffer layer 5.

[0157] Of course, optionally, in Figure 7a, an etch stop layer may also be provided between the hole interconnect layer 6 and the bonding surface of the second chip 2.

[0158] It is understandable that, along the thickness direction of the first substrate 11, based on the different dimensions of the first insulating protective layer 4, buffer layer 5, and other structures within the through-hole H, and their positional relationships, the first insulating protective layer 4 and buffer layer 5 can be formed separately in different process steps. Accordingly, as shown in Figures 5a and 6-8, the aperture of the through-hole H can be different at different locations. For example, the aperture of the portion of the through-hole H opposite to the first substrate 11 is larger than the aperture of the portion of the through-hole H opposite to each dielectric layer 121.

[0159] Referring again to Figures 5a and 6-8, the outer diameter of the first insulating protective layer 4 is larger than the outer diameter of the buffer layer 5. The outer diameters of the first insulating protective layer 4 and the buffer layer 5 are, for example, relatively uniform at different locations. Furthermore, the inner diameter of the first insulating protective layer 4 is equal to the outer diameter of the buffer layer 5.

[0160] As can be clearly seen in Figures 5a and 6-8, the first insulating protective layer 4 is disposed around the buffer layer 5, and the buffer layer 5 extends beyond the area enclosed by the first insulating protective layer 4. The orthographic projection of the buffer layer 5 onto the first substrate 11 is located within the orthographic projection range of the first insulating protective layer 4 onto the first substrate 11, and the outer boundary of the orthographic projection of the buffer layer 5 onto the first substrate 11 coincides with the inner boundary of the orthographic projection of the first insulating protective layer 4 onto the first substrate 11.

[0161] Furthermore, along the radial direction of the through-hole H, the distance between the outer surface of the first insulating protective layer 4 and the conductive post 3 is greater than the distance between the outer surface of the buffer layer 5 and the conductive post 3. The outer surface of the first insulating protective layer 4 and the outer surface of the buffer layer 5 are connected to form a first stepped surface (as shown by the dashed circle C near the first substrate 11 in Figure 5a). The outer surface of the first insulating protective layer 4 refers to the side surface of the first insulating protective layer 4 that extends along the thickness direction of the first substrate 11 and is away from the conductive post 3. The outer surface of the buffer layer 5 refers to the side surface of the buffer layer 5 that extends along the thickness direction of the first substrate 11 and is away from the conductive post 3.

[0162] For example, the materials of the first insulating protective layer 4 include a variety of materials. Optionally, the materials of the first insulating protective layer 4 include, but are not limited to, at least one of silicon oxide or silicon nitride. By selecting these materials to form the first insulating protective layer 4, the first insulating protective layer 4 can have insulating properties, and under the same etching conditions, the etching rate of the first insulating protective layer 4 can be lower than the etching rate of the dielectric layer 121.

[0163] The materials of the first insulating protective layer 4 and the buffer layer 5 can be the same or different, depending on actual needs. When the materials of the first insulating protective layer 4 and the buffer layer 5 are the same, there may not be a clear interface between them, but there will be a relatively obvious first step surface. When the materials of the first insulating protective layer 4 and the buffer layer 5 are different, there can be both a clear interface and a relatively obvious first step surface between them.

[0164] Some embodiments of this application also provide a method for fabricating a semiconductor device, such as for fabricating the semiconductor device 610 described in any of the above embodiments. FIG9 illustrates a flowchart of a method for fabricating a semiconductor device; FIGS. 10a-10g, 11a-11b, and 12a-12b respectively illustrate the structures corresponding to each step in the method for fabricating a semiconductor device. It should be understood that the steps shown in FIG9 are not exclusive, and other steps may be performed before, after, or between any of the steps shown in FIG9. Furthermore, some steps may be performed simultaneously or in a different order than that shown in FIG9.

[0165] The fabrication method of the above-mentioned semiconductor device is illustrated below with reference to the accompanying drawings. As shown in Figure 9, the fabrication method includes steps S100-S300.

[0166] S100, as shown in FIG10a, the first chip 1 and the second chip 2 are bonded together. The first chip 1 includes a first substrate 11 and a redistribution layer 12. The redistribution layer 12 is located between the first substrate 11 and the second chip 2, and the redistribution layer 12 includes a plurality of dielectric layers 121 stacked together.

[0167] For example, before bonding the first chip 1 and the second chip 2, the first chip 1 and the second chip 2 can be fabricated first. Taking the first chip 1 as an example, multiple field-effect transistors and other structures can be integrated on the first substrate 11 using a front-end of line (FEOL) process, and then a back-end of line (BEOL) process can be used to form a redistribution layer 12 on the side of the first substrate 11 where the field-effect transistors and other structures are integrated. Afterwards, the front side of the first chip 1 (e.g., the surface of the redistribution layer 12 away from the first substrate 11) can be bonded to the second chip 2.

[0168] For details regarding the first substrate 11, the redistribution layer 12, the second chip 2, and the bonding method between the first chip 1 and the second chip 2, please refer to the relevant descriptions above, which will not be repeated here.

[0169] S200, as shown in FIG10d, a via H is formed from the side of the first substrate 11 away from the second chip 2, penetrating the first substrate 11 and the aforementioned plurality of dielectric layers 121.

[0170] The aforementioned via H can be formed using a single etching process or a multi-etching process. In this embodiment, for example, a multi-etching process is used, which helps reduce damage to the sidewalls of the via H. For details, please refer to the relevant description below; further elaboration will not be repeated here.

[0171] As shown in Figure 10g, S300 forms a first insulating protective layer 4, a buffer layer 5, and a conductive pillar 3 within the through-hole H. The first insulating protective layer 4 is arranged in a ring between the first substrate 11 and the conductive pillar 3. The buffer layer 5 is arranged in a ring between the first insulating protective layer 4 and the conductive pillar 3, and between the aforementioned plurality of dielectric layers 121 and the conductive pillar 3. The mechanical strength of the buffer layer 5 is greater than the mechanical strength of the aforementioned plurality of dielectric layers 121.

[0172] For details regarding the first insulating protective layer 4, the buffer layer 5, and the conductive pillar 3, please refer to the relevant explanations above; they will not be repeated here.

[0173] The semiconductor device fabrication method provided in some embodiments of this application, by bonding the first chip 1 and the second chip 2 together, can utilize the second chip 2 to provide a carrier and support for the first chip 1, which facilitates etching the first substrate 11 and the redistribution layer 12 in the first chip 1 from the back side of the first chip 1 (that is, the side surface of the first substrate 11 away from the second chip 2) to form a through hole H that penetrates multiple dielectric layers 121 in the first substrate 11 and the redistribution layer 12.

[0174] By forming a first insulating protective layer 4, a buffer layer 5, and a conductive pillar 3 within the through-hole H, and by making the first insulating protective layer 4 encircle between the first substrate 11 and the conductive pillar 3, the first substrate 11 and the conductive pillar 3 can be separated. This achieves insulation between the first substrate 11 and the conductive pillar 3, preventing short circuits between them, and also protects the sidewalls of the first substrate 11 used to form the through-hole H, preventing damage to the first substrate 11 during the formation of the through-hole H.

[0175] By forming a buffer layer 5 between each dielectric layer 121 and the conductive pillar 3, and ensuring that the mechanical strength of the buffer layer 5 is greater than that of each dielectric layer 121, the buffer layer 5, with its good stress resistance, can effectively block the stress generated by the conductive pillar 3 and the stress generated between the conductive pillar 3 and the first substrate 11 during subsequent annealing and / or hot loading processes. This alleviates and reduces the stress transmitted to the dielectric layer 121, thereby providing better protection for the dielectric layer 121, reducing or even eliminating the risk of cracking in the dielectric layer 121 itself, ensuring the structural and electrical integrity of the semiconductor device 610, and improving the reliability of the semiconductor device 610.

[0176] In S200 and S300 above, the step of forming the through hole H can, for example, be interspersed with the steps of forming the first insulating protective layer 4, the buffer layer 5, and the conductive pillar 3. A schematic description is provided below with reference to the accompanying drawings.

[0177] In some embodiments, forming a through hole H and a first insulating protective layer 4 includes: S310-S330.

[0178] S310, as shown in Figure 10b, forms a first sub-through hole H1 that penetrates the first substrate 11.

[0179] For example, before forming the first sub-via H1, the first substrate 11 can be thinned from the back side of the first chip 1. The thickness of the first substrate 11 after thinning is approximately 10 μm. Of course, the thickness of the first substrate 11 after thinning is not limited to this and can be adjusted according to product requirements and process complexity.

[0180] The method for forming the first sub-via H1 includes, for example, forming a mask layer on the side of the first substrate 11 away from the second chip 2 using a photolithography process, the mask layer having an opening that exposes the first substrate 11; and then etching the first substrate 11 based on the mask layer using a Bosch etching process or other reactive ion etching (RIE) process to form the aforementioned first sub-via H1.

[0181] An insulating layer (e.g., made of silicon oxide) is typically disposed between the first substrate 11 and the redistribution layer 12. Etching of the first sub-via H1 needs to stop before the dielectric layer 121 closest to the first substrate 11 in the redistribution layer 12. For example, it can stop at the surface of the redistribution layer 12 closest to the first substrate 11, or at the surface of the first substrate 11 closest to the redistribution layer 12. Alternatively, the first sub-via H1 can also stop within the insulating layer. When the first sub-via H1 stops within the insulating layer, the over-etching amount needs to be controlled to avoid abnormal morphology (e.g., footing) while fully opening the first substrate 11, and to prevent the aperture of the first sub-via H1 at the end closest to the redistribution layer 12 from being larger than the aperture at the end furthest from the redistribution layer 12.

[0182] S320, as shown in FIG10c, a first insulating protective film 4a is formed covering the sidewalls and bottom wall of the first substrate 11 and the first sub-through hole H1.

[0183] For example, a first insulating protective film 4a can be formed by depositing a dielectric material on the side surface of the first substrate 11 away from the second chip 2 and on the sidewall and bottom wall of the first sub-via H1 using plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) processes.

[0184] S330, referring to Figures 10c and 10d, based on the first sub-via H1, the portion of the first insulating protective film 4a covering the bottom wall of the first sub-via H1 and the aforementioned plurality of dielectric layers 121 are etched to form a second sub-via H2 connected to the first sub-via H1, thereby obtaining the first insulating protective layer 4. The connected first sub-via H1 and second sub-via H2 can, for example, constitute the aforementioned via H.

[0185] For example, reactive ion etching (RIE) can be used to etch the first insulating protective film 4a and the multiple dielectric layers 121. Of course, if an insulating layer is provided between the first substrate 11 and the redistribution layer 12, and an etch stop layer is provided between two adjacent dielectric layers 121, the insulating layer and the etch stop layer will also be etched simultaneously. For example, the second sub-via H2 penetrates at least all the dielectric layers 121 in the redistribution layer 12 to ensure that the formed buffer layer 5 can cover all the dielectric layers 121, thus protecting each dielectric layer 121.

[0186] In this process, the first insulating protective film 4a can be used as a hard mask. For example, during the formation of the second sub-via H2, under the same etching conditions, the etching rate of each dielectric layer 121 is greater than the etching rate of the first insulating protective layer 4. That is, during the etching of multiple dielectric layers 121, it is difficult to etch the first insulating protective layer 4.

[0187] By dividing the etching of via H into etching of the first substrate 11 and etching of multiple dielectric layers 121 in the redistribution layer 12, and forming a first insulating protective film 4a before etching the redistribution layer 12, on the one hand, the first substrate 11 can be protected to prevent damage to the sidewalls of the first substrate 11 used to form the first sub-via H1. On the other hand, insulation can be provided between the first substrate 11 and the subsequently formed conductive pillar 3 to avoid short circuit between the first substrate 11 and the conductive pillar 3.

[0188] In some embodiments, as shown in FIG10d, the first chip 1 further includes an etch stop layer 13 located between the second chip 2 and the redistribution layer 12. FIG10d is illustrated with the etch stop layer 13 and the redistribution layer 12 in direct contact.

[0189] As shown in Figure 10d, in the above S330, during the process of forming the second sub-via H2 based on the first sub-via H1, a portion of the etch stop layer 13 is also etched so that the second sub-via H2 extends into the interior of the etch stop layer 13. That is, the second sub-via H2 penetrates a portion of the etch stop layer 13, but does not completely penetrate the etch stop layer 13.

[0190] This allows the portion of the etch stop layer 13 not penetrated by the second sub-via H2 to shield the hole interconnect layer 6 on the side of the etch stop layer 13 away from the first substrate 11, preventing premature exposure of the hole interconnect layer 6 on the side of the etch stop layer 13 away from the first substrate 11 and avoiding material backsplattering of the interconnect pattern 62 in the hole interconnect layer 6. Furthermore, etching the second sub-via H2 in stages, rather than directly etching to the hole interconnect layer 6 in one step, reduces the difficulty of controlling etching uniformity in a single etching step.

[0191] In some embodiments, in the above-described S300, the formation of the buffer layer 5 and the conductive pillar 3 includes: S340-S360.

[0192] S340, as shown in Figure 10e, forms a buffer film 5a covering the sidewalls and bottom wall of the first insulating protective layer 4 and the second sub-through hole H2.

[0193] For example, PECVD or ALD processes can be used to deposit the corresponding material to obtain the buffer film 5a. Here, in the process of depositing the buffer film 5a, for example, a precursor and deposition method that do not cause significant damage to the dielectric layer 121 can be selected. The thickness of the buffer film 5a can be flexibly adjusted, for example, based on factors such as the size of the subsequently filled conductive pillars 3, the breakdown voltage, and the parasitic capacitance.

[0194] The number of buffer films 5a can be one or more. Figure 10e illustrates two buffer films 5a. The materials or deposition methods of these two buffer films 5a can be the same or different. The thicknesses of these two buffer films 5a can be the same or different. For example, the buffer film 5a closer to the dielectric layer 121 has a smaller thickness and mechanical strength, while the buffer film 5a farther from the dielectric layer 121 has a larger thickness and mechanical strength.

[0195] When there are multiple buffer films 5a, it is necessary to balance the adhesion between the different buffer films 5a, specifically the adhesion between the buffer film 5a closest to the conductive post 3 and the conductive post 3. For example, the adhesion between the buffer film 5a closest to the conductive post 3 and the conductive post 3 is greater than the adhesion between the buffer film 5a relatively far from the conductive post and the conductive post 3.

[0196] By forming a buffer film 5a, the dielectric layer 121 can be prevented from being directly impacted by the conductive material during the subsequent formation of the conductive pillar 3. On the other hand, the buffer film 5a can repair the morphology of the corresponding side of the dielectric layer 121 in the via H, which is beneficial to improving the deposition uniformity of the material in the conductive pillar 3. Furthermore, it can buffer the stress generated by the conductive pillar 3 and the stress between the conductive pillar 3 and the first substrate 11 during the thermal expansion of the conductive pillar 3, reducing the stress on the dielectric layer 121 and preventing cracking of the dielectric layer 121.

[0197] S350, as shown in FIG10f, remove the portion of the bottom wall of the buffer film 5a covering the second sub-via H2, and etch the remaining portion of the etching stop layer 13.

[0198] For example, a RIE process can be used to etch the portion of the bottom wall of the buffer film 5a covering the second sub-via H2. During this process, the etch stop layer 13 is also etched until the interconnect pattern 62 of the via interconnect layer 6 is exposed. For example, by controlling the etching conditions, the risk of the interconnect pattern 62 being splashed onto the sidewall of the dielectric layer 121 under plasma bombardment and affecting the subsequent filling of conductive material can be avoided, thus reducing the risk of material diffusion of the interconnect pattern in the dielectric layer 121.

[0199] S360, as shown in Figure 10g, is formed by filling the through hole H with conductive material to form a conductive pillar 3.

[0200] For example, the conductive materials mentioned above include, but are not limited to, copper, tungsten, and polycrystalline silicon. For instance, when the conductive material includes copper, a diffusion barrier layer can be formed using PVD or CVD processes before filling the conductive material. The material of this diffusion barrier layer includes, but is not limited to, titanium nitride (TiN) or tantalum nitride (TaN). Then, copper is filled using an electrochemical plating (ECP) process. After filling the conductive material, a chemical mechanical polishing (CMP) process can be used to remove a portion of the buffer film 5a and the conductive material covering the first insulating protective layer 4, resulting in a buffer layer 5 and a conductive pillar 3 located within the through-hole H.

[0201] To prevent excessive deformation and extrusion of the conductive pillars 3 during subsequent processing, an annealing process can be performed after filling with conductive material or after grinding to induce more noticeable extrusion of the conductive pillars 3. Then, a CMP (Continuous Metallurgical Processing) process can be used to smooth the extruded portion of the conductive pillars 3. This prevents recurrence of conductive pillar extrusion in subsequent processing, improving the reliability of the semiconductor device.

[0202] Subsequently, a dielectric material can be deposited on the side of the first insulating protective layer 4 and the conductive pillar 3 away from the second chip 2 to protect the conductive pillar 3 and prevent it from oxidizing. Of course, during the subsequent interconnection process of the end of the conductive pillar 3 away from the second chip 2, this portion of the dielectric material will be removed, exposing the conductive pillar 3.

[0203] Figures 10a-10g are all schematic diagrams illustrating the first chip 1 including the via interconnect layer 6. In the case of the second chip 2 including the via interconnect layer 6, other structures (such as a second insulating protective layer) may be formed before the conductive pillars 3 are formed.

[0204] In some embodiments, when the second chip 2 includes the via interconnect layer 6, before the above-described S350, that is, before removing the portion of the buffer film 5a covering the bottom wall of the second sub-via H2 and etching the remaining portion of the above-described etch stop layer 13, the preparation method further includes: S351-S352.

[0205] S351, as shown in Figures 11a and 12a, based on the first sub-via H1 and the second sub-via H2, the portion of the buffer film 5a covering the bottom wall of the second sub-via H2, the remaining portion of the etch stop layer 13, and the bonding surface of the first chip 1 and the second chip 2 are etched to form a third sub-via H3 extending into the interconnect pattern 62 in the hole interconnect layer 6.

[0206] For example, a RIE process can be used to etch the structure between the buffer film 5a, the etch stop layer 13, the second via H2, and the via interconnect layer 6 to obtain a third sub-via H3 that is connected to the second sub-via H2. For example, the first sub-via H1, the second sub-via H2, and the third sub-via H3 constitute via H.

[0207] S352, as shown in Figures 11b and 12b, forms a second insulating protective layer 7 covering the sidewalls of the first sub-via H1, the second sub-via H2, and the third sub-via H3, with the second insulating protective layer 7 exposing the interconnect pattern 62.

[0208] The method for forming the second insulating protective layer 7 may include: forming a second insulating protective film covering the sidewalls of the first sub-via H1, the second sub-via H2, the third sub-via H3, and the bottom wall using a PECVD process or an ALD process, and then etching the portion of the second insulating protective film covering the bottom wall of the third sub-via H3 using a process such as RIE to open the second insulating protective film and form the second insulating protective layer 7 that exposes the interconnect pattern 62.

[0209] The adhesion force between the second insulating protective layer 7 and the conductive pillar 3 is greater than or equal to the adhesion force between the buffer layer 5 and the conductive pillar 3.

[0210] By forming the second insulating protective layer 7, the rough morphology of the sidewall of the via H can be filled and repaired, reducing the sidewall roughness of the via H. This facilitates good filling of the conductive pillar material. Furthermore, the second insulating protective layer 7 can alleviate and reduce the stress transmitted to the dielectric layer 121 due to the expansion of the conductive pillar 3, thus providing better protection for the dielectric layer 121. In addition, when the third sub-via H3 penetrates the second substrate 21 in the second chip 2, an insulating effect can be formed between the second substrate 21 and the conductive pillar 3, preventing short circuits between the second substrate 21 and the conductive pillar 3.

[0211] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first chip and a second chip are bonded together. The first chip includes a first substrate and a redistribution layer. The redistribution layer is located between the first substrate and the second chip and includes a plurality of dielectric layers stacked together. A via, originating from the side of the first substrate away from the second chip, penetrates the first substrate and the plurality of dielectric layers; The conductive post is located inside the through hole; A first insulating protective layer is located inside the through hole and is arranged in a ring between the first substrate and the conductive post; A buffer layer is located within the through hole and is arranged in a ring between the first insulating protective layer and the conductive pillar, and between the plurality of dielectric layers and the conductive pillar; the mechanical strength of the buffer layer is greater than the mechanical strength of the plurality of dielectric layers.

2. The semiconductor device according to claim 1, characterized in that, The material of the buffer layer includes at least one of silicon oxide, silicon nitride, or silicon carbonitride.

3. A semiconductor device, characterized in that, The semiconductor device includes: A first chip and a second chip are bonded together. The first chip includes a first substrate and a redistribution layer. The redistribution layer is located between the first substrate and the second chip and includes a plurality of dielectric layers stacked together. A via, originating from the side of the first substrate away from the second chip, penetrates the first substrate and the plurality of dielectric layers; The conductive post is located inside the through hole; A first insulating protective layer is located inside the through hole and is arranged in a ring between the first substrate and the conductive post; A buffer layer is located within the through-hole and is arranged in a ring between the first insulating protective layer and the conductive pillar, and between the plurality of dielectric layers and the conductive pillar; the material of the buffer layer includes at least one of silicon oxide, silicon nitride, or silicon carbonitride.

4. The semiconductor device according to any one of claims 1-3, characterized in that, Along the radial direction of the conductive pillar and in the direction from the conductive pillar to the redistribution layer, the buffer layer includes a first buffer sublayer and a second buffer sublayer stacked together; The mechanical strength of the first buffer sublayer is greater than or equal to the mechanical strength of the second buffer sublayer.

5. The semiconductor device according to any one of claims 1-4, characterized in that, The adhesion force between the buffer layer and the conductive pillar is greater than the adhesion force between the plurality of dielectric layers and the conductive pillar.

6. The semiconductor device according to claim 5, characterized in that, Along the radial direction of the conductive pillar and in the direction from the conductive pillar to the redistribution layer, the buffer layer includes a first buffer sublayer and a second buffer sublayer stacked together; The adhesion force between the first buffer sublayer and the conductive pillar is greater than or equal to the adhesion force between the second buffer sublayer and the conductive pillar.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The outer diameter of the first insulating protective layer is larger than the outer diameter of the buffer layer.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The first insulating protective layer is located on the side of the redistribution layer away from the second chip; The outer surface of the first insulating protective layer and the outer surface of the buffer layer are connected to form a first stepped surface.

9. The semiconductor device according to any one of claims 1-8, characterized in that, Under the same etching conditions, the etching rate of the plurality of dielectric layers is greater than the etching rate of the first insulating protective layer.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The first chip further includes an etch stop layer, which is located between the second chip and the redistribution layer; The via also penetrates the etch stop layer, and the buffer layer extends into the interior of the etch stop layer.

11. The semiconductor device according to claim 10, characterized in that, The surface of the etching stop layer near the first substrate and the portion of the etching stop layer that contacts the buffer layer constitute a second stepped surface.

12. The semiconductor device according to claim 10 or 11, characterized in that, The first chip further includes a via interconnect layer, which is located between the second chip and the etch stop layer; The via extends into the interconnect pattern in the via interconnect layer, and the conductive post contacts the interconnect pattern.

13. The semiconductor device according to claim 10 or 11, characterized in that, The second chip also includes a via interconnect layer; The via also penetrates the bonding surfaces of the first chip and the second chip and extends to the interconnect pattern in the via interconnect layer, with the conductive post in contact with the interconnect pattern.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a second insulating protective layer, which is located within the via and extends from the first substrate to the via interconnect layer. The second insulating protective layer surrounds the conductive post and is located between the buffer layer and the conductive post; The mechanical strength of the second insulating protective layer is greater than or equal to the mechanical strength of the buffer layer.

15. The semiconductor device according to claim 14, characterized in that, The adhesion force between the second insulating protective layer and the conductive pillar is greater than or equal to the adhesion force between the buffer layer and the conductive pillar.

16. The semiconductor device according to any one of claims 1-15, characterized in that, The first insulating protective layer also covers the side surface of the first substrate away from the second chip.

17. The semiconductor device according to any one of claims 1-16, characterized in that, The material of the first insulating protective layer includes at least one of silicon oxide or silicon nitride.

18. The semiconductor device according to any one of claims 1-17, characterized in that, The material of the first insulating protective layer is the same as the material of the buffer layer.

19. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A first chip and a second chip are bonded together. The first chip includes a first substrate and a redistribution layer. The redistribution layer is located between the first substrate and the second chip and includes a plurality of dielectric layers stacked together. A via is formed from the side of the first substrate away from the second chip, penetrating the first substrate and the plurality of dielectric layers; A first insulating protective layer, a buffer layer, and a conductive pillar are formed within the through hole; the first insulating protective layer is arranged in a ring between the first substrate and the conductive pillar; the buffer layer is arranged in a ring between the first insulating protective layer and the conductive pillar, and between the plurality of dielectric layers and the conductive pillar; the mechanical strength of the buffer layer is greater than the mechanical strength of the plurality of dielectric layers.

20. The preparation method according to claim 19, characterized in that, Forming the through-hole and the first insulating protective layer includes: A first sub-through hole is formed penetrating the first substrate; A first insulating protective film is formed to cover the sidewalls and bottom wall of the first substrate and the first sub-through hole; Based on the first sub-via, the portion of the bottom wall of the first insulating protective film covering the first sub-via and the plurality of dielectric layers are etched to form a second sub-via that is connected to the first sub-via.

21. The preparation method according to claim 20, characterized in that, The first chip further includes an etch stop layer, which is located between the second chip and the redistribution layer; During the process of forming the second sub-via based on the first sub-via, a portion of the etching stop layer is also etched so that the second sub-via extends into the interior of the etching stop layer.

22. The preparation method according to claim 20 or 21, characterized in that, Forming the buffer layer and the conductive pillars includes: A buffer film is formed covering the sidewalls and bottom wall of the first insulating protective layer and the second sub-through hole; Remove the portion of the bottom wall of the buffer film covering the second sub-via, and etch the remaining portion of the etching stop layer; The through-hole is filled with conductive material to form the conductive pillar.

23. The preparation method according to claim 22, characterized in that, The second chip further includes an interconnect layer; before removing the portion of the buffer film covering the bottom wall of the second sub-via and etching the remainder of the etch stop layer, the fabrication method further includes: Based on the first sub-via and the second sub-via, the portion of the buffer film covering the bottom wall of the second sub-via, the remaining portion of the etching stop layer, and the bonding surface of the first chip and the second chip are etched to form a third sub-via extending into the interconnect pattern in the hole interconnect layer. A second insulating protective layer is formed covering the sidewalls of the first sub-via, the second sub-via, and the third sub-via, the second insulating protective layer exposing the interconnect pattern.

24. An integrated circuit, characterized in that, The integrated circuit includes: The semiconductor device is the semiconductor device as described in any one of claims 1-18; A packaging structure in which the semiconductor device is packaged.

25. An electronic device, characterized in that, The electronic device includes: The integrated circuit is the integrated circuit as described in claim 24; The circuit board is electrically connected to the integrated circuit.

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