Address parsing method, electronic device, storage medium, and computer program product

Abstract

The present disclosure relates to the technical field of data processing. Provided are an address parsing method, an electronic device, a storage medium, and a computer program product. The address parsing method comprises: acquiring an address sequence to be processed (S210); vectorizing said address sequence to obtain a target embedding vector (S220); and using an address parsing model to perform prediction on the basis of the target embedding vector, so as to obtain an address label sequence (S230).

Description

Address resolution methods, electronic devices, storage media, and computer program products

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202510134884.8, filed on February 6, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of data processing technology, specifically to an address resolution method, electronic device, storage medium, and computer program product. Background Technology

[0004] In the context of globalization, more and more companies are expanding their businesses to overseas markets. This has created a surge in demand for cross-border logistics, making it a vital force supporting international trade. Simultaneously, the application of technologies such as the Internet of Things, big data, and artificial intelligence is bringing new opportunities to the cross-border logistics industry, driving its transformation towards digitalization, intelligence, and automation.

[0005] In the cross-border logistics sector, accurate international address resolution is crucial for parcel sorting and delivery. However, due to differences in local address standards, current international address resolution accuracy is insufficient, often leading to parcels needing to be resent or returned, thus increasing logistics costs. Therefore, improving the accuracy of international address resolution is essential. Summary of the Invention

[0006] In view of the above, this disclosure provides an address resolution method, an electronic device, a storage medium, and a computer program product.

[0007] The address resolution method disclosed herein includes: obtaining an address sequence to be processed; vectorizing the address sequence to be processed to obtain a target embedding vector; and predicting the target embedding vector using an address resolution model to obtain an address label sequence. The address resolution model includes an encoder, a decoder, and a fully connected linear layer. The decoder includes a neural network, where the dimension of the output of the hidden layer in the neural network is equal to the length of the address sequence, the number of neurons in the fully connected linear layer is equal to the dimension of the address label space, and the address label sequence includes the label corresponding to each word in the address sequence to be processed.

[0008] The address resolution method disclosed herein converts address sequences into target embedding vectors and utilizes the decoder and encoder in the address resolution model to capture and process the dependencies and contextual semantics in the target embedding vectors, obtaining the original output of the decoder at each time step. The original output is then mapped to address labels through a fully connected linear layer to obtain an address label sequence. Simultaneously, by adjusting the dimension of the output of the hidden layer in the decoder, the address resolution model produces prediction results with the same length as the address sequence, promoting the convergence process, improving the efficiency of the prediction process, and saving computational resources. Attached Figure Description

[0009] Figure 1 shows a schematic diagram of the system architecture of an address resolution method provided in an embodiment of this disclosure.

[0010] Figure 2 is a flowchart illustrating an address resolution method provided in an embodiment of this disclosure.

[0011] Figure 3 shows a flowchart illustrating the steps of vectorizing the address sequence to be processed to obtain the target embedding vector according to an embodiment of this disclosure.

[0012] Figure 4 is a flowchart illustrating the steps of obtaining a target embedding vector based on the sub-word vectors corresponding to multiple address sub-words according to an embodiment of this disclosure.

[0013] Figure 5 shows a flowchart illustrating the steps of predicting the target embedding vector using an address resolution model to obtain an address tag sequence according to an embodiment of this disclosure.

[0014] Figure 6 is a flowchart illustrating the steps for obtaining the address sequence to be processed according to an embodiment of this disclosure.

[0015] Figure 7 shows a schematic diagram of the structure of an address resolution device provided in an embodiment of this disclosure.

[0016] Figure 8 shows a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] In the logistics industry, address resolution plays a crucial role. During parcel transportation, it's essential to automatically parse the address information on waybills, extracting key details such as state / province, city, street, and postal code, and then outputting this information in a structured format for easy processing and use. For example, in the logistics sorting process, based on the structured address information, parcels are sorted onto appropriate conveyor belts and sent to designated areas or distribution centers, achieving automated parcel sorting, improving sorting efficiency, and reducing logistics costs.

[0019] Currently, international address resolution faces several technical challenges. First, addresses are written in different languages ​​around the world, requiring address resolution systems to handle multiple languages, including semantic understanding and character set support. Second, address formats vary significantly across countries and regions, and even within the same country and city, address formats may differ, increasing the complexity of resolution.

[0020] One approach in related technologies uses probabilistic machine learning models such as Hidden Markov Models (HMMs) and Conditional Random Fields (CRFs) for address resolution. This method can handle the uncertainty and dependencies in address data, but it lacks an understanding of the semantics of multilingual international addresses. Another approach uses CRFs trained with an average perceptron to improve the accuracy and efficiency of international address resolution, but this method cannot capture the contextual semantics of words in international addresses.

[0021] To address the aforementioned technical problems, this disclosure provides an address resolution method, comprising: acquiring an address sequence to be processed; vectorizing the address sequence to be processed to obtain a target embedding vector; and predicting the target embedding vector using an address resolution model to obtain an address label sequence. The address resolution model includes an encoder, a decoder, and a fully connected linear layer. The decoder includes a neural network, where the dimension of the output of the hidden layer in the neural network is equal to the length of the address sequence, the number of neurons in the fully connected linear layer is equal to the dimension of the address label space, and the address label sequence includes the label corresponding to each word in the address sequence to be processed, thereby improving the accuracy of international address resolution.

[0022] For example, in the logistics sorting scenario described above, the address sequence corresponding to the package can be parsed using the address parsing method described above, and the package can be sorted onto the appropriate conveyor belt and sent to the designated area or distribution center based on the parsing results, so as to improve the accuracy of sorting and transportation efficiency.

[0023] Figure 1 shows a schematic diagram of the system architecture of an address resolution method provided in an embodiment of this disclosure. As shown in Figure 1, the system may include a terminal 110 and a server 120, wherein a communication connection is established between the terminal 110 and the server 120.

[0024] The address resolution method provided in this disclosure can be executed by terminal 110, server 120, or both terminal 110 and server 120; this disclosure does not limit the execution of this method. For example, a sender fills out a waybill on terminal 110, which includes the international address of the package's destination. Terminal 110 sends the waybill information to server 120. Server 120 receives the waybill information and parses the international address within it, so that the sorting center can sort the package based on the parsing result.

[0025] In some implementations, terminal 110 may include a smartphone, tablet, personal computer, or other intelligent device capable of computing and communication functions. In cross-border logistics scenarios, terminal 110 may be a client used by customers or order managers. Server 120 may include a standalone physical server, a server cluster consisting of multiple servers, or a cloud server capable of cloud computing.

[0026] Those skilled in the art will understand that the number of terminals and servers shown in Figure 1 is merely illustrative, and any number of terminals and servers can be used as needed, and this disclosure does not impose any limitation on this.

[0027] The address resolution method provided in this disclosure will be illustrated below with reference to the accompanying drawings.

[0028] Figure 2 is a flowchart illustrating an address resolution method provided in an embodiment of this disclosure. As shown in Figure 2, the address resolution method provided in this embodiment includes: S210, obtaining an address sequence to be processed; S220, vectorizing the address sequence to be processed to obtain a target embedding vector; S230, using an address resolution model to predict the target embedding vector to obtain an address tag sequence.

[0029] The address sequence to be processed can be an address of a country or region written in a single language, or an address of a country or region written in multiple languages. For example, when processing addresses from bilingual countries like Canada, the address sequence to be processed may include both English and French words.

[0030] In a logistics scenario, the address sequence to be processed can be the delivery address or shipping address filled in on the package waybill, or it can be any address such as the transit center address.

[0031] In step S220, the address sequence to be processed is vectorized, converting it into a low-dimensional dense address vector representation to obtain the target embedding vector. The target embedding vector is the vector representation of the address sequence to be processed, reflecting its core features and semantic information. For example, word embedding methods such as FastText and Word2Vec can be used to generate the target embedding vector.

[0032] Next, in step S230, the target embedding vector is input into the address resolution model. The address resolution model predicts the target embedding vector to obtain an address label sequence. The address label sequence includes the label corresponding to each word in the address sequence to be processed, and the length of the address label sequence is the same as the length of the address sequence to be processed. The label corresponding to each word refers to the address category label of the word; for example, the label corresponding to a word could be a street number, street name, city, state / province, postal code, etc. The length of the address sequence is the number of words included in the address sequence, and the length of the address label sequence includes the number of labels included in the address label sequence.

[0033] Address resolution models can employ a sequence-to-sequence (Seq2Seq) network architecture. A sequence-to-sequence network architecture is a deep learning model that processes sequential data and is suitable for generative tasks that transform one sequence into another.

[0034] Specifically, the address resolution model includes an encoder, a decoder, and fully connected linear layers. The encoder and decoder contain neural networks, and the fully connected linear layers have activation functions. In the decoder's neural network, the dimension of the output of the hidden layers is equal to the length of the address sequence. The number of neurons in the fully connected linear layers is equal to the dimension of the address label space.

[0035] The neural networks in the encoder and decoder can be recurrent neural networks; in one example, they can be single-layer unidirectional Long Short-Term Memory (LSTM) networks. The activation function in the fully connected linear layer can be a softmax function. For example, the address resolution model can include a single-layer unidirectional LSTM encoder and a single-layer unidirectional LSTM decoder, followed by a fully connected linear layer with a softmax activation function.

[0036] The encoder first generates a context vector based on the input target embedding vector, which contains crucial information about the target embedding vector. Then, at each time step, the decoder decodes the context vector to obtain the decoder's raw output. This raw decoder output is then input into a fully connected linear layer. The neurons in this layer perform a linear transformation on the decoder's raw output, and an activation function transforms the neuron's output into the probability corresponding to each label in the address label space. The label with the highest probability is then used as part of the address label sequence. The decoding process ends after obtaining the label corresponding to each word in the address sequence. The resulting address label sequence includes the label corresponding to each word in the address sequence to be processed.

[0037] In related technologies, sequence-to-sequence network architectures are commonly used for generative tasks. They understand the context and semantics of input data and generate a natural language sequence related to the input sequence. During decoding, the decoder continuously makes predictions until it predicts the end-of-sequence (EOS) marker, which is relatively uncontrollable. For example, for the address sequence "123,Rue de L'universite,Quebec,QC,G1V 0A6,Canada", the decoder's prediction might be "Country is Canada, Province is Quebec, Street is Rue de L'universite, Zip code is G1V 0A6"; or it might be "Canada / Quebec / Rue de L'universite / G1V 0A6 / ". It is evident that for traditional sequence-to-sequence network architectures, the decoder's output at each time step has a certain degree of randomness, and it is impossible to determine when it will output the end-of-sequence (EOS) marker, which may cause the sequence-to-sequence network architecture to fail to converge quickly. Furthermore, due to the randomness of the generated content in traditional sequence-to-sequence network architectures, the predicted results obtained from decoding cannot be used directly and require further processing. Therefore, the traditional sequence-to-sequence network architecture has limitations in address resolution scenarios and needs to be improved.

[0038] In this embodiment of the disclosure, by setting the dimension of the output of the hidden layer of the neural network in the decoder to be consistent with the length of the address sequence, the decoder produces an original output sequence with the same length as the address sequence.

[0039] The number of neurons in a fully connected linear layer is equal to the dimension of the address label space. This address label space includes multiple predefined address category labels, such as street number, street name, city, state / province, and postal code. Therefore, a fully connected linear layer can map the decoder's raw output at each time step to labels in the address label space. Processing the raw output sequence with the same length as the address sequence using a fully connected linear layer results in an address label sequence of the same length, with a one-to-one correspondence between words in the address sequence and labels in the address label sequence.

[0040] Using the above method, the address resolution model is used to determine the label corresponding to each word in the address sequence. After obtaining the labels corresponding to all words in the address sequence, the decoding process of the decoder ends.

[0041] The following is a brief introduction to the training process of the address resolution model.

[0042] During the training of the address resolution model, multiple sets of training addresses and their corresponding target address label sequences are used as training data. The encoder in the address resolution model encodes the training addresses into context vectors, the decoder decodes these context vectors, and the fully connected linear layer maps the decoder's raw output to predicted values ​​for the training addresses. Based on the predicted values ​​and the target address label sequences, the cross-entropy loss function is used to calculate the loss value, and the optuna automatic parameter tuning strategy is employed to optimize the model parameters.

[0043] The training address should be an international address written in multiple languages, and its length should be the same as the length of the corresponding target address label sequence. The cross-entropy loss function is suitable for classification tasks and, when used in conjunction with the softmax activation function, can directly optimize the model's output probability. For sequence-to-sequence network architectures, the optuna automatic hyperparameter tuning strategy can efficiently search the hyperparameter space, reduce trial-and-error costs, and significantly improve model performance.

[0044] In this embodiment, the address sequence is converted into a target embedding vector, and the address resolution model is used to predict the target embedding vector to obtain an address label sequence. The sequence-to-sequence network architecture of the address resolution model can capture and process dependencies and contextual semantics in sequence data, making it suitable for processing address data with sequence characteristics. Here, sequence characteristics refer to the arrangement of data elements according to a certain order or rule; for address data, although the address writing formats differ between different countries or regions, they all follow certain rules and possess sequence characteristics.

[0045] Unlike traditional sequence-to-sequence network architectures, this embodiment applies a sequence-to-sequence network architecture, originally used for generative tasks, to classification tasks. By setting the dimension of the output of the hidden layer of the neural network in the decoder, the address parsing model generates an address label sequence with the same length as the address sequence, avoiding the problem that the decoder cannot accurately predict the end marker of the sequence, thereby promoting the convergence of the decoding process, improving the efficiency of the prediction process, and saving computing resources.

[0046] For each decoder's original output in the original output sequence, it is mapped to a label in the address label space through a fully connected linear layer, resulting in a label corresponding to each word in the address sequence. The presentation of the address label sequence in this embodiment facilitates the extraction of desired segments from the address sequence based on the address label sequence. The format of the generated address label sequence is also more suitable for the package sorting process, requiring no additional processing.

[0047] The following section will introduce the specific implementation methods for generating target embedding vectors.

[0048] Figure 3 shows a flowchart illustrating the steps of vectorizing the address sequence to be processed to obtain the target embedding vector according to an embodiment of this disclosure.

[0049] As shown in Figure 3, the step of vectorizing the address sequence to be processed to obtain the target embedding vector provided in this embodiment includes: S221, using a first embedding model to divide the address sequence to be processed into multiple address sub-words and determine the sub-word vectors corresponding to each of the multiple address sub-words; S222, obtaining the target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words.

[0050] The first embedding model segments the address sequence into multiple address subwords. During the segmentation process, each word in the address sequence can be broken down into one or more address subwords. Then, these multiple address subwords are converted into dense numerical vector representations, i.e., subword vectors, which capture the semantic information of the address sequence.

[0051] The first embedding model is a word embedding model trained in multiple languages. For example, the first embedding model could be a MultiBPEmb model. The MultiBPEmb model is based on the Byte-Pair Encoding (BPE) method and is pre-trained in multiple languages. The MultiBPEmb model provides multilingual support and is suitable for handling international addresses from different countries.

[0052] Next, a target embedding vector is generated based on the sub-word vectors corresponding to each of the multiple address sub-words. In this step, a recurrent neural network (RNN) can be used to process the multiple sub-word vectors to obtain the target embedding vector.

[0053] In this embodiment of the disclosure, during word segmentation, the first embedding model further divides the words in the address sequence. This allows the model to consider not only the words as a whole but also the components of each word in subsequent processing. This feature helps the model process and understand low-frequency words in international addresses. Furthermore, the first embedding model is trained in multiple languages, enabling it to better understand the address semantics of the address sequence.

[0054] The following section introduces one implementation method for obtaining the target embedding vector based on multiple sub-word vectors.

[0055] Figure 4 is a flowchart illustrating the steps of obtaining a target embedding vector based on the sub-word vectors corresponding to multiple address sub-words according to an embodiment of this disclosure.

[0056] As shown in Figure 4, the step of obtaining the target embedding vector based on the sub-word vectors corresponding to multiple address sub-words provided in this embodiment includes: S2221, using a bidirectional long short-term memory network model to fuse the sub-word vectors belonging to the same word in multiple sub-word vectors to obtain the word vector corresponding to each word in the address sequence to be processed; S2222, using a fully connected layer to concatenate the word vectors corresponding to each word in the address sequence to be processed into the target embedding vector.

[0057] The Bidirectional Long Short-Term Memory (Bi-LSTM) model captures bidirectional dependencies in sequences by combining the outputs of two LSTM networks, forward and backward, making it suitable for processing sequence data such as addresses. The Bi-LSTM model also fuses word vectors belonging to the same word from multiple word vectors.

[0058] At each time step, the forward LSTM and backward LSTM in the Bi-LSTM model produce a hidden state. For each word, the forward and backward hidden states corresponding to the last time step of word decomposition are concatenated to generate a word vector for each word, which helps to capture the order relationship between words.

[0059] Next, the word vectors corresponding to each word are concatenated through a fully connected layer to obtain the target embedding vector. The target embedding vector integrates the information contained in the entire address sequence, providing rich context for the next prediction process.

[0060] Bi-LSTM models can process both forward and backward information in sequence data simultaneously, enabling them to better understand the context. Furthermore, Bi-LSTM models have a strong ability to remember information from longer distances, making them suitable for address resolution scenarios.

[0061] The above embodiments describe one implementation method for generating target embedding vectors. The following describes another implementation method for generating target embedding vectors. In this embodiment, another embedding model is used to vectorize the address sequence, and the results of the two embedding models are combined to generate the target embedding vector.

[0062] Specifically, the target embedding vector is obtained based on the sub-word vectors corresponding to each of the multiple address sub-words, including: obtaining a first embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words; using a monolingual embedding model to vectorize the address sequence to be processed to obtain a second embedding vector; and concatenating the first embedding vector and the second embedding vector to obtain the target embedding vector.

[0063] Monolingual embedding models are word embedding models trained using corpora of the target language. The target language can be selected based on the specific circumstances.

[0064] For example, a monolingual embedding model can be a monolingual fastText model. The fastText model is trained on a large corpus and has the advantages of fast prediction speed, good performance, and low resource requirements.

[0065] Compared to multilingual embedding models, monolingual embedding models have a significant advantage when handling international addresses written in multiple languages. For international addresses containing words written in multiple languages, monolingual embedding models can uniformly project words written in multiple languages ​​into the same vector space, achieving alignment between different languages ​​and facilitating cross-language address resolution.

[0066] If each language uses its own embedding model to process words, the word embedding relationships in a sequence of addresses will be inconsistent, increasing processing costs.

[0067] Next, the multiple sub-word vectors generated by the first embedding model are merged to obtain the first embedding vector. In this process, RNN, Bi-LSTM, or other methods can be used; please refer to the steps described in the above embodiments for details, which will not be repeated here. It is understood that the step of merging multiple sub-word vectors to obtain the first embedding vector is independent of the step of generating the second embedding vector described above. The order of the two steps can be adjusted according to the actual situation, and this disclosure does not impose any restrictions on this.

[0068] After obtaining the first embedding vector and the second embedding vector, the first embedding vector and the second embedding vector are concatenated to obtain the target embedding vector.

[0069] Understandably, in some embodiments, the output of the monolingual embedding model can be used alone as the target embedding vector. Alternatively, the output of the first embedding model can be used alone as the target embedding vector. Or, as described in the embodiments of this disclosure, the target embedding vector is generated based on the outputs of the monolingual embedding model and the first embedding model.

[0070] Since monolingual embedding models are trained in a single-language environment, they have certain limitations. Combining the outputs of the monolingual embedding model with those of the first embedding model can leverage the strengths of both models and improve the accuracy of address resolution.

[0071] In some embodiments, a monolingual embedding model is used to vectorize the address sequence to be processed to obtain a second embedding vector, including: using the monolingual embedding model, segmenting words according to the monolingual roots included in the words in the address sequence to be processed to obtain multiple sub-words in the form of roots; and mapping the multiple sub-words in the form of roots to the second embedding vector.

[0072] Many languages ​​in the world, though distributed across different countries, share a common origin. Cognate languages ​​share many word roots; therefore, monolingual embedding models also perform well when dealing with other languages ​​that share a common origin with the target language.

[0073] For example, the target language includes French. That is, the monolingual embedding model is trained using a corpus of French.

[0074] French shares Latin roots with many European and American languages; therefore, monolingual embedding models trained on French corpora possess the ability to identify Latin roots. During word segmentation, these models can identify and segment Latin roots in address sequences written in European and American languages, improving model performance. For example, segmenting the word "avenue" yields the root words "a," "ven," and "ue," where "a" means "towards," "ven" means "to arrive" or "to come," and "ue" is a common nominalization suffix in French. It is understood that the above segmentation method is merely exemplary; depending on the word segmentation strategy employed by the monolingual embedding model, there are various ways to segment words in the address sequence.

[0075] Furthermore, when address sequences are written in multiple European and American languages, the monolingual embedding model performs well in handling multiple European and American languages.

[0076] In this embodiment of the disclosure, a monolingual embedding model is used to segment words in the address sequence into word roots, which improves the ability of the monolingual embedding model to process address sequences written in languages ​​cognate with the target language, thereby improving the accuracy of address resolution.

[0077] The above introduced several methods for generating target embedding vectors. The following section introduces an implementation method for generating address tag sequences.

[0078] Figure 5 shows a flowchart illustrating the steps of predicting the target embedding vector using an address resolution model to obtain an address tag sequence according to an embodiment of this disclosure.

[0079] As shown in Figure 5, the step of predicting the target embedding vector using the address resolution model to obtain the address tag sequence provided in this embodiment includes: S231, encoding the target embedding vector using an encoder to obtain the context vector corresponding to the target embedding vector; S232, decoding the context vector according to time steps to obtain the original output of the decoder corresponding to each time step; S233, in each time step, using a fully connected linear layer to transform the original output of the decoder corresponding to that time step to obtain the probability of each tag in the address tag space, and taking the tag with the highest probability as the tag corresponding to that time step; S234, generating the address tag sequence based on the tag corresponding to each time step.

[0080] In step S231, the encoder of the address resolution model generates a hidden state based on the input target embedding vector, and uses the last hidden state as the context vector corresponding to the target embedding vector.

[0081] In step S232, the context vector is used to initialize the decoder's hidden state. At the start of decoding, a Start of Sequence (BOS) marker is given to the decoder as input. The decoder decodes the context vector step by step, obtaining the decoder's raw output for each time step. During prediction, the decoder uses the prediction result of the previous time step as the input of the current time step, and predicts the raw output of the current time step based on the hidden state of the current step and the prediction result of the previous time step.

[0082] In step S233, for the raw output of the decoder at each time step, a fully connected linear layer is used to map the raw output to the address label space. Specifically, the neurons in the fully connected linear layer perform a linear transformation on the raw output at each time step, and the activation function in the fully connected linear layer further converts the output of the neurons into the probability corresponding to each label in the address label space, and takes the label with the highest probability as the label corresponding to that time step.

[0083] Repeat the above steps to obtain the label corresponding to each time step, and combine the labels corresponding to each time step into an address label sequence. In the address label sequence, each word in the address sequence has a corresponding label.

[0084] In this embodiment of the disclosure, an address tag sequence is generated through an address resolution model. This process does not rely on traditional named entity recognition technology, but directly predicts the components of the address, thus improving the efficiency and accuracy of address resolution.

[0085] The above details the generation methods for the target embedding vector and the address tag sequence. Prior to this, the address sequence can be preprocessed to simplify subsequent processing steps.

[0086] Figure 6 is a flowchart illustrating the steps for obtaining the address sequence to be processed according to an embodiment of this disclosure.

[0087] As shown in Figure 6, the step of obtaining the address sequence to be processed provided in this embodiment includes: S211, obtaining the original address sequence; S212, converting the text in the original address sequence to lowercase and / or deleting the delimiters of the address fields in the original address sequence to obtain the address sequence to be processed.

[0088] The original address sequence can be the address text entered by the customer or order administrator through the client; or it can be the address text identified from the order image data or voice data through text recognition methods; or it can be the address text that needs to be parsed obtained through other means.

[0089] Next, the original address sequence is preprocessed. Preprocessing methods include converting the text in the original address sequence to lowercase and removing delimiters from the address fields. The preprocessed original address sequence is then used as the address sequence to be processed.

[0090] Taking the address "123,Rue de L'universite,Quebec,QC,G1V 0A6,Canada" in the above embodiment as an example, the delimiter of the address field is a comma. During the preprocessing process, the comma "," in the original address sequence is deleted, and the single quote "'" in the original address sequence is retained.

[0091] The preprocessed original address sequence can be represented as "123rue de l'universite quebec qc g1v 0a6 canada".

[0092] In this embodiment of the disclosure, by preprocessing the original address sequence, the computational burden of subsequent processing steps can be reduced; irrelevant information such as delimiters can be identified and removed, making the cleaned data more concise and easier to process.

[0093] The automated address resolution method described in the above embodiments can quickly process large amounts of address data, reducing manual input and processing time and improving overall logistics processing speed. Furthermore, it can improve the accuracy of address resolution and has a certain fault tolerance, reducing the probability of delivery failures due to spelling errors, formatting errors, etc., in the address. Moreover, it can promptly identify missing items in the address sequence for subsequent correction processing.

[0094] The method embodiments of this disclosure have been described in detail above with reference to Figures 1 to 6. The apparatus embodiments of this disclosure are described in detail below with reference to Figure 7. It should be understood that the descriptions of the method embodiments correspond to the descriptions of the apparatus embodiments; therefore, any parts not described in detail can be referred to the foregoing method embodiments.

[0095] Figure 7 is a schematic diagram of the structure of an address resolution device provided in an embodiment of the present disclosure. As shown in Figure 7, the address resolution device 700 of the present disclosure embodiment includes: an acquisition module 710, a processing module 720, and a prediction module 730.

[0096] Specifically, the acquisition module 710 is configured to acquire the address sequence to be processed. The processing module 720 is configured to vectorize the address sequence to be processed to obtain the target embedding vector. The prediction module 730 is configured to predict the target embedding vector using the address parsing model to obtain the address label sequence. The address parsing model includes an encoder, a decoder, and a fully connected linear layer. The decoder includes a neural network where the dimension of the output of the hidden layer is equal to the length of the address sequence. The number of neurons in the fully connected linear layer is equal to the dimension of the address label space. The address label sequence includes the label corresponding to each word in the address sequence to be processed.

[0097] In some embodiments, the processing module 720 is further configured to use a first embedding model to segment the address sequence to be processed into multiple address sub-words and determine the sub-word vectors corresponding to each of the multiple address sub-words; and obtain a target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words.

[0098] In some embodiments, the processing module 720 is further configured to: obtain a first embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words; vectorize the address sequence to be processed using a monolingual embedding model to obtain a second embedding vector; and concatenate the first embedding vector and the second embedding vector to obtain a target embedding vector. The monolingual embedding model is trained using corpus of the target language.

[0099] In some embodiments, the processing module 720 is further configured to use a monolingual embedding model to segment words based on the monolingual roots included in the words in the address sequence to be processed, to obtain multiple sub-words in the form of roots; and to map the multiple sub-words in the form of roots into a second embedding vector.

[0100] In some embodiments, the processing module 720 is further configured to use a bidirectional long short-term memory network model to fuse sub-word vectors belonging to the same word in multiple sub-word vectors to obtain word vectors corresponding to each word in the address sequence to be processed; and use a fully connected layer to concatenate the word vectors corresponding to each word in the address sequence to be processed into a target embedding vector.

[0101] In some embodiments, the prediction module 730 is further configured to: encode the target embedding vector using an encoder to obtain a context vector corresponding to the target embedding vector; decode the context vector according to time steps to obtain the original output of the decoder for each time step; in each time step, use a fully connected linear layer to transform the original output of the decoder for that time step to obtain the probability of each tag in the address tag space, and take the tag with the highest probability as the tag for that time step; and generate an address tag sequence based on the tag for each time step.

[0102] In some embodiments, the acquisition module 710 is further configured to acquire the original address sequence; convert the text in the original address sequence to lowercase and remove the delimiters of the address fields in the original address sequence to obtain the address sequence to be processed.

[0103] Hereinafter, an electronic device according to an embodiment of the present disclosure will be described with reference to FIG8. FIG8 is a schematic structural diagram of an electronic device provided according to an embodiment of the present disclosure. As shown in FIG8, the electronic device 800 includes one or more processors 810 and memory 820.

[0104] The processor 810 may be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device 800 to perform desired functions.

[0105] The memory 820 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 810 may execute the program instructions to implement the address resolution methods of the various embodiments of this disclosure described above and / or other desired functions.

[0106] In some embodiments, the electronic device 800 may further include an input device 830 and an output device 840, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0107] The input device 830 may include, for example, a touch screen, a microphone, a keyboard, a mouse, etc. The output device 840 may include, for example, a display, a speaker, and a communication network and its connected remote output devices, etc.

[0108] Of course, for simplicity, Figure 8 only shows some of the components of the electronic device 800 that are relevant to this disclosure, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 800 may include any other suitable components depending on the specific application.

[0109] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products, including computer programs that, when executed by a processor, cause the processor to implement the steps in the address resolution methods according to various embodiments of this disclosure described above.

[0110] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0111] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the address resolution methods according to various embodiments of this disclosure described above.

[0112] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0113] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0114] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0115] It should also be noted that in the systems, apparatus, and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0116] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0117] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An address resolution method, characterized in that, include: Obtain the address sequence to be processed; The address sequence to be processed is vectorized to obtain the target embedding vector; The target embedding vector is predicted using an address resolution model to obtain an address label sequence. The address resolution model includes an encoder, a decoder, and a fully connected linear layer. The decoder includes a neural network. The dimension of the output of the hidden layer in the neural network is equal to the length of the address sequence. The number of neurons in the fully connected linear layer is equal to the dimension of the address label space. The address label sequence includes the label corresponding to each word in the address sequence to be processed.

2. The address resolution method according to claim 1, characterized in that, The vectorization process of the address sequence to be processed to obtain the target embedding vector includes: Using the first embedding model, the address sequence to be processed is segmented into multiple address sub-words, and the sub-word vector corresponding to each of the multiple address sub-words is determined; The target embedding vector is obtained based on the sub-word vectors corresponding to each of the multiple address sub-words.

3. The address resolution method according to claim 2, characterized in that, The process of obtaining the target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words includes: Based on the sub-word vectors corresponding to each of the multiple address sub-words, a first embedding vector is obtained; The address sequence to be processed is vectorized using a monolingual embedding model to obtain a second embedding vector. The monolingual embedding model is trained using corpus of the target language. The first embedding vector and the second embedding vector are concatenated to obtain the target embedding vector.

4. The address resolution method according to claim 3, characterized in that, The method of using a monolingual embedding model to vectorize the address sequence to be processed, obtaining a second embedding vector, includes: Using the monolingual embedding model, the words in the address sequence to be processed are segmented according to the monolingual word roots they contain, resulting in multiple sub-words in the form of word roots; The multiple subwords in the form of the root word are mapped to the second embedding vector.

5. The address resolution method according to claim 2, characterized in that, The process of obtaining the target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words includes: Using a bidirectional long short-term memory network model, sub-word vectors belonging to the same word from multiple sub-word vectors are fused to obtain the word vector corresponding to each word in the address sequence to be processed; Using a fully connected layer, the word vectors corresponding to each word in the address sequence to be processed are concatenated to form the target embedding vector.

6. The address resolution method according to claim 1, characterized in that, The step of using an address resolution model to predict the target embedding vector to obtain an address tag sequence includes: The target embedding vector is encoded using the encoder to obtain the context vector corresponding to the target embedding vector; The decoder decodes the context vector according to time steps, and obtains the original output of the decoder for each time step in sequence; In each time step, the fully connected linear layer is used to transform the original output of the decoder corresponding to that time step to obtain the probability of each tag in the address tag space, and the tag with the highest probability is taken as the tag corresponding to that time step. The address tag sequence is generated based on the tag corresponding to each time step.

7. The address resolution method according to claim 1, characterized in that, The process of obtaining the address sequence to be processed includes: Obtain the original address sequence; The text in the original address sequence is converted to lowercase, and the separators in the address fields of the original address sequence are removed to obtain the address sequence to be processed.

8. An address resolution device, characterized in that, include: The acquisition module is used to acquire the address sequence to be processed; The processing module is used to perform vectorization processing on the address sequence to be processed to obtain the target embedding vector; The prediction module is used to predict the target embedding vector using an address resolution model to obtain an address label sequence. The address resolution model includes an encoder, a decoder, and a fully connected linear layer. The decoder includes a neural network. The dimension of the output of the hidden layer in the neural network is equal to the length of the address sequence. The number of neurons in the fully connected linear layer is equal to the dimension of the address label space. The address label sequence includes the label corresponding to each word in the address sequence to be processed.

9. The address resolution device according to claim 8, characterized in that, The process of vectorizing the address sequence to be processed to obtain the target embedding vector includes: Using the first embedding model, the address sequence to be processed is segmented into multiple address sub-words, and the sub-word vector corresponding to each of the multiple address sub-words is determined; The target embedding vector is obtained based on the sub-word vectors corresponding to each of the multiple address sub-words.

10. The address resolution apparatus according to claim 9, characterized in that, The process of obtaining the target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words includes: Based on the sub-word vectors corresponding to each of the multiple address sub-words, a first embedding vector is obtained; The address sequence to be processed is vectorized using a monolingual embedding model to obtain a second embedding vector. The monolingual embedding model is trained using corpus of the target language. The first embedding vector and the second embedding vector are concatenated to obtain the target embedding vector.

11. The address resolution apparatus according to claim 10, characterized in that, The method of using a monolingual embedding model to vectorize the address sequence to be processed, obtaining a second embedding vector, includes: Using the monolingual embedding model, the words in the address sequence to be processed are segmented according to the monolingual word roots they contain, resulting in multiple sub-words in the form of word roots; The multiple subwords in the form of the root word are mapped to the second embedding vector.

12. The address resolution device according to claim 9, characterized in that, The process of obtaining the target embedding vector based on the sub-word vectors corresponding to each of the multiple address sub-words includes: Using a bidirectional long short-term memory network model, sub-word vectors belonging to the same word from multiple sub-word vectors are fused to obtain the word vector corresponding to each word in the address sequence to be processed; Using a fully connected layer, the word vectors corresponding to each word in the address sequence to be processed are concatenated to form the target embedding vector.

13. The address resolution apparatus according to claim 8, characterized in that, The method for predicting the target embedding vector using an address resolution model to obtain an address tag sequence includes: The target embedding vector is encoded using the encoder to obtain the context vector corresponding to the target embedding vector; The decoder decodes the context vector according to time steps, and obtains the original output of the decoder for each time step in sequence; In each time step, the fully connected linear layer is used to transform the original output of the decoder corresponding to that time step to obtain the probability of each tag in the address tag space, and the tag with the highest probability is taken as the tag corresponding to that time step. The address tag sequence is generated based on the tag corresponding to each time step.

14. The address resolution apparatus according to claim 8, characterized in that, The method for obtaining the address sequence to be processed includes: Obtain the original address sequence; The text in the original address sequence is converted to lowercase, and the separators in the address fields of the original address sequence are removed to obtain the address sequence to be processed.

15. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the address resolution method according to any one of claims 1 to 7 by executing the executable instructions.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the address resolution method according to any one of claims 1 to 7.

17. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the address resolution method according to any one of claims 1 to 7.

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