Communication method, communication apparatus, and communication system

Abstract

The present application relates to the technical field of communications, and discloses a communication method, a communication apparatus, and a communication system. In the method, a plurality of convolutional code encoders and corresponding convolutional code decoders are preset, so that a first communication apparatus can select a convolutional code encoder among the plurality of convolutional code encoders to perform channel encoding, and a second communication apparatus can select a corresponding convolutional code decoder among the plurality of convolutional code decoders to perform channel decoding. The method is flexible and is applicable to different communication requirements or communication scenarios; that is, on the basis of a communication requirement or a communication scenario, a corresponding convolutional code encoder and a corresponding convolutional code decoder can be selected.

Description

A communication method, communication device and communication system

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510139667.8, filed on February 7, 2025, entitled "A Communication Method, Communication Device and Communication System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a communication method, communication device and communication system. Background Technology

[0004] To improve communication performance, when transmitting data from the transmitter to the receiver, forward error correction (FEC) and other coding methods can be used for channel coding, thereby improving the reliability of data transmission. Convolutional coding is a type of FEC coding, and it is widely used due to its superior encoding and decoding performance.

[0005] Currently, a specific convolutional code encoding method is generally pre-defined. Both the sending end and the receiving end are aware of this specific convolutional code encoding method in advance. Thus, the sending end can perform corresponding encoding based on this specific convolutional code encoding method, and the receiving end can perform corresponding decoding based on this specific convolutional code encoding method.

[0006] However, the above-mentioned pre-defined specific convolutional code encoding method is not flexible enough and cannot meet different communication needs or communication scenarios. Summary of the Invention

[0007] This application provides a communication method, communication device, and communication system to provide flexible convolutional code encoding methods, thereby meeting different communication needs or communication scenarios.

[0008] In a first aspect, an embodiment of the present application provides a communication method. This method can be executed by a first communication device. Without special specification, the "first communication device" in the present application can refer to a communication device (such as a terminal device, etc.), or a component in the communication device (such as a processor, a chip, or a chip system, etc.), or can also be a logical module or software that can implement all or part of the functions of the communication device. The method includes: selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; transmitting the second bit sequence; wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as the number of registers of the second convolutional code encoder, and the number of exclusive-OR gates of the first convolutional code encoder is the same as the number of exclusive-OR gates of the second convolutional code encoder.

[0009] Based on the above solution, multiple convolutional code encoders are preset in advance, so that the first communication device can select one convolutional code encoder from multiple convolutional code encoders for channel coding. This method is relatively flexible and can be applied to different communication requirements or communication scenarios, that is, based on the communication requirements or communication scenarios, select the corresponding convolutional code encoder. Moreover, compared with the first convolutional code encoder, the second convolutional code encoder keeps the number of registers and exclusive-OR gates unchanged, so it will not increase power consumption, but since the code rate is reduced, the coding and decoding performance can be improved.

[0010] In a possible implementation method, the number of registers of the first convolutional code encoder is 6, and the number of exclusive-OR gates of the first convolutional code encoder is 12.

[0011] In a possible implementation method, the coefficients of the generating polynomial of the second convolutional code encoder include 161, 151, 107, and 131, and 161, 151, 107, and 131 are all octal values; or, the coefficients of the generating polynomial of the second convolutional code encoder include 145, 153, 113, and 125, and 145, 153, 113, and 125 are all octal values.

[0012] Based on the above solution, compared with the first convolutional code encoder, the second convolutional code encoder keeps the number of registers and exclusive-OR gates unchanged, so it will not increase power consumption, but since the code rate is reduced, the coding and decoding performance can be improved.

[0013] Second aspect, an embodiment of the present application provides a communication method. This method can be executed by a second communication device. Without special explanation, the "second communication device" in the present application can refer to a communication device (such as a network device, etc.), or a component in this communication device (such as a processor, a chip, or a chip system, etc.), or can also be a logical module or software that can implement all or part of the functions of the communication device. The method includes: receiving a second bit sequence; selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; wherein, the number of encoding branches of the first convolutional code decoder is A, the number of encoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as the number of registers of the second convolutional code decoder, and the number of exclusive-OR gates of the first convolutional code decoder is the same as the number of exclusive-OR gates of the second convolutional code decoder.

[0014] Based on the above solution, multiple convolutional code decoders are preset in advance, so that the second communication device can select a convolutional code decoder from multiple convolutional code decoders for channel decoding. This method is relatively flexible and can be applied to different communication requirements or communication scenarios, that is, select the corresponding convolutional code decoder based on the communication requirements or communication scenarios. Moreover, compared with the first convolutional code decoder, the second convolutional code decoder keeps the number of registers and exclusive-OR gates unchanged, so it will not increase power consumption, but since the code rate is reduced, the coding and decoding performance can be improved.

[0015] In a possible implementation method, the number of registers of the first convolutional code decoder is 6, and the number of exclusive-OR gates of the first convolutional code decoder is 12.

[0016] In a possible implementation method, the coefficients of the generating polynomial of the second convolutional code decoder include 161, 151, 107, and 131, and 161, 151, 107, and 131 are all octal values; or, the coefficients of the generating polynomial of the second convolutional code decoder include 145, 153, 113, and 125, and 145, 153, 113, and 125 are all octal values.

[0017] Based on the above solution, compared with the first convolutional code decoder, the second convolutional code decoder keeps the number of registers and exclusive-OR gates unchanged, so it will not increase power consumption, but since the code rate is reduced, the coding and decoding performance can be improved.

[0018] Third aspect, an embodiment of the present application provides a communication method. This method can be executed by a first communication device. Without special specification, the "first communication device" in the present application can refer to a communication device (such as a terminal device, etc.), or a component in the communication device (such as a processor, a chip, or a chip system, etc.), or can also be a logical module or software that can implement all or part of the functions of the communication device. The method includes: selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; sending the second bit sequence; wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as that of the second convolutional code encoder and less than 6, the A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

[0019] Based on the above solution, multiple convolutional code encoders are preset in advance, so that the first communication device can select a convolutional code encoder from multiple convolutional code encoders for channel encoding. This method is relatively flexible and can be applied to different communication requirements or communication scenarios, that is, based on the communication requirements or communication scenarios, select the corresponding convolutional code encoder. Moreover, by designing convolutional code encoders with a nested structure, it helps to reduce the number of registers and exclusive-OR gates, thereby reducing the complexity and can reduce power consumption.

[0020] In a possible implementation method, the number of registers of the first convolutional code encoder is 4.

[0021] Based on the above solution, compared with the prior art where the number of registers is 6, this solution sets the number of registers of the first convolutional code encoder to 4. Therefore, the number of registers is reduced, and the power consumption can be reduced.

[0022] In a possible implementation method, the coefficients of the generating polynomial of the first convolutional code encoder include 31 and 23; the coefficients of the generating polynomial of the second convolutional code encoder include 31, 23, 35, and 27, and 31, 23, 35, and 27 are all octal values; or,

[0023] the coefficients of the generating polynomial of the first convolutional code encoder include 21 and 33; the coefficients of the generating polynomial of the second convolutional code encoder include 21, 33, 25, and 37, and 21, 33, 25, and 37 are all octal values.

[0024] Based on the above solution, by designing a convolutional code encoder with a nested structure, it helps to reduce the number of registers and XOR gates, thereby reducing the complexity and lowering the power consumption.

[0025] In a fourth aspect, an embodiment of the present application provides a communication method. This method can be executed by a second communication device. Without special specification, the "second communication device" in the present application can refer to a communication device (such as a network device, etc.), or a component in this communication device (such as a processor, chip, or chip system, etc.), or can also be a logic module or software that can implement all or part of the functions of the communication device. The method includes: receiving a second bit sequence; selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; wherein, the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder and less than 6, the A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

[0026] Based on the above solution, multiple convolutional code decoders are preset in advance, so that the second communication device can select a convolutional code decoder from multiple convolutional code decoders for channel decoding. This method is relatively flexible and can be applied to different communication requirements or communication scenarios, that is, based on the communication requirements or communication scenarios, select the corresponding convolutional code decoder. Moreover, by designing a convolutional code decoder with a nested structure, it helps to reduce the number of registers and XOR gates, thereby reducing the complexity and lowering the power consumption.

[0027] In a possible implementation method, the number of registers of the first convolutional code decoder is 4.

[0028] Based on the above solution, compared with the number of registers being 6 in the prior art, this solution sets the number of registers of the first convolutional code decoder to 4. Therefore, the number of registers is reduced and the power consumption can be lowered.

[0029] In a possible implementation method, the coefficients of the generating polynomial of the first convolutional code decoder include 31 and 23; the coefficients of the generating polynomial of the second convolutional code decoder include 31, 23, 35, and 27, and 31, 23, 35, and 27 are all octal values; or,

[0030] The coefficients of the generating polynomial of the first convolutional code decoder include 21 and 33; the coefficients of the generating polynomial of the second convolutional code decoder include 21, 33, 25, and 37, and 21, 33, 25, and 37 are all octal values.

[0031] Based on the above solution, by designing a nested-structured convolutional code decoder, it helps to reduce the number of registers and exclusive-OR gates, thereby reducing complexity and lowering power consumption.

[0032] In a fifth aspect, an embodiment of the present application provides a communication method. This method can be executed by a first communication device. Without special explanation, the "first communication device" in the present application can refer to a communication device (such as a terminal device, etc.), or a component in the communication device (such as a processor, chip, or chip system, etc.), or can also be a logic module or software that can implement all or part of the functions of the communication device. The method includes: selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; transmitting the second bit sequence; where the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is different from the number of registers of the second convolutional code encoder, the A encoding branches of the first convolutional code encoder correspond one-to-one to A generating polynomials, the B encoding branches of the second convolutional code encoder correspond one-to-one to B generating polynomials, and any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

[0033] Based on the above solution, multiple convolutional code encoders are preset in advance, so that the first communication device can select a convolutional code encoder from multiple convolutional code encoders for channel coding. This method is relatively flexible and can be applied to different communication requirements or communication scenarios. That is, based on the communication requirements or communication scenarios, the corresponding convolutional code encoder is selected. By designing a nested-structured convolutional code encoder, it helps to reduce the number of registers and exclusive-OR gates, thereby reducing complexity and lowering power consumption.

[0034] In a possible implementation method, the number of registers of the first convolutional code encoder is equal to 4, and the number of registers of the second convolutional code encoder is greater than 4.

[0035] Based on the above solution, compared with the number of registers being 6 in the prior art, this solution sets the number of registers of the first convolutional code encoder to 4, so the number of registers is reduced and power consumption can be lowered.

[0036] In a possible implementation method, the coefficients of the generating polynomial of the first convolutional code encoder include 31 and 27, and both 31 and 27 are octal values. The coefficients of the generating polynomial of the second convolutional code encoder include 145, 135, 143, and 113, and 145, 135, 143, and 113 are all octal values; or,

[0037] the coefficients of the generating polynomial of the first convolutional code encoder include 25 and 23, and both 25 and 23 are octal values. The coefficients of the generating polynomial of the second convolutional code encoder include 125, 115, 161, and 153, and 125, 115, 161, and 153 are all octal values.

[0038] Based on the above scheme, by designing a convolutional code encoder with a nested structure, it helps to reduce the number of registers and exclusive-OR gates, thereby reducing the complexity and lowering the power consumption.

[0039] In a sixth aspect, an embodiment of the present application provides a communication method. This method can be executed by a second communication device. Without special explanation, the "second communication device" in the present application can refer to a communication device (such as a network device, etc.), or a component in the communication device (such as a processor, a chip, or a chip system, etc.), or can also be a logical module or software that can implement all or part of the functions of the communication device. The method includes: receiving a second bit sequence; selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; where the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is different from the number of registers of the second convolutional code decoder. The A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one, and any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials. <​​​​In one possible implementation, the number of registers in the first convolutional code decoder is equal to 4, and the number of registers in the second convolutional code decoder is greater than 4.

[0042] Based on the above scheme, compared with the existing technology which has 6 registers, this scheme sets the number of registers in the first convolutional code decoder to 4, thus reducing the number of registers and reducing power consumption.

[0043] In one possible implementation, the coefficients of the generator polynomial of the first convolutional code decoder include 31 and 27, where 31 and 27 are both octal values; the coefficients of the generator polynomial of the second convolutional code decoder include 145, 135, 143, and 113, where 145, 135, 143, and 113 are all octal values; or...

[0044] The coefficients of the generator polynomial of the first convolutional code decoder include 25 and 23, both of which are octal values. The coefficients of the generator polynomial of the second convolutional code decoder include 125, 115, 161 and 153, all of which are octal values.

[0045] Based on the above scheme, designing a nested convolutional code decoder helps reduce the number of registers and XOR gates, thereby reducing complexity and power consumption.

[0046] Seventhly, embodiments of this application provide a communication method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a terminal device), a component within that communication device (e.g., a processor, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: determining whether to add a cyclic redundancy check (CRC) bit sequence; if it is determined that a CRC bit sequence should be added, determining the length of the CRC bit sequence; and determining a first bit sequence based on the CRC bit sequence length and an information bit sequence, wherein the first bit sequence includes the information bit sequence and the first CRC bit sequence.

[0047] Based on the above scheme, it is possible to accurately determine whether to add a CRC bit sequence and accurately determine the length of the CRC bit sequence, which helps to reduce power consumption. Furthermore, in some cases, it is not necessary to add a CRC bit sequence or to add a shorter CRC bit sequence, thus reducing overhead.

[0048] In a possible implementation method, the determination of whether to add a CRC bit sequence includes: determining to add a CRC bit sequence when the length of the information bit sequence is greater than a first threshold value. Exemplarily, the first threshold value is equal to 16 bits.

[0049] Based on the above solution, based on the relationship between the length of the information bit sequence and the first threshold value, it is possible to accurately determine whether to add a CRC bit sequence, which helps to reduce power consumption.

[0050] In a possible implementation method, the determination of whether to add a CRC bit sequence includes: determining to add a CRC bit sequence according to indication information.

[0051] Based on the above solution, according to the indication information, it is possible to accurately determine whether to add a CRC bit sequence, which helps to reduce power consumption.

[0052] In a possible implementation method, the determination of the length of the CRC bit sequence includes: determining the length of the CRC bit sequence according to the length of the information bit sequence and a second threshold value. Exemplarily, the second threshold value is equal to 24 bits.

[0053] Based on the above solution, based on the relationship between the length of the information bit sequence and the second threshold value, it is possible to accurately determine the length of the CRC bit sequence, which helps to reduce power consumption.

[0054] In a possible implementation method, the determination of the first bit sequence according to the length of the CRC bit sequence and the information bit sequence includes: determining the first bit sequence according to the information bit sequence, the length of the CRC bit sequence, and a selected first CRC generation polynomial or a second CRC generation polynomial; wherein, the length of the first CRC generation polynomial is X, the length of the second CRC generation polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generation polynomial includes the first CRC generation polynomial.

[0055] Based on the above solution, by nesting the design of the first CRC generation polynomial and the second CRC generation polynomial, the number of registers and exclusive-OR gates can be reduced, thereby reducing power consumption.

[0056] Eighthly, embodiments of this application provide a communication method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a network device), a component within that communication device (e.g., a processor, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: determining whether a CRC bit sequence exists; if a CRC bit sequence exists, determining the length of the CRC bit sequence; and determining an information bit sequence based on the CRC bit sequence length and a first bit sequence, wherein the first bit sequence includes the information bit sequence and the first CRC bit sequence.

[0057] Based on the above scheme, it is possible to accurately determine whether a CRC bit sequence exists and to accurately determine the length of the CRC bit sequence, which helps to improve decoding accuracy.

[0058] In one possible implementation, determining whether a CRC bit sequence exists includes: if the length of the information bit sequence is greater than a first threshold value, determining that a CRC bit sequence exists. For example, the first threshold value is equal to 16 bits.

[0059] Based on the above scheme, and by considering the relationship between the length of the information bit sequence and the first threshold value, it is possible to accurately determine whether a CRC bit sequence exists, which helps to reduce power consumption.

[0060] In one possible implementation, determining whether a CRC bit sequence exists includes: determining the existence of a CRC bit sequence based on indication information.

[0061] Based on the above scheme, the presence of a CRC bit sequence can be accurately determined according to the indication information, which helps to reduce power consumption.

[0062] In one possible implementation, determining the CRC bit sequence length includes: determining the CRC bit sequence length based on the length of the information bit sequence and a second threshold value. For example, the second threshold value is equal to 24 bits.

[0063] Based on the above scheme, the CRC bit sequence length can be accurately determined by the relationship between the length of the information bit sequence and the second threshold value, which helps to reduce power consumption.

[0064] In a possible implementation method, determining the information bit sequence according to the CRC bit sequence length and the first bit sequence includes: determining the information bit sequence according to the first bit sequence, the CRC bit sequence length, and a selected first CRC generation polynomial or a second CRC generation polynomial; wherein, the length of the first CRC generation polynomial is X, the length of the second CRC generation polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generation polynomial includes the first CRC generation polynomial.

[0065] Based on the above solution, nested design of the first CRC generation polynomial and the second CRC generation polynomial can reduce the number of registers and exclusive-OR gates, thereby reducing power consumption.

[0066] In a ninth aspect, an embodiment of the present application provides a communication method, which can be executed by a first communication device. Without special explanation, the "first communication device" in the present application can refer to a communication device (such as a terminal device, etc.), or a component in the communication device (such as a processor, a chip, or a chip system, etc.), or can also be a logical module or software that can implement all or part of the communication device functions. The method includes: obtaining a first bit sequence according to a third bit sequence, where L is the number of registers during convolutional coding; when performing convolutional coding on the first bit sequence, performing convolutional coding on the first bit sequence to obtain a second bit sequence, and sending the second bit sequence; when not performing convolutional coding on the first bit sequence, sending the first bit sequence. Wherein, the lengths of the first bit sequence and the third bit sequence are both K. The first L bits of the third bit sequence are the same as the last L bits of the first bit sequence, and the bits from the (L + 1)-th bit to the K-th bit of the third bit sequence are the same as the bits from the 1st bit to the (K - L)-th bit of the first bit sequence.

[0067] Based on the above solution, at the sending end, regardless of whether convolutional coding needs to be performed, preprocessing operations are performed on the third bit sequence, so that the sending end does not need to additionally determine whether to perform convolutional coding, and thus the processing delay can be reduced.

[0068] In a possible implementation method, the third bit sequence is an information bit sequence; or, the third bit sequence includes an information bit sequence and a CRC bit sequence.

[0069] Tenthly, embodiments of this application provide a communication method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a network device), a component within that communication device (e.g., a processor, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: receiving a fourth bit sequence; if convolutional coding decoding is performed on the fourth bit sequence, performing convolutional coding decoding on the fourth bit sequence to obtain a first bit sequence, and obtaining a third bit sequence based on the first bit sequence; if convolutional coding decoding is not performed on the fourth bit sequence, obtaining the third bit sequence based on the fourth bit sequence; wherein, L is the number of registers used in convolutional coding. Wherein, if convolutional coding decoding is not performed on the fourth bit sequence, the fourth bit sequence is the same as the first bit sequence. Wherein, the length of both the first bit sequence and the length of the third bit sequence are K. The first L bits of the third bit sequence are the same as the last L bits of the first bit sequence, and the (L+1)th to the Kth bits of the third bit sequence are the same as the first to the KLth bits of the first bit sequence.

[0070] Based on the above scheme, at the receiving end, preprocessing is performed regardless of whether convolutional code decoding is required. Therefore, the receiving end does not need to make an additional judgment on whether to perform convolutional code decoding, thus reducing processing latency.

[0071] In one possible implementation, the third bit sequence is an information bit sequence; or, the third bit sequence includes both an information bit sequence and a CRC bit sequence.

[0072] Eleventhly, this application provides a communication device that performs the functions described in the first, third, fifth, seventh, and ninth aspects above. For example, the communication device includes modules, units, or means corresponding to the operations described in the first, third, fifth, seventh, and ninth aspects above. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0073] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the first, third, fifth, seventh, and ninth aspects mentioned above.

[0074] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the first, third, fifth, seventh, and ninth aspects above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first, third, fifth, seventh, and ninth aspects above, when the computer programs or instructions are executed.

[0075] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions described in the first, third, fifth, seventh, and ninth aspects above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first, third, fifth, seventh, and ninth aspects above.

[0076] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the first, third, fifth, seventh, and ninth aspects described above.

[0077] Understandably, the processor in aspect eleven can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application embodiment does not limit the type of memory or the arrangement of the memory and processor.

[0078] In a twelfth aspect, this application provides a communication device that performs the functions described in the second, fourth, sixth, eighth, and tenth aspects above. For example, the communication device includes modules, units, or means corresponding to the operations described in the second, fourth, sixth, eighth, and tenth aspects above. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0079] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the second, fourth, sixth, eighth, and tenth aspects mentioned above.

[0080] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the second, fourth, sixth, eighth, and tenth aspects above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the second, fourth, sixth, eighth, and tenth aspects above, when the computer programs or instructions are executed.

[0081] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions described in the second, fourth, sixth, eighth, and tenth aspects above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second, fourth, sixth, eighth, and tenth aspects above.

[0082] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any of the possible designs or implementations of the second, fourth, sixth, eighth, and tenth aspects described above.

[0083] Understandably, the processor in the twelfth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separately configured. In specific implementations, the memory can be integrated with the processor on the same chip, or it can be configured on different chips. This application does not limit the type of memory or the configuration of the memory and processor.

[0084] In a thirteenth aspect, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the first aspect, and the second communication device is used to perform the method described in the second aspect; or, the first communication device is used to perform the method described in the third aspect, and the second communication device is used to perform the method described in the fourth aspect; or, the first communication device is used to perform the method described in the fifth aspect, and the second communication device is used to perform the method described in the sixth aspect; or, the first communication device is used to perform the method described in the seventh aspect, and the second communication device is used to perform the method described in the eighth aspect; or, the first communication device is used to perform the method described in the ninth aspect, and the second communication device is used to perform the method described in the tenth aspect.

[0085] In a fourteenth aspect, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs in the first to tenth aspects described above is executed.

[0086] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0087] In a fifteenth aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to tenth aspects to be performed.

[0088] In a sixteenth aspect, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that a method in any of the possible designs in the first to tenth aspects described above is executed. Attached Figure Description

[0089] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0090] Figure 2 is a schematic diagram of a convolutional code encoder;

[0091] Figure 3 is a schematic diagram of a convolutional code encoder;

[0092] Figure 4 is a schematic diagram of a convolutional code encoder;

[0093] Figure 5 is a schematic diagram of the processing procedure at the sending end;

[0094] Figure 6 is a flowchart illustrating the communication method provided in an embodiment of this application;

[0095] Figure 7(a) is a schematic diagram of a convolutional code encoder;

[0096] Figure 7(b) is a schematic diagram of a convolutional code encoder;

[0097] Figure 8(a) is a schematic diagram of a convolutional code encoder;

[0098] Figure 8(b) is a schematic diagram of a convolutional code encoder;

[0099] Figure 9(a) is a schematic diagram of a convolutional code encoder;

[0100] Figure 9(b) is a schematic diagram of a convolutional code encoder;

[0101] Figure 10 is a flowchart illustrating the communication method provided in an embodiment of this application;

[0102] Figure 11 is a schematic diagram of the CRC generator polynomial corresponding to this example.

[0103] Figure 12 is a schematic diagram of the CRC generator polynomial corresponding to this example 2;

[0104] Figure 13 is a schematic diagram of the CRC generator polynomial corresponding to Example 3;

[0105] Figure 14 is a schematic diagram of the CRC generator polynomial corresponding to Example 4;

[0106] Figure 15 is a flowchart illustrating the communication method provided in an embodiment of this application;

[0107] Figure 16 is a flowchart illustrating the communication method provided in an embodiment of this application;

[0108] Figure 17 is a flowchart illustrating the communication method provided in an embodiment of this application;

[0109] Figure 18 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0110] Figure 19 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0111] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0112] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Worldwide Interoperability for Microwave Access (WiMAX) communication systems, 5th generation (5G) mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0113] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0114] (1) Network equipment

[0115] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0116] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system. For example, in an ambient internet of things (AIoT) system, this network device can also be a reader.

[0117] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. The RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or specific equipment form used in the network equipment.

[0118] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0119] (2) Terminal equipment

[0120] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, smart cities, etc. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or it can be a device that supports the terminal device in implementing that function, such as a chip system or a combination of devices or components that can implement the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0121] By way of example and not limitation, in this application, the terminal device can be a terminal device in an Internet of Things (IoT) system. The IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection. Exemplarily, the terminal device in the embodiments of this application can be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that can be worn directly on the body or integrated into a user's clothing or accessories. Wearable devices are not merely hardware devices; they can also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly defined, wearable smart devices include those with comprehensive functions, large size, and the ability to achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those focused on a specific application function and requiring cooperation with other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0122] As a specific example, the terminal device in this application embodiment can be a device in an AIoT system, and can be referred to as an AIoT device. AIoT technology can be applied to scenarios such as inventory, sensing, controllers, and positioning. For hundreds or even trillions of AIoT devices, manually replacing them or using rechargeable batteries to power all AIoT devices would lead to high maintenance costs and serious environmental problems, and may even pose safety hazards in some use cases (such as wireless sensors in the power and oil industries). Therefore, in order to reduce the size, complexity, and power consumption of AIoT devices, AIoT devices can be battery-free devices or devices that do not require manual replacement or charging and have energy storage capabilities. It should be understood that AIoT devices can also be referred to as tags, A-IoT devices, devices, electronic AIoT devices, AIoT tags, smart AIoT devices, transponders, or data carriers, etc., and this application does not specifically limit them. To be suitable for different use cases, AIoT devices can include various types of devices, such as device 1, device 2a, device 2b, and device c. Among them, device 1 does not have downlink and uplink power amplification capabilities and has a small frequency modulation range. Device 1 can acquire energy through carrier waves (CW) emitted by other devices. For example, it can transmit signals to other devices by reflecting carrier waves emitted by other devices. This method of sending signals to other devices by reflecting carrier waves can also be called backscatter. The device that transmits (or provides) the carrier wave can also be called a CW device or a CW node. Device 2a is a device that needs to transmit signals via backscatter. Device 2b is a device that can generate signals internally (actively transmit signals), meaning device 2b does not need to transmit signals by reflecting carrier waves. Device c is also a device that can generate signals internally (actively transmit signals), meaning device c does not need to transmit signals by reflecting carrier waves. Compared to devices 1, 2a, and 2b, device c can be understood as a wide-area coverage device, meaning device c has a larger uplink coverage area. Devices 1, 2a, and 2b can be understood as local coverage devices, meaning their uplink coverage area is smaller.It should be understood that a larger uplink coverage range can be interpreted as an uplink coverage range greater than or equal to a certain threshold, and a smaller uplink coverage range can be interpreted as an uplink coverage range less than a certain threshold; or, a larger uplink coverage range and a smaller uplink coverage range are relative, that is, the uplink coverage range of device c is greater than that of device 1, device 2a, and device 2b. This application does not make specific limitations in this regard. In AIoT systems, AIoT devices can improve the uplink coverage range through channel coding. Since AIoT devices are usually power-constrained devices, for example, device 1 typically has an output power consumption of about 1 microwatt (μW); devices 2a and 2b typically have an output power consumption of no more than a few hundred μW, and device c typically has an output power consumption of 1 milliwatt (mW), AIoT devices usually use convolutional codes with lower complexity for encoding, thereby improving the uplink coverage range of the AIoT device without exceeding its power consumption limits.

[0123] By way of example and not limitation, in the embodiments of this application, the terminal device can also be a terminal device in an MTC (Mechanical, Communication, and Telecommunications) system. Furthermore, the terminal device can also be an on-board module, on-board component, on-board chip, or on-board unit, etc., built into a vehicle as one or more components or units. The vehicle can implement the methods provided in this application through the built-in on-board module, on-board component, on-board chip, or on-board unit, etc. Therefore, the embodiments of this application can also be applied to vehicle-to-everything (V2X), long-term evolution-vehicle (LTE-V) technology, vehicle-to-vehicle (V2V) technology, etc.

[0124] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0125] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0126] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0127] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0128] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0129] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0130] (1) Bitrate

[0131] Code rate refers to the ratio of the number of bits in the bit sequence before encoding to the number of bits in the bit sequence after encoding during data transmission. Code rate determines the efficiency and reliability of data transmission. The bit sequence before encoding can be an information bit sequence, or a bit sequence composed of an information bit sequence and a CRC bit sequence.

[0132] (2) Bit fronting

[0133] Bit fronting refers to moving at least one bit from the end of a bit sequence to the beginning of the sequence. For example, the original bit sequence is c0, c1, c2, c3, c4, c5, ..., c K-1If the size of the bit prepend is denoted by L, then the bit sequence obtained after the bit prepend operation is c. K-L ,c K-L+1 ,c K-L+2 ,…,c K-2 ,c K-1 c0,c1,c2,c3,c4,c5,…,c K-L-1 For example, L can be the number of registers in a convolutional code encoder.

[0134] (3) Bit postposition

[0135] Bit postposition refers to moving at least one bit from the beginning of a bit sequence to the end of the sequence. For example, the original bit sequence is c0, c1, c2, c3, c4, c5, ..., c K-1 If the size of the bit postposition is denoted by L, then the bit sequence obtained after the bit postposition operation is c. L ,c L+1 ,c L+2 ,…,c K-1 ,c0,c1,…,c L-1 For example, L can be the number of registers in a convolutional code encoder.

[0136] (4) Convolutional code encoding

[0137] Convolutional coding is a coding technique used for error detection and correction. It involves performing modulo-2 multiplication on the input bit sequence with one or more generator polynomials, then outputting the results in parallel to form the encoded bit sequence. The output of convolutional coding can be one or more bit sequences, with each bit sequence corresponding to a generator polynomial.

[0138] It should be understood that in the embodiments of this application, the bit sequence may also be referred to as a bit stream or data stream, etc. This application does not specifically limit it in this regard.

[0139] Convolutional code encoding can be implemented using a convolutional code encoder. A convolutional code encoder can also be called a convolutional encoder, convolutional code structure, or convolutional coding structure. A convolutional code encoder may include registers (or shift registers) and XOR gates (or XOR devices, modulo-2 adders).

[0140] (5) Generating polynomials

[0141] The generator polynomial is a rule used to describe the output operation result of a convolutional code encoder. Specifically, the generator polynomial defines how to combine the input bit sequence and the state of the registers to generate the operation result.

[0142] Figure 2 is a schematic diagram of a convolutional code encoder. In this example, the convolutional code encoder includes 6 registers (represented by "D" in the figure) and 12 XOR gates (represented by "⊕" in the figure). The registers are used to store bit values, and the XOR gates are used to perform XOR operations.

[0143] This convolutional encoder includes three coding branches, namely coding branch 1, coding branch 2, and coding branch 3 in the figure. Each input bit (e.g., c)... k The convolutional encoder can output 3 bits, with each coding branch outputting 1 bit. The output of each coding branch depends on the input bits, the register state, and the generator polynomial. Referring to Figure 2, when the input bit c... k Afterwards, the encoded branch 1 is based on c k The state of the register and the generator polynomial G0, output bits And for It is 0 or 1; the encoded branch 2 is based on c k The state of the register and the generator polynomial G1, output bits And for It is either 0 or 1; the coded branch 3 is based on c k The state of the register and the generator polynomial G2, output bits And for It can be 0 or 1.

[0144] In the example in Figure 2, the coefficient of G0 is 133, and 133 is an octal value. The binary value corresponding to octal 133 is 1011011. The leftmost "1" in 1011011 corresponds to the input bit c. k In the sequence 1011011, the six bits excluding the leftmost "1" correspond one-to-one with six registers. A 0 indicates that the value of the corresponding register is not involved in the XOR operation, while a 1 indicates that the value of the corresponding register is involved in the XOR operation. The polynomial corresponding to 1011011 is: 1 + x 2 +x 3 +x 5 +x 6 .

[0145] The coefficient of G1 is 171, and 171 is an octal value. The binary value corresponding to octal 171 is 1111001. The leftmost "1" in 1111001 corresponds to the input bit c. k In the sequence 1111001, the six bits excluding the leftmost "1" correspond one-to-one with six registers. A 0 indicates that the value of the corresponding register is not involved in the XOR operation, while a 1 indicates that the value of the corresponding register is involved in the XOR operation. The polynomial corresponding to 1111001 is: 1 + x + x 2 +x3 +x 6 .

[0146] The coefficient of G2 is 165, and 165 is an octal value. The binary value corresponding to octal 165 is 1110101. The leftmost "1" in 1110101 corresponds to the input bit c. k In the sequence 1110101, the six bits excluding the leftmost "1" correspond one-to-one with six registers. A 0 indicates that the value of the corresponding register is not involved in the XOR operation, while a 1 indicates that the value of the corresponding register is involved in the XOR operation. The polynomial corresponding to 1110101 is: 1 + x + x 2 +x 4 +x 6 .

[0147] After encoding a 1-bit convolutional code, the values ​​of the registers can be updated. For example, from left to right, the value in register 5 is updated to register 6, the value in register 4 is updated to register 5, the value in register 3 is updated to register 4, the value in register 2 is updated to register 3, the value in register 1 is updated to register 2, and so on. k Update to the first register. After the update is complete, the three output bits corresponding to the next input bit can be calculated based on the next input bit, the current register state, and the multinomials generated by each encoding branch.

[0148] By using convolutional coding, the final encoded result contains redundant information, thereby improving the reliability of data transmission. For example, in the example in Figure 2, each input bit is encoded by convolutional coding to output 3 bits, so the code rate is 1 / 3. Generally, the code rate is equal to 1 / M, where M is the number of coding branches.

[0149] It should be noted that the initial values ​​of each register in the convolutional code encoder can be set to 0, the last N bits of the bit sequence to be encoded, or the first N bits of the bit sequence to be encoded. Here, N is the number of registers. For example, taking Figure 2 as an example, N = 6, assuming the bit sequence to be encoded is represented as c0, c1, c2, c3, c4, c5, ..., c K-1 Then the initial values ​​of all six registers in Figure 2 are 0, or from left to right, they are c. K-1 c K-2 c K-3 c K-4 c K-5 c K-6(Refer to Figure 3), or from left to right: c5, c4, c3, c2, c1, c0 (Refer to Figure 4).

[0150] The encoding process implemented by the convolutional code encoder shown in Figure 3 is also called tail-biting convolutional code encoding, and the encoding process implemented by the convolutional code encoder shown in Figure 4 is also called head-biting convolutional code encoding.

[0151] (6) Processing procedure at the sending end

[0152] Figure 5 illustrates the processing flow at the transmitting end. The CRC module at the transmitting end generates a CRC bit sequence based on the information bit sequence. This CRC bit sequence assists the decoding at the receiving end, improving the decoding success rate. The FEC module at the transmitting end performs FEC encoding on the bit sequence to be encoded, specifically convolutional coding, to obtain the encoded bit sequence. This encoded bit sequence can be sent to the receiving end, or it can be sent to the receiving end after bit interleaving and / or modulation.

[0153] The CRC module performs optional operations; it can generate a CRC bit sequence or not.

[0154] In one scenario, if it is not necessary to generate a CRC bit sequence, then the bit sequence to be encoded is the information bit sequence.

[0155] In another scenario, if a CRC bit sequence needs to be generated, the bit sequence to be encoded includes both the information bit sequence and the CRC bit sequence. For example, the bit sequence to be encoded might be represented as c0, c1, c2, c3, c4, c5, ..., c K-1 If the first KP bits of the bit sequence to be encoded form the information bit sequence, and the last P bits of the bit sequence to be encoded form the CRC bit sequence, where P is the number of bits in the CRC bit sequence and P is a positive integer.

[0156] To improve communication performance, the transmitting end can use coding methods such as FEC to channel-code the data when sending it to the receiving end, thereby improving the reliability of data transmission. Among them, convolutional coding is a type of FEC coding, which is widely used due to its good encoding and decoding performance.

[0157] Currently, a specific convolutional code encoding method is generally preset (such as the convolutional code encoding method shown in Figure 2). Both the sending end and the receiving end know this specific convolutional code encoding method in advance, so that the sending end can perform corresponding encoding based on the specific convolutional code encoding method, and the receiving end can perform corresponding decoding based on the specific convolutional code encoding method.

[0158] However, the above-mentioned pre-defined specific convolutional code encoding method is not flexible enough and cannot meet different communication needs or communication scenarios.

[0159] To address the aforementioned issues, this application provides corresponding solutions.

[0160] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a terminal device, encoding device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The "second communication device" in this application can refer to a communication device (e.g., a network device, decoding device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. As a specific example, in an AIoT system, the first communication device can be an AIoT device (i.e., a tag), and the second communication device can be a reader.

[0161] Figure 6 is a flowchart illustrating a communication method provided in an embodiment of this application. The method is executed by a first communication device and a second communication device, and includes the following steps:

[0162] Step 601: The first communication device selects either the first convolutional code encoder or the second convolutional code encoder to encode the first bit sequence to obtain the second bit sequence.

[0163] The first bit sequence is also called the bit sequence before encoding or the bit sequence to be encoded, and the second bit sequence is also called the bit sequence after encoding or the encoded bit sequence.

[0164] The first communication device is configured with a plurality of candidate convolutional encoders, which include at least a first convolutional encoder and a second convolutional encoder, and optionally one or more other convolutional encoders. For ease of explanation, this application uses the first and second convolutional encoders as examples. It should be noted that in this application, the first communication device can select a convolutional encoder not only from the first and second convolutional encoders, but also from other convolutional encoders among the plurality of candidate convolutional encoders.

[0165] Accordingly, the second communication device is equipped with a plurality of candidate convolutional code decoders that correspond one-to-one with the plurality of candidate convolutional code encoders. The plurality of candidate convolutional code decoders include at least a first convolutional code decoder and a second convolutional code decoder, and optionally include one or more other convolutional code decoders. The first convolutional code decoder corresponds to the first convolutional code encoder, and the second convolutional code decoder corresponds to the second convolutional code encoder.

[0166] In step 602, the first communication device sends the second bit sequence. Correspondingly, the second communication device receives the second bit sequence.

[0167] The first communication device transmits the second bit sequence, which can be done by directly transmitting the second bit sequence or by interleaving and / or modulating the second bit sequence before transmission. This application does not limit this.

[0168] Step 603: The second communication device selects either the first convolutional code decoder or the second convolutional code decoder to decode the second bit sequence to obtain the first bit sequence.

[0169] When the first communication device selects the first convolutional code encoder for channel coding, the second communication device selects the first convolutional code decoder for channel decoding; when the first communication device selects the second convolutional code encoder for channel coding, the second communication device selects the second convolutional code decoder for channel decoding.

[0170] Based on the above scheme, multiple convolutional code encoders and corresponding convolutional code decoders are pre-set. Thus, the first communication device can select one convolutional code encoder from these encoders for channel coding, and the second communication device can select the appropriate convolutional code decoder from these decoders for channel decoding. This method is flexible and applicable to different communication needs or scenarios; that is, it selects the appropriate convolutional code encoder and decoder based on the communication requirements or scenario.

[0171] This application does not limit the specific implementation of selecting the convolutional code encoder. For example, taking a tag as the first communication device, the tag can select the convolutional code encoder based on the distance between the tag and the base station. For instance, if the tag is close to the base station, its coverage is better, so the tag may not use convolutional code encoding, or it may use a convolutional code encoder with a higher code rate for channel coding, thereby improving data transmission efficiency without affecting demodulation performance. Conversely, if the tag is far from the base station, its coverage is poor, so the tag can use a convolutional code encoder with a lower code rate for channel coding, thereby improving demodulation performance and ensuring correct data transmission.

[0172] In addition, the first communication device may also select a convolutional code encoder according to one or more of the type of the first message, the length of the information bit sequence, the repetition times of the information bit sequence, and the bandwidth. The information bit sequence is carried in the first message.

[0173] Taking the first convolutional code encoder and the second convolutional code encoder among multiple candidate convolutional code encoders as examples, various design methods of the first convolutional code encoder and the second convolutional code encoder will be introduced below.

[0174] In the first implementation method, the number of encoding branches of the first convolutional code encoder is A, and the number of encoding branches of the second convolutional code encoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code encoder is the same as that of the second convolutional code encoder, and the number of exclusive-OR gates of the first convolutional code encoder is the same as that of the second convolutional code encoder. Correspondingly, the number of encoding branches of the first convolutional code decoder is A, and the number of encoding branches of the second convolutional code decoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder, and the number of exclusive-OR gates of the first convolutional code decoder is the same as that of the second convolutional code decoder.

[0175] Exemplarily, the number of registers of both the first convolutional code encoder and the second convolutional code encoder is 6, and the number of exclusive-OR gates of both the first convolutional code encoder and the second convolutional code encoder is 12. Correspondingly, the number of registers of both the first convolutional code decoder and the second convolutional code decoder is 6, and the number of exclusive-OR gates of both the first convolutional code decoder and the second convolutional code decoder is 12.

[0176] For example, the first convolutional encoder is shown in Figure 2, and its code rate is 1 / 3. The second convolutional encoder is shown in Figure 7(a), and its code rate is 1 / 4. The coefficients of the generator polynomial of the second convolutional encoder include 161, 151, 107, and 131, and 161, 151, 107, and 131 are all octal values. For example, the generator polynomial of the second convolutional encoder is [161, 151, 107, 131]. It should be noted that the positions of the coefficients in the generator polynomial can be interchanged; for example, the generator polynomial of the second convolutional encoder can also be [131, 107, 161, 151] or [161, 151, 131, 107], etc. Accordingly, the coefficients of the generator polynomial of the second convolutional code decoder include 161, 151, 107, and 131, where 161, 151, 107, and 131 are all octal values. For example, the generator polynomial of the second convolutional code decoder is [161, 151, 107, 131]. It should be noted that the positions of the coefficients in this generator polynomial can be interchanged; for example, the generator polynomial of the second convolutional code decoder could also be [131, 107, 161, 151] or [161, 151, 131, 107], etc.

[0177] For example, the first convolutional encoder is shown in Figure 2, and its code rate is 1 / 3. The second convolutional encoder is shown in Figure 7(b), and its code rate is 1 / 4. The coefficients of the generator polynomial of the second convolutional encoder include 145, 153, 113, and 125, and 145, 153, 113, and 125 are all octal values. For example, the generator polynomial of the second convolutional encoder is [145, 153, 113, 125]. It should be noted that the positions of the coefficients in the generator polynomial can be interchanged; for example, the generator polynomial of the second convolutional encoder can also be [145, 153, 125, 113] or [153, 113, 125, 145], etc. Accordingly, the coefficients of the generator polynomial of the second convolutional code decoder include 145, 153, 113, and 125, all of which are octal values. For example, the generator polynomial of the second convolutional code decoder is [145, 153, 113, 125]. It should be noted that the positions of the coefficients in the generator polynomial can be interchanged; for example, the generator polynomial of the second convolutional code decoder could also be [145, 153, 125, 113] or [153, 113, 125, 145], etc.

[0178] Based on this implementation method, the second convolutional encoder maintains the same number of registers and XOR gates as the first convolutional encoder, thus not increasing power consumption, but improving encoding and decoding performance by reducing the code rate.

[0179] Implement Method 2. The number of encoding branches of the first convolutional code encoder is A, and the number of encoding branches of the second convolutional code encoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code encoder is the same as that of the second convolutional code encoder and less than 6. The A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, and the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one. The B generating polynomials include the A generating polynomials. Here, the B generating polynomials including the A generating polynomials means that there are A generating polynomials in the B generating polynomials that are exactly the same as the A generating polynomials. Correspondingly, the number of decoding branches of the first convolutional code decoder is A, and the number of decoding branches of the second convolutional code decoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder and less than 6. The A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, and the B encoding branches of the second convolutional code decoder correspond to B generating polynomials one by one. The B generating polynomials include the A generating polynomials.

[0180] Exemplarily, the number of registers of both the first convolutional code encoder and the second convolutional code encoder is 4. Correspondingly, the number of registers of both the first convolutional code decoder and the second convolutional code decoder is 4.

[0181] For example, a first convolutional encoder is shown in Figure 8(a). This first convolutional encoder has a code rate of 1 / 2. It includes the four registers shown in Figure 8(a) and the first two encoding branches. The coefficients of the generator polynomial of this first convolutional encoder include 31 and 23, both of which are octal values. Correspondingly, a first convolutional decoder has a code rate of 1 / 2. The coefficients of the generator polynomial of this first convolutional decoder include 31 and 23, both of which are octal values. A second convolutional encoder is shown in Figure 8(a). This second convolutional encoder has a code rate of 1 / 3. It includes the first three encoding branches shown in Figure 8(a). The coefficients of the generator polynomial of this second convolutional encoder include 31, 23, and 35, all of which are octal values. For example, the generator polynomial of the second convolutional code encoder is [31,23,35] or [23,31,35], etc. Correspondingly, the code rate of the second convolutional code decoder is 1 / 3, and the coefficients of the generator polynomial of the second convolutional code decoder include 31, 23, and 35, and 31, 23, and 35 are all octal values. For example, the generator polynomial of the second convolutional code decoder is [31,23,35] or [23,31,35], etc. Alternatively, as shown in Figure 8(a), the second convolutional code encoder has a code rate of 1 / 4, includes the four coding branches shown in Figure 8(a), and the coefficients of the generator polynomial of the second convolutional code encoder include 31, 23, 35, and 27, and 31, 23, 35, and 27 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [31,23,35,27], [23,31,35,27], or [31,23,27,35], etc. Correspondingly, the code rate of the second convolutional code decoder is 1 / 4, and the coefficients of the generator polynomial of the second convolutional code decoder include 31, 23, 35, and 27, where 31, 23, 35, and 27 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [31,23,35,27], [23,31,35,27], or [31,23,27,35], etc.

[0182] For example, a first convolutional encoder is shown in Figure 8(b). This first convolutional encoder has a code rate of 1 / 2. It includes the four registers shown in Figure 8(b) and the first two encoding branches. The coefficients of the generator polynomial of this first convolutional encoder include 2¹ and 3³, both of which are octal values. Correspondingly, a first convolutional decoder has a code rate of 1 / 2. The coefficients of the generator polynomial of this first convolutional decoder include 2¹ and 3³, both of which are octal values. A second convolutional encoder is shown in Figure 8(b). This second convolutional encoder has a code rate of 1 / 3. It includes the first three encoding branches shown in Figure 8(b). The coefficients of the generator polynomial of this second convolutional encoder include 2¹, 3³, and 2⁵, all of which are octal values. For example, the generator polynomial of the second convolutional code encoder is [21,33,25] or [33,21,35], etc. Correspondingly, the code rate of the second convolutional code decoder is 1 / 3, and the coefficients of the generator polynomial of the second convolutional code decoder include 21, 33, and 25, and 21, 33, and 25 are all octal values. For example, the generator polynomial of the second convolutional code decoder is [21,33,25] or [33,21,35], etc. Alternatively, as shown in Figure 8(b), the second convolutional code encoder has a code rate of 1 / 4, includes the four coding branches shown in Figure 8(b), and the coefficients of the generator polynomial of the second convolutional code encoder include 21, 33, 25, and 37, and 21, 33, 25, and 37 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [21,33,25,37], [33,21,25,37], or [21,33,37,25]. Correspondingly, the code rate of the second convolutional code decoder is 1 / 4, and the coefficients of the generator polynomial of the second convolutional code decoder include 21, 33, 25, and 37, where 21, 33, 25, and 37 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [21,33,25,37], [33,21,25,37], or [21,33,37,25].

[0183] Based on the above implementation method two, by designing a nested structure convolutional code encoder and convolutional code decoder, it is helpful to reduce the number of registers and XOR gates, thereby reducing complexity and power consumption.

[0184] Implementation method three: The number of encoding branches of the first convolutional code encoder is A, and the number of encoding branches of the second convolutional code encoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code encoder is different from the number of registers of the second convolutional code encoder. The A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, and the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one. Any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials. Accordingly, the number of decoding branches of the first convolutional code decoder is A, and the number of decoding branches of the second convolutional code decoder is B. Both A and B are positive integers and A < B. The number of registers of the first convolutional code decoder is different from the number of registers of the second convolutional code decoder. The A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, and the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one. Any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

[0185] Exemplarily, the number of registers of the first convolutional code encoder is equal to 4, and the number of registers of the second convolutional code encoder is greater than 4. Accordingly, the number of registers of the first convolutional code decoder is equal to 4, and the number of registers of the second convolutional code decoder is greater than 4.

[0186] For example, a first convolutional encoder is shown in Figure 9(a). This first convolutional encoder has a code rate of 1 / 2, includes the four registers shown in Figure 9(a), and the coefficients of its generator polynomial include 31 and 27, both of which are octal values. Correspondingly, a first convolutional decoder has a code rate of 1 / 2, and the coefficients of its generator polynomial include 31 and 27, both of which are octal values. A second convolutional encoder is shown in Figure 9(a). This second convolutional encoder has a code rate of 1 / 3, includes the six registers shown in Figure 9(a) and the first three coding branches, and the coefficients of its generator polynomial include 145, 135, and 143, all of which are octal values. For example, the generator polynomial of this second convolutional encoder could be [145, 135, 143], etc. Accordingly, the code rate of the second convolutional code decoder is 1 / 3, and the coefficients of its generator polynomial include 145, 135, and 143, all of which are octal values. For example, the generator polynomial of the second convolutional code decoder is [145, 135, 143], etc. Alternatively, as shown in Figure 9(a), the code rate of the second convolutional code encoder is 1 / 4. This second convolutional code encoder includes the 6 registers and 4 coding branches shown in Figure 9(a), and the coefficients of its generator polynomial include 145, 135, 143, and 113, all of which are octal values. For example, the generator polynomial of the second convolutional code encoder is [145, 135, 143, 113] or [145, 135, 113, 143], etc. Accordingly, the code rate of the second convolutional code decoder is 1 / 4, and the coefficients of the generator polynomial of the second convolutional code decoder include 145, 135, 143, and 113, where 145, 135, 143, and 113 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [145, 135, 143, 113] or [145, 135, 113, 143], etc.

[0187] Referring to Figure 9(a), it can be seen that the generator polynomial of the first convolutional encoder is [31, 27], where 31 corresponds to the binary representation 11001, and the corresponding polynomial is 1+x+x. 4 The binary representation of 27 is 10111, and the corresponding polynomial is 1+x. 2 +x 3 +x 4 When the generator polynomial of the second convolutional encoder is [145, 135, 143], where 145 corresponds to the binary representation 1100101, the corresponding polynomial is 1+x+x. 4 +x6 The binary representation of 135 is 1011101, and the corresponding polynomial is 1+x. 2 +x 3 +x 4 +x 6 The binary representation of 143 is 1100011, and the corresponding polynomial is 1+x+x. 5 +x 6 It can be seen that 1+x+x 4 It is 1+x+x 4 +x 6 The proper subset of , that is, 1+x+x 4 +x 6 It includes 1+x+x 4 And 1+x 2 +x 3 +x 4 It is 1+x 2 +x 3 +x 4 +x 6 The proper subset of , that is, 1+x 2 +x 3 +x 4 +x 6 Includes 1+x 2 +x 3 +x 4 Other forms of the second convolutional encoder have a similar relationship to the first convolutional encoder, and will not be elaborated further.

[0188] For example, a first convolutional encoder is shown in Figure 9(b). This first convolutional encoder has a code rate of 1 / 2, includes the four registers shown in Figure 9(b), and the coefficients of its generator polynomial include 25 and 23, both of which are octal values. Correspondingly, a first convolutional decoder has a code rate of 1 / 2, and the coefficients of its generator polynomial include 25 and 23, both of which are octal values. A second convolutional encoder is shown in Figure 9(b). This second convolutional encoder has a code rate of 1 / 3, includes the six registers shown in Figure 9(b) and the first three encoding branches, and the coefficients of its generator polynomial include 125, 115, and 161, all of which are octal values. For example, the generator polynomial of this second convolutional encoder could be [125, 115, 161], etc. Accordingly, the code rate of the second convolutional code decoder is 1 / 3, and the coefficients of its generator polynomial include 125, 115, and 161, all of which are octal values. For example, the generator polynomial of the second convolutional code decoder is [125, 115, 161], etc. Alternatively, as shown in Figure 9(b), the code rate of the second convolutional code encoder is 1 / 4. This second convolutional code encoder includes the 6 registers and 4 coding branches shown in Figure 9(b), and the coefficients of its generator polynomial include 125, 115, 161, and 153, all of which are octal values. For example, the generator polynomial of the second convolutional code encoder is [125, 115, 161, 153] or [125, 115, 153, 161], etc. Accordingly, the code rate of the second convolutional code decoder is 1 / 4, and the coefficients of the generator polynomial of the second convolutional code decoder include 125, 115, 161, and 153, where 125, 115, 161, and 153 are all octal values. For example, the generator polynomial of the second convolutional code encoder is [125, 115, 161, 153] or [125, 115, 153, 161], etc.

[0189] Based on the above implementation method three, by designing a nested structure convolutional code encoder and convolutional code decoder, it is helpful to reduce the number of registers and XOR gates, thereby reducing complexity and power consumption.

[0190] The embodiments in Figure 6 above illustrate the design of various convolutional code encoders and decoders. These embodiments can be understood as improvements to the FEC module in the processing flow shown in Figure 5. Below, for the CRC module shown in Figure 5, an improved scheme is proposed as shown in Figure 10. That is, the embodiment in Figure 10 can be executed by the CRC module within the first communication device.

[0191] Figure 10 is a schematic flowchart of a communication method provided in an embodiment of this application. The embodiment in Figure 10 can be implemented in combination with the embodiment in Figure 6, or they can be implemented separately.

[0192] The method includes the following steps:

[0193] Step 1001: The first communication device determines whether to add a CRC bit sequence.

[0194] For example, if the length of the information bit sequence is greater than a first threshold, the first communication device determines to add a CRC bit sequence. If the length of the information bit sequence is less than or equal to the first threshold, the first communication device determines not to add a CRC bit sequence.

[0195] For example, if the length of the information bit sequence is greater than or equal to a first threshold, the first communication device determines to add a CRC bit sequence. If the length of the information bit sequence is less than the first threshold, the first communication device determines not to add a CRC bit sequence.

[0196] For example, the first threshold value is equal to 16 bits.

[0197] For example, the first communication device determines whether to add or not add a CRC bit sequence based on the indication information. For instance, the MAC layer of the first communication device adds indication information at a fixed position in a first message, which carries an information bit sequence. If the indication information indicates the addition of a CRC bit sequence, the physical layer of the first communication device determines to add the CRC bit sequence based on the indication information; if the indication information indicates the non-addition of a CRC bit sequence, the physical layer of the first communication device determines not to add the CRC bit sequence based on the indication information. The indication information can be a 1-bit information; a value of 1 indicates that a CRC bit sequence needs to be added, and a value of 0 indicates that a CRC bit sequence does not need to be added.

[0198] Step 1002: The first communication device determines the length of the CRC bit sequence if it has determined that a CRC bit sequence needs to be added.

[0199] For example, the first communication device determines the CRC bit sequence length based on the length of the information bit sequence and a second threshold value. For instance, if the length of the information bit sequence is greater than or equal to the second threshold value, the CRC bit sequence length is determined to be a first length; if the length of the information bit sequence is less than the second threshold value, the CRC bit sequence length is determined to be a second length. For example, the first length is 6 and the second length is 16.

[0200] For example, the second threshold value is greater than or equal to the aforementioned first threshold value.

[0201] For example, the second threshold value is equal to 24 bits. For instance, if the length of the information bit sequence is greater than or equal to 24 bits, the CRC bit sequence length is determined to be 16 bits; if the length of the information bit sequence is less than 24 bits, the CRC bit sequence length is determined to be 6 bits.

[0202] Step 1003: The first communication device determines the first bit sequence based on the CRC bit sequence length and the information bit sequence.

[0203] The first bit sequence includes an information bit sequence and a first CRC bit sequence.

[0204] For example, the first communication device determines a first CRC bit sequence based on the CRC bit sequence length and the information bit sequence, and then determines a first bit sequence based on the first CRC bit sequence and the information bit sequence.

[0205] As one implementation method, the first bit sequence can be a bit sequence concatenated with the first CRC bit sequence from the information bit sequence. That is, the first bit sequence is divided into two parts: the first part is the information bit sequence, and the second part is the first CRC bit sequence. In this case, the first bit sequence can be referred to as the bit sequence without post-preprocessing.

[0206] As another implementation, the first bit sequence can also be a bit sequence obtained by post-placing the first L bits of the third bit sequence. This third bit sequence is the bit sequence obtained by concatenating the information bit sequence with the first CRC bit sequence; that is, the third bit sequence is divided into two parts: the first part is the information bit sequence, and the second part is the first CRC bit sequence. For example, the third bit sequence is c0, c1, c2, c3, c4, c5, ..., c K-1 Then the first bit sequence is c L ,c L+1 ,c L+2 ,…,c K-1 ,c0,c1,…,c L-1 For example, L can be the number of registers in a convolutional code encoder.

[0207] Based on the above scheme, it is possible to accurately determine whether to add a CRC bit sequence and accurately determine the length of the CRC bit sequence, which helps to reduce power consumption. Furthermore, in some cases, it is not necessary to add a CRC bit sequence or to add a shorter CRC bit sequence, thus reducing overhead.

[0208] Exemplarily, step 1003 may be: The first communication device may determine a first bit sequence according to the information bit sequence, the length of the CRC bit sequence, and the selected first CRC generation polynomial or second CRC generation polynomial. Among them, the length of the first CRC generation polynomial is X, the length of the second CRC generation polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generation polynomial includes the first CRC generation polynomial, that is, the first CRC generation polynomial is a proper subset of the second CRC generation polynomial. For example, when the length of the CRC bit sequence is the first length, the first CRC generation polynomial is selected; when the length of the CRC bit sequence is the second length, the second CRC generation polynomial is selected. Based on this method, by nesting the design of the first CRC generation polynomial and the second CRC generation polynomial, the number of registers and exclusive-OR gates can be reduced, thereby reducing power consumption.

[0209] As an example, specific examples of the first CRC generation polynomial and the second CRC generation polynomial are given below.

[0210] Example 1, the first CRC generation polynomial is D 6 + D 5 + 1, and the corresponding binary is [1, 1, 0, 0, 0, 0, 1]; the second CRC generation polynomial is D 16 + D 15 + D 6 + D 5 + 1, and the corresponding binary is [1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1].

[0211] FIG. 11 is a schematic diagram of the CRC generation polynomial corresponding to Example 1. Among them, CRC-6 represents the first CRC generation polynomial, and CRC-16 represents the second CRC generation polynomial. D0 to D 15 in the figure are all registers.

[0212] Example 2, the first CRC generation polynomial is D 6 + D 5 + 1, and the corresponding binary is [1, 1, 0, 0, 0, 0, 1]; the second CRC generation polynomial is D 16 + D 14 + D 6 + D 5 + 1, and the corresponding binary is [1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1].

[0213] FIG. 12 is a schematic diagram of the CRC generation polynomial corresponding to Example 2. Among them, CRC-6 represents the first CRC generation polynomial, and CRC-16 represents the second CRC generation polynomial. D0 to D15 All are registers.

[0214] Example 3, the first CRC generator polynomial is D 6 +D+1 corresponds to the binary representation [1,0,0,0,0,0,1,1]; the second CRC generator polynomial is D. 16 +D 12 +D 6 +D+1 corresponds to the binary representation of [1,0,0,0,0,0,0,0,0,0,1,0,0,0,0,1,1].

[0215] Figure 13 is a schematic diagram of the CRC generator polynomial corresponding to Example 3. CRC-6 represents the first CRC generator polynomial, and CRC-16 represents the second CRC generator polynomial. In the figure, D0~D... 15 All are registers.

[0216] Example 4, the first CRC generator polynomial is D 6 +D 5 +D 2 +D+1 corresponds to the binary representation [1,1,0,0,1,1,1]; the second CRC generator polynomial is D. 16 +D 14 +D 6 +D 5 +D 2 +D+1 corresponds to the binary representation of [1,0,1,0,0,0,0,0,0,0,1,1,0,0,1,1,1].

[0217] Figure 14 is a schematic diagram of the CRC generator polynomial corresponding to Example 4. CRC-6 represents the first CRC generator polynomial, and CRC-16 represents the second CRC generator polynomial. In the figure, D0~D... 15 All are registers.

[0218] The following uses the CRC generator polynomial D to generate the CRC bit sequence. 16 +D 12 +D 5 Taking +1 as an example, let's introduce the process of generating the first CRC bit sequence. Where, D 16 +D 12 +D 5 The binary representation of +1 is [1,0,0,0,1,0,0,0,0,0,0,1,0,0,0,0,1]. Assume the information bit sequence is a0,a1,a2,a3,…,a A-1 First, in a0, a1, a2, a3, ..., a A-1 Adding 16 zeros at the end gives a0, a1, a2, a3, ..., a A-1,0,…,0, and then a0,a1,a2,a3,…,a A-1 Perform modulo-2 division on 0, ..., 0 and 10001000000100001, and take the lower 16 bits of the remainder as the first CRC bit sequence. For example, when a0, a1, a2, a3, ..., a A-1 If the result is [1,1,1,0,1,1,1,1,1,1,0,0,1,1,0,1,1,0,1,1,0,1,1,1,0,1,0,1,0,1,0,1,0,1], then the first CRC bit sequence is [1,0,1,1,1,0,0,1,0,1,1,0,1,0,0,0].

[0219] Figure 15 is a schematic flowchart of a communication method provided in an embodiment of this application. The embodiment in Figure 15 can be implemented in combination with the embodiment in Figure 6, or they can be implemented separately. The embodiment in Figure 15 is an embodiment of the receiving end (or decoding end) corresponding to the embodiment in Figure 10.

[0220] The method includes the following steps:

[0221] Step 1501: The second communication device determines whether a CRC bit sequence exists.

[0222] For example, if the length of the information bit sequence is greater than a first threshold, the second communication device determines that a CRC bit sequence exists. If the length of the information bit sequence is less than or equal to the first threshold, the second communication device determines that a CRC bit sequence does not exist.

[0223] For example, if the length of the information bit sequence is greater than or equal to a first threshold, the second communication device determines that a CRC bit sequence exists. If the length of the information bit sequence is less than the first threshold, the second communication device determines that a CRC bit sequence does not exist.

[0224] For example, the first threshold value is equal to 16 bits.

[0225] The second communication device can know the length of the information bit sequence in advance.

[0226] For example, the second communication device determines whether a CRC bit sequence exists or not based on the indication information.

[0227] Step 1502: If the second communication device determines that a CRC bit sequence exists, it determines the length of the CRC bit sequence.

[0228] Exemplarily, the second communication device determines the length of the CRC bit sequence according to the length of the information bit sequence and the second threshold. For example, when the length of the information bit sequence is greater than or equal to the second threshold, it is determined that the length of the CRC bit sequence is the first length; when the length of the information bit sequence is less than the second threshold, it is determined that the length of the CRC bit sequence is the second length. Exemplarily, the first length is 6 and the second length is 16.

[0229] Exemplarily, the second threshold is greater than or equal to the foregoing first threshold.

[0230] Exemplarily, the second threshold is equal to 24 bits. For example, when the length of the information bit sequence is greater than or equal to 24 bits, it is determined that the length of the CRC bit sequence is 16 bits; when the length of the information bit sequence is less than 24 bits, it is determined that the length of the CRC bit sequence is 6 bits.

[0231] Step 1503: The second communication device determines the information bit sequence according to the length of the CRC bit sequence and the first bit sequence.

[0232] The first bit sequence includes the information bit sequence and the first CRC bit sequence.

[0233] Exemplarily, the second communication device determines the first CRC bit sequence according to the length of the CRC bit sequence and the first bit sequence, and then determines the information bit sequence according to the first CRC bit sequence and the first bit sequence.

[0234] Based on the above solution, it is possible to accurately determine whether there is a CRC bit sequence and accurately determine the length of the CRC bit sequence, which helps to improve the decoding accuracy.

[0235] Exemplarily, step 1503 may be: The second communication device can determine the information bit sequence according to the first bit sequence, the length of the CRC bit sequence, and the selected first CRC generation polynomial or the second CRC generation polynomial. Among them, the length of the first CRC generation polynomial is X, the length of the second CRC generation polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generation polynomial includes the first CRC generation polynomial, that is, the first CRC generation polynomial is a proper subset of the second CRC generation polynomial. For example, when the length of the CRC bit sequence is the first length, the first CRC generation polynomial is selected; when the length of the CRC bit sequence is the second length, the second CRC generation polynomial is selected. Based on this method, by nesting the design of the first CRC generation polynomial and the second CRC generation polynomial, the number of registers and exclusive-OR gates can be reduced, thereby reducing power consumption.

[0236] For the specific design of the first CRC generator polynomial and the second CRC generator polynomial, please refer to the examples in Figures 11 to 14, which will not be elaborated further.

[0237] Furthermore, this application proposes an improved scheme, as shown in Figures 16 and 17, for the CRC module shown in Figure 5. Specifically, in the existing scheme, when the transmitting end (e.g., the first communication device) determines that the FEC module needs to perform convolutional coding and uses bite-head convolutional coding, the CRC module needs to postpone the first L bits of the bit sequence (hereinafter referred to as the third bit sequence) after concatenating the information bit sequence with the CRC bits to obtain a new bit sequence (hereinafter referred to as the first bit sequence), and input the first bit sequence into the FEC module for convolutional coding; when it is determined that the FEC module does not need to perform convolutional coding, the CRC module does not need to postpone the first L bits of the third bit sequence. Therefore, the transmitting end determines whether to postpone the first L bits of the third bit sequence based on whether convolutional coding is required, and this additional determination action will cause the transmitting end to increase the processing delay. A similar problem exists at the receiving end, where it needs to determine whether to perform convolutional code decoding and thus decide whether to prepend the last L bits of the corresponding bit sequence. This additional determination will increase the processing delay at the receiving end. The embodiments shown in Figures 16 and 17 below can solve this problem.

[0238] Figure 16 is a flowchart illustrating a communication method provided in an embodiment of this application. The method is executed by the sending end and includes the following steps:

[0239] Step 1601: The first communication device obtains the first bit sequence based on the third bit sequence.

[0240] The lengths of the first and third bit sequences are both K. The first L bits of the third bit sequence are the same as the last L bits of the first bit sequence, and the (L+1)th to the Kth bits of the third bit sequence are the same as the first to the KLth bits of the first bit sequence.

[0241] This can also be understood as reversing the first L bits of the third bit sequence (or bit reversing) to obtain the first bit sequence. For the meaning of bit reversal, please refer to the previous description.

[0242] Where L is the number of registers used in convolutional coding.

[0243] The third bit sequence can be an information bit sequence, or it can include both an information bit sequence and a CRC bit sequence, that is, a bit sequence following an information bit sequence concatenated with a CRC bit sequence.

[0244] For example, the third bit sequence is c0, c1, c2, c3, c4, c5, ..., c K-1 After the bit postposition operation, the first bit sequence obtained is c. L ,c L+1 ,c L+2 ,…,c K-1 ,c0,c1,…,c L-1 .

[0245] Step 1602: The first communication device performs convolutional coding on the first bit sequence to obtain a second bit sequence, and then sends the second bit sequence.

[0246] In other words, if convolutional coding is required in advance, specifically bit convolutional coding, then since the first bit sequence has already undergone bit post-processing, the first communication device can directly input the first bit sequence into the convolutional code encoder to complete channel coding and output the second bit sequence.

[0247] Step 1603: The first communication device transmits the first bit sequence without performing convolutional coding on the first bit sequence.

[0248] That is, if it is pre-set that convolutional coding is not required, the first bit sequence is sent directly.

[0249] Steps 1602 and 1603 above are optional and do not require a judgment operation. For example, if convolutional encoding is preset to be required, then step 1602 is executed and step 1603 is not executed; if convolutional encoding is preset to be not required, then step 1603 is executed and step 1602 is not executed.

[0250] Based on the above scheme, at the sending end, regardless of whether convolutional coding is required, the third bit sequence is bit-postped. Thus, the sending end does not need to make an additional judgment on whether to perform convolutional coding, thereby reducing processing latency.

[0251] As an implementation method, when the embodiment of Figure 16 is combined with the embodiment of Figure 10, the above step 1003 may specifically be: the first communication device determines the first CRC bit sequence according to the CRC bit sequence length and the information bit sequence, and determines the third bit sequence based on the information bit sequence and the first CRC bit sequence. The third bit sequence includes the information bit sequence and the first CRC bit sequence, and the first CRC bit sequence is located after the information bit sequence. Then the first communication device puts the first L bits of the third bit sequence after the first bit sequence to obtain the first bit sequence.

[0252] Figure 17 is a flowchart illustrating a communication method provided in an embodiment of this application. This method is executed by the receiving end, and the embodiment in Figure 17 corresponds to the embodiment in Figure 16. The method includes the following steps:

[0253] Step 1701: The second communication device receives the fourth bit sequence.

[0254] In cases where the first and second communication devices have pre-agreed to perform convolutional code encoding and decoding, the fourth bit sequence refers to the second bit sequence in the embodiment of Figure 16.

[0255] In the case that the first communication device and the second communication device have agreed in advance that convolutional code encoding and decoding are not required, the fourth bit sequence refers to the first bit sequence in the embodiment of FIG16.

[0256] Step 1702: When the second communication device performs convolutional code decoding on the fourth bit sequence, it performs convolutional code decoding on the fourth bit sequence to obtain the first bit sequence, and obtains the third bit sequence based on the first bit sequence.

[0257] If the first communication device and the second communication device have agreed in advance that convolutional code encoding and decoding need to be performed, the fourth bit sequence refers to the second bit sequence in the embodiment of Figure 16. The second communication device performs convolutional code decoding on the second bit sequence to obtain the first bit sequence, and then obtains the third bit sequence based on the first bit sequence.

[0258] The lengths of the first and third bit sequences are both K. The first L bits of the third bit sequence are the same as the last L bits of the first bit sequence, and the (L+1)th to the Kth bits of the third bit sequence are the same as the first to the KLth bits of the first bit sequence.

[0259] This can also be understood as prepending (or bit prepending) the last L bits of the first bit sequence to obtain the third bit sequence. For the meaning of bit prepending, please refer to the previous description.

[0260] Step 1703: The second communication device obtains the third bit sequence based on the fourth bit sequence without performing convolutional code decoding on the fourth bit sequence.

[0261] If the first communication device and the second communication device have agreed in advance that they do not need to perform convolutional code encoding and decoding, the fourth bit sequence refers to the first bit sequence in the embodiment of Figure 16. Then, the second communication device recovers the third bit sequence based on the first bit sequence.

[0262] For the relationship between the first bit sequence and the third bit sequence, please refer to the description in step 1702.

[0263] This can also be understood as prepending (or bit prepending) the last L bits of the first bit sequence to obtain the third bit sequence.

[0264] The third bit sequence can be an information bit sequence, or it can include both an information bit sequence and a CRC bit sequence, that is, a bit sequence following an information bit sequence concatenated with a CRC bit sequence.

[0265] Steps 1702 and 1703 above are optional and do not require a judgment operation. For example, if convolutional code decoding is preset to be required, then step 1702 is executed and step 1703 is not executed; if convolutional code decoding is preset to be not required, then step 1703 is executed and step 1702 is not executed.

[0266] Based on the above scheme, at the receiving end, regardless of whether convolutional code decoding is required, a bit pre-processing operation is performed. Therefore, the receiving end does not need to make an additional judgment on whether to perform convolutional code decoding, thus reducing processing latency.

[0267] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0268] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0269] In the case of adopting an integrated unit, FIG. 18 shows a possible exemplary block diagram of the device involved in the embodiments of the present application. As shown in FIG. 18, the device 1800 may include: a processing unit 1802 and a communication unit 1803. The processing unit 1802 is used to control and manage the operations of the device 1800. The communication unit 1803 is used to support the communication between the device 1800 and other devices. Optionally, the communication unit 1803 is also referred to as a transceiver unit, and may include a receiving unit and / or a transmitting unit, which are respectively used to perform receiving and transmitting operations. The device 1800 may further include a storage unit 1801, which is used to store the program code and / or data of the device 1800.

[0270] The device 1800 may be the first communication device in the above embodiments. The processing unit 1802 may support the device 1800 to perform the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1802 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1803 may support the communication between the device 1800 and other devices.

[0271] For example, in one embodiment, the processing unit 1802 is used to select a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; the communication unit 1803 is used to transmit the second bit sequence; wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as that of the second convolutional code encoder, and the number of exclusive-OR gates of the first convolutional code encoder is the same as that of the second convolutional code encoder.

[0272] For another example, in another embodiment, the processing unit 1802 is used to select a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; the communication unit 1803 is used to transmit the second bit sequence; wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as that of the second convolutional code encoder and is less than 6, the A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

[0273] For another example, in another embodiment, a processing unit 1802 is configured to select a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence, so as to obtain a second bit sequence; a communication unit 1803 is configured to transmit the second bit sequence; wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is different from the number of registers of the second convolutional code encoder, the A encoding branches of the first convolutional code encoder respectively correspond to A generating polynomials, the B encoding branches of the second convolutional code encoder respectively correspond to B generating polynomials, and any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

[0274] For another example, in another embodiment, a processing unit 1802 is configured to determine whether to add a CRC bit sequence; in the case of determining to add a CRC bit sequence, determine the length of the CRC bit sequence; and determine the first bit sequence according to the length of the CRC bit sequence and the information bit sequence, where the first bit sequence includes the information bit sequence and a first CRC bit sequence.

[0275] In a possible implementation method, the processing unit 1802 is configured to determine whether to add a CRC bit sequence, including: being configured to determine to add a CRC bit sequence when the length of the information bit sequence is greater than a first threshold.

[0276] In a possible implementation method, the processing unit 1802 is configured to determine whether to add a CRC bit sequence, including: being configured to determine to add a CRC bit sequence according to indication information.

[0277] In a possible implementation method, the processing unit 1802 is configured to determine the length of the CRC bit sequence, including: being configured to determine the length of the CRC bit sequence according to the length of the information bit sequence and a second threshold.

[0278] In a possible implementation method, the processing unit 1802 is configured to determine the first bit sequence according to the length of the CRC bit sequence and the information bit sequence, including: being configured to determine the first bit sequence according to the information bit sequence, the length of the CRC bit sequence, and a selected first CRC generating polynomial or a second CRC generating polynomial; wherein, the length of the first CRC generating polynomial is X, the length of the second CRC generating polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generating polynomial includes the first CRC generating polynomial.

[0279] For another example, in another embodiment, the processing unit 1802 is configured to postpone the first L bits of the third bit sequence to obtain a first bit sequence, where L is the number of registers during convolutional code encoding; the processing unit 1802 is further configured to, when performing convolutional code encoding on the first bit sequence, perform convolutional code encoding on the first bit sequence to obtain a second bit sequence, and send the second bit sequence through the communication unit 1803; the processing unit 1802 is further configured to, when not performing convolutional code encoding on the first bit sequence, send the first bit sequence through the communication unit 1803.

[0280] The device 1800 may be the second communication device in the above embodiment. The processing unit 1802 may support the device 1800 to perform the actions of the second communication device in the above method embodiments. Alternatively, the processing unit 1802 mainly performs the internal actions of the second communication device in the method embodiments, and the communication unit 1803 may support the communication between the device 1800 and other devices.

[0281] For example, in one embodiment, the communication unit 1803 is configured to receive a second bit sequence; the processing unit 1802 is configured to select a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; where the number of encoding branches of the first convolutional code decoder is A, the number of encoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder, and the number of exclusive-OR gates of the first convolutional code decoder is the same as that of the second convolutional code decoder.

[0282] For another example, in another embodiment, the communication unit 1803 is configured to receive a second bit sequence; the processing unit 1802 is configured to select a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; where the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder and is less than 6, the A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

[0283] For another example, in another embodiment, a communication unit 1803 is configured to receive a second bit sequence; a processing unit 1802 is configured to select a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; wherein, the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is different from the number of registers of the second convolutional code decoder, the A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one, and any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

[0284] For another example, in another embodiment, a processing unit 1802 is configured to determine whether there is a CRC bit sequence; in the case of determining that there is a CRC bit sequence, determine the length of the CRC bit sequence; and determine an information bit sequence according to the length of the CRC bit sequence and the first bit sequence, where the first bit sequence includes the information bit sequence and a first CRC bit sequence.

[0285] In a possible implementation method, the processing unit 1802 is configured to determine whether there is a CRC bit sequence, including: being configured to determine that there is a CRC bit sequence when the length of the information bit sequence is greater than a first threshold.

[0286] In a possible implementation method, the processing unit 1802 is configured to determine whether there is a CRC bit sequence, including: being configured to determine that there is a CRC bit sequence according to indication information.

[0287] In a possible implementation method, the processing unit 1802 is configured to determine the length of the CRC bit sequence, including: being configured to determine the length of the CRC bit sequence according to the length of the information bit sequence and a second threshold.

[0288] In a possible implementation method, the processing unit 1802 is configured to determine an information bit sequence according to the length of the CRC bit sequence and the first bit sequence, including: being configured to determine the information bit sequence according to the first bit sequence, the length of the CRC bit sequence, and a selected first CRC generating polynomial or a second CRC generating polynomial; wherein, the length of the first CRC generating polynomial is X, the length of the second CRC generating polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generating polynomial includes the first CRC generating polynomial.

[0289] For example, in another embodiment, the communication unit 1803 is used to receive a fourth bit sequence; the processing unit 1802 is used to perform convolutional code decoding on the fourth bit sequence to obtain a first bit sequence, and to prepend the last L bits of the first bit sequence to obtain a third bit sequence; the processing unit 1802 is also used to prepend the last L bits of the fourth bit sequence to obtain the third bit sequence if convolutional code decoding is not performed on the fourth bit sequence; wherein, L is the number of registers during convolutional code encoding.

[0290] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0291] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0292] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0293] Based on the same technical concept, this application also provides a communication device for implementing the functions of the first or second communication device described above. As shown in FIG19, the device may be a communication equipment or a component of a communication equipment (e.g., a processor, chip, or chip system). The device includes a processor 1901 and a communication interface 1902, and optionally, a memory 1903. The memory 1903 may be independent of the processor 1901 or integrated into the processor 1901; no specific limitation is made. It is understood that FIG19 only shows the main components of the communication device. Furthermore, the communication device may further include input / output devices (not shown in the figure).

[0294] The processor 1901 is used to execute the program code stored in the memory 1903, specifically to perform the actions of the aforementioned processing unit 1802, which will not be described in detail here. The communication interface 1902 is specifically used to perform the actions of the aforementioned communication unit 1803, which will not be described in detail here.

[0295] Processor 1901 can be a CPU, a digital processing unit, etc. Processor 1901 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1902 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency (RF) transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1901 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0296] The communication interface 1902 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1902 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are mainly used for receiving user input data and outputting data to the user.

[0297] Memory 1903 is used to store programs executed by processor 1901. Memory 1903 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1903 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0298] When the communication device is powered on, the processor 1901 can read the software program in the memory 1903, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1901 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1901. The processor 1901 converts the baseband signal into data and processes the data.

[0299] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0300] This application embodiment does not limit the specific connection medium between the communication interface 1902, processor 1901, and memory 1903. In Figure 19, the memory 1903, processor 1901, and communication interface 1902 are connected via a bus 1904, which is represented by a thick line in Figure 19. The connection methods between other components are only illustrative and are not intended to be limiting. Buses can be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 19, but this does not mean that there is only one bus or one type of bus.

[0301] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0302] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0303] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0304] (3) Application-specific integrated circuit (ASIC), such as modem;

[0305] (4) Modules that can be embedded in other devices;

[0306] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0307] (6) Others, etc.

[0308] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0309] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0310] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0311] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0312] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0313] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. A communication method, characterized in that, The method includes: Selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; Transmitting the second bit sequence; Wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as the number of registers of the second convolutional code encoder, and the number of exclusive-OR gates of the first convolutional code encoder is the same as the number of exclusive-OR gates of the second convolutional code encoder.

2. The method as described in claim 1, characterized in that, The number of registers of the first convolutional code encoder is 6, and the number of exclusive-OR gates of the first convolutional code encoder is 12.

3. The method as described in claim 2, characterized in that, The coefficients of the generating polynomial of the second convolutional code encoder include 161, 151, 107, and 131, and 161, 151, 107, and 131 are all octal values; or, The coefficients of the generating polynomial of the second convolutional code encoder include 145, 153, 113, and 125, and 145, 153, 113, and 125 are all octal values.

4. A communication method, characterized in that, The method includes: Selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; Transmitting the second bit sequence; Wherein, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is the same as the number of registers of the second convolutional code encoder and is less than 6, the A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

5. The method as described in claim 4, characterized in that, The number of registers of the first convolutional code encoder is 4.

6. The method according to claim 5, wherein The coefficients of the generating polynomial of the first convolutional code encoder include 31 and 23; the coefficients of the generating polynomial of the second convolutional code encoder include 31, 23, 35, and 27, and 31, 23, 35, and 27 are all octal values; or, The coefficients of the generating polynomial of the first convolutional code encoder include 21 and 33; the coefficients of the generating polynomial of the second convolutional code encoder include 21, 33, 25, and 37, and 21, 33, 25, and 37 are all octal values.

7. A communication method, characterized in that, The method includes: Selecting a first convolutional code encoder or a second convolutional code encoder to encode a first bit sequence to obtain a second bit sequence; Transmitting the second bit sequence; Among them, the number of encoding branches of the first convolutional code encoder is A, the number of encoding branches of the second convolutional code encoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code encoder is different from the number of registers of the second convolutional code encoder, the A encoding branches of the first convolutional code encoder correspond to A generating polynomials one by one, the B encoding branches of the second convolutional code encoder correspond to B generating polynomials one by one, and any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

8. The method as described in claim 7, characterized in that, The number of registers of the first convolutional code encoder is equal to 4, and the number of registers of the second convolutional code encoder is greater than 4.

9. The method according to claim 8, wherein the coefficients of the generating polynomial of the first convolutional code encoder include 31 and 27, and both 31 and 27 are octal values, the coefficients of the generating polynomial of the second convolutional code encoder include 145, 135, 143 and 113, and both 145, 135, 143 and 113 are octal values; or the coefficients of the generating polynomial of the first convolutional code encoder include 25 and 23, and both 25 and 23 are octal values, the coefficients of the generating polynomial of the second convolutional code encoder include 125, 115, 161 and 153, and both 125, 115, 161 and 153 are octal values.

10. The method according to any one of claims 1 to 9, characterized in that, It further includes: judging whether to add a cyclic redundancy check (CRC) bit sequence; when it is determined to add a CRC bit sequence, determining the length of the CRC bit sequence; determining the first bit sequence according to the length of the CRC bit sequence and the information bit sequence, where the first bit sequence includes the information bit sequence and the first CRC bit sequence.

11. The method as described in claim 10, characterized in that, The judging whether to add a CRC bit sequence includes: when the length of the information bit sequence is greater than a first threshold value, determining to add a CRC bit sequence.

12. The method as described in claim 10, characterized in that, The judging whether to add a CRC bit sequence includes: determining to add a CRC bit sequence according to indication information.

13. The method according to any one of claims 10 to 12, characterized in that, The determining the length of the CRC bit sequence includes: determining the length of the CRC bit sequence according to the length of the information bit sequence and a second threshold value.

14. The method according to any one of claims 10 to 13, characterized in that, The determining the first bit sequence according to the length of the CRC bit sequence and the information bit sequence includes: determining the first bit sequence according to the information bit sequence, the length of the CRC bit sequence, and the selected first CRC generating polynomial or second CRC generating polynomial; wherein, the length of the first CRC generating polynomial is X, the length of the second CRC generating polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generating polynomial includes the first CRC generating polynomial.

15. A communication method, characterized in that, The method includes: receiving a second bit sequence; selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; Among them, the number of encoding branches of the first convolutional code decoder is A, the number of encoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder, and the number of exclusive-OR gates of the first convolutional code decoder is the same as that of the second convolutional code decoder.

16. The method as described in claim 15, characterized in that, The number of registers of the first convolutional code decoder is 6, and the number of exclusive-OR gates of the first convolutional code decoder is 12.

17. The method as described in claim 16, characterized in that, The coefficients of the generating polynomial of the second convolutional code decoder include 161, 151, 107, and 131, and 161, 151, 107, and 131 are all octal values; or, The coefficients of the generating polynomial of the second convolutional code decoder include 145, 153, 113, and 125, and 145, 153, 113, and 125 are all octal values.

18. A communication method, characterized in that, The method includes: Receiving a second bit sequence; Selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; Among them, the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is the same as that of the second convolutional code decoder and is less than 6, the A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one, and the B generating polynomials include the A generating polynomials.

19. The method as described in claim 18, characterized in that, The number of registers of the first convolutional code decoder is 4.

20. The method according to claim 19, wherein The coefficients of the generating polynomial of the first convolutional code decoder include 31 and 23; the coefficients of the generating polynomial of the second convolutional code decoder include 31, 23, 35, and 27, and 31, 23, 35, and 27 are all octal values; or, The coefficients of the generating polynomial of the first convolutional code decoder include 21 and 33; the coefficients of the generating polynomial of the second convolutional code decoder include 21, 33, 25, and 37, and 21, 33, 25, and 37 are all octal values.

21. A communication method, characterized in that, The method includes: Receiving a second bit sequence; Selecting a first convolutional code decoder or a second convolutional code decoder to decode the second bit sequence to obtain a first bit sequence; Among them, the number of decoding branches of the first convolutional code decoder is A, the number of decoding branches of the second convolutional code decoder is B, both A and B are positive integers and A < B; the number of registers of the first convolutional code decoder is different from the number of registers of the second convolutional code decoder. The A decoding branches of the first convolutional code decoder correspond to A generating polynomials one by one, and the B decoding branches of the second convolutional code decoder correspond to B generating polynomials one by one. Any one of the A generating polynomials is a proper subset of the corresponding generating polynomial among the B generating polynomials.

22. The method as described in claim 21, characterized in that, The number of registers of the first convolutional code decoder is equal to 4, and the number of registers of the second convolutional code decoder is greater than 4.

23. The method as described in claim 22, characterized in that, The coefficients of the generating polynomial of the first convolutional code decoder include 31 and 27, and both 31 and 27 are octal values. The coefficients of the generating polynomial of the second convolutional code decoder include 145, 135, 143, and 113, and 145, 135, 143, and 113 are all octal values; or, The coefficients of the generating polynomial of the first convolutional code decoder include 25 and 23, and both 25 and 23 are octal values. The coefficients of the generating polynomial of the second convolutional code decoder include 125, 115, 161, and 153, and 125, 115, and both 161 and 1 also represent octal values.

24. The method according to any one of claims 15 to 23, characterized in that, It further includes: Judge whether there is a cyclic redundancy check (CRC) bit sequence; When it is determined that there is a CRC bit sequence, determine the length of the CRC bit sequence; According to the length of the CRC bit sequence and the first bit sequence, determine the information bit sequence. The first bit sequence includes the information bit sequence and the first CRC bit sequence.

25. The method as described in claim 24, characterized in that, The judgment of whether there is a CRC bit sequence includes: When the length of the information bit sequence is greater than the first threshold value, determine that there is a CRC bit sequence.

26. The method as described in claim 24, characterized in that, The judgment of whether there is a CRC bit sequence includes: According to the indication information, determine that there is a CRC bit sequence.

27. The method according to any one of claims 24 to 26, characterized in that, The determination of the length of the CRC bit sequence includes: According to the length of the information bit sequence and the second threshold value, determine the length of the CRC bit sequence.

28. The method according to any one of claims 24 to 27, characterized in that, The determination of the information bit sequence according to the length of the CRC bit sequence and the first bit sequence includes: According to the first bit sequence, the length of the CRC bit sequence, and the selected first CRC generating polynomial or the second CRC generating polynomial, determine the information bit sequence; Among them, the length of the first CRC generating polynomial is X, the length of the second CRC generating polynomial is Y, both X and Y are positive integers and X < Y, and the second CRC generating polynomial includes the first CRC generating polynomial.

29. A communication device, characterized in that, It includes a processor, the processor is coupled with a memory, and a computer program is stored in the memory; the processor is used to call part or all of the computer program in the memory, so that the method described in any one of claims 1 to 14 is executed.

30. A communication device, characterized in that, The device includes a processor coupled to a memory in which a computer program is stored; the processor is configured to invoke part or all of the computer program in the memory such that the method as described in any one of claims 15 to 28 is executed.

31. A communication system, characterized in that, It includes a first communication device for performing the method according to any one of claims 1 to 14, and a second communication device for performing the method according to any one of claims 15 to 28.

32. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when some or all of the computer program is executed by a computer, causes the method as described in any one of claims 1 to 28 to be performed.

33. A computer program product, characterized in that, When the computer reads and executes the computer program product, the method as described in any one of claims 1 to 28 is performed.

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