Display substrate and display apparatus

Abstract

Provided are a display substrate and a display apparatus. The display substrate comprises: a base; a plurality of pixel units and a plurality of data lines, which are located in a display area; and a plurality of data lead-out lines and a plurality of first-type test circuit groups, which are located in a first bezel area, wherein the plurality of first-type test circuit groups are electrically connected to the plurality of data lead-out lines; and at least one first-type test circuit group comprises at least one first-type test circuit arranged in a first direction; and the first-type test circuit comprises a plurality of transistors arranged in the first direction, and the first-type test circuit is configured to provide a first-type test data signal to a column of pixel units, wherein the column of pixel units comprises a plurality of pixel units arranged in the first direction.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202510145335.0, filed on February 10, 2025, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This embodiment provides a display substrate and a display device.

[0006] On one hand, this embodiment provides a display substrate, including: a substrate, a plurality of pixel units, a plurality of data lines, a plurality of data lead-out lines, and a plurality of first-type test circuit groups. The substrate includes: a display area and a first border area located on one side of the display area along a first direction. The plurality of pixel units and the plurality of data lines are disposed on the substrate and located in the display area, the plurality of pixel units being electrically connected to the plurality of data lines, and the pixel units including a plurality of sub-pixels. The plurality of data lead-out lines are located in the first border area and are electrically connected to the plurality of data lines. The plurality of first-type test circuit groups are located in the first border area and connected to the plurality of data lead-out lines. At least one of the plurality of first-type test circuit groups includes at least one first-type test circuit arranged along the first direction; the first-type test circuit includes a plurality of transistors arranged along the first direction, and the first-type test circuit is configured to provide a first-type test data signal to a column of pixel units, the column of pixel units including a plurality of pixel units arranged along the first direction.

[0007] In some exemplary embodiments, the plurality of sub-pixels of the pixel unit includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light. The first type of test circuit includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit; each of the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit includes at least one transistor. The first test circuit is configured to provide a first type of test data signal to the first sub-pixel of the e-th row pixel unit in the column of pixel units during a first time period, and to provide a first type of test data signal to the second sub-pixel of the (e+1)-th row pixel unit in the column of pixel units during a second time period; the second test circuit is configured to provide a first type of test data signal to a column of third sub-pixels in the column of pixel units; the third test circuit is configured to provide a first type of test data signal to the first sub-pixel of the (e+1)-th row pixel unit in the column of pixel units during the first time period, and to provide a first type of test data signal to the second sub-pixel of the e-th row pixel unit in the column of pixel units during the second time period; wherein, e is a positive integer; the fourth test circuit is configured to provide a first type of test data signal to another column of third sub-pixels in the column of pixel units.

[0008] In some exemplary embodiments, the first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the at least one first type of test circuit group are arranged sequentially along the first direction.

[0009] In some exemplary embodiments, the display substrate further includes: a plurality of first test control lines, a plurality of second test control lines, a plurality of third test control lines, a plurality of first test data lines, a plurality of second test data lines, and at least one third test data line located in the first frame region. The first test circuit includes: at least one first test transistor and at least one second test transistor. The gate of the at least one first test transistor is connected to one of the plurality of first test control lines. The first electrode of the at least one first test transistor is connected to one of the plurality of first test data lines. The gate of the at least one second test transistor is connected to one of the plurality of second test control lines. The first electrode of the at least one second test transistor is connected to one of the plurality of second test data lines. The second electrodes of the at least one first test transistor and the at least one second test transistor are connected to the same data lead among the plurality of data leads. The second test circuit includes: at least one third test transistor, the gate of the at least one third test transistor being connected to one of the plurality of third test control lines, the first terminal of the at least one third test data line being connected to the at least one third test data line, and the second terminal of the at least one third test transistor being connected to one of the plurality of data lead lines. The third test circuit includes: at least one fourth test transistor and at least one fifth test transistor. The gate of the at least one fourth test transistor is connected to another second test control line among the plurality of second test control lines. The first terminal of the at least one fourth test transistor is connected to another first test data line among the plurality of first test data lines. The gate of the at least one fifth test transistor is connected to another first test control line among the plurality of first test control lines. The first terminal of the at least one fifth test transistor is connected to another second test data line among the plurality of second test data lines. The second terminals of the at least one fourth test transistor and the at least one fifth test transistor are connected to the same data lead among the plurality of data leads. The fourth test circuit includes: at least one sixth test transistor. The gate of the at least one sixth test transistor is connected to another third test control line among the plurality of third test control lines. The first terminal of the at least one sixth test transistor is connected to the at least one third test data line. The second terminal of the sixth test transistor is connected to one of the plurality of data leads. The data leads connected to the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit are different.

[0010] In some exemplary embodiments, the display substrate includes: four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines, and one third test data line; the first second test control line, the first first test control line, the first first test data line, the first second test data line, the second second test control line, the second first test control line, the first third test control line, the third third test data line, the second third test control line, the second first test data line, the third first test control line, the third second test control line, the fourth first test control line, and the second second test data line are arranged sequentially along the first direction; the first type of test circuit of the at least one first type of test circuit group includes: a first test transistor, a second test transistor, a third test transistor, a fourth test transistor, a fifth test transistor, and a sixth test transistor; the first test transistor and the first first test control line and the second second test data line are arranged sequentially along the first direction; The first test data line is connected and located between the first test control line and the first test data line in the first direction; the second test transistor is connected to the first second test data line and the second second test control line and located between the first second test data line and the second second test control line in the first direction; the third test transistor is connected to the first third test control line and the third test data line and located between the first third test control line and the third test data line in the first direction; the fourth test transistor is connected to the second first test data line and the third second test control line and located between the second first test data line and the third first test control line in the first direction; the fifth test transistor is connected to the fourth first test control line and the second second test data line and located between the fourth first test control line and the second second test data line in the first direction.

[0011] In some exemplary embodiments, the display substrate includes: two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines, and three third test data lines; the first second test control line, the first first test data line, the second first test data line, the first first test control line, the second second test control line, the first second test data line, the second second test data line, the first third test control line, the first third test data line, the second third test data line, the third third test data line, the second third test control line, the third second test control line, the third first test data line, the fourth first test data line, the second first test control line, the fourth second test control line, the third second test data line, and the fourth second test data line are arranged sequentially along the first direction; the first type of test circuit of the at least one first type of test circuit group includes: two first test transistors, two second... The system includes a test transistor, two third test transistors, two fourth test transistors, two fifth test transistors, and two sixth test transistors. The two first test transistors are located in the first direction between the first first test data line and the second first test data line. The two second test transistors are located in the first direction between the first second test data line and the second second test data line. The two third test transistors are located in the first direction between the first third test data line and the second third test data line. The two sixth test transistors are located in the first direction between the second third test data line and the third third test data line. The two fourth test transistors are located in the first direction between the third first test data line and the fourth first test data line. The two fifth test transistors are located in the first direction between the third second test data line and the fourth second second test data line.

[0012] In some exemplary embodiments, the first first test transistor of the first type of test circuit is connected to the first first test data line and the first first test control line, and the second first test transistor is connected to the second first test data line and the first first test control line; the first second test transistor is connected to the first second test data line and the second second test control line, and the second second test transistor is connected to the second second test data line and the second second test control line; the first third test transistor is connected to the first third test data line and the first third test control line, and the second third test transistor is connected to the second third test data line and the first... The third test control line is connected; the first sixth test transistor is connected to the second third test data line and the second third test control line, and the second sixth test transistor is connected to the third third test data line and the second third third test control line; the first fourth test transistor is connected to the third first test data line and the third second test control line, and the second fourth test transistor is connected to the fourth first test data line and the third second second test control line; the first fifth test transistor is connected to the third second test data line and the second first test control line, and the second fifth test transistor is connected to the fourth second test data line and the second first test control line.

[0013] In some exemplary embodiments, the at least one first type of test circuit group includes two first type of test circuits arranged along the first direction. The first test circuit, the first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the first first type of test circuit are arranged sequentially along the first direction, and the second test circuit, the fourth test circuit, the first test circuit, and the third test circuit of the second first type of test circuit are arranged sequentially along the first direction.

[0014] In some exemplary embodiments, the display substrate includes: four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines, and two third test data lines. The first first test control lines, first first test data lines, first second test data lines, first second test control lines, first third test control lines, first third test data lines, second third test control lines, second second test control lines, second first test data lines, second second test data lines, second first test control lines, third third test control lines, second third test data lines, fourth third test control lines, third first test control lines, third first test data lines, third second test data lines, third second test control lines, fourth second test control lines, fourth first test data lines, fourth second test data lines, and fourth first test control lines are arranged sequentially along the first direction.

[0015] In some exemplary embodiments, the display substrate further includes: a plurality of second-type test circuit groups, at least one of the plurality of second-type test circuit groups including: at least one second-type test circuit arranged along the first direction, the second-type test circuit including a plurality of transistors arranged along the first direction, the second-type test circuit being configured to provide a second-type test data signal to the column of pixel units.

[0016] In some exemplary embodiments, the second type of test circuit includes a fifth test circuit, a sixth test circuit, a seventh test circuit, and an eighth test circuit. The column of pixel units includes four columns of sub-pixels; the fifth, sixth, seventh, and eighth test circuits of the second type of test circuit are configured to provide second type of test data signals to the four columns of sub-pixels; the eighth, seventh, sixth, and fifth test circuits of the second type of test circuit are arranged sequentially along the first direction.

[0017] In some exemplary embodiments, the fifth test circuit includes at least one seventh test transistor, the sixth test circuit includes at least one eighth test transistor, the seventh test circuit includes at least one ninth test transistor, and the eighth test circuit includes at least one tenth test transistor. The display substrate further includes multiple fourth test control lines, multiple fourth test data lines, and multiple fifth test data lines located in the first frame region. The gates of the seventh and eighth test transistors are connected to the same fourth test control line among the multiple fourth test control lines. The first terminals of the seventh and eighth test transistors are connected to the same fourth test data line among the multiple fourth test data lines. The second terminal of the seventh test transistor is connected to one of the multiple data lead-out lines, and the second terminal of the eighth test transistor is connected to another data lead-out line among the multiple data lead-out lines. The gates of the ninth test transistor and the tenth test transistor are connected to the same fourth test control line among the plurality of fourth test control lines. The first terminals of the ninth test transistor and the tenth test transistor are connected to the same fifth test data line among the plurality of fifth test data lines. The second terminal of the ninth test transistor is connected to another data lead among the plurality of data lead lines. The second terminal of the tenth test transistor is connected to another data lead among the plurality of data lead lines.

[0018] In some exemplary embodiments, the display substrate further includes: two first frame power lines and three second frame power lines located in the first frame region, wherein the first second frame power line and the second second frame power line are located on both sides of the two first frame power lines and the third second frame power line, and the two first frame power lines are located on both sides of the third second frame power line.

[0019] In some exemplary embodiments, the display substrate further includes: four sets of initial signal lines located in the first frame region, wherein the first set of initial signal lines is located on the side of the first second frame power line away from the third second frame power line, the second set of initial signal lines is located on the side of the first second frame power line close to the third second frame power line, the third set of initial signal lines is located on the side of the second second frame power line close to the third second frame power line, and the fourth set of initial signal lines is located on the side of the second second frame power line away from the third second frame power line.

[0020] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0021] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0022] Overview of the attached figures

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2A is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0026] Figure 2B is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of the arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure;

[0028] Figure 4 is a circuit schematic diagram of a first type of test circuit according to at least one embodiment of the present disclosure;

[0029] Figure 5 is an equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0030] Figure 6 is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0031] Figure 7A is a schematic diagram of the first semiconductor layer in Figure 6;

[0032] Figure 7B is a schematic diagram of the first semiconductor layer and the first gate metal layer in Figure 6;

[0033] Figure 7C is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 6;

[0034] Figure 8 is another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0035] Figure 9 is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0036] Figure 10A is a schematic diagram of the first semiconductor layer and the first gate metal layer in Figure 9;

[0037] Figure 10B is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 9;

[0038] Figure 11 is another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0039] Figure 12 is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0040] Figure 13 is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 12;

[0041] Figure 14 is another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure;

[0042] Figure 15 is an equivalent circuit diagram of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure;

[0043] Figure 16 is a plan view of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure;

[0044] Figure 17 is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 16;

[0045] Figure 18 is a partial wiring diagram of the first border region of at least one embodiment of the present disclosure;

[0046] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0047] Detailed Explanation

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0049] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0050] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0051] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0052] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0053] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0054] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0055] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0056] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0057] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0058] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0059] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0060] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate can be a closed polygon including linear edges. The display substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first border area B1 and a fourth border area B4 located on both sides of the display area AA along a first direction D1, and a second border area B2 and a third border area B3 located on both sides of the display area AA along a second direction D2. The first border area B1 may be connected to the second border area B2 and the third border area B3, and the fourth border area B4 may be connected to the second border area B2 and the third border area B3. The first border area B1, the second border area B2, the third border area B3, and the fourth border area B4, after being connected, can surround the display area AA. For example, the first border area B1 may also be referred to as the lower border area of ​​the display substrate, the second border area B2 may also be referred to as the left border area of ​​the display substrate, the third border area B3 may also be referred to as the right border area of ​​the display substrate, and the fourth border area B4 may also be referred to as the upper border area of ​​the display substrate. However, this embodiment is not limited in this respect.

[0061] In some examples, as shown in Figure 1, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 arranged sequentially along the side away from the display region AA in a first direction D1. The first sub-region B11 may be connected to the second border region B2, the third border region B3, and the display region AA. The bent region B12 may connect the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back side of the display region AA.

[0062] In some examples, as shown in Figure 1, the second sub-region B13 may include: a circuit setting area B133, a first signal access area B131, and a second signal access area B132 arranged sequentially along the first direction D1 away from the bending area B12. The circuit setting area B133 may be provided with multiple electrostatic discharge circuits and multiple test circuits. The multiple test circuits may be configured to provide test data signals to multiple data lines DL of the display area AA. The multiple electrostatic discharge circuits may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. For example, the multiple electrostatic discharge circuits may be located on the side of the multiple test circuits closer to the bending area B12.

[0063] In some examples, the first signal access area B131 may be provided with a plurality of first contact pads, which may be configured to connect to an integrated circuit (IC). Some of the plurality of first contact pads may be configured to provide data signals to multiple data lines. The second signal access area B132 may be provided with a plurality of second contact pads, which may be configured to bond to an external flexible printed circuit board (FPC). At least one first contact pad in the first signal access area B131 and at least one second contact pad in the second signal access area B132 may be connected by an inner lead bonding (ILB).

[0064] In some examples, the display area AA may include: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and emission control signals, or may include scan signals, reset control signals, and emission control signals.

[0065] In some examples, the second direction D2 can be the extension direction of the grid line GL within the display area AA (e.g., the row direction); the first direction D1 can be the extension direction of the data line DL within the display area AA (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0066] In some examples, a pixel unit of the display area AA may include multiple sub-pixels. For instance, a pixel unit may include four sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and two third sub-pixels emitting a third color light (e.g., green light). In other examples, a pixel unit may include three sub-pixels, which may be a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.

[0067] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the processing difficulty of the display substrate, and improves product yield.

[0068] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this. In other examples, when a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement.

[0069] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0070] Figure 2A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 2A illustrates the structure of a sub-pixel of display area AA as an example. In this example, the pixel circuit includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0071] In some examples, as shown in FIG2A, the display area of ​​the display substrate may include a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate 10. The circuit structure layer 12 may include at least pixel circuits for multiple sub-pixels, and each sub-pixel's pixel circuit may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least light-emitting elements for multiple sub-pixels. In other examples, the display substrate may also include a touch structure layer located on the side of the encapsulation structure layer 14 away from the substrate 10.

[0072] In some examples, Figure 2A illustrates a subpixel comprising a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 can be a low-temperature polycrystalline silicon thin-film transistor, and the second-type transistor 22 can be an oxide thin-film transistor.

[0073] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer, wherein the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second planarization layer) may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 can be inorganic insulating layers, while the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can also be provided on the side of the first semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can also be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistors in the pixel circuit to avoid external light affecting the performance of the transistors. In other examples, the sixth insulating layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the seventh insulating layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0074] In some examples, as shown in FIG2A, the first semiconductor layer of the display area may include at least: a first active layer 210 of a first type transistor 21. The first active layer 210 of the first type transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate 213 of the first type transistor 21, and a first electrode 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first type transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the first active layer 210 onto the substrate 10. The second gate metal layer may include at least: a second electrode 232 of the capacitor 23, and a third gate 224 of the second type transistor 22. The orthographic projections of the second electrode 232 and the first electrode 231 of the capacitor 23 onto the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least: a second active layer 220 of the second type transistor 22. The third gate metal layer may include at least: a second gate 223 of the second type transistor 22. The orthographic projection of the second gate 223 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The orthographic projection of the third gate 224 of the second type transistor 22 onto the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 onto the substrate 10. The third gate 224 may be the bottom gate of the second type transistor 22, and the second gate 223 may be the top gate of the second type transistor 22.

[0075] In some examples, as shown in FIG2A, the first source-drain metal layer of the display area may include at least: a first source 211 and a first drain 212 of a first type transistor 21, and a second source 221 and a second drain 222 of a second type transistor 22. The fifth insulating layer 105 may have multiple pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 in the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, and the third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least a portion of the surface at both ends of the second active layer 220. The first source 211 of the first type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer may include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain 212 of the first type transistor 21 in the pixel circuit through the fifth pixel via formed by the sixth insulating layer 106 and the seventh insulating layer 107. This example demonstrates the electrical connection between the pixel circuit and the light-emitting element via the first adapter electrode 241.

[0076] In some examples, the gate lines of the display area may be located, for example, in the first and third gate metal layers; the data lines of the display area may be located, for example, in the second source-drain metal layer; the first power lines of the display area may be located, for example, in the second source-drain metal layer; the first data connection segment of the data connection line of the display area may be located, for example, in the first source-drain metal layer; and the second data connection segment may be located, for example, in the second source-drain metal layer. This embodiment is not limited in this respect. In other examples, the circuit structure layer of the display area may further include a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate, and the data connection lines may be located in the third source-drain metal layer.

[0077] In some examples, as shown in Figure 2A, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on an eighth insulating layer 108 and electrically connected to a first transition electrode 241 through a sixth pixel via formed in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0078] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0079] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0080] In some examples, as shown in Figure 2A, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density, preventing the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, such as polymer materials containing desiccants or polymer materials that can block moisture, or polymer resins to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141 and 143. It may also include water-absorbing materials such as desiccants to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited to these limitations. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0081] Figure 2B is another partial cross-sectional schematic diagram of the display area according to at least one embodiment of the present disclosure. In some examples, the transistor types of the multiple pixel transistors in the pixel circuit can be the same, for example, they can all be low-temperature polycrystalline silicon thin-film transistors. Figure 2B illustrates an example of each sub-pixel including a first-type transistor 21 and a capacitor 23.

[0082] In some examples, as shown in FIG2B, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer; a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source / drain metal layer and the second source / drain metal layer; and an eighth insulating layer 108 may be disposed on the side of the second source / drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The remaining structure of the display area of ​​the display substrate of this example can be referred to the description of the embodiment shown in FIG2A, and will not be repeated here.

[0083] In some implementations, the test circuit located in the first bezel area requires a large amount of routing space, which limits the arrangement space of other traces in the first bezel area. The limited space for some traces in the first bezel area (such as traces for transmitting power signals and control signals) can easily affect the display effect of the display substrate.

[0084] This embodiment provides a display substrate, including: a substrate, multiple pixel units, multiple data lines, multiple data lead-out lines, and multiple first-type test circuit groups. The substrate includes a display area and a first border area located on one side of the display area along a first direction. The multiple pixel units and multiple data lines are disposed on the substrate and located in the display area. The multiple pixel units are electrically connected to the multiple data lines, and each pixel unit includes multiple sub-pixels. The multiple data lead-out lines are located in the first border area and are electrically connected to the multiple data lines. The multiple first-type test circuit groups are located in the first border area and are connected to the multiple data lead-out lines. Each first-type test circuit group includes at least one first-type test circuit arranged along the first direction, and the first-type test circuit includes multiple transistors arranged along the first direction. The first-type test circuits are configured to provide first-type test data signals to a column of pixel units. A column of pixel units includes multiple pixel units arranged along the first direction.

[0085] In some examples, multiple groups of first-type test circuits can be arranged along a second direction. The second direction intersects the first direction; for example, the plane containing the second and first directions is parallel to the plane containing the substrate, and the second direction can be perpendicular to the first direction.

[0086] The display substrate provided in this embodiment arranges at least one type of test circuit along a first direction, and arranges multiple transistors of the type of test circuit along the first direction. This helps to compress the arrangement space of the test circuit along the second direction in the first frame area, thereby helping to optimize the arrangement space of the remaining traces in the first frame area and ensuring the trace width of the remaining traces.

[0087] The following examples illustrate the solution of this embodiment.

[0088] Figure 3 is a schematic diagram of the arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, a pixel unit in the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light. Multiple pixel units can be arranged in an array within the display area AA. The pixel circuits of the multiple sub-pixels can be arranged in an array along a first direction D1 and a second direction D2. Within a single pixel unit, the light-emitting elements of the four sub-pixels can be arranged in different columns along the second direction D2. The light-emitting elements of the first sub-pixel 15 and the second sub-pixel 16 can be arranged in the same row, and the light-emitting elements of the two third sub-pixels 17a and 17b can be arranged in the same row. The rows containing the light-emitting elements of the first sub-pixel 15 and the third sub-pixel 17a can be spaced apart along the first direction D1. In this example, the first sub-pixel 15 can be a red sub-pixel (R), the second sub-pixel 16 can be a blue sub-pixel (B), and the third sub-pixels 17a and 17b can be green sub-pixels (G). For example, the third sub-pixel 17a can be the first green sub-pixel (G1), and the third sub-pixel 17b can be the second green sub-pixel (G2).

[0089] In some examples, as shown in Figure 3, multiple pixel units arranged along the second direction D2 can be a row of pixel units, and multiple pixel units arranged along the first direction D1 can be a column of pixel units. Multiple pixel units can include multiple first pixel units and multiple second pixel units, and the arrangement order of the four sub-pixels within the first and second pixel units can be different. For example, the e-th row of pixel units can include: multiple first pixel units arranged sequentially along the second direction D2; the first sub-pixel 15, third sub-pixel 17a, second sub-pixel 16, and third sub-pixel 17b of the first pixel unit are arranged sequentially along the second direction D2. The (e+1)-th row of pixel units can include: multiple second pixel units arranged sequentially along the second direction D2; the second sub-pixel 16, third sub-pixel 17b, first sub-pixel 15, and third sub-pixel 17a of the second pixel unit can be arranged sequentially along the second direction D2. A column of pixel units can include: first pixel units and second pixel units alternately arranged along the first direction D1. Here, e can be an integer greater than 0. For example, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in RG1BG2, and the subpixels of even-numbered rows of pixel units can be arranged in BG2RG1; or, the subpixels of odd-numbered rows of pixel units in the display area can be arranged in BG2RG1, and the subpixels of even-numbered rows of pixel units can be arranged in RG1BG2.

[0090] In some examples, multiple subpixels arranged along the first direction D1 can be a column of subpixels. A column of pixels can include four columns of subpixels, such as columns j to j+3. The j-th and j+2-th subpixels can include: a first subpixel 15 and a second subpixel 16 alternately arranged along the first direction D1; the j+1-th and j+3-th subpixels can include: a third subpixel 17a and 17b alternately arranged along the first direction D1. j can be an integer greater than 1. The pixel circuit of each column of subpixels can be connected to the same data line. For example, the j-th column of subpixels can be connected to data line DLj, the j+1-th column of subpixels can be connected to data line DLj+1, the j+2-th column of subpixels can be connected to data line DLj+2, and the j+3-th column of subpixels can be connected to data line DLj+3.

[0091] Figure 4 is a circuit schematic diagram of a first type of test circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the first type of test circuit may include: a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404.

[0092] In some examples, the first test circuit 401 may include: a first test transistor T1 and a second test transistor T2. The gate of the first test transistor T1 is connected to the first test control line SWR, and the first terminal of the first test transistor T1 may be connected to the first test data line DR; the gate of the second test transistor T2 may be connected to the second test control line SWB, and the first terminal of the second test transistor T2 may be connected to the second test data line DB; the second terminals of the first test transistor T1 and the second terminal of the second test transistor T2 may be connected to the same data lead (e.g., data lead DA(n)). Here, n is a positive integer.

[0093] In some examples, the second test circuit 402 may include a third test transistor T3. The gate of the third test transistor T3 may be connected to a third test control line SWG, the first terminal of the third test transistor T3 may be connected to a third test data line DG, and the second terminal of the third test transistor T3 may be connected to a data lead (e.g., data lead DA(n+1)).

[0094] In some examples, the third test circuit 403 may include a fourth test transistor T4 and a fifth test transistor T5. The gate of the fourth test transistor T4 may be connected to the second test control line SWB, and the first terminal of the fourth test transistor T4 may be connected to the first test data line DR. The gate of the fifth test transistor T5 may be connected to the first test control line SWR, and the first terminal of the fifth test transistor T5 may be connected to the second test data line DB. The second terminals of the fourth test transistor T4 and the fifth test transistor T5 may be connected to the same data lead (e.g., data lead DA(n+2)).

[0095] In some examples, the fourth test circuit 404 may include a sixth test transistor T6. The gate of the sixth test transistor T6 may be connected to the third test control line SWG, the first terminal of the sixth test transistor T6 may be connected to the third test data line DG, and the second terminal of the sixth test transistor T6 may be connected to a data lead (e.g., data lead DA(n+3)).

[0096] In some examples, data lead-out line DA(n) can be connected to data line DLj, and the connected column of sub-pixels can include a first sub-pixel (R) and a second sub-pixel (B). Similarly, data lead-out line DA(n+2) can be connected to data line DLj+2, and the connected column of sub-pixels can also include a first sub-pixel (R) and a second sub-pixel (B). For a row of pixel units in the display area, the sub-pixels connected to data lead-out line DA(n) and data lead-out line DA(n+2) emit different colors of light. For example, for the e-th row of pixel units, data lead-out line DA(n) can be connected to the first sub-pixel via data line DLj, and data lead-out line DA(n+2) can be connected to the second sub-pixel via data line DLj+2; for the (e+1)-th row of pixel units, data lead-out line DA(n) can be connected to the second sub-pixel via data line DLj, and data lead-out line DA(n+2) can be connected to the first sub-pixel via data line DLj+2.

[0097] In some examples, data lead-out line DA(n+1) can be connected to data line DLj+1, and the connected column of sub-pixels includes a third sub-pixel (e.g., including a first green sub-pixel G1 and a second green sub-pixel G2 arranged at intervals); data lead-out line DA(n+3) can be connected through data line DLj+3, and the connected column of sub-pixels includes a third sub-pixel (e.g., including a first green sub-pixel G1 and a second green sub-pixel G2 arranged at intervals).

[0098] In some examples, the first test control line SWR can be configured to control the first test transistor T1 in the first test circuit 401 and the fifth test transistor T5 in the third test circuit 403 to turn on, and the second test control line SWB can be configured to control the second test transistor T2 in the first test circuit 401 and the fourth test transistor T4 in the third test circuit 403 to turn on, so that the first type of test data signal transmitted by the first test data line DR and the second test data line DB can be written to different data lines through the data lead-out line.

[0099] In some examples, the first type of test data signal may include: a first test data signal provided by a first test data line, a second test data signal provided by a second test data line, and a third test data signal provided by a third test data line. The first test circuit 401 can be configured to provide a first type of test data signal (e.g., a first test data signal) to the first sub-pixel of the e-th row pixel unit in a column of pixel units during a first time period, and to provide a first type of test data signal (e.g., a second test data signal) to the second sub-pixel of the e+1-th row pixel unit in the same column of pixel units during a second time period; the third test circuit 403 can be configured to provide a first type of test data signal (e.g., a first test data signal) to the first sub-pixel of the e+1-th row pixel unit in the same column of pixel units during a first time period, and to provide a first type of test data signal (e.g., a second test data signal) to the second sub-pixel of the e-th row pixel unit in the same column of pixel units during a second time period; the second test circuit 402 can be configured to provide a first type of test data signal (e.g., a third test data signal) to a column of third sub-pixels in the same column of pixel units; and the fourth test circuit 404 can be configured to provide a first type of test data signal (e.g., a third test data signal) to another column of third sub-pixels in the same column of pixel units.

[0100] In some examples, during display testing (e.g., color display testing), a control device can provide a conduction signal to the first test control line SWR (or the second test control line SWB) and the third test control line SWG, and provide the required first-type test data signals to multiple test data lines (e.g., including the first test data line DR, the second test data line DB, and the third test data line DG), so that multiple data lines in the display area obtain the first-type test data signals, and determine whether there are defective sub-pixels by the color of the displayed screen, and locate the defective sub-pixels.

[0101] In some examples, to achieve a narrow bezel design, the data lines in the display area are divided into two categories. The first category of data lines can be directly connected to the data leads in the first bezel area. The second category of data lines can be connected to the data leads in the first bezel area via data connection lines located in the display area. This effectively reduces the length of the first sub-area along the first direction, thereby significantly reducing the size of the bottom bezel of the display substrate. During the conversion of the second category of data lines via data connection lines, the order of the data leads in the first bezel area is disrupted, making the order of the data leads in the first bezel area different from the order of the data lines in the display area. To ensure compatibility with integrated circuits, the order of the data signals provided by the multiple first contact pads in the first signal access area can adapt to the arrangement order of the data signals in the display area after conversion via data connection lines. That is, the data signals provided by the multiple first contact pads can have a first order, undergo a data conversion in the second sub-area to change the order of the data signals, or have a second order, undergo another data conversion in the first sub-area to restore the order of the data signals to the first order, allowing the data lines in the display area to receive the required data signals. Based on this, the order of the first type of test data signals provided by the test circuit set in the second sub-region is the aforementioned second order, and after being converted back to the first order in the first sub-region, they are provided to the data lines of the display area.

[0102] Figure 5 is an equivalent circuit diagram of multiple first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 6 is a plan view of multiple first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 7A is a schematic diagram of the first semiconductor layer in Figure 6; Figure 7B is a schematic diagram of the first semiconductor layer and the first gate metal layer in Figure 6; Figure 7C is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 6. This example uses the film layer structure of a display substrate as shown in Figure 2B as an example for illustration. The order of the first-type test signals provided by the multiple first-type test circuit groups in this example can be the aforementioned second order.

[0103] In some examples, as shown in Figures 5 and 6, the display substrate may include a plurality of first-type test circuit groups located in a circuit setting area of ​​a first frame region and arranged along a second direction D2. Figures 5 and 6 illustrate six first-type test circuit groups as an example. Each first-type test circuit group may include one first-type test circuit. The first-type test circuit may include a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404. At least one first-type test circuit may have its first test circuit 401, second test circuit 402, fourth test circuit 404, and third test circuit 403 arranged sequentially along the first direction D1 in a direction away from the display area; at least one first-type test circuit may have its third test circuit 403, second test circuit 402, fourth test circuit 404, and first test circuit 401 arranged sequentially along the first direction D1 in a direction away from the display area.

[0104] The following description uses the first type of test circuit group shown in Figures 5 and 6 as an example. The first test transistor T1 and the second test transistor T2 of the first test circuit 401, the third test transistor T3 of the second test circuit 402, the sixth test transistor T6 of the fourth test circuit 404, and the fourth test transistor T4 and the fifth test transistor T5 of the third test circuit 403 can be arranged sequentially in the first direction D1, for example, along the direction away from the display area AA.

[0105] In some examples, multiple data leads can be divided into multiple groups of data leads, each group of which may include the following four: a first data lead 51, a second data lead 52, a third data lead 53, and a fourth data lead 54. For example, a group of data leads may be configured to provide data signals or test data signals to a column of pixel units.

[0106] In some examples, the first border area can also be provided with multiple first test control lines (e.g., four first test control lines SWR1, SWR2, SWR3, and SWR4), multiple second test control lines (e.g., three second test control lines SWB1, SWB2, and SWB3), multiple third test control lines (e.g., including two third test control lines SWG1 and SWG2), multiple first test data lines (e.g., two first test data lines DR1 and DR2), multiple second test data lines (e.g., two second test data lines DB1 and DB2), and one third test data line DG. The four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines, and one third test data line within the circuit setting area can be of the same layer and all extend along the second direction D2.

[0107] In some examples, the first second test control line SWB1, the first first test control line SWR1, the first first test data line DR1, the first second test data line DB1, the second second test control line SWB2, the second first test control line SWR2, the first third test control line SWG1, the third test data line DG, the second third test control line SWG2, the second second test data line DR2, the third first test control line SWR3, the third second test control line SWB3, the fourth first test control line SWR4, and the second second test data line DB2 can be arranged in the first direction D1 along a direction away from the display area. Specifically, the first second test control line SWB1 and the first first test control line SWR1 can be adjacent in the first direction D1; the first first test data line DR1 and the first second test data line DB1 can be adjacent in the first direction D1; the second second test control line SWB2, the second first test control line SWR2 and the first third test control line SWG1 can be adjacent in the first direction D1; the second third test control line SWG2 and the second first test data line DR2 can be adjacent in the first direction D1; and the third first test control line SWR3, the third second test control line SWB3 and the fourth first test control line SWR4 can be adjacent in the first direction D1.

[0108] In some examples, in the first type 1 test circuit group, the first test transistor T1 may be located between the first first test control line SWR1 and the first first test data line DR1, and connected to both the first first test control line SWR1 and the first first test data line DR1; the second test transistor T2 may be located between the first second test data line DB1 and the second second test control line SWB2, and connected to both the first second test data line DB1 and the second second test control line SWB2; the third test transistor T3 may be located between the first third test control line SWG1 and the third test data line DG, and connected to both the first third test control line SWG1 and the first first test data line DR1. The three test data lines DG are connected; the sixth test transistor T6 can be located between the third test data line DG and the second third test control line SWG2, and is connected to the third test data line DG and the second third test control line SWG2; the fourth test transistor T4 can be located between the second first test data line DR2 and the third first test control line SWR3, and is connected to the second first test data line DR2 and the third second test control line SWB3; the fifth test transistor T5 can be located between the fourth first test control line SWR4 and the second second test data line DB2, and is connected to the fourth first test control line SWR4 and the second second test data line DB2.

[0109] In some examples, as shown in Figure 7A, the first semiconductor layer of the circuit setting area in the first frame region may include: the active layer T10 of the first test transistor T1, the active layer T20 of the second test transistor T2, the active layer T30 of the third test transistor T3, the active layer T40 of the fourth test transistor T4, the active layer T50 of the fifth test transistor T5, and the active layer T60 of the sixth test transistor T6. The active layers T10 of the first test transistor T1, T20 of the second test transistor T2, and T30 of the third test transistor T3 in a first-type test circuit group can be aligned along the first direction D1. The active layers T60 of the sixth test transistor T6, T40 of the fourth test transistor T4, and T50 of the fifth test transistor T5 can be arranged sequentially along the first direction D1. The active layers T60 of the sixth test transistor T6 and T30 of the third test transistor T3 may be slightly misaligned in the second direction D2.

[0110] In some examples, as shown in FIG7B, the first gate metal layer of the circuit setting area of ​​the first frame region may include: the gate T11 of the first test transistor T1, the gate T21 of the second test transistor T2, the gate T31 of the third test transistor T3, the gate T41 of the fourth test transistor T4, the gate T51 of the fifth test transistor T5, the gate T61 of the sixth test transistor T6, multiple data leads (e.g., including the second data lead 52 and the fourth data lead 54), and multiple connection blocks (e.g., including the first connection block 311 and the second connection block 312).

[0111] In some examples, the orthographic projection of the gate T11 of the first test transistor T1, the gate T31 of the third test transistor T3, and the gate T51 of the fifth test transistor T5 onto the substrate can be approximately an L-shaped horizontal flip shape; the orthographic projection of the gate T21 of the second test transistor T2 and the gate T41 of the fourth test transistor T4 onto the substrate can be approximately an L-shaped shape rotated 180 degrees clockwise; and the orthographic projection of the gate T61 of the sixth test transistor T6 onto the substrate can be approximately an L-shaped vertical flip shape.

[0112] In some examples, the second data lead 52 and a first connection block 311 can be an integral structure, and the orthographic projection of the first connection block 311 onto the substrate can be located on the side of the active layer T30 of the third test transistor T3 closer to the second test transistor T2 in the first direction D1. The fourth data lead 54 and a second connection block 312 can be an integral structure, and the orthographic projection of the second connection block 312 onto the substrate can be located on the side of the active layer T60 of the sixth test transistor T6 away from the third test transistor T3 in the first direction D1.

[0113] In some examples, the second data lead 52 is a broken line extending along the first direction D1, with the bend located between the second test transistor T2 and the third test transistor T3. The fourth data lead 54 is a straight line extending along the first direction D1.

[0114] In some examples, as shown in FIG7C, the second gate metal layer of the circuit setting area of ​​the first frame region may include: multiple data leads (e.g., including the first data lead 51 and the third data lead 53) and multiple connection blocks (e.g., including the third connection block 313, the fourth connection block 314, the fifth connection block 315 and the sixth connection block 316).

[0115] In some examples, the first data lead 51 can be a straight line extending along the first direction D1 and located on one side of a first type of test circuit group along the second direction D2. The first data lead 51 can be integrated with the third connection block 313 and the fourth connection block 314. The third connection block 313 is connected to the side of the first data lead 51 near the first test transistor T1 and can be located on the side of the active layer T10 of the first test transistor T1 away from the second test transistor T2. The fourth connection block 314 can be connected to the side of the first data lead 51 near the second test transistor T2 and can be located on the side of the active layer T20 of the second test transistor T2 away from the first test transistor T1.

[0116] In some examples, the third data lead 53 can be a zigzag line extending along the first direction D1, and is integrally structured with the fifth connecting block 315 and the sixth connecting block 316. The bend of the third data lead 53 can be located between the active layer T30 of the third test transistor T3 and the active layer T60 of the sixth test transistor T6. The fifth connecting block 315 is connected to the side of the third data lead 53 near the fourth test transistor T4, and the fifth connecting block 315 can be located on the side of the active layer T40 of the fourth test transistor T4 near the fifth test transistor T5; the sixth connecting block 316 can be connected to the side of the third data lead 53 near the fifth test transistor T5, and the sixth connecting block 316 can be located on the side of the active layer T50 of the fifth test transistor T5 near the fourth test transistor T4.

[0117] In some examples, the first data lead 51, the second data lead 52, the third data lead 53, and the fourth data lead 54 can be arranged along the second direction D2. The active layer T10 of the first test transistor T1 and the active layer T20 of the second test transistor T2 can be located between a portion of the first data lead 51 and the second data lead 52. The active layer T30 of the third test transistor T3 can be located between another portion of the second data lead 52 and a portion of the third data lead 53. The active layer T60 of the sixth test transistor T6, the active layer T40 of the fourth test transistor T4, and the active layer T50 of the fifth test transistor T5 can be located between another portion of the third data lead 53 and the fourth data lead 54.

[0118] In some examples, as shown in Figure 6, the first source-drain metal layer of the circuit setting area in the first frame region may include: multiple test control lines (e.g., first test control lines SWR1, SWR2, SWR3, SWR4, second test control lines SWB1, SWB2, SWB3, and third test control lines SWG1, SWG2), multiple test data lines (e.g., first test data lines DR1, DR2, second test data lines DB1, DB2, and third test data line DG), and multiple connection electrodes (e.g., first connection electrode 411, second connection electrode 412, third connection electrode 413, fourth connection electrode 414, fifth connection electrode 415, and sixth connection electrode 416). The orthographic projection of the first connection electrode 411 to the sixth connection electrode 416 onto the substrate may be approximately a strip extending along the first direction D1.

[0119] In some examples, the first connection electrode 411 can be connected to the third connection block 313 and the second region of the active layer T10 of the first test transistor T1; since the third connection block 313 and the first data lead 51 are integrally structured, the first test transistor T1 is electrically connected to the first data lead 51. The first region of the active layer T10 of the first test transistor T1 can be connected to the first first test data line DR1. The gate T11 of the first test transistor T1 can be connected to the first first test control line SWR1.

[0120] In some examples, the second connection electrode 412 can be connected to the fourth connection block 314 and the second region of the active layer T20 of the second test transistor T2. Since the fourth connection block 314 and the first data lead 51 are integrally formed, the second test transistor T2 is electrically connected to the first data lead 51. The first region of the active layer T20 of the second test transistor T2 can be connected to the first second test data line DB1. The gate T21 of the second test transistor T2 can be connected to the second second test control line SWB2.

[0121] In some examples, the third connection electrode 413 can be connected to the first connection block 311 and the second region of the active layer T30 of the third test transistor T3. Since the first connection block 311 and the second data lead 52 are integrally structured, the third test transistor T3 is electrically connected to the second data lead 52. The first region of the active layer T30 of the third test transistor T3 can be connected to the third test data line DG. The gate T31 of the third test transistor T3 can be connected to the first third test control line SWG1.

[0122] In some examples, the sixth connection electrode 416 can be connected to the second connection block 312 and the second region of the active layer T60 of the sixth test transistor T6. Since the second connection block 312 and the fourth data lead 54 are integrally formed, an electrical connection between the sixth test transistor T6 and the fourth data lead 54 can be achieved. The first region of the active layer T60 of the sixth test transistor T6 can be connected to the third test data line DG. The gate T61 of the sixth test transistor T6 can be connected to the second third test control line SWG2.

[0123] In some examples, the fourth connection electrode 414 can be connected to the fifth connection block 315 and the second region of the active layer T40 of the fourth test transistor T4. Since the fifth connection block 315 and the third data lead 53 are integrally structured, an electrical connection between the fourth test transistor T4 and the third data lead 53 can be achieved. The first region of the active layer T40 of the fourth test transistor T4 can be connected to the second first test data line DR2. The gate T41 of the fourth test transistor T4 can be connected to the third second test control line SWB3.

[0124] In some examples, the fifth connection electrode 415 can be connected to the sixth connection block 316 and the second region of the active layer T50 of the fifth test transistor T5. Since the sixth connection block 316 and the third data lead 53 are integrally structured, an electrical connection between the fifth test transistor T5 and the third data lead 53 can be achieved. The first region of the active layer T50 of the fifth test transistor T5 can be connected to the second test data line DB2. The gate T51 of the fifth test transistor T5 can be connected to the fourth first test control line SWR4.

[0125] This example arranges the six transistors of the first type of test circuit along the first direction, which can save the routing space occupied by the first type of test circuit in the second direction. This is beneficial to increase the routing space of the circuit setting area on both sides of the second direction, and facilitates the setting of other traces.

[0126] Figure 8 is another equivalent circuit diagram of multiple first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 9 is a plan view of multiple first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 10A is a schematic diagram of the first semiconductor layer and the first gate metal layer in Figure 9; Figure 10B is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 9. This example uses the film layer structure of the display substrate shown in Figure 2B as an example for illustration. The order of the first-type test data signals provided by the multiple first-type test circuit groups in this example can be the aforementioned second order. Figures 8 and 9 illustrate six first-type test circuit groups as an example, each first-type test circuit group including a first test circuit 401, a second test circuit 402, a third test circuit 403 and a fourth test circuit 404. The first test circuit 401 may include two first test transistors T1a and T1b, and two second test transistors T2a and T2b; the second test circuit 402 may include two third test transistors T3a and T3b; the third test circuit 403 may include two fourth test transistors T4a and T4b, and two fifth test transistors T5a and T5b; and the fourth test circuit 404 may include two sixth test transistors T6a and T6b.

[0127] The following description uses the first type of test circuit group illustrated in Figures 8 and 9 as an example. The first test circuit 401, second test circuit 402, fourth test circuit 404, and third test circuit 403 of this first type of test circuit group can be arranged sequentially along the first direction D1, away from the display area AA. Specifically, the first test transistors T1a and T1b, the second test transistors T2a and T2b, the third test transistors T3a and T3b, the sixth test transistors T6a and T6b, the fourth test transistors T4a and T4b, and the fifth test transistors T5a and T5b can be arranged sequentially along the first direction D1, away from the display area AA.

[0128] In some examples, multiple data leads can be divided into multiple groups of data leads, each group of data leads may include: a first data lead 51, a second data lead 52, a third data lead 53 and a fourth data lead 54.

[0129] In some examples, the first border area can also be provided with multiple first test control lines (e.g., two first test control lines SWR1 and SWR2), multiple second test control lines (e.g., four second test control lines SWB1, SWB2, SWB3, and SWB4), multiple third test control lines (e.g., two third test control lines SWG1 and SWG2), multiple first test data lines (e.g., four first test data lines DR1, DR2, DR3, and DR4), multiple second test data lines (e.g., four second test data lines DB1, DB2, DB3, and DB4), and multiple third test data lines (e.g., three third test data lines DG1, DG2, and DG3). The two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines, and three third test data lines within the circuit setting area can be of the same layer and all extend along the second direction D2.

[0130] In some examples, the first second test control line SWB1, the first first test data line DR1, the second first test data line DR2, the first first test control line SWR1, the second second test control line SWB2, the first second test data line DB1, the second second test data line DB2, the first third test control line SWG1, the first third test data line DG1, the second third test data line DG2, the third third test data line DG3, the second third test control line SWG2, the third second test control line SWB3, the third first test data line DR3, the fourth first test data line DR4, the second first test control line SWR2, the fourth second test control line SWB4, the third second test data line DB3, and the fourth second test data line DB4 can be arranged in the first direction D1 along a direction away from the display area. Specifically, the first second test control line SWB1 and the first first test data line DR1 can be adjacent in the first direction D1; the second first test data line DR2, the first first test control line SWR1, the second second test control line SWB2, and the first second test data line DB1 can be adjacent in the first direction D1; the second second test data line DB2, the first third test control line SWG1, and the first third test data line DG1 can be adjacent in the first direction D1; the third third test data line DG3, the second third test control line SWG2, the third second test control line SWB3, and the third first test data line DR3 can be adjacent in the first direction D1; and the fourth first test data line DR4, the second first test control line SWR2, the fourth second test control line SWB4, and the third second test data line DB3 can be adjacent in the first direction D1.

[0131] In some examples, as shown in Figures 10A and 10B, the active layers T10a and T10b of the first test transistor T1a, the active layers T20a and T20b of the second test transistor T2a and T2b can be aligned along the first direction D1. The gates T11a and T11b of the first test transistor T1a and T11b can be a single, integrated structure. Similarly, the gates T21a and T21b of the second test transistor T2a and T2b can also be a single, integrated structure.

[0132] In some examples, the active layers T30a and T30b of the third test transistor T3a and the third test transistor T3b can be aligned along the first direction D1. The gates T31a and T31b of the third test transistor T3a and the third test transistor T3b can be a single structure.

[0133] In some examples, the active layers T60a and T60b of the sixth test transistor T6a and the sixth test transistor T6b can be aligned along the first direction D1. The gates T61a and T61b of the sixth test transistor T6a and the sixth test transistor T6b can be a single structure.

[0134] In some examples, the active layers T40a and T40b of the fourth test transistor T4a, the fifth test transistor T5a and T50b can be aligned along the first direction D1. The gates T41a and T41b of the fourth test transistor T4a and the fifth test transistor T4b can be a single, integrated structure. Similarly, the gates T51a and T51b of the fifth test transistor T5a and the fifth test transistor T5b can be a single, integrated structure.

[0135] In some examples, the first data lead 51 is located on the second gate metal layer and is integrally structured with the third connection block 313 and the fourth connection block 314. The orthogonal projection of the third connection block 313 onto the substrate may be located between the active layer T10a of the first test transistor T1a and the active layer T10b of the first test transistor T1b. The orthogonal projection of the fourth connection block 314 onto the substrate may be located between the active layer T20a of the second test transistor T2a and the active layer T20b of the second test transistor T2b.

[0136] In some examples, the first region of the active layer T10a of the first test transistor T1a can be connected to the first first test data line DR1, the second region of the active layer T10b of the first test transistor T1b can be connected to the second first test data line DR2, and the gates of the first test transistors T1a and T1b can be connected to the first first test control line SWR1. The second regions of the active layers T10a and T10b of the first test transistors T1a and T1b can be connected to the third connection block 313 via the seventh connection electrode 417 located in the first source-drain metal layer.

[0137] In some examples, the first region of the active layer T20a of the second test transistor T2a can be connected to the first second test data line DB1, and the first region of the active layer T20b of the second test transistor T2b can be connected to the second second test data line DB2. The gates of the second test transistors T2a and T2b can be connected to the second second test control line SWB2. The second regions of the active layer T20a of the second test transistor T2a and the second regions of the active layer T20b of the second test transistor T2b can be connected to the fourth connection block 314 through the eighth connection electrode 418 located in the first source-drain metal layer.

[0138] In some examples, the second data lead 52 may be located in the first gate metal layer and be integral with the first connection block 311. The orthogonal projection of the first connection block 311 onto the substrate may be located between the active layer T30a of the third test transistor T3a and the active layer T30b of the third test transistor T3b.

[0139] In some examples, the first region of the active layer T30a of the third test transistor T3a can be connected to the first third test data line DG1, and the first region of the active layer T30b of the third test transistor T3b can be connected to the second third test data line DG2. The gates of the third test transistors T3a and T3b can be connected to the first third test control line SWG1. The second regions of the active layer T30a of the third test transistor T3a and the second regions of the active layer T30b of the third test transistor T3b can be connected to the first connection block 311 through the ninth connection electrode 419 located in the first source-drain metal layer.

[0140] In some examples, the third data lead 53 may be located in the second gate metal layer and integrated with the fifth connection block 315 and the sixth connection block 316. The orthogonal projection of the fifth connection block 315 onto the substrate may be located between the active layer T40a of the fourth test transistor T4a and the active layer T40b of the fourth test transistor T4b. The orthogonal projection of the sixth connection block 316 onto the substrate may be between the active layer T50a of the fifth test transistor T5a and the active layer T50b of the fifth test transistor T5b.

[0141] In some examples, the first region of the active layer T40a of the fourth test transistor T4a can be connected to the third first test data line DR3, and the first region of the active layer T40b of the fourth test transistor T4b can be connected to the fourth first test data line DR4. The gates of the fourth test transistors T4a and T4b can be connected to the third second test control line SWB3. The second regions of the active layer T40a of the fourth test transistor T4a and the second regions of the active layer T40b of the fourth test transistor T4b can be connected to the fifth connection block 315 through the tenth connection electrode 420 located in the first source-drain metal layer.

[0142] In some examples, the first region of the active layer T50a of the fifth test transistor T5a can be connected to the third second test data line DB3, and the first region of the active layer T50b of the fifth test transistor T5b can be connected to the fourth second test data line DB4. The gates of the fifth test transistors T5a and T5b can be connected to the second first test control line SWR2. The second regions of the active layer T50a of the fifth test transistor T5a and the second regions of the active layer T50b of the fifth test transistor T5b can be connected to the sixth connection block 316 through the eleventh connection electrode 421 located in the first source-drain metal layer.

[0143] In some examples, the fourth data lead 54 may be located in the first gate metal layer and integrated with the second connection block 312. The orthogonal projection of the second connection block 312 onto the substrate may be located between the active layer T60a of the sixth test transistor T6a and the active layer T60b of the sixth test transistor T6b.

[0144] In some examples, the first region of the active layer T60a of the sixth test transistor T6a can be connected to the second third test data line DG2, and the first region of the active layer T60b of the sixth test transistor T6b can be connected to the third third test data line DG3. The gates of the sixth test transistors T6a and T6b can be connected to the second third test control line SWG2. The second regions of the active layer T60a of the sixth test transistor T6a and the second regions of the active layer T60b of the sixth test transistor T6b can be connected to the second connection block 312 through the twelfth connection electrode 422 located in the first source-drain metal layer.

[0145] In some examples, in the first type 1 test circuit group in Figure 9, the first test transistors T1a and T1b can be located between the first first test data line DR1 and the second first test data line DR2; the second test transistors T2a and T2b can be located between the first second test data line DB1 and the second second test data line DB2; the third test transistors T3a and T3b can be located between the first third test data line DG1 and the second third test data line DG2; the sixth test transistors T6a and T6b can be located between the second third test data line DG2 and the third third test data line DG3; the fourth test transistors T4a and T4b can be located between the third first test data line DR3 and the fourth first test data line DR4; and the fifth test transistors T5a and T5b can be located between the third second test data line DB3 and the fourth second test data line DB4.

[0146] In this example, the first type of test circuit includes twelve transistors, which are arranged along the first direction. This saves the wiring space occupied by the first type of test circuit in the second direction and ensures the stability of the test circuit. Further descriptions of the display substrate in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0147] Figure 11 is another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 12 is a plan view of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. Figure 13 is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 12. This example is illustrated using the film layer structure of a display substrate as shown in Figure 2B. The order of the first-type test data signals provided by the test circuit in this example can be the same as the order of the data signals provided by the first contact pad in the first signal access area. That is, in this example, data connection lines do not need to be provided in the display area, and the order of the data signals required by the data lines can be the same as the order of the data signals provided by the data lead-out lines.

[0148] In some examples, as shown in Figures 11 to 13, the display substrate may include: a circuit setting area located in the first frame region and arranged along the second direction D2, comprising multiple first-type test circuit groups. Figures 11 and 12 illustrate four first-type test circuit groups as an example. Each first-type test circuit group may include two first-type test circuits arranged along the first direction D1. Each first-type test circuit may include: a first test circuit 401, a second test circuit 402, a third test circuit 403, and a fourth test circuit 404. Within a first-type test circuit group, the first first test circuit 401, the first second test circuit 402, the first fourth test circuit 404, the first third test circuit 403, the second second test circuit 402, the second fourth test circuit 404, the second first test circuit 401, and the second third test circuit 403 may be arranged sequentially along the first direction D1.

[0149] In some examples, multiple data leads can be divided into multiple groups of data leads, each group of which may include the following eight: first data lead 51, second data lead 52, third data lead 53, fourth data lead 54, fifth data lead 55, sixth data lead 56, seventh data lead 57, and eighth data lead 58. One type-one test circuit group in this example can be configured to provide type-one test data signals to two columns of pixel circuits.

[0150] In some examples, the first border area can be configured with multiple first test control lines (e.g., four first test control lines SWR1, SWR2, SWR3, and SWR4), multiple second test control lines (e.g., four second test control lines SWB1, SWB2, SWB3, and SWB4), multiple third test control lines (e.g., including four third test control lines SWG1, SWG2, SWG3, and SWG4), multiple first test data lines (e.g., four first test data lines DR1, DR2, DR3, and DR4), multiple second test data lines (e.g., four second test data lines DB1, DB2, DB3, and DB4), and multiple third test data lines (e.g., including two third test data lines DG1 and DG2). The four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines, and two third test data lines within the circuit setup area can be of the same layer and all extend along the second direction D2.

[0151] In some examples, the first test control line SWR1, the first test data line DR1, the first second test data line DB1, the first second test control line SWB1, the first third test control line SWG1, the first third test data line DG1, the second third test control line SWG2, the second second test control line SWB2, the second first test data line DR2, the second second test data line DB2, the second second test control line SWR2, the third third test control line SWG3, the second third test data line DG2, the fourth fourth test control line SWG4, the third first test control line SWR3, the third first test data line DR3, the third second test data line DB3, the third second test control line SWB3, the fourth second test control line SWB4, the fourth first test data line DR4, the fourth second test data line DB4, and the fourth first test control line SWR4 can be arranged along the first direction D1, for example, along a direction away from the display area.

[0152] Specifically, the first test data line DR1 and the first and second test data lines DB1 can be adjacent in the first direction D1; the first and second test control lines SWB1 and the first and third test control lines SWG1 can be adjacent in the first direction D1; the second and third test control lines SWG2 and SWB2 can be adjacent in the first direction D1; the second and first test data lines DR2 and DB2 can be adjacent in the first direction D1; the second and first test control lines SWR2 and SWG3 can be adjacent in the first direction D1; the fourth and third test control lines SWG4 and SWR3 can be adjacent in the first direction D1; the third and first test data lines DR3 and DB3 can be adjacent in the first direction D1; the third and second test control lines SWB3 and SWB4 can be adjacent in the first direction D1; and the fourth and first test data lines DR4 and DB4 can be adjacent in the first direction D1.

[0153] In some examples, a first test transistor T1 can be placed between the first first test control line SWR1 and the first first test data line DR1; a second test transistor T2 can be placed between the first second test data line DB1 and the first second test control line SWB1; a third test transistor T3 can be placed between the first third test control line SWG1 and the first third test data line DG1; a sixth test transistor T6 can be placed between the first third test data line DG1 and the second third test control line SWG2; a fourth test transistor T4 can be placed between the second second test control line SWB2 and the second first test data line DR2; and a fifth test transistor can be placed between the second second test data line DB2 and the second first test control line SWR2. A third test transistor T3 can be placed between the third test control line SWG3 and the second third test data line DG2. A sixth test transistor T6 can be placed between the second third test data line DG2 and the fourth third test control line SWG4. A first test transistor T1 can be placed between the third first test control line SWR3 and the third first test data line DR3. A second test transistor T2 can be placed between the third second test data line DB3 and the third second test control line SWB3. A fourth test transistor T4 can be placed between the fourth second test control line SWB4 and the fourth first test data line DR4. A fifth test transistor T5 can be placed between the fourth first test data line DR4 and the fourth first test control line SWR4.

[0154] In some examples, the first data lead 51 can be integrated with a third connection block 313 and a fourth connection block 314, the third connection block 313 being connected to a first first test transistor T1, and the fourth connection block 314 being connected to a first second test transistor T2. The second data lead 52 can be integrated with a first connection block 311, the first connection block 311 being connected to a first third test transistor T3. The third data lead 53 can be integrated with a fifth connection block 315 and a sixth connection block 316, the fifth connection block 315 being connected to a first fourth test transistor T4, and the sixth connection block 316 being connected to a first fifth test transistor T5. The fourth data lead 54 can be integrated with a second connection block 312, the second connection block 312 being connected to a first sixth test transistor T6. The fifth data lead 55 can be integrated with another third connection block 313 and another fourth connection block 314. The third connection block 313 is connected to the second first test transistor T1, and the fourth connection block 314 is connected to the second second test transistor T2. The sixth data lead 56 can be integrated with another first connection block 311, which is connected to the second third test transistor T3. The seventh data lead 57 can be integrated with another fifth connection block 315 and another sixth connection block 316. The fifth connection block 315 is connected to the second fourth test transistor T4, and the sixth connection block 316 is connected to the second fifth test transistor T5. The eighth data lead 58 can be integrated with another second connection block 312, which is connected to the second sixth test transistor T6.

[0155] In this example, each type I test circuit includes six transistors, and the twelve transistors of two type I test circuits are arranged along the first direction. This saves the routing space occupied by the type I test circuit group in the second direction, which is beneficial for increasing the routing space of the circuit setting area on both sides of the second direction and facilitating the setting of other traces. Further descriptions of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0156] Figure 14 is another equivalent circuit diagram of a plurality of first-type test circuit groups according to at least one embodiment of the present disclosure. The order of the first-type test data signals provided by the test circuit in this example can be the same as the order of the data signals provided by the first contact pad in the first signal access area. That is, in this example, data connection lines do not need to be provided in the display area, and the order of the data signals required by the data lines can be the same as the order of the data signals provided by the data leads. For example, the first data lead 51 and the third data lead 53 can each be configured to provide first-type test data signals to a column of sub-pixels including the first sub-pixel and the second sub-pixel, and the second data lead 52 and the fourth data lead 54 can each be configured to provide first-type test data signals to a column of third sub-pixels.

[0157] In some examples, as shown in Figure 14, each group of first-type test circuits may include one first-type test circuit. The first test circuit 401, the second test circuit 402, the fourth test circuit 404, and the third test circuit 403 of the first-type test circuit may be along the first direction D1. The two first test control lines SWR1 and SWR2, the two second test control lines SWB1 and SWB2, the two third test control lines SWG1 and SWG2, the two first test data lines DR1 and DR2, the two second test data lines DB1 and DB2, and the one third test data line DG may be of the same layer and extend at least along the second direction D2.

[0158] In some examples, the first first test control line SWR1, the first first test data line DR1, the first second test data line DB1, the first second test control line SWB1, the first third test control line SWG1, the third test data line DG, the second third test control line SWG2, the second first test data line DR2, the second second test control line SWB2, the second first test control line SWR2, and the second second test data line DB2 can be arranged sequentially along the first direction D1.

[0159] Specifically, the first test transistor T1 can be located between the first test control line SWR1 and the first test data line DR1; the second test transistor T2 can be located between the first second test data line DB1 and the first second test control line SWB1; the third test transistor T3 can be located between the first third test control line SWG1 and the third test data line DG; the sixth test transistor T6 can be located between the third test data line DG and the second third test control line SWG2; the fourth test transistor T4 can be located between the second first test data line DR2 and the second second test control line SWB2; and the fifth test transistor T5 can be located between the second first test control line SWR2 and the second second test data line DB2.

[0160] This example arranges the six transistors of the first type of test circuit along the first direction, which can save the routing space occupied by the first type of test circuit group along the second direction. Further details regarding this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0161] Figure 15 is an equivalent circuit diagram of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure. Figure 16 is a plan view of a plurality of second-type test circuit groups according to at least one embodiment of the present disclosure. Figure 17 is a schematic diagram of the first semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 16.

[0162] In some examples, a plurality of second-type test circuit groups can be disposed in the first border area, and the plurality of second-type test circuit groups can be located on the side of the plurality of first-type test circuit groups away from the display area. The second-type test circuit groups can include at least one second-type test circuit arranged along the first direction D1. The second-type test circuits can include a fifth test circuit 405, a sixth test circuit 406, a seventh test circuit 407, and an eighth test circuit 408. The fifth test circuit 405 and the seventh test circuit 407 can each be configured to provide second-type test data signals to a column of sub-pixels including a first sub-pixel and a second sub-pixel, and the sixth test circuit 406 and the eighth test circuit 408 can each be configured to provide second-type test data signals to a column of third sub-pixels. For example, the fifth test circuit 405 can be connected to the first data lead 51, the sixth test circuit 406 can be connected to the second data lead 52, the seventh test circuit 407 can be connected to the third data lead 53, and the eighth test circuit 408 can be connected to the fourth data lead 54.

[0163] In some examples, the fifth test circuit 405 may include at least one seventh test transistor T7. The sixth test circuit 406 may include at least one eighth test transistor T8. The seventh test circuit 407 may include at least one ninth test transistor T9. The eighth test circuit 408 may include at least one tenth test transistor T10. The tenth test transistor T10, the ninth test transistor T9, the eighth test transistor T8, and the seventh test transistor T7 of a second type of test circuit group may be arranged sequentially along the first direction D1 in a direction away from the display area.

[0164] In some examples, the first border area can be configured with multiple fourth test control lines (e.g., two fourth test control lines SWD1 and SWD2), multiple fourth test data lines (e.g., two fourth test data lines DD1-1 and DD1-2), and two fifth test data lines (e.g., two fifth test data lines DD2-1 and DD2-2). The fourth test data lines can be configured to provide fourth test data signals, and the fifth test data lines can be configured to provide fifth test data signals. The second type of test circuit can be configured to provide second type test data signals (e.g., including fourth and fifth test data signals) to multiple data lines during monochrome display testing to perform monochrome display testing.

[0165] In some examples, the gates of the seventh test transistor T7, the eighth test transistor T8, the ninth test transistor T9, and the tenth test transistor T10 are all connected to the fourth test control line. For example, the gate T71 of the seventh test transistor T7 and the gate T81 of the eighth test transistor T8 can be a single structure and connected to the second fourth test control line SWD2 located in the first source-drain metal layer. The first region of the active layer T70 of the seventh test transistor T7 and the fourteenth connection electrode 424 located in the second gate metal layer can be connected through the twenty-first connection electrode 431 located in the first source-drain metal layer. The first region of the active layer T80 of the eighth test transistor T8 and the fourteenth connection electrode 424 located in the second gate metal layer can be connected through the twentieth connection electrode 430 located in the first source-drain metal layer. The fourteenth connection electrode 424 can be connected to the second fourth test data line DD1-2 located in the first source-drain metal layer. The second region of the active layer T70 of the seventh test transistor T7 can be connected to the first data lead 51 located in the second gate metal layer through the twenty-second connection electrode 432 located in the first source-drain metal layer. The second region of the active layer T80 of the eighth test transistor T8 can be connected to the second data lead 52 located in the first gate metal layer via the nineteenth connection electrode 429 located in the first source-drain metal layer.

[0166] In some examples, the gate T91 of the ninth test transistor T9 and the gate T101 of the tenth test transistor T10 can be a single structure and connected to the first fourth test control line SWD1 located in the first source-drain metal layer. The first region of the active layer T90 of the ninth test transistor T9 and the thirteenth connection electrode 423 located in the second gate metal layer can be connected through the seventeenth connection electrode 427 located in the first source-drain metal layer. The first region of the active layer T100 of the tenth test transistor T10 and the thirteenth connection electrode 423 located in the second gate metal layer can be connected through the sixteenth connection electrode 426 located in the first source-drain metal layer. The thirteenth connection electrode 423 can be connected to the first fifth test data line DD2-1 located in the first source-drain metal layer. The second region of the active layer T90 of the ninth test transistor T9 can be connected to the third data lead 53 located in the second gate metal layer through the eighteenth connection electrode 428 located in the first source-drain metal layer. The second region of the active layer T100 of the tenth test transistor T10 can be connected to the fourth data lead 54 located in the first gate metal layer via the fifteenth connection electrode 425 located in the first source-drain metal layer.

[0167] In this example, the second type of test circuit includes four transistors. The four transistors of the second type of test circuit are arranged along the first direction, which can save the routing space occupied by the second type of test circuit in the second direction.

[0168] Figure 18 is a partial wiring diagram of the first frame region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 18, the circuit setting area B133 of the first frame region may be located on the side of the first signal access area B131 near the bending area B12. The first frame region may be provided with multiple first frame power lines (e.g., two first frame power lines VDD1 and VDD2), multiple second frame power lines (e.g., three second frame power lines VSS1, VSS2, and VSS3), multiple third frame power lines (e.g., two third frame power lines VGLa and VGLb), multiple fourth frame power lines (e.g., two fourth frame power lines VGHa and VGHb), and multiple sets of initial signal lines (e.g., including a first set of initial signal lines INITa, a second set of initial signal lines INITb, a third set of initial signal lines INITC, and a fourth set of initial signal lines INITd). Multiple first-frame power lines, multiple second-frame power lines, multiple third-frame power lines, multiple fourth-frame power lines, and multiple sets of initial signal lines can extend to the second signal access area B132 and connect to the corresponding second contact pads within the second signal access area B132.

[0169] In some examples, a first border power line can be configured to provide a first power signal to the pixel circuit of a sub-pixel in the display area, and a second border power line can be configured to provide a second power signal to the light-emitting element of the sub-pixel in the display area, wherein the first power signal can be greater than the second power signal. A third border power line can be configured to provide a third power signal to the gate driving circuits located in the second and third border areas, and a fourth border power line can be configured to provide a fourth power signal to the gate driving circuits located in the second and third border areas, wherein the third power signal can be greater than the fourth power signal. The gate driving circuit can be configured to provide a pixel control signal to the pixel circuit of the sub-pixel in the display area. Multiple sets of initial signal lines can be configured to provide initial signals to the pixel circuits of the sub-pixels in the display area.

[0170] In some examples, the third second-border power line VSS3 can be located between the two first-border power lines VDD1 and VDD2. The portion of the third second-border power line VSS3 extending along the first direction D1 within the second sub-region B13 can be located on both sides of the circuit setup area B133. The portion of the third second-border power line VSS3 extending along the second direction D2 within the second sub-region B13 can be located on the side of the circuit setup area B133 closest to the bending area B12. The first second-border power line VSS1 can be located on the side of the first first-border power line VDD1 away from the third second-border power line VSS3, and the second second-border power line VSS2 can be located on the side of the second first-border power line VDD2 away from the third second-border power line VSS3.

[0171] In some examples, the second set of initial signal lines INITb can be located between the first second-border power line VSS1 and the first first-border power line VDD1, and the third set of initial signal lines INITc can be located between the second second-border power line VSS2 and the second first-border power line VDD2. The first set of initial signal lines INITa can be located on the side of the first second-border power line VSS1 away from the first first-border power line VDD1, and the fourth set of initial signal lines INITd can be located on the side of the second second-border power line VSS2 away from the second first-border power line VDD2.

[0172] In some examples, the first third-border power line VGLa can be located between the first set of initial signal lines INITa and the first second-border power line VSS1. The second third-border power line VGLb can be located between the fourth set of initial signal lines INITa and the second second-border power line VSS2. The first fourth-border power line VGHa can be located on the side of the first set of initial signal lines INITa away from the first third-border power line VGLa, and the second fourth-border power line VGHb can be located on the side of the fourth set of initial signal lines INITa away from the second third-border power line VGLb.

[0173] In this example, after the test circuit in the circuit setting area B133 is compressed along the second direction as described in the aforementioned embodiment, the increased routing space on both sides of the circuit setting area B133 along the second direction D2 facilitates the arrangement of multiple second-frame power lines, multiple sets of initial signal lines, multiple third-frame power lines, and multiple fourth-frame power lines, further optimizing current density. By setting three second-frame power lines, the voltage drop across the second power signal can be effectively reduced, thus lowering power consumption. By setting two sets of third-frame power lines and two sets of fourth-frame power lines, the voltage drop of the third and fourth power signals can be improved. By setting multiple sets of initial signal lines, display defects such as three-screen layouts and dimming on both sides of the display screen can be improved.

[0174] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 19, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0175] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0176] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes: a display area and a first border area located on one side of the display area along a first direction; Multiple pixel units and multiple data lines are disposed on the substrate and located in the display area. The multiple pixel units are electrically connected to the multiple data lines. Each pixel unit includes multiple sub-pixels. Multiple data leads are located in the first border area, and the multiple data leads are electrically connected to the multiple data lines; Multiple first-type test circuit groups are located in the first frame area and connected to the multiple data leads; At least one of the plurality of first-type test circuit groups includes at least one first-type test circuit arranged along the first direction; the first-type test circuit includes a plurality of transistors arranged along the first direction, and the first-type test circuit is configured to provide a first-type test data signal to a column of pixel units, the column of pixel units including a plurality of pixel units arranged along the first direction.

2. The display substrate according to claim 1, wherein, The pixel unit includes a plurality of sub-pixels: a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, and two third sub-pixels that emit a third color light; The first type of test circuit includes: a first test circuit, a second test circuit, a third test circuit, and a fourth test circuit; each of the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit includes at least one transistor; The first test circuit is configured to provide a first type of test data signal to the first sub-pixel of the e-th row pixel unit in the column of pixel units during a first time period, and to provide a first type of test data signal to the second sub-pixel of the e+1-th row pixel unit in the column of pixel units during a second time period; The second test circuit is configured to provide a first type of test data signal to a column of third sub-pixels in the column of pixel units; The third test circuit is configured to provide a first type of test data signal to the first sub-pixel of the (e+1)th row pixel unit in the column of pixel units during the first time period, and to provide a first type of test data signal to the second sub-pixel of the eth row pixel unit in the column of pixel units during the second time period; where e is a positive integer; The fourth test circuit is configured to provide a first type of test data signal to another column of third sub-pixels in the column of pixel units.

3. The display substrate according to claim 2, wherein, The first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the at least one first type of test circuit group are arranged sequentially along the first direction.

4. The display substrate according to claim 2 or 3, further comprising: Multiple first test control lines, multiple second test control lines, multiple third test control lines, multiple first test data lines, multiple second test data lines, and at least one third test data line are located in the first border area; The first test circuit includes at least one first test transistor and at least one second test transistor. The gate of the at least one first test transistor is connected to one of the plurality of first test control lines. The first electrode of the at least one first test transistor is connected to one of the plurality of first test data lines. The gate of the at least one second test transistor is connected to one of the plurality of second test control lines. The first electrode of the at least one second test transistor is connected to one of the plurality of second test data lines. The second electrodes of the at least one first test transistor and the at least one second test transistor are connected to the same data lead among the plurality of data lead-out lines. The second test circuit includes: at least one third test transistor, the gate of the at least one third test transistor being connected to one of the plurality of third test control lines, the first terminal of the at least one third test data line being connected to the at least one third test data line, and the second terminal of the at least one third test transistor being connected to one of the plurality of data lead lines. The third test circuit includes at least one fourth test transistor and at least one fifth test transistor. The gate of the at least one fourth test transistor is connected to another second test control line among the plurality of second test control lines. The first terminal of the at least one fourth test transistor is connected to another first test data line among the plurality of first test data lines. The gate of the at least one fifth test transistor is connected to another first test control line among the plurality of first test control lines. The first terminal of the at least one fifth test transistor is connected to another second test data line among the plurality of second test data lines. The second terminals of the at least one fourth test transistor and the at least one fifth test transistor are connected to the same data lead among the plurality of data lead lines. The fourth test circuit includes: at least one sixth test transistor, the gate of the at least one sixth test transistor is connected to another third test control line among the plurality of third test control lines, the first terminal of the at least one sixth test transistor is connected to the at least one third test data line, and the second terminal of the sixth test transistor is connected to one of the plurality of data lead-out lines. The data leads connected to the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit are different.

5. The display substrate according to claim 4, comprising: Four first test control lines, three second test control lines, two third test control lines, two first test data lines, two second test data lines, and one third test data line; Among them, the first second test control line, the first first test control line, the first first test data line, the first second test data line, the second second test control line, the second first test control line, the first third test control line, the third third test data line, the second third test control line, the second first test data line, the third first test control line, the third second test control line, the fourth first test control line, and the second second test data line are arranged sequentially along the first direction; The first type of test circuit of the at least one first type of test circuit group includes: a first test transistor, a second test transistor, a third test transistor, a fourth test transistor, a fifth test transistor and a sixth test transistor; The first test transistor is connected to the first first test control line and the first first test data line, and is located between the first first test control line and the first first test data line in the first direction; The second test transistor is connected to the first second test data line and the second second test control line, and is located between the first second test data line and the second second test control line in the first direction; The third test transistor is connected to the first third test control line and the third test data line, and is located between the first third test control line and the third test data line in the first direction; The fourth test transistor is connected to the second first test data line and the third second test control line, and is located between the second first test data line and the third first test control line in the first direction; The fifth test transistor is connected to the fourth first test control line and the second second test data line, and is located between the fourth first test control line and the second second test data line in the first direction.

6. The display substrate according to claim 4, comprising: Two first test control lines, four second test control lines, two third test control lines, four first test data lines, four second test data lines, and three third test data lines; Among them, the first second test control line, the first first test data line, the second first test data line, the first first test control line, the second second test control line, the first second test data line, the second second test data line, the first third test control line, the first third test data line, the second third test data line, the third third test data line, the second third test control line, the third second test control line, the third first test data line, the fourth first test data line, the second first test control line, the fourth second test control line, the third second test data line, and the fourth second test data line are arranged sequentially along the first direction; The first type of test circuit of the at least one first type of test circuit group includes: two first test transistors, two second test transistors, two third test transistors, two fourth test transistors, two fifth test transistors, and two sixth test transistors; The two first test transistors are located between the first first test data line and the second first test data line in the first direction; The two second test transistors are located between the first second test data line and the second second test data line in the first direction; The two third test transistors are located between the first third test data line and the second third test data line in the first direction; The two sixth test transistors are located between the second third test data line and the third third test data line in the first direction; The two fourth test transistors are located between the third first test data line and the fourth first test data line in the first direction; The two fifth test transistors are located in the first direction between the third second test data line and the fourth second test data line.

7. The display substrate according to claim 6, wherein, The first test transistor of the first type of test circuit is connected to the first test data line and the first test control line, and the second test transistor is connected to the second test data line and the first test control line. The first second test transistor is connected to the first second test data line and the second second test control line, and the second second test transistor is connected to the second second test data line and the second second test control line; The first third test transistor is connected to the first third test data line and the first third test control line, and the second third test transistor is connected to the second third test data line and the first third test control line; The first sixth test transistor is connected to the second third test data line and the second third test control line, and the second sixth test transistor is connected to the third third test data line and the second third test control line; The first fourth test transistor is connected to the third first test data line and the third second test control line, and the second fourth test transistor is connected to the fourth first test data line and the third second test control line; The first fifth test transistor is connected to the third second test data line and the second first test control line, and the second fifth test transistor is connected to the fourth second test data line and the second first test control line.

8. The display substrate according to claim 4, wherein, The at least one first type of test circuit group includes two first type of test circuits arranged along the first direction. The first test circuit, the first test circuit, the second test circuit, the fourth test circuit, and the third test circuit of the first first type of test circuit are arranged sequentially along the first direction. The second test circuit, the fourth test circuit, the first test circuit, and the third test circuit of the second first type of test circuit are arranged sequentially along the first direction.

9. The display substrate according to claim 8, comprising: Four first test control lines, four second test control lines, four third test control lines, four first test data lines, four second test data lines, and two third test data lines; The first test control line, the first test data line, the first second test data line, the first second test control line, the first third test control line, the first third test data line, the second third test control line, the second second test control line, the second first test data line, the second second test data line, the second first test control line, the third third test control line, the second third test data line, the fourth third test control line, the third first test control line, the third first test data line, the third second test data line, the third second test control line, the fourth second test control line, the fourth first test data line, the fourth second test data line, and the fourth first test control line are arranged sequentially along the first direction.

10. The display substrate according to any one of claims 1 to 9, further comprising: A plurality of second-type test circuit groups, at least one of the plurality of second-type test circuit groups including: at least one second-type test circuit arranged along the first direction, the second-type test circuit including a plurality of transistors arranged along the first direction, the second-type test circuit being configured to provide a second-type test data signal to the column of pixel units.

11. The display substrate according to claim 10, wherein, The second type of test circuit includes: the fifth test circuit, the sixth test circuit, the seventh test circuit, and the eighth test circuit; The pixel unit comprises four columns of sub-pixels; the fifth, sixth, seventh, and eighth test circuits of the second type of test circuit are configured to provide second type of test data signals to the four columns of sub-pixels; The eighth test circuit, the seventh test circuit, the sixth test circuit, and the fifth test circuit of the second type of test circuit are arranged sequentially along the first direction.

12. The display substrate according to claim 11, wherein, The fifth test circuit includes at least one seventh test transistor; the sixth test circuit includes at least one eighth test transistor; the seventh test circuit includes at least one ninth test transistor; and the eighth test circuit includes at least one tenth test transistor. The display substrate further includes: multiple fourth test control lines, multiple fourth test data lines, and multiple fifth test data lines located in the first frame area; The gates of the seventh test transistor and the eighth test transistor are connected to the same fourth test control line among the plurality of fourth test control lines. The first terminals of the seventh test transistor and the eighth test transistor are connected to the same fourth test data line among the plurality of fourth test data lines. The second terminal of the seventh test transistor is connected to one of the plurality of data lead-out lines, and the second terminal of the eighth test transistor is connected to another of the plurality of data lead-out lines. The gates of the ninth test transistor and the tenth test transistor are connected to the same fourth test control line among the plurality of fourth test control lines. The first terminals of the ninth test transistor and the tenth test transistor are connected to the same fifth test data line among the plurality of fifth test data lines. The second terminal of the ninth test transistor is connected to another data lead among the plurality of data lead lines. The second terminal of the tenth test transistor is connected to another data lead among the plurality of data lead lines.

13. The display substrate according to any one of claims 1 to 12, further comprising: Two first-frame power lines and three second-frame power lines are located in the first-frame area. The first and second second-frame power lines are located on both sides of the two first-frame power lines and the third second-frame power line, and the two first-frame power lines are located on both sides of the third second-frame power line.

14. The display substrate according to claim 13, further comprising: The four initial signal lines located in the first frame area are: the first initial signal line is located on the side of the first second frame power line away from the third second frame power line; the second initial signal line is located on the side of the first second frame power line close to the third second frame power line; the third initial signal line is located on the side of the second second frame power line close to the third second frame power line; and the fourth initial signal line is located on the side of the second second frame power line away from the third second frame power line.

15. A display device comprising a display substrate as claimed in any one of claims 1 to 14.

Images