Arrangement of a frequency multiplier in current reuse with an active input balun
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-05
- Publication Date
- 2026-08-13
Smart Images
Figure EP2025053010_13082026_PF_FP_ABST
Abstract
Description
[0001] A FREQUENCY MULTIPLIER ARRANGEMENT
[0002] TECHNICAL FIELD
[0003] The present disclosure relates generally to the field of wireless communications. More particularly, it relates to a frequency multiplier arrangement for receiving an input signal, for frequency multiplying the input signal, and for providing the frequency multiplied signal as an output signal. The present disclosure further relates to an apparatus for a wireless communications network, the apparatus comprising the frequency multiplier arrangement.
[0004] BACKGROUND
[0005] In wireless communications networks, network nodes (such as base stations) and wireless devices (such as user equipments, UEs) are provided with radio units. A radio unit often comprises a mixer for each transmit and receive unit, where each mixer is provided a local oscillator (LO) signal (originating from an LO). The chain of components between the LO and one of the inputs of a mixer may be called an LO-chain. The LO-chain may, e.g., comprise one or more amplifiers. For high-frequency radio units, e.g., above 100 GHz, the LO-chain sometimes also comprises one or more frequency multipliers circuits. However, frequency multipliers circuits may also be present in LO-chains for frequencies lower than 100 GHz. Including a frequency multiplier circuit may improve overall performance compared to omitting the frequency multiplier circuit and directly generate the desired frequency of the LO signal provided to the mixer by the LO.
[0006] The frequency of the output of a frequency multiplier circuit is N-times that of the frequency of the input signal, where N is a natural number larger than one. There are various types of frequency multiplier topologies. One example is the Gilbert mixer type multiplier.
[0007] Another type of frequency multiplier is the harmonic amplification type multiplier, which utilizes a transistor to generate harmonics. In some such types, the input signal at a frequency (fo) is applied at the base / gate, and the output signal at a frequency of Nfo is taken from the collector / drain.
[0008] To suppress undesired odd-order harmonics, a push-push configuration is often implemented in transistor-based frequency multiplier circuits. In many such circuits, a balun converts a single-ended input signal into a differential signal, to drive two common-emitter (CE) configured transistors in a push-push configuration. The respective outputs from two transistor's collectors / drai ns are connected, which forms a single-ended output. In a push-push configuration, the odd-order harmonics at the two collectors / drains have the same amplitude but with a 180° phase difference. Consequently, the odd-order harmonics will be suppressed at the output port. In contrast, the even-order harmonics generated by two transistors have the same amplitude and the same phase. Thus, the even-order harmonics are added constructively at the output port.Unfortunately, a passive balun (e.g., made of coupled transmission lines) occupies a large chip area, is relatively lossy, and presents a limited frequency bandwidth. A passive circuit (such as a passive balun) is a circuit that does not require an external power source to operate.
[0009] One approach to eliminate the passive balun in a frequency multiplier is disclosed by G. -Y. Chen et. al. in "A ka-band broadband active frequency doubler using CB-CE balanced configuration in 0.18 m SiGe BiCMOS process," 2012 IEEE / MTT-S International Microwave Symposium Digest, Montreal, QC, Canada, 2012, pp. 1-3. In said disclosure, the multiplier cell comprises of a common-emitter (CE) configured transistor and a commonbase (OB) configured transistor. However, since the CE and CB transistors have different gain, the fundamental and the third harmonic may not be sufficiently suppressed at the output (due to imbalances between the two transistor outputs).
[0010] Another approach to reduce chip area is to utilize an active balun instead of a passive balun. An active circuit (such as an active balun) is a circuit that requires an external power source to operate. As an example, F. van Raay and G. Kompa disclose a frequency multiplier circuit with an active balun and a common-emitter push-push multiplier cell in "Design and stability test of a 2-40 GHz frequency doubler with active balun," 2000 IEEE MTT-S International Microwave Symposium Digest (Cat. No.00CH37017), Boston, MA, USA, 2000, pp. 1573-1576 vol.3. A potential drawback of using an active balun, however, is increased direct current (DC) power consumption, which reduces energy efficiency.
[0011] Furthermore, for multiplier circuits using an active balun, an interstage impedance matching network may be required between the active balun and the multiplier cell. The interstage impedance matching network may require a relatively large chip area and may induce losses, which reduces output power and energy efficiency. Thus, there is a need for improved frequency multiplier arrangement suitable for high frequencies (such as, e.g., above 100 GHz) with good performance metrics in terms of chip area, output power, energy efficiency, and suppression of undesired harmonics at the output port.
[0012] SUMMARY
[0013] It is an object of the present disclosure to mitigate, alleviate or eliminate one or more of the above-identified deficiencies and disadvantages in the prior art and solve at least the above-mentioned problem. In particular, an object is to provide improved frequency multiplier arrangements. This object is attained at least in part by a frequency multiplier arrangement for receiving an input signal, for frequency multiplying the input signal, and for providing the frequency multiplied signal as an output signal. The frequency multiplier arrangement comprises an active balun and a multiplier cell. The active balun comprises two primary transistors, an unbalanced input port configured to receive the input signal, and a balanced output port configured to provide a differential signal. The multiplier cell comprises two primary transistors, a balanced input port configured to receive the differential signal, an unbalanced output port configured to provide the frequency multiplied signal as the output signal, and a first direct current (DC), supply feed configured to receive a first supply current. The frequency multiplier arrangementis configured such that respective portions of the supply current are provided to each of the two primary transistors of the multiplier cell, and to each of the two primary transistors of the active balun via the two primary transistors of the multiplier cell, respectively, and via respective parts of the balanced output port of the active balun.
[0014] In the disclosed frequency multiplier arrangement, both DC and alternating current (AC) are coupled between the balanced output port of the active balun and the balanced input port of the multiplier cell. This enables usage of less DC power consumption during operation (which corresponds to improved energy efficiency) of the disclosed frequency multiplier arrangement as compared to other solutions where DC is blocked and only AC is coupled between the balanced output port of the active balun and the balanced input port of the multiplier cell. Furthermore, due to less losses in a practical implementation, the energy efficiency of the disclosed frequency multiplier arrangement may be improved further.
[0015] Furthermore, there is no need for two separate DC supply feeds (one for the multiplier cell and another for the active balun). Thus, the disclosed frequency multiplier arrangement may enable simpler routing of supply feed lines. In addition, no capacitors (as DC blocks) are needed between the active balun and the multiplier cell, which may reduce the required chip area and may further reduce losses.
[0016] Furthermore, the active balun of the disclosed frequency multiplier arrangement requires a small chip area as compared to other solutions using a passive balun.
[0017] In some embodiments, the frequency multiplied signal comprises a harmonic frequency of at least two times a fundamental frequency of the input signal.
[0018] In some embodiments, each of the two primary transistors of the multiplier cell is galvanically connected to a respective transistor of the two primary transistors of the active balun. In other words, the respective connections between primary transistors of the multiplier cell and the primary transistors of the active balun is free from DC blocks (such as a capacitor arranged in series).
[0019] In some embodiments, a respective current-collecting terminal of each transistor of the two primary transistors of the active balun is galvanically connected to a respective current-sourcing terminal of the two primary transistors of the multiplier cell.
[0020] In some embodiments, the first DC supply feed is configured to provide respective portions of the first supply current to respective current-collecting terminals of the two primary transistors of the multiplier cell.
[0021] In some embodiments, the active balun comprises a first bias feed configured to receive a first bias voltage and configured to provide the first bias voltage or respective portions of the first bias voltage to respective control terminals of the two primary transistors of the active balun.
[0022] In some embodiments, the multiplier cell comprises a second bias feed configured to receive a second bias voltage and configured to provide the second bias voltage or respective portions of the second bias voltage to respective control terminals of the two primary transistors of the multiplier cell.In some embodiments, the multiplier cell is configured such that the fundamental frequency of the input signal received at the unbalanced input port of the active balun is suppressed at the unbalanced output port of the multiplier cell. Suppressing the fundamental frequency at the unbalanced output port is particularly desired when the frequency multiplier arrangement is used in an LO chain before a mixer (for up- or down conversion).
[0023] Furthermore, in some embodiments, the multiplier cell is configured such that odd-order harmonics of the input signal received at the unbalanced input port of the active balun is suppressed at the unbalanced output port of the multiplier cell.
[0024] In some embodiments, the two primary transistors of the multiplier cell are arranged in a push-push configuration. The respective outputs from two primary transistors of the multiplier cell may be connected to form the unbalanced output port. In the push-push configuration, odd-order harmonics at the two transistor outputs have the same amplitude (ideally) but with a 180° phase difference (ideally). Consequently, the odd-order harmonics, including the fundamental, will be suppressed at the unbalanced output port. In this way, no additional filter for suppressing the fundamental is required. In contrast, even-order harmonics at the two transistor outputs have the same amplitude (ideally) and the same phase (ideally). Thus, the even-order harmonics are added constructively at the output port. Furthermore, the frequency multiplier cell may also be configured to function as a differential amplifier, which compensates potential amplitude and phase mismatch of the differential signal from the active balun, which improves suppression of the fundamental and other odd-order harmonics.
[0025] In some embodiments, the two primary transistors of the multiplier cell are arranged in respective common-base configurations, in respective common-gate configurations, or in a capacitor cross-coupled configuration.
[0026] In some embodiments, the frequency multiplier arrangement comprises a matching network. The matching network comprising respective transmission lines arranged in series between the respective parts of the balanced output port of the active balun and the respective parts of the balanced input port of the multiplier cell. The disclosed frequency multiplier arrangement does not require a large inter-stage impedance matching network between the active balun and the multiplier cell, which further reduces the chip area and the associated losses. In some embodiments, the multiplier cell comprises a common-base or common-gate configured transistor stage arranged between the two primary transistors of the multiplier cell and the unbalanced output port of the multiplier cell. In this way, the output power of the multiplier cell is increased. Said transistor stage may amplify harmonics generated by the multiplier cell, and also generate the harmonics by itself. Also note that several transistor stages may be stacked on top of one another in a multiplier cell.
[0027] In some embodiments, the two primary transistors of the active balun are arranged in a common-emitter and a common-base configuration, respectively, or in a common-source and a common-gate configuration, respectively. In some embodiments, the active balun comprises one or more amplifier stages arranged in connection to the unbalanced input port of the active balun. In this way, the gain of the frequency multiplier arrangement may be increased.In some embodiments, the two primary transistors of the active balun are arranged in a differential-pair configuration.
[0028] There is also disclosed herein an apparatus for wireless communications. The apparatus comprises the frequency multiplier arrangement according to the discussions above. The apparatus is associated with the above-discussed advantages. The apparatus may, e.g., be a network node or a wireless device.
[0029] BRIEF DESCRIPTION OF THE DRAWINGS
[0030] With reference to the appended drawings, below follows a more detailed description of embodiments of the present disclosure cited as examples. In the drawings:
[0031] Figure 1 is a schematic illustration of a wireless communications network;
[0032] Figure 2 is a schematic illustration of a frequency multiplier arrangement according to embodiments;
[0033] Figures 3a-3b illustrate multiplier cells according to embodiments;
[0034] Figure 4 illustrates a power booster according to embodiments;
[0035] Figure 5 illustrates a multiplier cell according to embodiments;
[0036] Figures 6a to 6d illustrate active baluns according to embodiments;
[0037] Figure 7 illustrates a frequency multiplier arrangement according to embodiments, using the multiplier cell of Figure 3a and the active balun of Figure 6a;
[0038] Figure 8 illustrates a frequency multiplier arrangement according to embodiments, using the multiplier cell of Figure 3a and the active balun of Figure 6b;
[0039] Figure 9 illustrates a frequency multiplier arrangement according to embodiments, using the multiplier cell of Figure 5 and the active balun of Figure 6b;
[0040] Figures 10a and 10b show plots of simulated performance for the frequency multiplier arrangement of Figure 7; Figures 11a and 11b show plots of simulated performance for the frequency multiplier arrangement of Figure 8; and
[0041] Figures 12a and 12b show plots of simulated performance for the frequency multiplier arrangement of Figure 9.
[0042] DETAILED DESCRIPTION
[0043] The present disclosure is described below with reference to the accompanying drawings, in which certain aspects of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments and aspects set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey thescope of the present disclosure to those skilled in the art. The same features are denoted by the same reference signs throughout the description.
[0044] It is to be understood that the present disclosure is not limited to the embodiments described herein and illustrated in the drawings; rather, the skilled person will recognize that many changes and modifications may be made within the scope of the appended claims.
[0045] Figure 1 depicts a wireless communications network 100 in which embodiments herein may operate. In some embodiments, the wireless communications network 100 may be a radio communications network, such as, sixth generation (6G), New Radio (NR), or NR+ telecommunications network. However, the wireless communications network 100 may also employ technology of any one of third / fourth / fifth generation, Long Term Evolution (LTE), LTE-Advanced, Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Ultra Mobile Broadband (UMB), or any other similar network or system. The wireless communications network 100 may also employ technology transmitting on millimeter-waves (mmW), such as, e.g., an ultra-dense network (UDN). In some embodiments, the wireless communications network 100 may also employ transmissions supporting WiFi transmissions, e.g., the wireless communications standard IEEE 802.11 ad or similar, or other non-cellular wireless transmissions.
[0046] The wireless communications network 100 comprises a network node 110. The network node 110 may serve wireless devices in at least one cell 115, or coverage area. The network node 110 may correspond to any type of network node or radio network node capable of communicating with a wireless device and / or with another network node, such as, a base station (BS), a radio base station, gNB, eNB, eNodeB, a Home NodeB, a Home eNodeB, a femto BS, or a pico BS in the wireless communications network 100. Further examples of the network node 110 may be a repeater, multi-standard radio (MSR) radio node such as MSR BS, network controller, radio network controller (RNC), base station controller (BSC), relay, donor node controlling relay, base transceiver station (BTS), access point (AP), transmission points, transmission nodes, a remote radio unit (RRU), a remote radio head (RRH), nodes in distributed antenna system (DAS), or core network node. The network node 110 may be arranged to communicate with a remote data processing unit 140, e.g., via a core network 150 of the wireless communications network 100. The remote data processing unit 140 may, for example, be a remote standalone server, a cloud-implemented server, a distributed server, dedicated data processing resources in a server farm, or similar.
[0047] As is also shown in Figure 1, a wireless device 121 is located within the cell 115. The wireless device 121 is configured to communicate within the wireless communications network 100 via the network node 110 over a radio link served by the network node 110. The wireless device 121 may transmit data over an air or radio interface to the network node 110 in uplink (UL), transmissions 132 and the radio base station may transmit data over an air or radio interface to the wireless device 121 in downlink (DL) transmissions 131. The wireless device 121 may refer to any type of wireless devices or user equipment (UE) communicating with a network node and / or with another wireless device in a cellular, mobile or radio communication network or system. Examples of such wireless devicesare mobile phones, cellular phones, personal digital assistants (PDAs), smart phones, tablets, sensors equipped with a UE, laptop mounted equipment (LME) (e.g. universal serial bus, USB), laptop embedded equipment (LEE), machine type communication (MTC) devices, or machine to machine (M2M) device, customer premises equipment (CPE), target device, device-to-device (D2D) wireless device, wireless device capable of machine to machine (M2M) communication.
[0048] As mentioned, it is desired to provide improved frequency multiplier arrangements. As part of the developing of the embodiments described herein, it has been realized that when both DC and AC is coupled between a balanced output port of an active balun and a balanced input port of a multiplier cell, energy efficiency may be improved. Thus, there is disclosed herein a frequency multiplier arrangement 200, 700, 800, 900.
[0049] Figure 2 shows a schematic illustration of a frequency multiplier arrangement 200 according to embodiments, and Figures 7, 8, and 9 show frequency multiplier arrangement 700, 800, and 900, respectively, which are respective example embodiments.
[0050] The disclosed frequency multiplier arrangement 200, 700, 800, 900 comprises an active balun (such as 220, 600a-600d) and a multiplier cell (such as 210, 300a, 300b, 500). The active balun of the frequency multiplier arrangement 200, 700, 800, 900 requires a small chip area as compared to other solutions using a passive balun.
[0051] Figures 3a and 3b illustrate example multiplier cells 300a and 300b, respectively, that may be used in the disclosed frequency multiplier arrangement. Figure 4 illustrates an example power booster 400 that may be utilized by a multiplier cell, such as 300a or 300b. Figure 5 shows an example multiplier cell 500, which is similar to the multiplier cell 300a, but utilizes the power booster of Figure 4. Figures 6a-6d illustrate example active baluns 600a, 600b, 600c, and 600d, respectively, that may be used in the disclosed frequency multiplier arrangement.
[0052] In particular, the frequency multiplier arrangement 700 of Figure 7 uses the multiplier cell 300a of Figure 3a and the active balun 600a of Figure 6a. The frequency multiplier arrangement 800 of Figure 8 uses the multiplier cell 300a of Figure 3a and the active balun 600b of Figure 6b. The frequency multiplier arrangement 900 of Figure 9 uses the multiplier cell 500 of Figure 5 and the active balun 600b of Figure 6b.
[0053] Any of the transistors in the embodiments disclosed herein may be a bipolar junction transistor (BJT). A BJT comprises a base, a collector, and an emitter, which may be called a control terminal, a current-collecting terminal, and a current-sourcing terminal, respectively. Any of the transistors in the embodiments disclosed herein may be a field-effect transistor (FET). A FET comprises a gate, a drain, and a source, which may be called a control terminal, a current-collecting terminal, and a current-sourcing terminal, respectively.
[0054] The frequency multiplier arrangement 200, 700, 800, 900 is suitable for receiving an input signal, for frequency multiplying the input signal, and for providing the frequency multiplied signal as an output signal. In some embodiments, the frequency multiplier arrangement 200, 700, 800, 900 is configured to receive the input signal, to frequency multiplying the input signal, and to provide the frequency multiplied signal as the output signal.The active balun 220, 600a-600d comprises two primary transistors QBI, QB2, an unbalanced input port 601 configured to receive the input signal, and a balanced output port 602 configured to provide a differential signal The input signal may comprise a fundamental tone with frequency fo. In Figures 2, 7, 8, and 9, the input signal is denoted “ln(fo)”.
[0055] The input signal provided to the unbalanced input port 601 may be referred to as a single-ended signal. In single-ended signaling, one wire carries an alternating signal which may contain alternating current (AC) and alternating voltage (and possibly also direct current and direct voltage), while another wire is connected to a reference voltage (often ground). An unbalanced port comprises a pair of terminals (also called nodes) for single-ended signaling. In contrast to single-ended signaling, differential signaling uses two wires carrying respective signals equal in magnitude but opposite in electric polarity. A balanced port comprises two terminals (also called nodes) for differential signaling. A port (balanced or unbalanced) comprises a pair of terminals connecting or for connecting a first circuit to a second circuit, as a position of entry or exit for electrical energy. The unbalanced input port 601 may be connected to an external circuit (not shown), such as a local oscillator.
[0056] The differential signal provided at the balanced output port 602 may comprise the frequency fo, but where two parts (or terminals or nodes) constituting the balanced output port 602 carries the signal with a 180-degree phase difference (ideally) and with equal amplitude (ideally). Note that in practice, there may be some unbalance in magnitude and / or phase.
[0057] The multiplier cell 210, 300a, 300b, 500 comprises two primary transistors QMI, QM2, a balanced input port 301 configured to receive the differential signal, an unbalanced output port 302 configured to provide the frequency multiplied signal as the output signal, and a first DC supply feed 312 configured to receive a first supply current lcM1- The first supply current ICMI is a DC current. A DC supply feed is an arrangement comprising one or more ports for receiving DC current and DC voltage from a supply, and circuitry for distributing the DC current and DC voltage to one or more transistors. The supply may provide a constant DC voltage VCMI to the first DC supply feed 312. During operation of the frequency multiplier arrangement, the primary transistors QMI , QM2 of the multiplier cell 210, 300a, 300b, 500 may draw respective DC currents from the supply.
[0058] The frequency multiplier cell 210, 300a, 300b, 500 is configured to receive the differential signal at the balanced input port 301, and to multiply the differential signal to provide a frequency multiplied signal as the output signal at the unbalanced output port 302. In other words, the frequency multiplied signal may comprises a harmonic frequency of at least two times a fundamental frequency of the input signal. The output signal provided by unbalanced output port 302 may be referend to as a single-ended signal. The output signal comprises at least one (desired) overtone of the input signal. Thus, the output signal (at the unbalanced output port 302) comprises at least a tone of frequency Nfo, where N is a natural number larger than one. In Figure 2, the output signal is denoted “Out(Nfo)”, and in Figures 7, 8, and 9, the output signal is denoted “Out(2fo)”.Note that the two primary transistors QMI, QM2 individually may output respective signals which comprises several tones (including the fundamental tone), and that it may be desired to handle the outputs of the primary transistors QMI, QM2 such that the frequency multiplier cell 210, 300a, 300b, 500 only outputs energy (of a significant level) at a single (desired) overtone at the unbalanced output port 302. One way to achieve such suppression is to utilize filter. Another way is to arrange the two primary transistors QMI, QM2 in a push-push configuration, which is discussed in more detail further below. Thus, in some embodiments, the multiplier cell 210, 300a, 300b, 500 may be configured such that the fundamental frequency of the input signal received at the unbalanced input port 601 of the active balun 220, 600a-600d is suppressed at the unbalanced output port 302 of the multiplier cell 210, 300a, 300b, 500.
[0059] The unbalanced output port 302 may be connected to an external circuit (not shown), such as a mixer. The balanced output port 602 is connected to the balanced input port 301. Thus, these two ports may be considered to have the same (differential) nodes.
[0060] The frequency multiplier arrangement 200, 700, 800, 900 is configured such that respective portions of the supply current ICMI are provided to each of the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500, and to each of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d via the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500, respectively, and via respective parts of the balanced output port 602 of the active balun 220, 600a-600d. In particular, the frequency multiplier arrangement 200, 700, 800, 900 is configured such that said respective portions of the supply current ICMI are provided during operation of the frequency multiplier arrangement 200, 700, 800, 900. Thus, during operation of the frequency multiplier arrangement, a supply may provide a constant DC voltage VcMito the first DC supply feed 312, and the primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 may draw respective DC currents from the supply, and the primary transistors QBI, QB2 of the active balun 220, 600a-600d may draw respective DC currents from the supply via the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500, respectively, and via respective parts of the balanced output port 602 of the active balun 220, 600a-600d.
[0061] In particular, each of the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 may be galvanically connected to a respective transistor of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d. In other words, the respective connections between primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 and the primary transistors QBI, QB2 of the active balun 220, 600a-600d is free from DC blocks (such as a capacitor arranged in series).
[0062] In the frequency multiplier cell 210, 300a, 300b, 500, the active balun 220, 600a-600d and the multiplier cell 210, 300a, 300b, 500 are DC coupled. In other words, the active balun and the multiplier cell share (reuse) DC current. In this way, the energy efficiency of the frequency multiplier arrangement may be increased.
[0063] Furthermore, the active balun and frequency multiplier share a single DC supply, instead of using two separated DC supplies. Thus, the disclosed frequency multiplier arrangement may enable simpler routing of supply feed lines.In addition, no capacitors (as DC blocks) are needed between the active balun and the multiplier cell. This may reduce the required chip area and may reduce losses.
[0064] In a first example, a different frequency multiplier arrangement (than the ones disclosed herein) may use two separate supply feeds (one for the multiplier cell and another for the active balun). In the first example, respective supply voltages (Vxand Vy) and respective supply currents (lxand ly) may be the same (Vx=Vy, lx=ly). In a second example, for the disclosed frequency multiplier arrangement 200, 700, 800, 900 (with said first DC supply feed 312), the first supply voltage (VCMI) may be doubled compared to the first example, and the first supply current (lCMi) may be the same as for the first example (VCMi=2Vx=2Vy, lCMi=lx=ly). In that case, the DC power consumption would be equal for the first and the second examples if losses are not considered. However, due to losses in practical implementations, it has been found that the first supply voltage (VCMI) for the second example may be selected as less than doubled than the one of the different frequency multiplier arrangement of the first example (VcMi<2Vx=2Vy). In this case, the DC power consumption for the disclosed frequency multiplier arrangement 200, 700, 800, 900 is lower for a given output power (which means a higher energy efficiency) compared to the different frequency multiplier arrangement.
[0065] In general, different kinds of active baluns and different kinds of multiplier cells may be utilized in the disclosed frequency multiplier arrangement. As mentioned, Figures 3a, 3b, and 5 illustrate example multiplier cells that may be used in the disclosed frequency multiplier arrangement, and Figures 6a-6d illustrate example active baluns that may be used in the disclosed frequency multiplier arrangement.
[0066] The multiplier cell 300a, as shown in Figure 3a, has two primary transistors QMI, and QM2. The respective sizes of those two transistors may be equal or unequal. The respective current-sourcing terminals form the balanced input port 301. The respective control terminals of two transistors are galvanically connected. The first DC supply feed 312 is implemented by an AC choke, and is configured to receive a first supply current ICMI and a first supply voltage VCMI. The first DC supply feed 312 is configured to provide respective portions of the first supply current ICMI to respective current-collecting terminals of the two primary transistors QMI, QM2 of the multiplier cell 300a. During operation of the multiplier cell 300a, the primary transistors QMI, QM2 may draw respective DC currents from a supply connected to the first DC supply feed 312. Furthermore, a capacitor C3 is arranged in series with the unbalanced output port 302 as a DC block.
[0067] The multiplier cell 300a comprises a second bias feed 311 configured to receive a second bias voltage VbMi and to provide the second bias voltage VbMi to respective control terminals of the two primary transistors QMI , QM2 of the multiplier cell 300a. A bias voltage is a DC voltage. A bias voltage is for setting an operating point of a transistor. A bias feed is an arrangement comprising one or more ports for receiving DC voltage from a supply and circuitry for distributing the DC voltage to one or more transistors. In Figure 3a, the second bias voltage VbMi is provided via a resistor R to the respective control terminals of two transistors. The shunted capacitor C and resistor R are connected in parallel from the perspective of AC. The respective current-collecting terminals areconnected to form the unbalanced output port 302. The two primary transistors QMI, QM2 of the multiplier cell 300a are arranged in a push-push configuration. Furthermore, the two primary transistors QMI, QM2 of the multiplier cell 300a is arranged in respective common-control terminal configurations (which may be called respective commongate configurations when the transistors are respective FETs, and respective common-base configurations when the transistors are respective BJTs).
[0068] The multiplier cell 300b, as shown in Figure 3b, has two primary transistors QMI , and QM2. The respective sizes of those two transistors may be equal or unequal. The respective current-sourcing terminals form the balanced input port 301. For each transistor, a control terminal is capacitively coupled via capacitor C to a current sourcing terminal of the other transistor. Thus, the two primary transistors QMI, QM2 of the multiplier cell 300b is arranged in a capacitor cross-coupled configuration. This configuration may enhance the gain difference between the common- and differential mode. The first DC supply feed 312 is implemented by an AC choke, and is configured to receive a first supply current lcMiand a first supply voltage VcMi. The first DC supply feed 312 is configured to provide respective portions of the first supply current ICMI to respective current-collecting terminals of the two primary transistors QMI , QM2 of the multiplier cell 300b. During operation of the multiplier cell 300b, the primary transistors QMI , QM2 may draw respective DC currents from a supply connected to the first DC supply feed 312. Furthermore, a capacitor C3 is arranged in series with the unbalanced output port 302 as a DC block.
[0069] The multiplier cell 300b comprises a second bias feed 311 configured to receive a second bias voltage VbMi and to provide the second bias voltage VbMi to respective control terminals of the two primary transistors QMI , QM2 of the multiplier cell 300b. In particular, the second bias voltage VbMi is provided via respective resistors R to the respective control terminals of two transistors. The respective current-collecting terminals are connected to form the unbalanced output port 302. Respective transmission lines TL1 , TL2 are arranged in series at respective current-collecting terminals. The two primary transistors QMI, QM2 of the multiplier cell 300b are arranged in a push-push configuration.
[0070] In an ideal case, the there is no unbalance in the differential signal provided to the multiplier cell 300a, 300b at the balanced input port 301. In that case, and if the multiplier cell is perfectly symmetrical, the respective outputs from two current-collecting terminals comprise the fundamental and higher-order harmonics. The fundamental and odd-order harmonic signals are in differential-mode, while even-order harmonic signals are in common mode. The phase difference (A(pout) of the respective transistor outputs, at a frequency nfo, may be expressed as A(pout(nfo)=n x Atpin (fo), where n is a natural number excluding zero and represents order of the harmonic (n=1 for the fundamental component), fo is the fundamental frequency, and A(pin(fo) is the phase difference at the input to the two transistors. When A(pin(fo)=180°, the fundamental and odd-order harmonics are cancelled at the unbalanced output port 302, while the even-order harmonics are added constructively. In most cases, the amplitude of the 2ndharmonic is higher than that of the 4thand other higher even-order harmonics, which makes the output signal at the unbalanced output port 302 dominated by the 2ndharmonic. Thus, the multiplier cell 300a, 300b may advantageously be used as a frequency doubler.For multiplier cell 300a, for a common-mode input, the shunted resistor R (AC-wise) and the shunted capacitor C loaded at the respective bases / gates of QMI and QM2 reduce gain of common-base / common-gate configured transistors QMI and QM2, similar to an emitter degeneration for common-emitter / common-source configured transistors. While, for differential-mode input, the respective bases / gates of QMI and QM2 is a virtual ground (I ,e. , the shunted resistor R and C have no influence on the gain of common-base / common-gate configured QMI and QM2). Therefore, the gain for the differential mode input signal is higher than that for the common-mode input signal.
[0071] For multiplier cell 300b, for a common-mode input, the instantaneous AC voltage across each transistor's base / gate and emitter / source has the same value, i.e., there is no AC signal input (no voltage difference).
[0072] Assuming the input differential signal is a balanced signal, the voltage signals at two ports, driven by injected differential AC currents, are V(t) and -V(t). respectively. The voltage signal across the base / gate and emitter / source becomes 2V(t) for one transistor, and - 2V(t) for another transistor Therefore, the differential model signal is amplified, while the common-mode signal disappears at the output in theory. On the other hand, the different fundamental signal with doubled amplitude will generate a larger harmonic at desired frequency, compared to that generated by a common-base configured transistor pair which has a grounded base / gate (V=0), thus, the voltage signal across the base / gate and the emitter / source is V(t).
[0073] In practice, however, the differential signal provided to the multiplier cell 300a, 300b may not be perfectly balanced (e.g., due to a non-ideal balun). As a consequence, the fundamental and odd-order harmonics are not perfectly cancelled at the unbalanced output port 302.
[0074] Suppression of the fundamental and odd-order harmonics at the unbalanced output port 302 may be increased by utilizing a cascaded differential amplifier at the current-collecting terminals of the primary transistors QMI, QM2 of the multiplier cell 300a, 300b. Such a cascaded differential amplifier may amplify differential mode signals but suppress / attenuate common mode signals, and, consequently, improve the suppression of undesired fundamental and odd-order harmonics at the unbalanced output port 302 of the multiplier cell.
[0075] Thus, it may be beneficial if the multiplier cell itself has a function similar to a differential amplifier. This may be achieved by the particular configurations of Figures 3a and 3b. In particular, in Figure 3a, the control terminals of the two primary transistors QMI, QM2 (which are in respective common-control terminal configurations) are AC grounded for differential inputs at the balanced input port 301 (see node "A” in Figure 3a). While for commonmode inputs at the balanced input port 301, the control terminals of two transistors are grounded through the resistor R and the capacitor C, which are connected in parallel (AC-wise). The parallel RC circuit (which may be written as R / / C) presents resistance of 2R and a capacitance of C / 2, respectively. The parallel RC circuit presents a so-called "base degeneration”, which suppress the gain of the multiplier cell. This function is similar to emitter degeneration for a common emitter configured transistor. The different gain between common mode and differential mode signal lets the multiplier cell present a function similar to a differential amplifier. While, at the same time, the multiplier cell provides the in-phase 2ndharmonic at two current collecting terminals (when the input signal into the balanced input port 301 is in differential mode at the fundamental frequency fo).For Figure 3b, the current control terminal of one primary transistor, e.g. QMI, is connected with one terminal of the balanced input port 301 via a capacitor C, so is the current source terminal of another primary transistor, e.g. QM2‘ While the current source terminal of QMI is connected with another terminal of balanced input port 301, so is the current control terminal of QM2 via a capacitor C. There are a common-mode component (signal) and a differential-mode component (signal) in the voltage / current signal at the two terminals of the balanced input port 301. For the common-mode component, the two terminals of the balanced input port 301 have the same voltage / current signal, and the signal across one of the primary transistor's current control terminal and current source terminal is equal, i.e., no AC signal. Therefore, the common mode component is not amplified. For the differential mode component, the two terminals of the balanced input port 301 have the voltage / current signal with the same amplitude but with a 180-degree phase difference. The signal across one of the primary transistor's current control terminal and current source terminal is 2V(t) / 2l(t), where V(t) / I(t) represents the differential-mode signal at one terminal of the balanced input port 301. Thus, the differential mode component is amplified.
[0076] To increase the output power of the multiplier cell, a power booster may be stacked on top of the primary transistors of the multiplier cell. The power booster may, e.g., be implemented by a common-control terminal (i.e. common-base or common gate) configured transistor stage 400. In particular, the multiplier cell may comprise a common-base or common-gate terminal configured transistor stage 400 arranged between the two primary transistors QMI , QM2 of the multiplier cell 210, 500 and the unbalanced output port 302 of the multiplier cell 210, 500. Figure 4 shows an example of a common-control terminal configured transistor stage 400.
[0077] The stage 400 comprises two transistors QM3, QM4. Each of these transistors is configured in a common-control terminal (i.e. common-base or common-gate) configuration. The respective control terminals of the two transistors QM3, QM4 are provided with a bias voltage VbM2 via respective resistors R to the respective control terminals of two transistors QM3, QM4. A respective grounded capacitor C is connected to the respective control terminals of the two transistors QM3, QM4. A transmission line TL3 is arranged in series with the current-collecting terminal of the transistor QM3. A transmission line TL4 is arranged in series with the current-collecting terminal of the transistor QM4.
[0078] Figure 5 shows a multiplier cell 500 comprising the common-control terminal configured transistor stage 400. The multiplier cell 500 is similar to the multiplier cell 300a, but utilizes the transistor stage 400 of Figure 4. Note that the transistor stage 400 could also be implemented in the multiplier cell 300b of Figure 3b. Also note that several transistor stages may be stacked on top of one another in a multiplier cell. When including the transistor stage 400 in a multiplier cell, the transistor stage 400 amplifies the harmonics but also generate the harmonics by itself. In other words, the transistor stage 400 has dual functions: 1) amplifying the 2ndharmonic and 2) multiplying the fundamental component.
[0079] In the multiplier cell 500, the first DC supply feed 312 is implemented by an AC choke, and is configured to receive a first supply current ICMI and a first supply voltage VCMI. The first DC supply feed 312 is configured to provide respective portions of the first supply current ICMI to respective current-collecting terminals of the two primary transistors QMI , QM2 of the multiplier cell 500 via the transistor QM3, QM4, respectively. During operation ofthe multiplier cell 500, the transistors QM3, QM4 may draw respective DC currents from a supply connected to the first DC supply feed 312, and the primary transistors QMI, QM2 may draw respective DC currents from the supply via the transistors QM3, QM4, respectively. Furthermore, a capacitor C3 is arranged in series with the unbalanced output port 302 as a DC block.
[0080] In Figure 5, it can be seen that a transmission line TL1 is arranged in series between the current-collecting terminal of the transistor QMI and the current-sourcing terminal of the transistor QM3, and a transmission line TL2 is arranged in series between the current-collecting terminal of the transistor QM2 and the current-sourcing terminal of transistor QM4. The transmission lines TL1 and TL3, at the branch of l+ may have different lengths than the transmission lines TL2 and TL4 at the branch of I.. The different lengths may compensate phase and amplitude errors in certain extend (such that the fundamental and odd-order harmonics are cancelled at the unbalanced output port 302, while the even-order harmonics are added constructively).
[0081] Furthermore, inherent parasitic capacitances of each transistor may limit the bandwidth of the multiplier cell. Figure 5 shows parasitic capacitances of each transistor as dashed lines, namely Cpara_Ti, Cpara_Ti', Cpara_T2, CPara_T2’, Cpara_T3, Cpara_T3’, Cpara_T4, Cpara_T4’. However, with a transmission line, transistor parasitic capacitances (e.g., at the emitter or at the collector) may be incorporated / absorbed into a n-network (which is a 3rd- order low-pass filter), to migrate the influence of the parasitic capacitances. For instance, TL1 and the parasitic capacitance Cpara_Ti' at the current-collecting terminal of QMI, as well as the parasitic capacitance Cpara_T3’ at the currentsourcing terminal of the transistor QM3 form a n-network. While parasitic capacitances Cpara_T3 and Cpara_T4 at the current-collecting terminals of QM3 and QM4 may be incorporated into an impedance matching network (not shown in Figure 5) along with TL3 and TL4.
[0082] As mentioned, different kinds of multiplier cells may be utilized in the disclosed frequency multiplier arrangement. In general, multiplier cell 210, 300a, 300b, 500 may comprise a second bias feed 311 configured to receive a second bias voltage VbMi and to provide the second bias voltage VbMi or respective portions of the second bias voltage VbMi to respective control terminals of the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500. In general, the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 may be arranged in a push-push configuration. In general, the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 may be arranged in respective common-base configurations, in respective common-gate configurations, or in a capacitor cross-coupled configuration. In general, the multiplier cell 210, 300a, 300b, 500 may comprise a common-base or common-gate terminal configured transistor stage 400 arranged between the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500 and the unbalanced output port 302 of the multiplier cell 210, 300a, 300b, 500. In general, the multiplier cell 210, 300a, 500 may be configured such that, the control terminals of two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b are AC grounded for differential inputs at the balanced input port 301 of the multiplier cell 210, 300a, , 500, and presented with a parallel RC circuit for common-mode at the balanced input port 301 the multiplier cell 210, 300a, 500. In general, the multiplier cell 200, 300b, may be configured such that the control terminal of QMI or QM2 is connected to one terminal of the balanced input port 301 via a capacitor, and the sourceterminal of QMI or QM2 is connected to another terminal of the balanced input port 301. In general, the first DC supply feed 312 may be configured to provide respective portions of the first supply current lcMito respective current-collecting terminals of the two primary transistors QMI, QM2 of the multiplier cell 210, 300a, 300b, 500.
[0083] There are various types of active baluns. For example, a common-current sourcing terminal common-control terminal (i.e., common-source common-gate or common-emitter common-base) configured active balun, with a shunted diode D1, is shown in Figure 6a. A single-ended signal injected into the unbalanced input port 601 configured appears at the current sourcing terminal of the transistor QBI and at the control terminal of the transistor QB2 simultaneously. The respective outputs at the current collecting terminals of QBI and QB2 have a 180-degree phase difference. The control terminal of QB2 is connected to ground through a capacitor C2. The diode D1 provides a DC path for current sourcing terminal of QBI and the control terminal of QB2. The active balun 600a comprises a first bias feed 610 configured to receive a first bias voltage VbBi and configured to provide or respective portions of the first bias voltage VbBi to respective control terminals of the two primary transistors QBI, QB2 of the active balun 600a. In particular, the first bias feed 610 is formed by the resistor R and is configured to receive a first bias voltage VbBi and supply it to the control terminal of QBI, and to the control terminal of QB2 via (through) QBI. A transmission line with TL7 is arranged in series with the diode D1. With a suitable length of a transmission line TL7, impedance to ground may be increased, avoiding leakage of the input signal to the ground. Different length of TL5 and TLe may modify the phases of output signals l+ and I.. All transmission lines may be configured to absorb the transistors' parasitic capacitances. Respective nodes of TL5 and TLe form the balanced output port 602. Furthermore, a capacitor Ci is arranged in series at the input port 601 as a DC block. Said capacitor may be a part of impedance matching network (not shown in Figure 6a) at the input port.
[0084] The active balun disclosed herein may comprise one or more amplifier stages arranged in connection to the unbalanced input port 601 of the active balun. Figure 6b shows another example of an active balun, namely, active balun 600b, which comprises a transistor QB3 that forms an amplifier stage. The active balun 600b is similar to the active balun 600a, except that the diode D1 and transmission line TLz is replaced by the transistor QB3, the transmission line TLs, and a resistor R. The single-ended input signal is applied at the base / gate of the transistor QB3. Through a transmission line TLs, the collector / drain of QB3 is connected to the emitter / source of QBI and the base / gate of QB2 simultaneously. The transistor QB3 is provided with a bias voltage VbB2 via a resistor R. Figure 6c shows another example of an active balun, namely, active balun 600c. In the active balun 600c, the two primary transistors QBI , QB2 of the active balun 600c are arranged in a capacitor cross-coupled configuration. This configuration reduces mismatching of amplitude and phase at the differential output signal of the active balun. For each transistor QBI, QB2, a control terminal is capacitively coupled via capacitor C to a current sourcing terminal of the other transistor. The active balun 600c comprises a first bias feed 610 configured to receive a first bias voltage VbBi and configured to provide the first bias voltage VbBi to respective control terminals of the two primary transistors QBI, QB2 of the active balun 600c. In particular, the first bias feed 610 is formed by two resistors (R) and is configured to receive a first bias voltage VbBi and supply it to the respective control terminal of QBI andQB2. Transistors QB3, QB4 form an amplifier stage. The single-ended input signal is applied at the base / gate of the transistor QB3. Through a transmission line TLs, the collector / drain of QB3 is connected to the emitter / source of QBI and the base / gate of QB4 via capacitor C2, as well as the base / gate of QB2 via capacitor C3 simultaneously. The transistor QB3 is provided with a bias voltage VbB2 via a resistor R. The transistor QB4 is provided with a bias voltage VbB3 via a resistor R. A capacitor Ci is arranged in series at the input port 601 as a DC block. Said capacitor may be a part of impedance matching network (not shown in Figure 6c) at the input port. Furthermore, a capacitor C2 is arranged in series between QB3 and of QB4 as a DC block. The collector / drain of QB4 is connected to the emitter / source of QB2 and the base / gate of QBI via capacitor C3 simultaneously.
[0085] The active balun 600c thus comprises a transistor pair in a capacitor cross-coupled configuration (QBI and QB2), as well as two transistors in a common-emitter and a common-base configuration (QB3 and QB4). This configuration improves the balance of the differential output in magnitude and / or phase, as well increases the output power. This is because the capacitor cross-coupled pair amplifies the differential input signal and suppress the common-mode input signals (two signal in-phase).
[0086] Figure 6d shows another example of an active balun, namely, active balun 600d. In the active balun 600d, the two primary transistors QBI, QB2 of the active balun 600d are arranged in a differential-pair configuration. The input signal appears at the base / gate of a common-emitter / common-source configured transistor QBI. A fraction of the input signal appears at the emitter / source of a common-base / common-gate configured transistor QB2. Capacitor C2 at the base of QB2 introduces an AC ground. The active balun 600d comprises a first bias feed 610 configured to receive a first bias voltage VbBi and configured to provide the first bias voltage VbBi to respective control terminals of the two primary transistors QBI, QB2 of the active balun 600d. In particular, the first bias feed 610 is formed by two resistors (R) and is configured to receive a first bias voltage VbBi and supply it to the respective control terminal of QBI and QB2 The outputs from the collectors / drains of the two primary transistors QBI, QB2 has a 180-degree phase difference. In Figure 6d, an additional DC current source / supply (shown as IDC in the figure) is arranged at a node between the current sourcing terminals of the two primary transistors QBI, QB2 of the active balun 600d. When the active balun 600d is paired with a multiplier cell in the disclosed frequency multiplier arrangement, DC current flows via the balanced output port 602 and via the source / supply (IDC).
[0087] As mentioned, different kinds of active baluns may be utilized in the disclosed frequency multiplier arrangement. In general, the active balun 220, 600a-600d may comprise a first bias feed 610 configured to receive a first bias voltage VbBi and configured to provide the first bias voltage VbBi or respective portions of the first bias voltage VbBito respective control terminals of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d. In general, the two primary transistors QBI, QB2 of the active balun 220, 600a-600d may be arranged in a common-emitter and a common-base configuration, respectively, or in a common-source and a common-gate configuration, respectively. Furthermore, the active balun 220, 600b, 600c may comprise an amplifier stage (QBS) or amplifier stages (QB3 and QB4) arranged in connection to the unbalanced input port 601 of the active balun 220, 600b, 600c. Furthermore, the two primary transistors QBI, QB2 of the active balun 220, 600dmay be arranged in a differential-pair configuration. In general, the balun 220, 600a-600d may be configured to provide a differential current at the balanced output port 602 of the active balun 220, 600a-600d.
[0088] With reference to Figures 7-9, the frequency multiplier arrangements 700, 800, 900 act as respective frequency doublers. As is shown in Figures 7-9, frequency multiplier arrangements 700, 800, 900 may comprise a capacitor Ci is arranged in series in connection to the unbalanced input port 601 as a DC block, and a capacitor C3 is arranged in series at the unbalanced output port 302 as a DC block.
[0089] As is shown in the examples of Figures 7-9, the frequency multiplier arrangement 200, 700, 800, 900 disclosed herein may comprise an input matching network (comprising TLini, TLn2, TLn3, and Ci) arranged at the unbalanced input port 601. Furthermore, the frequency multiplier arrangement 200, 700, 800, 900 disclosed herein may comprise an output matching network (comprising TL1 , TL2, TL0Uti, TL0Ut2, and C3) arranged at the unbalanced output port 302. The input and output matching networks are configured to match respective port impedances, such as 50 Ohm. The first DC supply feed 312 is comprises an input port at TL0Uti.
[0090] As is shown in the examples of Figures 7-9, the frequency multiplier arrangement disclosed herein 200, 700, 800, 900 may comprise a matching network, where the matching network comprises respective transmission lines TL5, TL6arranged in series between the respective parts of the balanced output port 602 of the active balun 220, 600a-600d and the respective parts of the balanced input port 301 of the multiplier cell 210, 300a, 300b, 500. Thus, the disclosed frequency multiplier arrangement does not require a large inter-stage impedance matching network between the active balun and the multiplier cell, which reduces the chip area and the associated losses.
[0091] In Figure 7, during operation of the frequency multiplier arrangement 700, the primary transistors QMI, QM2 may draw respective DC currents from a supply connected to the first DC supply feed 312, and the primary transistors QBI, QB2 may draw respective DC currents from the supply via the transistors QMI, QM2, respectively. The first DC supply feed 312 may be configured to provide respective portions of the first supply current ICMI to respective current-collecting terminals of the two primary transistors QMI , QM2 of the multiplier cell 300a.
[0092] In Figure 8, during operation of the frequency multiplier arrangement 800, the primary transistors QMI, QM2 may draw respective DC currents from a supply connected to the first DC supply feed 312, the primary transistors QBI, QB2 may draw respective DC currents from the supply via the transistors QMI , QM2., and the transistor QB3 may draw respective DC currents from the supply via transistor QBI and transistor QMI. The first DC supply feed 312 may be configured to provide respective portions of the first supply current lcMito respective current-collecting terminals of the two primary transistors QMI, QM2 of the multiplier cell 300a.
[0093] In Figure 9, during operation of the frequency multiplier arrangement 900, the transistors QM3, QM4 may draw respective DC currents from a supply connected to the first DC supply feed 312, the primary transistors QMI, QM2 may draw respective DC currents from the supply via the transistors QM3, QM4, respectively, and the primary transistors QBI, QB2 may draw respective DC currents from the supply via the primary transistors QMI, QM2, respectively, and via the transistors QM3, QM4, respectively. Furthermore, transistor QB3 may draw respective DCcurrents from the supply via transistor QBI as well as transistors QMI and QM3 The first DC supply feed 312 may be configured to provide respective portions of the first supply current lcMito respective current-collecting terminals of the two primary transistors QMI, QM2 of the multiplier cell 500 via the transistor QM3, QM4, respectively.
[0094] As is shown in the examples of Figures 7-9, in the frequency multiplier arrangement disclosed herein 200, 700, 800, 900, a respective current-collecting terminal of each transistor of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d may be galvanically connected to a respective current-sourcing terminal of the two primary transistors QMI , QM2 of the multiplier cell 210, 300a, 300b, 500.
[0095] In some embodiments, respective portions of the second bias voltage VbMi are provided as DC voltages to the current collecting terminals of two primary transistors QBI, QB2 of the active balun 220, 600a-600d via the two primary transistors QMI , QM2 of the multiplier cell 210, 300a, 300b, 500, respectively, and via respective parts of the balanced output port 602 of the active balun 220, 600a-600d. The second bias voltage VbMi may be supplied to respective control terminals of each of the primary transistors QMI , QM2 of the multiplier cell 210, 300a, 300b, 500. The second bias voltage VbMi may be supplied directly to each of said control terminals. Each DC voltage at the respective control terminals is coupled through the respective primary transistors QMI, QM2 to the respective current sourcing terminals of each primary transistors QMI, QM2 (i.e., there is a voltage drop across the control terminal and the current sourcing terminal). The respective portions of the DC voltage at the respective current sourcing terminals are coupled to the respective current-collecting terminals of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d. Consequently, the respective operation points of the two primary transistors QMI , QM2 of the multiplier cell 210, 300a, 300b, 500 is set by the first DC supply feed 312 and the particular value of the second bias voltage VbMi. The respective operation points of the two primary transistors QBI, QB2 of the active balun 220, 600a-600d is set by the particular value of the second bias voltage VbMiand set by the particular value of the first bias voltage VbBi.
[0096] There is also disclosed herein an apparatus for wireless communications. The apparatus comprises the multiplier arrangement 200, 700, 800, 900 according to the discussions above. The apparatus may be a network node 110 or a wireless device 121, as discussed in connection to Figure 1.
[0097] Figures 10a-12b show plots of simulated performance. In particular, Figures 10a and 10b show plots of simulated performance for the frequency multiplier arrangement 700 of Figure 7; Figures 11a and 11b show plots of simulated performance for the frequency multiplier arrangement 800 of Figure 8; and Figures 12a and 12b show plots of simulated performance for the frequency multiplier arrangement 900 of Figure 9. In these simulations, a 130 nm silicon-germanium HBT technology is used. The input signal is a single tone signal and swept from 56-94 GHz in Figures 10a-10b, and from 60-88 GHz in Figures 11 a-12b. Correspondingly, the output frequency of the output signal (2ndharmonic of the input signal) corresponds to a frequency range from 112-188 GHz in Figures 10a-10b, and from 120-176 GHz in Figures 11 a-12b. Source and load impedances are 50 Ohm. The power of the input signal is 5 dBm. The supply voltage VCMI is 2.6 V for Figures 10a- 11 b and 3.5 V for Figures 12a-12b. Biasvoltages VbMi and VbBi are 2.15V, 1.5V, respectively for Figure 10a-10b. Bias voltages VbMi ,VbBi and VbB2are 2.15V, 1.5V, and 0.7V, respectively for the Figure 11a-11b. Bias voltages VbM2, VbMi BI and VbB2 are 3.15 V 2.15V, 1.5V, and 0.7V, respectively for the Figure 12a-12b.
[0098] Suppression of undesired harmonics may be expressed by the harmonic rejection ratio (HRR), which is the power difference between the desired 2ndharmonic and the undesired harmonic, i.e.,
[0099] HRR2i= P2- Pi( / = 1,3,4,,,)
[0100] where i is the order of the harmonic, e.g., i =1 is the fundamental. HRR21 and HRR23 are parameters that may be used to evaluate the matching quality of the differential output signals from the active balun, as well as the rejection of the common-mode signals in the frequency multiplier cell.
[0101] The efficiency of the frequency multiplier arrangement is another parameter that may be used to evaluate the performance. It may be defined as
[0102]
[0103] where Pout and Pin are output power at the desired harmonic frequency and input power at the fundamental frequency, respectively. PDC is the overall DC power consumption of the arrangement.
[0104] Figures 10a, 11a, and 12a show output power (of the 2ndharmonic), HRR21 and HRR23 versus input frequency. Figures 10b, 11b, and 12b show efficiency and DC power consumption versus input frequency.
[0105] In Figure 10a, it can be seen that the maximum output power is 3.56 dBm at an input frequency of 71 GHz (output frequency 142 GHz). The 3-dB bandwidth of the output power is 69 GHz (from 115 GHz to 184 GHz). The fractional bandwidth is 46.1%. Within the 3-dB band, the harmonic rejection ratio of the fundamental (HRR21) varies between 11.1 dBc and 24.7 dBc, and the harmonic rejection ratio of the third-order harmonic (HRR32) between 12.2 dBc and 26 dBc. The amplitude of other high order harmonics is far lower that of the fundamental or the 3rdharmonic. Thus, their respective HRRs are not presented in the plots.
[0106] In Figure 10b, it can be seen that, within the 3-dB band, the efficiency varies between 2.18% to 4.57%. The maximum efficiency occurs at input frequency of 70 GHz (output frequency 140 GHz). The DC power consumption varies between 36.5 mW and 44.3 mW.
[0107] In Figure 11a, it can be seen that the maximum output power is 5.53 dBm at an input frequency of 73.5 GHz (output frequency 147 GHz) which is 1.97 dB higher than the results of Figure 10a. The 3-dB bandwidth of the output is 47.4 GHz (from 124.6 GHz to 172 GHz). The fractional bandwidth is 32%, which is less than the results of Figure 10a. Within the 3-dB band, HRR21 varies between 14.7 dBc and 24.5 dBc, and HRR32 between 17.2 dBc and 29 dBc, which are better values than the results of Figure 10a.
[0108] In Figure 11b, it can be seen that, within the 3-dB band, the efficiency varies between 3.42% to 5.24%. The maximum efficiency occurs at input frequency of 76.5 GHz (output frequency 153 GHz). The efficiency is about 1percentage point better than that of the results of Figure 10b. The DC power consumption varies between 48.6 mW and 67.4 mW.
[0109] In Figure 12a, it can be seen that the maximum output power is 7.78 dBm at an input frequency of 72 GHz (output frequency 144 GHz), which is 2.25 dB higher than that of the results of Figure 11a. The 3-dB output frequency band width is 53 GHz (from 120 GHz to 173 GHz). The fractional bandwidth is 36.1%. In the 3-dB band, HRR21 varies from 21.4 dBc to 32.9 dBc, and HRR23 varies from 20 dBc to 40 dBc. The rejection of undesired harmonics is the best among the frequency multiplier arrangements 700, 800, and 900.
[0110] In Figure 12b, it can be seen that the efficiency has a maximum of 5.26% at an input frequency of 74.5 GHz (output frequency 149 GHz). Within the 3-dB band, the efficiency varies between 3.43% to 5.26%, which is similar to the results of Figure 11 b. The DC power consumption varies between 83.8 mW and 113 mW.
[0111] The description of the example embodiments provided herein have been presented for purposes of illustration. The description is not intended to be exhaustive or to limit example embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of various alternatives to the provided embodiments. The examples discussed herein were chosen and described to explain the principles and the nature of various example embodiments and its practical application to enable one skilled in the art to utilize the example embodiments in various manners and with various modifications as are suited to the particular use contemplated. The features of the embodiments described herein may be combined in all possible combinations of methods, apparatus, modules, systems, computer programs, and computer program products. It should be appreciated that the example embodiments presented herein may be practiced in any combination with each other.
[0112] It should be noted that the word "comprising” does not necessarily exclude the presence of other elements or steps than those listed and the words "a” or "an” preceding an element do not exclude the presence of a plurality of such elements. It should further be noted that any reference signs do not limit the scope of the claims, that the example embodiments may be implemented at least in part by means of both hardware and software, and that several "means”, "units” or "devices” may be represented by the same item of hardware.
[0113] The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be construed as limiting.
Claims
CLAIMS1. A frequency multiplier arrangement (200, 700, 800, 900) for receiving an input signal, for frequency multiplying the input signal, and for providing the frequency multiplied signal as an output signal,wherein the frequency multiplier arrangement (200, 700, 800, 900) comprises an active balun (220, 600a-600d) and a multiplier cell (210, 300a, 300b, 500),wherein the active balun (220, 600a-600d) comprises two primary transistors (QBI, QB2), an unbalanced input port (601) configured to receive the input signal, and a balanced output port (602) configured to provide a differential signal,wherein the multiplier cell (210, 300a, 300b, 500) comprises two primary transistors (QMI, QM2), a balanced input port (301) configured to receive the differential signal, an unbalanced output port (302) configured to provide the frequency multiplied signal as the output signal, and a first direct current, DC, supply feed (312) configured to receive a first supply current (lcMi),and wherein frequency multiplier arrangement (200, 700, 800, 900) is configured such that respective portions of the supply current (ICMI) are provided to each of the two primary transistors (QMI and QM?) of the multiplier cell (210, 300a, 300b, 500), and to each of the two primary transistors (QBI, QB2) of the active balun (220, 600a-600d) via the two primary transistors (QMI, QM2) of the multiplier cell (210, 300a, 300b, 500), respectively, and via respective parts of the balanced output port (602) of the active balun (220, 600a-600d).
2. The frequency multiplier arrangement (200, 700, 800, 900) according to claim 1, wherein each of the two primary transistors (QMI, QM2) of the multiplier cell (210, 300a, 300b, 500) is galvanically connected to a respective transistor of the two primary transistors (QBI, QB2) of the active balun (220, 600a-600d).
3. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein a respective current-collecting terminal of each transistor of the two primary transistors (QBI, QB2) of the active balun (220, 600a-600d) is galvanically connected to a respective current-sourcing terminal of the two primary transistors (QMI, QM2) of the multiplier cell (210, 300a, 300b, 500).
4. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the first DC supply feed (312) configured to respective portions of the first supply current (ICMI) to respective currentcollecting terminals of the two primary transistors (QMI , QM2) of the multiplier cell (210, 300a, 300b, 500).
5. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the active balun (220, 600a-600d) comprises a first bias feed (610) configured to receive a first bias voltage (VbBi) and configured to provide the first bias voltage (VbBi) or respective portions of the first bias voltage (VbBi) to respective control terminals of the two primary transistors (QBI, QB2) of the active balun (220, 600a-600d).
6. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein multiplier cell (210, 300a, 300b, 500) comprises a second bias feed (311) configured to receive a second bias voltage (VbMi) and to provide the second bias voltage (VbMi) or respective portions of the second bias voltage(VbMi) to respective control terminals of the two primary transistors (QMI, QM?) of the multiplier cell (210, 300a, 300b, 500).
7. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, comprising a matching network, the matching network comprising respective transmission lines (TLs, TLe) arranged in series between the respective parts of the balanced output port (602) of the active balun (220, 600a-600d) and the respective parts of the balanced input port (301) of the multiplier cell (210, 300a, 300b, 500).
8. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the two primary transistors (QMI, QM?) of the multiplier cell (210, 300a, 300b, 500) are arranged in a push-push configuration.
9. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the two primary transistors (QMI, QM2) of the multiplier cell (210, 300a, 300b, 500) are arranged in respective common-base configurations, in respective common-gate configurations, or in a capacitor cross-coupled configuration.
10. The frequency multiplier arrangement (200, 900) according to any previous claim, wherein the multiplier cell (210, 500) comprises a common-base or common-gate configured transistor stage (400) arranged between the two primary transistors (QMI , QM2) of the multiplier cell (210, 500) and the unbalanced output port (302) of the multiplier cell (210, 500).
11. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the two primary transistors (QBI, QB2) of the active balun (220, 600a-600d) are arranged in a common-emitter and a common-base configuration, respectively, or in a common-source and a common-gate configuration, respectively.
12. The frequency multiplier arrangement (200, 900) according to claim 11, wherein the active balun (220, 600b, 600c) comprises one or more amplifier stages (QB3, QB4) arranged in connection to the unbalanced input port (601) of the active balun (220, 600b, 600c).
13. The frequency multiplier arrangement (200) according to any of claims 1-10, wherein the two primary transistors (QBI, QB2) of the active balun (220, 600d) are arranged in a differential-pair configuration.
14. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the frequency multiplied signal comprises a harmonic frequency of at least two times a fundamental frequency of the input signal.
15. The frequency multiplier arrangement (200, 700, 800, 900) according to any previous claim, wherein the multiplier cell (210, 300a, 300b, 500) is configured such that the fundamental frequency of the input signal received at the unbalanced input port (601) of the active balun (220, 600a-600d) is suppressed at the unbalanced output port (302) of the multiplier cell (210, 300a, 300b, 500).
16. An apparatus (110, 121) for a wireless communications network (100), the apparatus comprising the frequency multiplier arrangement (200, 700, 800, 900) according to any of claims 1-15.
17. The apparatus (110, 121) according to claim 16, wherein the apparatus is a network node (110) or a wireless device (121).