System and method for metrology and inspection data mapping of partial field design layouts

Abstract

A non-transitory computer-readable medium stores a set of instructions for performing operations that include, based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario from a plurality of exposure scenarios matches an arrangement of the multiple reticle images with first and second reticle images respectively disposed at first and second locations of the field. The operations also include determining one or more lithography performance metrics based on a measurement of exposed patterns at the field. The operations also include mapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

Description

SYSTEM AND METHOD FOR METROLOGY AND INSPECTION DATA MAPPING OF PARTIAL FIELD DESIGN LAYOUTSCROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to US Application No. 63 / 755,574, filed February 7, 2025, and which is incorporated herein in its entirety by reference.FIELD

[0002] The description herein relates to metrology and lithographic processes.BACKGROUND

[0003] In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection can be performed using systems such as optical microscopes or charged particle beam microscopes (e.g., a scanning electron microscope (SEM)). As the sizes of IC components continue to shrink, accuracy and speed of defect detection become more and more important for yield and throughput. However, imaging resolution and throughput of inspection tools struggle to keep pace with the ever-decreasing feature size of IC components. Decreasing feature sizes also increases the risk of errors in lithography stitching, a process by which a large design is divided into smaller sections and then precisely aligned during exposure to seamlessly “stitch” together the complete pattern on the wafer.SUMMARY

[0004] Embodiments of the present disclosure provide a method for mapping lithography performance metrics from measurements to locations on a wafer based on exposure scenario.

[0005] In some embodiments, a non-transitory computer-readable medium for mapping lithography performance metrics from measurements to locations on a wafer based on exposure scenario is provided. The non-transitory computer-readable medium can store a set of instructions that is executable by at least one processor of an apparatus to cause the apparatus to perform operations. The operations can comprise, based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario of a plurality of exposure scenarios matches an arrangement of the multiple reticle images in the field. The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field. The operations can also comprise determining one or more lithography performance metrics based on a measurement of exposed patterns at the field. The operation scan also comprise mapping the one or more lithographyperformance metrics to the first location and the second location based on the determined exposure scenario.

[0006] In some embodiments, a system for mapping lithography performance metrics from measurements to locations on a wafer based on exposure scenario is provided. The system can comprise one or more processors and one or more memory devices. The one or more memory devices can store set of instructions that is executable by the one or more processors to cause the system to perform operations. The operations can comprise, based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario of a plurality of exposure scenarios matches an arrangement of the multiple reticle images in the field. The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field. The operations can also comprise determining one or more lithography performance metrics based on a measurement of exposed patterns at the field. The operation scan also comprise mapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

[0007] In some embodiments, a system for mapping lithography performance metrics from measurements to locations on a wafer based on exposure scenario is provided. The system can comprise a lithographic apparatus, a metrology apparatus, and a controller. The lithographic apparatus can expose a wafer according to a wafer exposure process. The metrology apparatus can take measurements of the wafer for ascertaining a quality of the wafer exposure process. The controller can comprise circuitry. The controller can, based on a determination that the wafer exposure process is configured to use multiple reticle images to expose a field of the wafer, determine which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field. The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field. The controller can also determine one or more lithography performance metrics based on a measurement of exposed patterns at the field. The controller can also map the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

[0008] In some embodiments, a method for mapping lithography performance metrics from measurements to locations on a wafer based on exposure scenario is provided. The method can comprise, based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field. The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field. The method can also comprise determining one or more lithography performance metrics based on a measurement of exposedpatterns at the field. The method can also comprise mapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.BRIEF DESCRIPTION OF FIGURES

[0009] The above and other aspects of the present disclosure will become more apparent from the description of example embodiments, taken in conjunction with the accompanying drawings.

[0010] FIG. 1 shows an example charged-particle beam inspection system, consistent with embodiments of the present disclosure.

[0011] FIG.2 shows an example multi-beam inspection apparatus, consistent with embodiments of the present disclosure that can be a part of the charged-particle beam inspection system of FIG. 1.

[0012] FIG.3 shows an example set of wafer field arrangements, consistent with embodiments of the present disclosure.

[0013] FIG.4 shows a flowchart of an example process flow for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments of the present disclosure.

[0014] FIG.5 shows a flowchart with more details of the example process flow for mapping lithography performance to locations on a wafer based on exposure scenario in FIG. 4, consistent with embodiments of the present disclosure.

[0015] FIG. 6 shows a flowchart of an example method for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments of the present disclosure.

[0016] FIG. 7A shows a system of apparatuses used for lithographic fabrication, consistent with embodiments of the present disclosure.

[0017] FIG. 7B shows an example computing system for performing one or more operations of the process flows or methods disclosed herein, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0018] Reference will now be made in detail to example embodiments, examples of which are illustrated in the drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of example embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses, systems, and methods consistent with aspects related to subject matter that may be recited in the appended claims. For example, although some embodiments are described in the context of utilizing charged-particle beams (e.g., electron beams), the disclosure is not so limited. Unless infeasible, embodiments described herein can be implemented in any other type of charged particledevice (e.g., proton beams). Furthermore, other imaging systems may be used, such as optical imaging, photodetection, x-ray detection, or the like.

[0019] Electronic devices are constructed of circuits formed on a substrate. The substrate is typically of a semiconductor material (e.g., silicon) and is often referred to as a wafer by persons of skill in the art. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. With advancements in technology, the size of these circuits has decreased dramatically so that many more of them can fit on the substrate. For example, an IC chip in a smart phone can be as small as a fingernail and yet may include over 2 billion transistors, the size of each transistor being less than 1 / 1, 000th the width of a human hair.

[0020] Making these ICs with extremely small structures or components is a complex, timeconsuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process, that is, to improve the overall yield of the process.

[0021] Yield is a metric that characterizes failure rate in device fabrication, which relates to cost and efficiency. Yield can be defined as a ratio of all the wafers that are produced by a fab to the number of wafers that were introduced to the fab. Or yield can be the number of working chips that survive the device fabrication process performed on a wafer to the number of potential chips that can be fabricated from that wafer in the ideal case of zero failure. As some wafers or chips fail during fabrication, the overall yield is less than 100%. For example, to obtain a 75% yield for a 50-step process (where a step can be indicative of the number of layers formed on a wafer), each individual step should have a yield greater than 99.4%. In contrast, if individual steps have a yield of 95%, the compounding errors at each step result in an overall process yield as low as 7-8%. Every wafer or chip lost during fabrication is a sunk cost and lost time for the fab.

[0022] Integral to the making of these ICs with extremely small structures are highly accurate inspection processes, performed in between one or more fabrication steps, to ascertain whether fabrication steps are performing at expected tolerances. Errors in even one step have the potential to result in defects in the finished IC, rendering it useless. A goal of the manufacturing process is to avoid such defects to maximize the number / yield of functional ICs made in the process.

[0023] Inspection can be carried out using a scanning charged-particle microscope (e.g., a scanning electron microscope (SEM)). A scanning charged-particle microscope can be used to image extremely small structures of ICs, by capturing an image of the structures on the wafer. The image can be used to determine if the structure was formed properly (e.g., having the expected dimensions and being properly located on the wafer). If the structure is defective, then the process can be adjusted, so the defect is less likely to recur.

[0024] The working principle of a SEM is analogous to that of a camera. A camera takes a picture by receiving and recording intensity of light reflected or emitted from people or objects. SEMs captureimages by receiving and recording energies or quantities of electrons reflected or emitted from the structures of the wafer. Similar to how a camera uses a light source (e.g., ambient, sunlight, or a flash), SEMs use an electron source to send a beam(s) of electron to a surface of a wafer that has structures of interest for imaging. The electron beam(s) can be deflected and the wafer can be moved (on a movement stage) so that a plurality of regions of the wafer can be irradiated by the electrons. When the electrons are reflected or emitted (“exiting”) from the structures (e.g., from the wafer surface, from the structures underneath the wafer surface, or both), a detector of the SEM can receive and record the energies or quantities of those electrons to generate an inspection image of the regions of the wafer that were irradiated by electrons.

[0025] Some SEMs use a single electron beam (referred to as a “single-beam SEM”) to capture a single image. Some SEMs use multiple electron beams (referred to as a “multibeam SEM”) to capture multiple sub-images of the wafer in parallel. The multiple sub-images can be viewed separately or stitched together to generate a complete image. Multibeam parallelization is a technique that increases the number of electrons being received at a detector, thereby increasing efficiency and speed of measurement.

[0026] Speed, or throughput, has been a traditionally important metric alongside yield. Throughput is a measurable quantity that characterizes the manufacture speed of a fab (e.g., number of IC units produced per unit time). Throughput has become even more important in view of recent global chip shortages. As there are multiple steps in the fabrication of a chip device (e.g., multiple steps for multiple layers), each step can have a characteristic throughput. For an inspection operation among the fabrication steps, throughput can characterize how quickly an inspection process can clear a wafer before moving on to the next wafer. Innovations in the design or functions of inspection tools can increase throughput, or at least resolve problems in another aspect while mitigating adverse impact to throughput.

[0027] There is a need to provide improved inspection tools to overcome limitations of the current state of the art and allow for faster and more efficient device fabrication cycles. Innovating IC architectures can involve making trade offs in next generation lithographic apparatus designs, as well as experimenting with new IC design layouts and varying exposure parameters. Lithographic apparatuses with high numerical aperture (NA) capability can achieve even smaller IC features, but pose a challenge in terms of filling an entire field on just one mask (multiple masks can be used, but alignment stitching become a concern). Achieving optimal design layouts and exposure parameters for a multi-image -per-field exposure can be a tedious and untenable process of trial, error, and inspection.

[0028] Some embodiments of the present disclosure provide a system and method for mapping lithography performance metrics to locations on a wafer based on exposure scenario. Mapping can be performed in an automated manner using design layout to wafer mapping techniques (e.g., die-to-database alignment). Multiple design layouts (for multiple reticle images as used in a single field) canbe merged and metrology information from a wafer measurement can be precisely mapped back to the design layout coordinates for in automated fashion. The manner in which the metrology information is labeled and presented to an IC innovator can greatly expedite and enhance the optimization of design layouts and exposure parameters for high-NA lithography systems.

[0029] Objects and advantages of the disclosure can be realized by the elements and combinations as set forth in embodiments described herein. However, embodiments of the present disclosure are not necessarily required to achieve such example objects or advantages. Some embodiments can achieve a different feature or enhancement without necessarily achieving any expressly stated object or advantage.

[0030] As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component can comprise A or B, then, unless specifically stated otherwise or infeasible, the component can comprise A, or B, or A and B. As a second example, if it is stated that a component can comprise A, B, or C, then, unless specifically stated otherwise or infeasible, the component can comprise A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0031] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described.

[0032] The term “patterning device” may be considered synonymous with similar terms of art, such as “reticle” or “mask.” The term “patterning device” used herein should be broadly interpreted as referring to any device that can be used to impart a pattern on a cross section of a radiation beam. The radiation beam then can recreate the pattern in a target portion of a substrate.

[0033] The term “projection system” used herein should be broadly interpreted as encompassing any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic, or electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, or for other factors such as the use of an immersion liquid or the use of a vacuum. Any use of the term “projection lens” herein may be considered as synonymous with the more general term “projection system.”

[0034] Illumination can be understood to be a form of radiation. Hence, the terms “radiation” and “illumination” can be used herein interchangeably.

[0035] FIG. 1 illustrates a schematic diagram of an example electron beam inspection (EBI) system 100, consistent with embodiments of the present disclosure. EBI system 100 can be used for imaging. EBI system 100 can comprise a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. Beam tool 104 can be located within main chamber 101. EFEM 106 can comprise a first loading port 106a and a second loading port 106b. EFEM 106 can comprise additional loading port(s). First loading port 106a and second loading port 106b can receivewafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). The term “lot” can refer to a plurality of wafers that can be loaded for processing as a batch.

[0036] One or more robotic arms (not shown) in EFEM 106 can transport the wafers to load / lock chamber 102. Load / lock chamber 102 can be connected to a load / lock vacuum pump system (not shown) that can evacuate gas molecules in load / lock chamber 102 to reach a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transport the wafer from load / lock chamber 102 to main chamber 101. Main chamber 101 can be connected to a main chamber vacuum pump system (not shown) that can evacuate gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer can be subject to inspection by beam tool 104. Beam tool 104 can be a singlebeam system or a multibeam system.

[0037] A controller 109 can be electronically connected to beam tool 104. Controller 109 can be a computer configured to execute various controls of EBI system 100. While controller 109 is shown in FIG. 1 as being outside of the structure that includes main chamber 101, load / lock chamber 102, and EFEM 106, in some embodiments, controller 109 can be part of the structure.

[0038] In some embodiments, controller 109 comprises one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor can comprise a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controllers, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), any type circuitry capable of data processing, or any combination of any number thereof. The processor can be a virtual processor. The virtual processor can include one or more processors distributed across multiple machines or devices coupled via a network.

[0039] In some embodiments, controller 109 further comprises one or more memories (not shown). A memory can be a generic or specific electronic device capable of storing instructions, code, or data accessible by the processor (e.g., via a bus). For example, the memory can comprise a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, any type of storage device, or any combination of any number thereof. The instructions, code, or data can include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory can be a virtual memory. The virtual memory can include one or more memories distributed across multiple machines or devices coupled via a network.

[0040] FIG.2 illustrates a schematic diagram of an example beam tool 104 and an image processing system 290 that can be configured for use in EBI system 100 (FIG. 1), consistent with embodiments of the present disclosure.

[0041] Beam tool 104 can be a multibeam device. Beam tool 104 can comprise a charged-particle source 202 configured to emit a primary charged-particle beam 210, a gun aperture 204, a condenser lens 206, a source conversion unit 212, a primary projection optical system 220, a motorized wafer stage 280, a wafer holder 282, a secondary optical system 242, and a charged-particle detection device 244. Primary charged-particle beam 210 can comprise a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210. Primary projection optical system 220 can comprise a beam separator 222, a deflection scanning unit 226, and an objective lens 228. Charged-particle detection device 244 can comprise detection sub-regions 246, 248, and 250.

[0042] Charged-particle source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 can be aligned with a primary optical axis 260 of beam tool 104. Secondary optical system 242 and charged-particle detection device 244 can be aligned with a secondary optical axis 252 of beam tool 104.

[0043] Charged-particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or other particle carrying electric charges. In some embodiments, charged-particle source 202 can be an electron source. For example, charged-particle source 202 can comprise a cathode, an extractor, or an anode. Primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged-particle beam 210 (in this case, a primary electron beam) with a crossover 208 (virtual or real crossover). For simplicity, some embodiments will be described in the context of electrons as the charged particles. However, it is to be appreciated that any charged particle can be used in any embodiment of this disclosure, not limited to electrons. Primary charged-particle beam 210 can be visualized as being emitted from crossover 208. Gun aperture 204 can block off peripheral charged particles of primary charged-particle beam 210 to reduce Coulomb interactions (or Coulomb effect). The Coulomb effect can cause the size of a probe spot (or beam spot) of an electron beam to increase and blur, thereby reducing resolution.

[0044] Source conversion unit 212 can comprise an array of image-forming elements and an array of beam-limit apertures. The array of image-forming elements can comprise an array of micro-deflectors or micro-lenses. The array of image-forming elements can form a plurality of parallel images (virtual or real) of crossover 208 with a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210. The array of beam-limit apertures can limit the plurality of beamlets 214, 216, and 218. While three beamlets 214, 216, and 218 are shown in FIG.2, embodiments of the present disclosure are not so limited. In some embodiments, beam tool 104 can be configured to generate a first number of beamlets. For example, the first number of beamlets can be in a range from 1 to 1000 or from 200-500. The first number of beamlets can be, for example, 400 beamlets.

[0045] Condenser lens 206 can focus primary charged-particle beam 210. The electric currents of beamlets 214, 216, and 218 downstream of source conversion unit 212 can be varied by adjusting the focusing power of condenser lens 206 or by changing the radial sizes of the corresponding beam-limit apertures within the array of beam-limit apertures. Condenser lens 206 may be an adjustable condenser lens that may be configured so that the position of its first principal plane is movable. The adjustable condenser lens may be configured to be magnetic, which may result in off-axis beamlets 216 and 218 landing on the beamlet-limit apertures with rotation angles. The rotation angles change with the focusing power and the position of the first principal plane of the adjustable condenser lens. In some embodiments, the adjustable condenser lens may be an adjustable anti-rotation condenser lens, which involves an anti-rotation lens with a movable first principal plane. An example of an adjustable condenser lens is further described in U.S. Publication No. 2017 / 0025241, which is incorporated by reference herein in its entirety.

[0046] Objective lens 228 can focus beamlets 214, 216, and 218 onto a wafer 230 for imaging, and can form a plurality of probe spots 270, 272, and 274 on a surface of wafer 230.

[0047] Beam separator 222 can be a beam separator of Wien filter type, generating an electrostatic dipole field and a magnetic dipole field. The force exerted by the electrostatic dipole field on a charged particle (e.g., an electron) of beamlets 214, 216, and 218 can be substantially equal in magnitude and opposite in a direction to the force exerted on the charged particle by magnetic dipole field. Beamlets 214, 216, and 218 can, therefore, pass straight through beam separator 222 with zero or minimal deflection angle. However, the total dispersion of beamlets 214, 216, and 218 generated by beam separator 222 can also be non-zero. Beam separator 222 can separate secondary charged-particle beams 236, 238, and 240 from beamlets 214, 216, and 218 and direct secondary charged-particle beams 236, 238, and 240 towards secondary optical system 242.

[0048] Deflection scanning unit 226 can deflect beamlets 214, 216, and 218 to scan probe spots 270, 272, and 274 over a surface area of wafer 230. In response to the incidence of beamlets 214, 216, and 218 at probe spots 270, 272, and 274, secondary charged-particle beams 236, 238, and 240 can be emitted from wafer 230. Secondary charged-particle beams 236, 238, and 240 can comprise charged particles (e.g., electrons) with a distribution of energies. For example, secondary charged-particle beams 236, 238, and 240 can be secondary electron beams including secondary electrons (energies < 50 eV) and backscattered electrons (energies between 50 eV and landing energies of beamlets 214, 216, and 218). Secondary optical system 242 can focus secondary charged-particle beams 236, 238, and 240 onto detection sub-regions 246, 248, and 250 of charged-particle detection device 244. Detection sub-regions 246, 248, and 250 can be configured to detect corresponding secondary charged-particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, or the like) used to reconstruct a scanning charged-particle microscope image (e.g., SEM image) of structures on or underneath the probed surface of wafer 230.

[0049] The generated signals can represent intensities of secondary charged-particle beams 236, 238, and 240 and can be provided to image processing system 290 that is in communication with charged-particle detection device 244, primary projection optical system 220, and motorized wafer stage 280. The movement speed of motorized wafer stage 280 can be synchronized and coordinated with the beam deflections controlled by deflection scanning unit 226, such that the movement of the scanning of probe spots (e.g., probe spots 270, 272, and 274) can orderly cover regions of interests on the wafer 230. The movement of the scanning can be, for example, a raster movement. The parameters of such synchronization and coordination can be adjusted to adapt to different materials of wafer 230. For example, different materials of wafer 230 can have different resistance-capacitance characteristics that can cause different signal sensitivities to the movement of the scanning of the probe spots.

[0050] The intensity of secondary charged-particle beams 236, 238, and 240 can vary according to the external or internal structure of wafer 230, and thus can indicate whether wafer 230 includes defects. Moreover, as discussed above, beamlets 214, 216, and 218 can be projected onto different locations of the top surface of wafer 230, or different sides of local structures of wafer 230, to generate secondary charged-particle beams 236, 238, and 240 that can have different intensities. Therefore, by mapping the intensity of secondary charged-particle beams 236, 238, and 240 with the areas of wafer 230, image processing system 290 can reconstruct an image that reflects the characteristics of internal or external structures of wafer 230.

[0051] In some embodiments, image processing system 290 can include an image acquirer 292, a storage 294, and a controller 296. Image acquirer 292 can comprise one or more processors. For example, image acquirer 292 can comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, or the like, or a combination thereof. Image acquirer 292 can be communicatively coupled to charged-particle detection device 244 of beam tool 104 through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. Image acquirer 292 can receive a signal from charged-particle detection device 244. Image acquirer 292 can construct an image (e.g., as a digital representation, an image data file) based on one or more signals from charged-particle detection device 244. Image acquirer 292 can thus acquire scanning charged-particle microscope images of probed regions of wafer 230. Image acquirer 292 can perform various postprocessing functions, such as generating contours that are representative of structures in the image, superimposing indicators on an acquired image, or the like. Image acquirer 292 can perform adjustments of brightness and contrast of acquired images.

[0052] In some embodiments, storage 294 is a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable memory, or the like. Storage 294 can be coupled with image acquirer 292. Storage 294 can be used for saving scanned raw image data as original images, as well as post-processed images. Image acquirer 292 and storage 294can be connected to controller 296. Image acquirer 292, storage 294, and controller 296 can be integrated together as one control unit.

[0053] In some embodiments, image acquirer 292 acquires one or more scanning charged-particle microscope images of a wafer based on one or more imaging signals received from charged-particle detection device 244. An imaging signal can correspond to a scanning operation for conducting charged-particle imaging. An acquired image can be a single image comprising a plurality of imaging areas or an image of an imaging area. The single image can be stored in storage 294. The single image can be an original image that is divided into a plurality of regions. Each of the regions can comprise one imaging area containing a feature of wafer 230. The acquired images can comprise multiple images of a single imaging area of wafer 230 sampled multiple times over a time sequence. The multiple images can be stored in storage 294. In some embodiments, image processing system 290 performs image processing steps with the multiple images of the same location of wafer 230.

[0054] In some embodiments, image processing system 290 comprises measurement circuits (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary charged particles (e.g., secondary electrons). The charged-particle distribution data collected during a detection time window, in combination with corresponding scan path data of beamlets 214, 216, and 218 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 230, and thereby can be used to reveal defects in the wafer.

[0055] In some embodiments, when electrons of primary charged-particle beam 210 are projected onto a surface of wafer 230 (e.g., probe spots 270, 272, and 274), the electrons of primary charged-particle beam 210 can penetrate the surface of wafer 230 for a certain depth to interact with deeper matter in wafer 230. Some electrons of primary charged-particle beam 210 can elastically interact with (e.g., in the form of elastic scattering or collision) the materials of wafer 230. Electrons can be reflected or recoiled out of the surface of wafer 230. An elastic interaction conserves the total kinetic energies of the bodies (e.g., electrons of primary charged-particle beam 210) of the interaction, in which the kinetic energy of the interacting bodies does not convert to other forms of energy (e.g., heat, electromagnetic energy, or the like). Such reflected electrons generated from elastic interaction may be referred to as backscattered electrons (BSEs).

[0056] In some embodiments, some electrons of primary charged-particle beam 210 inelastically interact with (e.g., in the form of inelastic scattering or collision) the materials of wafer 230. An inelastic interaction does not conserve the total kinetic energies of the bodies of the interaction, in which some or all of the kinetic energy of the interacting bodies convert to other forms of energy. For example, through the inelastic interaction, the kinetic energy of some electrons of primary charged-particle beam 210 can cause electron excitation and transition of atoms of the materials. Such inelastic interaction can also generate electrons that exit the surface of wafer 230, which may be referred to as secondary electrons (SEs). Yield or emission rates of BSEs and SEs can depend on, e.g., the materialunder inspection and the landing energy of the electrons of primary charged-particle beam 210 landing on the surface of the material, among others. The energy of the electrons of primary charged-particle beam 210 can be imparted in part by its acceleration voltage (e.g., the acceleration voltage between the anode and cathode of charged-particle source 202 in FIG.2). The quantity of BSEs and SEs can be more or fewer (or even the same) than the injected electrons of primary charged-particle beam 210.

[0057] An image can be in the form of an analog signal (e.g., detector signals from an SEM).Alternatively, or additionally, an image can have a digital form, which can be stored as a digital file, reside in volatile memory, be transmitted as a digital signal, or the like. When describing image analysis, image manipulation, and other image processes, it is to be appreciated that such processes can be executed on any form or representation of the image. For example, cropping an image can correspond to truncating the corresponding pixels in a digital image file.

[0058] The images generated by SEM can be used for defect inspection. For example, a generated image of a test device region of a wafer can be compared with a reference image that corresponds to the same test device region. The reference image can be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect can be identified. For another example, the SEM can scan multiple regions of the wafer, each region including a test device region designed as the same, and generate multiple images capturing those test device regions as manufactured. The multiple images can be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect can be identified.

[0059] In some embodiments, charged particle implementations described herein can be modified to use photons instead, for example, such as light in the visible, UV, DUV, EUV, x-ray, or any other wavelength range. For example, in a photon embodiment, a secondary beam spot can refer to reflected, refracted, diffracted or scattered light from a sample upon which a primary light beam is incident. Therefore, while detectors in the present disclosure may be described in the context of electron detection, some embodiments of the present disclosure can be directed to detecting other charged particles or photons.

[0060] Inspection tool like the ones in FIGS. 1 and 2 can be used to inspect the results of a lithography fabrication process, thereby generating metrology information or data. Collection, analysis, labeling, and presentation of the metrology information can be a slow and costly process.

[0061] FIG. 3 shows an example set of wafer field arrangements 300, consistent with embodiments of the present disclosure. In some embodiments, a single-image exposure scenario involves a full field 302, a reticle image 304, and a plurality of dies 306. Full field 302 can be one of a plurality of fields on a wafer. A wafer can be apportioned according to an array of fields (e.g., a 300 mm diameter wafer can be apportioned using an array of 25 mm x 25 mm fields). Reticle image 304 can comprise patterns for plurality of dies 306. Plurality of dies 306 can be arranged as an array within full field302. The illustrated example shows a 4x3, but any suitable arrangement can be used based on die size (e.g., 1x1, 2x1, 2x2, or the like). The area of reticle image 304 can fill the area of full field 302 (e.g., approximately complete or substantial fill). Each of dies 306 can be characterized by a reference position 308 (e.g., a center position of the die).

[0062] In this manner, a single reticle image can be used to expose a single field (e.g., a one-to-one correspondence). The one-to-one image-to-field arrangement can be suitable for low-NA lithography systems, which are constrained in terms of demagnification. For example, optical hardware limitations of low-NA systems can prevent the shrinking of a reticle image beyond a certain size. In the scenario of full field 302, the each die 306 can be printed in a single exposure operation without having to split the dies into smaller sections (which precludes the use of stitching). In lithography, stitching is a technique that involves splitting a design into smaller sections and aligning the smaller sections during exposure. Stitched patterns can involve very precise alignments, which increases the risk of printing error. Regions of a field or die where stitching is involved can instigate higher scrutiny or otherwise be of greater interest during quality control.

[0063] In some embodiments, a multi-image exposure scenario (e.g., a second scenario) involves a field 310, a reticle image 312, a plurality of dies 314, and a plurality of dies 314'. Full field 310 can be one of a plurality of fields on a wafer. Reticle image 312 can comprise patterns for plurality of dies 314. Plurality of dies 314 can be arranged as an array within full field 310. The illustrated example shows a 2x3, but any suitable arrangement can be used based on die size (e.g., 1x1, 2x1, 2x2, or the like). Reticle image 312 can be associated with a high-NA lithography system (e.g., provides more powerful demagnification). Hence, the area of reticle image 312 can fail to fill the area of full field 310. In the multi-image exposure scenario of full field 310, reticle image 312 can be used again to expose the remaining area of full field 310. Plurality of dies 314' represent the second set of dies that result from reusing reticle image 312 in the same field. Plurality of dies 314' can be arranged as an array within full field 310. The illustrated example shows a 2x3 arrangement, but any suitable arrangement can be used based on die size (e.g., 1x1, 2x1, 2x2, or the like).

[0064] A line 316 is used to indicate exposure of a top half of field 308 and a bottom half of field 308 using the same reticle image 312. The relative alignments of the two exposures of reticle image 312 can be characterized by reference positions 318 and 318’ (e.g., center positions of reticle image alignments).

[0065] In this manner, a single reticle image can be used multiple times to expose a single field (e.g., a multiple images to one field correspondence). High-NA lithography systems can have hardware limitations that can impose a maximum reticle image size. For example, optical hardware limitations of high-NA systems allow for more demagnification to achieve smaller device features, but also prevent the use of larger masks (e.g., reticles). It can be difficult to fill the empty space of field 308 that arises from more powerful demagnification. In the multi-image exposure scenario of full field 310, pluralities of dies 314 and 314' can be arranged such that the each of the dies is printed in asingle exposure operation without having to split the dies into smaller sections, thereby avoiding stitching.

[0066] In some embodiments, a multi-image exposure scenario (e.g., a second scenario) involves a full field 320, a reticle image 322, a plurality of dies 324, a reticle image 326, and a plurality of dies 328 (diagonal crosshatch fill). Full field 320 can be one of a plurality of fields on a wafer. Reticle image 322 can comprise patterns for plurality of dies 324. Plurality of dies 324 can be arranged as an array within full field 320. The illustrated example shows a 4x3 arrangement, but any suitable arrangement can be used based on die size (e.g., 1x1, 2x1, 2x2, or the like). Reticle image 322 can be associated with a high-NA lithography system. Hence, the area of reticle image 322 can fail to fill the area of full field 320. In the multi-image exposure scenario of full field 320, reticle image 326 can be used to expose the remaining area of full field 320. The device patterns of reticle image 326 can be different from the device patterns of reticle image 322. Plurality of dies 328 represent the second set of dies that result from using reticle image 326 in the same field. Plurality of dies 328 can be arranged as an array within full field 320. The illustrated example shows a 2x3 arrangement, but any suitable arrangement can be used based on die size (e.g., 1x1, 2x1, 2x2, or the like).

[0067] The relative alignments of the two exposures of reticle image 322 and reticle image 326 can be characterized by reference positions 330 and 332, respectively (e.g., center positions of reticle image alignments).

[0068] In this manner, multiple reticle images can be used to expose a single field. In the multiimage exposure scenario of full field 320, pluralities of dies 324 and 328 can be arranged such that the each of the dies can be printed in a single exposure operation without having to split the dies into smaller sections, thereby avoiding stitching.

[0069] In some embodiments, a multi-image exposure scenario (e.g., a third scenario) involves a full field 334, a reticle image 336 and a reticle image 338. Full field 334 can be one of a plurality of fields on a wafer. Reticle image 336 can comprise patterns for a plurality of complete dies 340 and patterns for a plurality of portions 342 (checker crosshatch fill) of a plurality of dies 344. The plurality of dies 340 and plurality of portions 342 can be arranged as an array within full field 334. Any suitable arrangement of dies can be used based on die size. Reticle image 336 can be associated with a high-NA lithography system. Hence, the area of reticle image 336 can fail to fill the area of full field 334.

[0070] Moreover, limitations of the high-NA lithography system can impose a limit on the maximum size of a physical reticle. Certain IC designs can demand inconvenient die sizes (e.g., die 340 is one such example). The physical restrictions of the high-NA systems and IC design limitations can create a situation where a chip manufacturer is forced to choose between either making a smaller reticle image to exactly fit the number of dies (inefficient exposure time, slower throughput) or to split a die design into smaller sections to maximize reticle image area but also introduce a higher risk of printing error when the die sections are stitched together. In the multi-image exposure scenario of full field 334, stitching is chosen.

[0071] Reticle image 338 can be used to expose the remaining area of full field 334. Reticle image 338 can differ from reticle image 336 in that reticle image 338 can comprise patterns for the missing portions 346 (diagonal crosshatch fill) of plurality of dies 344, as well as patterns for a plurality of complete dies 348. Plurality of dies 348 and plurality of portions 346 can be arranged as an array within full field 334. Any suitable arrangement of dies can be used based on die size.

[0072] The relative alignments of the two exposures of reticle image 336 and reticle image 338 can be characterized by reference positions 350 and 352, respectively (e.g., center positions of reticle image alignments). Precise alignment techniques can be used to stitch each portion to a corresponding portion 346, thereby completing the plurality of dies 344. Stitching region 354 indicates where portions 342 and 346 come together. In this manner, multiple reticle images can be stitched when exposing a single field. Stitching region 354 can be a high risk error area that could trigger additional metrology scrutiny.

[0073] The scenarios described above for fields 302, 310, 320, and 334 can have different error risk factors that affect the choice of post-exposure metrology. IC manufacturers are continually innovating chip architectures. Different architectures can fall into different ones of the scenarios described above (e.g., for fields 302, 310, 320, and 334). It is inconvenient, time consuming, and costly for IC manufacturers to manually map lithography performance metrics (e.g., error metrics) based on different reticle image scenarios. Hence, some embodiments of the present disclosure allow automatic mapping of lithography performance metrics to corresponding portions of a field based on exposure arrangements inferred from an exposure lot report used by a lithographic apparatus.

[0074] FIG.4 shows a flowchart of an example process flow 400 for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments of the present disclosure. The process flow can be executed using devices and functions described in reference to FIGS. 1-3 (e.g., as controller 109 (FIG. 1), image processing system 290 (FIG.2), or the like).

[0075] In some embodiments, operation 402 can comprise determining whether a wafer exposure process will use multiple reticle images to expose a field of a wafer. An example wafer 404 is illustrated as an inset. The determination can be performed by an algorithm that can receive, as input, information about exposure operations performed by a lithographic apparatus. For example, the lithographic apparatus can expose a plurality of fields on wafer 404 using one or more reticle images 406 and 408 (diagonal crosshatch fill). The apportionment of each reticle image on wafer 404 is performed according to a predetermined grid (e.g., user preference or user instructions). The reticle image apportionment information, or exposure lot information (e.g., exposure lot report from a lithographic scanner), can be received by the algorithm, which then analyzes the exposure lot information to determine whether the exposure process involves exposing a single field of wafer 404 using multiple reticle images (e.g., as in exposure scenarios for fields 310, 320, or 334 (FIG.3)). The return values of operation 402 can be true or false, yes or no, or the like.

[0076] Based on determining that the field was configured to be exposed with the multiple reticle images (e.g., return value is “yes”), operation 410 can comprise determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field. The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field. The plurality of exposure scenarios can comprise multi-image scenarios 412, 414, and 416. Multi-image scenario 412 (e.g., a first scenario) can correspond to the scenario of full field 310 of FIG.3 (e.g., a single reticle image used multiple times in one field, no stitching). Multi-image scenario 414 (e.g., a second scenario) can correspond to the scenario of full field 320 of FIG. 3 (e.g., multiple reticles images used in one field, no stitching). Multi-image scenario 416 (e.g., a third scenario) can correspond to the scenario of full field 334 of FIG. 3 (e.g., multiple reticle images used in one field with stitching).

[0077] At operation 418, a lithography performance metric can be obtained from a measurement of exposed patterns at the field. When an exposure process concludes and patterns are subsequently etched, the fabrication results can be checked using a measurement tool (e.g., SEM or scanning charged-particle microscope described in reference to FIGS. 1 and 2). A lithography performance metric can be any property that helps quantify the quality of lithographic fabrication. For example, the lithography performance metric can be a critical dimension (CD) of the patterns associated with reticle images 406 or 408. Other examples of lithography performance metrics include edge placement error (EPE), defect count or density, overlay error, or the like.

[0078] At operation 420, the one or more lithography performance metrics can be automatically mapped to locations of the field (e.g., mapped to the first location and the second location of the field). For example, values for a CD can be ascertained at operation 418. A CD value can be mapped to stitching region 354 (FIG. 3) if the determined exposure scenario at operation 410 is multi-image scenario 416. Exposure parameters can also be mapped to the field locations (e.g., focus, dose, or the like). The automatic mapping of lithography performance metrics can be achieved by using an image coordinate alignment technique (e.g., Die-to-Database (D2DB) alignment), which can align a design layout associated with a reticle image to the inspection measurement used in operation 418. The design layout can be provided in the form of a layout file. The layout file can be in a Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, an Open Artwork System Interchange Standard (OASIS) format, a Caltech Intermediate Format (CIF), or the like. Additional details of data mapping will be explained below in reference to FIG.5.

[0079] In some embodiments, if operation 402 returns a false result, process flow 400 proceeds with single-image scenario 422, which can correspond to the scenario of full field 302 (e.g., one-to-one image-to-field arrangement).

[0080] At operation 424, exposure parameters can be mapped to the fields of wafer 404 (e.g., fullfield map) based on single-image scenario 422. The exposure parameters can be obtained from the exposure lot information introduced at operation 402. In other words, a full-field map of wafer 404can be generated in which focus, dose, and other exposure parameters are associated with locations on wafer 404.

[0081] At operation 426 a design layout for the single reticle image can be obtained (e.g., from a GDS file).

[0082] At operation 428, one or more lithography performance metrics can be obtained from a measurement of exposed patterns at the field. Operation 428 can be performed using the functions described in reference to operation 418.

[0083] At operation 430, the one or more lithography performance metrics can be automatically mapped to locations of fields on wafer 404 using the design layout information obtained at operation 426. The one or more lithography performance metrics mapping information can be combined with the full-field map of exposure parameters determined at operation 424. Operation 430 can be performed using the functions described in reference to operation 420 and one or more functions described in reference to FIG.5 (e.g., D2DB).

[0084] FIG. 5 shows a flowchart of an example process flow 500 for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments of the present disclosure. The process flow can be executed using devices and functions described in reference to FIGS. 1-4 (e.g., as controller 109 (FIG. 1), image processing system 290 (FIG. 2), or the like). In some embodiments, process flow 500 can represent a more detailed view of operations 418 and 420 of FIG. 4.

[0085] Process flow 500 can be executed based on a determined multi-image scenario 502 (e.g., one of the exposure scenarios determined at operation 410 (FIG. 4)).

[0086] At operation 504, a full-field size or stitching region size can be determined (e.g., a size of stitching region 354 (FIG.4)). The full-field size or stitching region size can be determined based on exposure lot information or user input. Knowing the full-field or stitching region size is useful for determining how many fields can fit on a wafer (e.g., wafer 404 (FIG.4)).

[0087] At operation 506, a full-field map on the wafer can be determined based on the full-field size or stitching region size determined at operation 504. Wafer 404 (FIG. 4) is an illustration of a fullfield wafer map, of which the relative positions of each reticle image is provided. In generating the full-field map on the wafer, exposure parameters used by the exposure apparatus can be tagged or associated to positions on the wafer. For example, reticle image 406 (FIG. 4) is exposed using a first dose setting and a first focus setting, while reticle image 408 (FIG. 4) is exposed using a second dose and a second focus setting. A significance of the full-field map is that it can act as a coordinate system that informs how and where each device feature is printed on the wafer.

[0088] It is noted that image information can be represented in several forms. For example, a graphical representation of an image (e.g., displayed at a display device) can also be represented as digital data (e.g., saved as a file in memory). An analog representation can be in the form of electrical signals that convey the image information. The present disclosure can refer to generating, analyzing,or processing of images. Image-related functions and operations described herein can be performed with respect to any representation of an image (e.g., graphical, electrical signal, binary data, or the like). For example, generating a map, design layout, or other image information can refer to generating an actual graphical representation of the image information or generating a binary-data representation of the image information that can be read and processed by a computing device.

[0089] In some embodiments, at operation 508, one or more design layouts of the reticle images can be obtained (e.g., from GDS files). A single design layout can be obtained if a single reticle image is used multiple times in a field (e.g., multi-image scenario 412 (FIG.4)). A plurality of design layouts can be obtained if multiple reticle images are used in a field (e.g., multi-image scenarios 414 or 416 (FIG. 4)).

[0090] At operation 510, it can be determined whether design layouts are to be combined. The return values of operation 510 can be true or false, yes or no, or the like. The determination can be made based on analysis of a exposure lot information (e.g., the same exposure lot information analyzed at operation 402 (FIG. 4)). Combining design layouts can be useful for exposures that involve stitching.

[0091] Based on determining that the design layouts are to be combined (e.g., return value of operation 510 is “yes”), operation 504' can execute to determine a full field size or stitching region size (e.g., a size of stitching region 354 (FIG.4)). Operation 504' can be the same as operation 504, in which case operation 504' can be modified to use the results operation 504 (or vice versa) rather than performing a redundant operation.

[0092] At operation 512, a full-field design layout can be determined based on the determined full field size or stitching region size from operation 504'. Even though the coordinate systems of multiple design layouts are initially unrelated, operation 512 can provide a combined coordinate system for the combined patterns of multiple reticle images in the field (e.g., generates a combined GDS coordinate system).

[0093] Based on determining that the design layouts are not to be combined (e.g., return value of operation 510 is “no”), operation 512 can proceed to determine the full-field design layout without the information from operation 504'.

[0094] The described processes so far can provide information about where each device feature is positioned in a field (e.g., from combined design layout coordinates of operation 512) and where each of those device features are disposed on a wafer (e.g., from the full-field map of operation 506). To automatically map lithography performance metrics to the wafer, a measurement of the fabricated device features can be obtained (e.g., SEM or scanning charged-particle microscope described in reference to FIGS. 1 and 2). The measurement can be performed by instructing the inspection tool on which dies on the wafer to inspect. Hence, the measurement can be tagged or associated with wafer position information (e.g., die coordinates).

[0095] In some embodiments, at operation 514, one or more lithography performance metrics are obtained from inspection measurements of one or more locations on the wafer (e.g., performed afterexposure to check results). The one or more lithography performance metrics can be tagged based on which location of the wafer the measurement was taken. For example, a stitching region of an zthdie on the wafer can be inspected. A measurement of the die can include measurement of defect count. The measurement can be focused on a specific region of the die (e.g., a stitching region).

[0096] At operation 516, measured features from the inspection measurements (e.g., from SEM images) can be aligned relative to the full-field map coordinates established using operations 506 and 512. As an example, the alignment can be performed using a D2DB alignment, which can be performed in an automated manner (e.g., a process similar or analogous to machine vision for identifying features in an image). The one or more lithography performance metrics can then be assigned to specific locations of the full-field map coordinates.

[0097] Innovating IC architectures can involve experimenting with new design layouts and varying exposure parameters. Experimental trials can yield errors. The manner in which the error information is labeled and presented to the innovator can greatly expedite and enhance subsequent tuning of exposure parameters. Hence, at operation 518, the one or more mapped lithography performance metrics can be labeled and organized according to exposure parameters, the reticle image used, field region, or the like. The labeling can be achieved by tagging or associating the exposure parameters, the reticle image used, field region, or the like, to corresponding ones of the one or more lithography performance parameters (e.g., via generating metadata).

[0098] As an example of metrics labeling and organization, table 520 is provided in FIG.5. In the table, the field ID denotes a given field on the wafer, focus and dose are exposure parameters (arbitrary units) for a given reticle image used in the field, CD indicates a critical dimension (arbitrary units) (any lithography performance metric can be used), and Expo_Image indicates a location in the field with respect to the reticle image that was used. In this example, two reticle images (ret_image A and ret_image B) were used in field 1, which also includes a stitching region. If the lithography performance metric shows detriment in a given region for a given set of exposure parameters, potential solutions for problem regions can be achieved more efficiently (e.g., by tuning parameters, tuning alignments, or the like), thereby saving time and resources in innovation cycles.

[0099] FIG.6 shows a flowchart of a method 600 for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments of the present disclosure. The method can be executed using devices and functions described in reference to FIGS. 1-5 (e.g., as controller 109 (FIG. 1), image processing system 290 (FIG. 2), or the like).

[0100] In some embodiments, at operation 602, it is determined whether a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer (e.g., whether a full field 302, 310, 320, or 334 of wafer 404 is exposed using reticle images 304, 312, 322, 326, 336, 338, 406, or 408 (FIGS.3 and 4)).

[0101] At operation 604, based on determining that the wafer exposure process is configured to use the multiple reticle images, it can be determined that an exposure scenario from among a plurality ofexposure scenarios matches an arrangement of the multiple reticle images in the field (e.g., determine which of multi-image scenarios 412, 414, or 416 match the arrangement of the reticle images (FIG.4)). The determined exposure scenario can comprise a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field (e.g., multi-image scenario 416 can comprise reticle image 336 disposed at a first location of full field 334 and a reticle image 338 disposed at a second location of full field 334, with stitching region 354 therebetween).

[0102] At operation 606, one or more lithography performance metrics can be determined based on a measurement of exposed patterns at the field. Post-exposure results can be checked using a measurement tool (e.g., SEM or scanning charged-particle microscope described in reference to FIGS. 1 and 2). The measurement can be analyzed with respect to CD, EPE, defect count, or the like.

[0103] At operation 608, the one or more lithography performance metrics can be mapped to the first location and the second location based on the determined exposure scenario. The mapping can be performed using a D2DB alignment of an inspection image as described in reference to operation 516 (FIG. 5). Automatic mapping of lithography performance metrics to potential problem regions of a field can provide insightful error information to IC designers and manufacturers.

[0104] FIG.7A shows a system of apparatuses used for lithographic fabrication, consistent with embodiments of the present disclosure. In some embodiments, the system can comprise a lithographic projection apparatus 701, a metrology apparatus 702, and a controller 703. Lithographic projection apparatus 701 can form structures on a wafer according to prescribed lithographic processing conditions (e.g., a focus and dose for a radiation source). Metrology apparatus 702 can perform measurements and obtain metrology information of the formed on the wafer. Metrology information can comprise, but is not limited to, critical dimension, edge placement, and overlay. Controller 703 with a memory can be communicatively connected to metrology apparatus 702 to store the obtained metrology information. Controller 703 can be a computing device that is separate or modular with respect to (e.g., a personal computer) lithographic projection apparatus 701 and metrology apparatus 702. Or controller 703 can be part of lithographic projection apparatus 701 or metrology apparatus 702 (e.g., controller 109 or image processing system 290 (FIGS. 1 and 2)).

[0105] Controller 703 can be a generic or specific electronic device capable of manipulating or processing information. Controller 703 can comprise any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (or “NPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. Controller 703 can also be a virtual processor that comprises one or more processors distributed across multiple machines or devices coupled via a network.

[0106] Controller 703 can further comprise one or more memories (not shown). A memory can be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). The memory can comprise any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes and data can comprise an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory can also be a virtual memory that comprises one or more memories distributed across multiple machines or devices coupled via a network.

[0107] FIG.7B shows an example computing system 704 for performing one or more operations of the process flows or methods disclosed herein, consistent with embodiments of the present disclosure. In some embodiments, computing system 704 can comprise a memory 706 storing a set of instructions and at least one processor 705 configured to execute the set of instructions to cause computing system 704 to perform operations or manipulations on data for processing. Computing system 704 can comprise processor 705. When processor 705 executes instructions described herein, computing system 704 can become a specialized machine for preprocessing, encoding, or decoding image data. Processor 705 can be any type of circuitry capable of manipulating or processing information. For example, processor 705 can comprise any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (“NPU”), a microcontroller unit (“MCU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. Processor 705 can also be a set of processors grouped as a single logical component. For example, processor 705 can comprise multiple processors, including a processor 705a, a processor 705b, and so on up to a processor 705n (e.g., two or more processors).

[0108] Memory 706 can store data (e.g., a set of instructions, computer codes, intermediate data, or the like). The stored data can include program instructions (e.g., program instructions for calibrating a tuning engine) and data for processing (e.g., metrology data). Processor 705 can access the program instructions and data for processing (e.g., via bus 707), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory 706 can comprise a highspeed random-access storage device or a non-volatile storage device. In some embodiments, memory 706 can comprise any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 706 can also be a group of memories (not shown in FIG.7B) grouped as a single logical component.

[0109] Bus 707 can be a communication device that transfers data between components included in computing system 704, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0110] For ease of explanation without causing ambiguity, processor 705 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of computing system 704.

[0111] Computing system 704 can further comprise a network interface 708 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 708 can comprise any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0112] In some embodiments, optionally, computing system 704 can further comprise peripheral interface 709 to provide a connection to one or more peripheral devices. The peripheral device can comprise, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), an input device (e.g., a computing device), or the like.

[0113] A non-transitory computer-readable medium can be provided for storing instructions for a processor of a controller (e.g., controller 109, image processing system 290, or controller 703 (FIGS.1, 2, and 7)) for mapping lithography performance to locations on a wafer based on exposure scenario, consistent with embodiments in the present disclosure. For example, the instructions stored in the non-transitory computer-readable medium can be executed by the circuitry of the controller for performing process flow 400, process flow 500, or method 600 in part or entirely. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read-Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), a Field Programmable Gate Array (FPGA), and Erasable Programmable Read-Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0114] Some embodiments can further be described using the following clauses:1. A non-transitory computer-readable medium that stores a set of instructions that is executable by at least one processor of an apparatus to cause the apparatus to perform operations, the operations comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.2. The non-transitory computer-readable medium of clause 1, wherein the operations further comprise:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.3. The non-transitory computer-readable medium of clauses 1 or 2, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.4. The non-transitory computer-readable medium of any one of clauses 1 to 3, wherein the operations further comprise:determining a size of the field based on the arrangement of the multiple reticle images in the field.5. The non-transitory computer-readable medium of any one of clauses 1 to 4, the operations further comprising:determining a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.6. The non-transitory computer-readable medium of any one of clauses 1 to 5, wherein the operations further comprise:generating a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.7. The non-transitory computer-readable medium of clause 6, wherein the operations further comprise:performing a die-to-database alignment using the measurement of the exposed patterns and the combined design layout.8. The non- transitory computer-readable medium of any one of clauses 1 to 7, wherein the operations further comprise:labeling the one or more lithography performance metrics according to exposure parameters and based on the mapping of the one or more lithography performance metrics to the first location and the second location.9. The non-transitory computer-readable medium of clause 8, wherein the operations further comprise:tabulating the labeled one or more lithography performance metrics according to exposure parameters and mapped location on the wafer.10. The non-transitory computer-readable medium of any one of clauses 1 to 9, wherein the operations further comprise:determining whether the wafer exposure process is configured to use a single reticle image to expose the field;based on determining that the wafer exposure process is configured to use the single reticle image, mapping the one or more lithography performance metrics to locations of the field.11. A system comprising:one or more processors; andone or more memory devices configured to store a set of instructions that is executable by the one or more processors to cause the system to perform operations, the operations comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.12. The system of clause 11, wherein the operations further comprise:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.13. The system of clauses 11 or 12, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.14. The system of any one of clauses 11 to 13, wherein the operations further comprise:determining a size of the field based on the arrangement of the multiple reticle images in the field.15. The system of any one of clauses 11 to 14, wherein the operations further comprise:determining a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.16. The system of any one of clauses 11 to 15, wherein the operations further comprise:generating a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.17. The system of clause 16, wherein the operations further comprise:performing a die-to-database alignment using the measurement of the exposed patterns and the combined design layout.18. The system of any one of clauses 11 to 17, wherein the operations further comprise:labeling the one or more lithography performance metrics according to exposure parameters and based on the mapping of the one or more lithography performance metrics to the first location and the second location.19. The system of clause 18, wherein the operations further comprise:tabulating the labeled one or more lithography performance metrics according to exposure parameters and mapped location on the wafer.20. The system of any one of clauses 11 to 19, wherein the operations further comprise:determining whether the wafer exposure process is configured to use a single reticle image to expose the field; andbased on determining that the wafer exposure process is configured to use the single reticle image, mapping the one or more lithography performance metrics to locations of the field.21. The system of any one of clauses 11 to 20, wherein the controller is part of the lithographic apparatus, part of the metrology apparatus, or part of an apparatus different from the lithographic apparatus and the metrology apparatus.22. A system comprising:a lithographic apparatus configured to expose a wafer according to a wafer exposure process; a metrology apparatus configured to take measurements of the wafer for ascertaining a quality of the wafer exposure process; anda controller comprising circuitry and configured to:based on a determination that the wafer exposure process is configured to use multiple reticle images to expose a field of the wafer, determine which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determine one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmap the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.23. The system of clause 22, wherein the controller is further configured to analyze exposure lot data used by the lithographic apparatus to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.24. The system of any one of clauses 22 or 23, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.25. The system of any one of clauses 22 to 24, wherein the controller is further configured to:determine a size of the field based on the arrangement of the multiple reticle images in the field.26. The system of any one of clauses 22 to 25, wherein the controller is further configured to determine a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.27. The system of any one of clauses 22 to 26, wherein the controller is further configured to generate a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.28. The system of clause 27, wherein the controller is further configured to perform a die-to-database alignment using the measurement of the exposed patterns and the combined design layout.29. The system of any one of clauses 22 to 28, wherein the controller is further configured to label the one or more lithography performance metrics according to exposure parameters and based on the mapping of the one or more lithography performance metrics to the first location and the second location.30. The system of clause 29, wherein the controller is further configured to tabulate the labeled one or more lithography performance metrics according to exposure parameters and mapped location on the wafer.31. The system of any one of clauses 22 to 30, wherein the controller is further configured to:determine whether the wafer exposure process is configured to use a single reticle image to expose the field; andbased on a determination that the wafer exposure process is configured to use the single reticle image, map the one or more lithography performance metrics to locations of the field.32. A method comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.33. The method of clause 32, wherein the operations further comprise:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.34. The method of clauses 32 or 33, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.35. The method of any one of clauses 32 to 34, further comprising:determining a size of the field based on the arrangement of the multiple reticle images in the field.36. The method of any one of clauses 32 to 35, further comprising:determining a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.37. The method of any one of clauses 32 to 36, further comprising:generating a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.38. The method of clause 37, further comprising:performing a die-to-database alignment using the measurement of the exposed patterns and the combined design layout.39. The method of any one of clauses 32 to 38, further comprising:labeling the one or more lithography performance metrics according to exposure parameters and based on the mapping of the one or more lithography performance metrics to the first location and the second location.40. The method of clause 39, further comprising:tabulating the labeled one or more lithography performance metrics according to exposure parameters and mapped location on the wafer.41. The method of any one of clauses 32 to 40, further comprising:determining whether the wafer exposure process is configured to use a single reticle image to expose the field;based on determining that the wafer exposure process is configured to use the single reticle image, mapping the one or more lithography performance metrics to locations of the field.

[0115] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings and that various modifications and changes may be made without departing from the scope thereof.

Claims

CLAIMS1. A non-transitory computer-readable medium that stores a set of instructions that is executable by at least one processor of an apparatus to cause the apparatus to perform operations, the operations comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

2. The non-transitory computer-readable medium of claim 1, wherein the operations further comprise:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.

3. The non-transitory computer-readable medium of claim 1, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.

4. The non-transitory computer-readable medium of claim 1, wherein the operations further comprise:determining a size of the field based on the arrangement of the multiple reticle images in the field.

5. The non-transitory computer-readable medium of claim 1, the operations further comprising: determining a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.

6. The non-transitory computer-readable medium of claim 1, wherein the operations further comprise:generating a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.

7. The non-transitory computer-readable medium of claim 6, wherein the operations further comprise:performing a die-to-database alignment using the measurement of the exposed patterns and the combined design layout.

8. The non-transitory computer-readable medium of claim 1, wherein the operations further comprise:labeling the one or more lithography performance metrics according to exposure parameters and based on the mapping of the one or more lithography performance metrics to the first location and the second location.

9. The non-transitory computer-readable medium of claim 8, wherein the operations further comprise:tabulating the labeled one or more lithography performance metrics according to exposure parameters and mapped location on the wafer.

10. The non-transitory computer-readable medium of claim 1, wherein the operations further comprise:determining whether the wafer exposure process is configured to use a single reticle image to expose the field;based on determining that the wafer exposure process is configured to use the single reticle image, mapping the one or more lithography performance metrics to locations of the field.

11. A system comprising:one or more processors; andone or more memory devices configured to store a set of instructions that is executable by the one or more processors to cause the system to perform operations, the operations comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field,wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

12. The system of claim 11, wherein the operations further comprise:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.

13. The system of claim 11, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.

14. The system of claim 11, wherein the operations further comprise:determining a size of the field based on the arrangement of the multiple reticle images in the field.

15. A method comprising:based on a determination that a wafer exposure process is configured to use multiple reticle images to expose a field of a wafer, determining which exposure scenario, from among a plurality of exposure scenarios, matches an arrangement of the multiple reticle images in the field, wherein the determined exposure scenario comprises a first reticle image disposed at a first location of the field and a second reticle image disposed at a second location of the field;determining one or more lithography performance metrics based on a measurement of exposed patterns at the field; andmapping the one or more lithography performance metrics to the first location and the second location based on the determined exposure scenario.

16. The method of claim 15, further comprising:determining whether the wafer exposure process is configured to use the multiple reticle images to expose the field of the wafer by analyzing exposure lot data used by a lithographic apparatus that is configured to execute the wafer exposure process, wherein the exposure lot data comprises coordinate information of a distribution of the multiple reticle images at fields of the wafer.

17. The method of claim 15, wherein the plurality of exposure scenarios comprises:a first multi-image exposure scenario without stitching; anda second multi-image exposure scenario with stitching.

18. The method of claim 15, further comprising:determining a size of the field based on the arrangement of the multiple reticle images in the field.

19. The method of claim 15, further comprising:determining a size of a stitching region of overlap between the first reticle image and the second reticle image based on the arrangement of the multiple reticle images in the field.

20. The method of claim 15, further comprising:generating a combined design layout by combining a first design layout associated with the first reticle image and a second design layout associated with the second reticle image based on the arrangement of the multiple reticle images in the field.

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