High-efficiency converter

Abstract

The invention addresses the problem of efficiently converting and regulating mains input power into output power or into output currents for operating loads, in particular in applications with varying power requirements. More particularly, the invention provides improvements in the circuit arrangement which make it possible to connect the inputs of two converters both in series and in parallel depending on the instantaneous input voltage and / or the input current, and depending on the instantaneous phase angle. In addition, flexibility is increased by a second bypass mode which, under certain conditions, allows the second converter to be bypassed. This dynamic and flexible switching between operating modes is intended to improve efficiency and to reduce the inrush current surge when the mains voltage is applied, while at the same time ensuring that the input current of the circuit arrangement remains sinusoidal, in order to meet the requirements relating to current consumption, sinusoidal current consumption, mains harmonics and the THD value, and to maximise the efficiency of energy conversion.

Description

[0001] 2024PF00026

[0002] 1

[0003] HIGHLY EFFICIENT CONVERTER

[0004] DESCRIPTION

[0005] Technical field

[0006] The present application relates generally to circuit arrangements for power conversion, and in particular to an arrangement that enables both serial and parallel operation of converters.

[0007] background

[0008] Since the following discussion primarily focuses on circuit details of an LED driver or LED operating device that incorporates a corresponding electronic circuit, the terms "circuit arrangement," "LED driver," and "LED operating device" are used synonymously. Because the electronic circuit includes two converters for transforming the mains input power, the terms "converter" and "power converter" are used synonymously. The German term "Hochsetzsteller" (boost converter) is used synonymously with the English term "boost converter," which is also commonly used in German. Similarly, the German term "Tiefsetzsteller" (buckle converter) is used synonymously with the English term "buck converter" or "buck."

[0009] A potential-isolated converter is a converter with potential isolation according to EN 61558 / IEC 61558 for creating a SELV-2024PF00026

[0010] 2

[0011] compliant circuit arrangement. This usually involves the use of a transformer to separate the two potentials.

[0012] Safety extra-low voltage (SELV) refers to an electrical voltage that, due to its low level and its insulation from higher-voltage circuits, e.g., by means of safety isolating transformers, offers special protection against electric shock (EN 61558; IEC 61558 Safety of transformers). If the nominal voltage is less than 25 V AC or 60 V DC, a protective conductor to prevent direct contact is not required when operating a device with safety extra-low voltage.

[0013] Conventional converters, as shown in the block diagram of Fig. 1, typically have two stages to meet the multiple requirements of modern converters for converting alternating current (AC) voltage to direct current (DC) voltage or DC current. The first stage, or first converter, the power factor correction (PFC), usually operates as a power factor corrector to ensure a high power factor for the mains power, meeting the requirements of as many countries worldwide as possible. The power factor corrector is implemented as a boost converter, operating at an intermediate potential with a relatively high voltage of approximately 370 V. This high voltage is necessary so that the boost converter can operate at maximum efficiency at every conceivable operating point. This means that the switching transistor can operate with zero voltage switching (ZVS) across virtually its entire operating range, thus minimizing losses.

[0014] The second stage, HB, is usually a buck converter that reduces the high voltage at the intermediate potential, hereinafter referred to as the DC link voltage, to the potential required by the load 5. The output of the second stage, HB, can be voltage-controlled or current-controlled; that is, a predetermined voltage or a predetermined current is provided at the output. Since this voltage is often quite low, relatively high losses occur in the second stage, just as in the first stage, which has to step up from a sectionally low voltage to a very high voltage of 370V over a mains half-cycle. The overall efficiency of such a circuit arrangement consisting of the two converter stages is therefore limited. This is due to 2024PF00026

[0015] 3

[0016] This is because the two converters are always connected in series, meaning each converter must handle the entire power of the load. The output of the first converter is coupled to the input of the second converter; this coupling point is the intermediate potential or DC link voltage U_P2. A typical example of this is described in patent US 2017 / 0077818 A1. This patent discloses a two-stage power regulator comprising a first stage with a hybrid boost-bypass function and a second flyback converter stage. The first stage, a boost-bypass converter, includes a boost inductor, a bypass diode, and a boost switching element.The operation of this converter is divided into three intervals: a first interval in which the boost is active to increase the output voltage; a second interval in which the boost is deactivated and the output voltage drops towards the input voltage; and a third interval in which the output voltage follows the input voltage and energy is transferred via the bypass diode. This approach allows the output voltage of the first stage to be dynamically adjusted.

[0017] However, a disadvantage of the solution described in D1 is that it relies on the operation of a single boost-bypass converter in the first stage. Although this converter offers various operating modes to adapt to input conditions, it lacks the flexibility that results from dynamically switching the inputs of two separate converters between series and parallel configurations. The entire power flow must always pass through a fixed cascade, which makes it difficult to optimize overall efficiency over a wide range of operating conditions. In particular, the strategy of active current addition from two separately operating converters in parallel to precisely shape a sinusoidal input current is not taught in D1.

[0018] There is therefore a need for an improved converter arrangement that overcomes the efficiency limits of conventional two-stage converters, especially those with a fixed series connection, and enables a more flexible and efficient power conversion process while simultaneously ensuring high power quality and reduced component stress. 2024PF00026

[0019] Task

[0020] It is therefore an object of the invention to provide a circuit arrangement that has better efficiency at approximately the same cost.

[0021] Description of the invention

[0022] This application addresses the problem of efficiently converting and regulating grid input power into output power for operating loads. Particularly in applications with varying power requirements, there is a need to minimize conversion losses over a wide load and voltage range without compromising the quality of the power factor correction.

[0023] The problem is solved according to the invention with a circuit arrangement according to independent claim 1. The circuit arrangement comprises a first converter, a second converter and a control circuit that dynamically operates the converters in different operating modes to maximize overall efficiency.

[0024] The inventive core concept lies in the ability of the control circuit to actively switch the circuit topology between a serial and a parallel operating mode:

[0025] In serial operating mode, which is used in the first part of a mains half-wave, the input of the second converter is coupled to the output of the first converter and thus to the second, high potential. 2024PF00026

[0026] 5

[0027] In parallel operating mode, which is used in a second sub-segment of a mains half-wave, at least a portion of the input power is bypassed at one of the converters. This mode can be implemented in two alternative ways: 1. Alternative A (Parallel Inputs): The inputs of both converters are connected in parallel. Here, the power for the second converter is bypassed at the first converter. In this mode, the sum of the input currents of both active converters is regulated to produce a sinusoidal mains alternating current.

[0028] Alternative B (Parallel Outputs): The outputs of both converters are temporarily connected in parallel by bypassing the second converter. The input current of the active first converter is regulated to produce a sinusoidal AC mains current.

[0029] The control circuit is further configured so that the total current draw from the mains exhibits an essentially sinusoidal waveform in all operating modes. This sinusoidal mains input current is achieved by the controlled addition of the respective input currents in parallel operating mode, or by the control of the input current of the first converter in series operating mode, as well as by averaging the currents across a capacitor coupled to the first potential, and by rectification in a mandatory rectifier to rectify the mains AC voltage.

[0030] Here, the input currents of the first and second converters are averaged with a short time constant or a short averaging window (over approximately...).

[0031] 100 ps), so that the through-modulated inductor currents (peak-peak value) generated by the high-frequency clocking of the converters are no longer considered in the modulation, but rather as their average value. The mains input current is thus considered, for example, around the average inductor current. This averaging is so short-term with respect to the mains half-wave that it can be considered an instantaneous value, since the course of the mains half-wave is in the millisecond range, whereas the slight averaging of the inductor currents is in the picosecond range. This dynamic switching between a series and various parallel operating modes enables highly efficient use of the 2024PF00026

[0032] 6

[0033] Mains input power and represents a significant improvement over the state of the art. By adding the input currents of the first and second converters in the second part of the mains half-wave to a sinusoidal mains alternating current, a more efficient power factor correction is achieved, which leads to an increase in the energy efficiency of the entire circuit arrangement.

[0034] The ability to convert input power into stable output power to operate a load, while maintaining a sinusoidal waveform of the mains alternating current, contributes to compliance with power quality standards.

[0035] This invention has the advantage that it enables effective intermediate energy storage through the use of a buffer storage device. This is particularly advantageous in a preferred embodiment that describes the use of a buffer capacitor to limit voltage ripples.

[0036] This invention has the advantage of enabling the decoupling of the various operating elements of the circuit arrangement, resulting in improved overall efficiency. This advantage is closely related to some advantageous embodiments dealing with switching between series and parallel operating modes.

[0037] In a particularly preferred embodiment, the first sub-area of ​​the network half-wave is divided temporally into two sub-areas at the beginning and end of the network half-wave, so that a switch between series and parallel operation takes place twice in one network half-wave.

[0038] The division of the first part of the network half-wave into two sub-areas at the beginning and at the end is due to the approximate symmetry of the voltage and current waveforms with respect to the imaginary center line of a network half-wave.

[0039] In a further preferred embodiment, the switching operations are essentially symmetrical about the center of the mains half-wave, that is, symmetrical about the phase angle of 90 degrees of the mains half-wave. 2024PF00026

[0040] 7

[0041] In a particularly preferred embodiment, the circuit arrangement is designed such that the operation of the first and second converters is switched between serial and parallel operation during each half-wave of the mains supply.

[0042] According to the invention, switching between the serial and the various parallel operating modes is accomplished by selectively controlling semiconductor switches that selectively activate or deactivate the corresponding current paths.

[0043] In a further preferred embodiment, the switch from series to parallel operation is carried out when the magnitude of the current mains input current of the mains half-wave becomes greater than the input current of the second converter plus a predetermined separation current, and the switch from parallel operation to series operation is then carried out when the magnitude of the current mains input current of the mains half-wave becomes less than the input current of the second converter plus a predetermined separation current of the second converter.

[0044] The adaptive switching between serial and parallel operation enables efficient adjustment to fluctuating mains voltages.

[0045] In a further preferred embodiment, the switch from series to parallel operation occurs when the current AC mains voltage during the mains half-cycle is greater than the voltage at the load plus a predetermined offset voltage of the second converter. The switch from parallel to series operation occurs when the current AC mains voltage is again less than the voltage at the load plus a predetermined offset voltage of the second converter.

[0046] The control circuit is further configured such that the total current draw from the input is regulated in all sub-ranges of the mains half-wave so that the resulting mains AC current has an essentially sinusoidal waveform. This sinusoidal mains input current is obtained by the controlled addition of the respective input currents in parallel operating mode or by the regulation of the input current of the first converter in series operating mode, as well as by averaging the 2024PF00026

[0047] 8

[0048] Currents across a capacitor coupled to the first potential, and through rectification at a mandatory rectifier to rectify the mains AC voltage.

[0049] Ensuring a sinusoidal input current reduces harmonics in the network, resulting in lower electromagnetic interference (EMI), lower harmonic distortion (THD), and improved power quality.

[0050] A sinusoidal sum current of the converters contributes to compliance with grid standards and enables the use of the circuit arrangement in a wide variety of applications.

[0051] In another preferred embodiment, the first converter is a boost converter, and the second converter is either a buck converter, a flyback converter, or another buck converter.

[0052] The use of a boost converter as the first converter and a buck converter or another buck isolating converter as the second converter allows for flexible adaptation to different input and output voltage levels, which expands the applicability of the circuit arrangement.

[0053] In another embodiment, the load is an LED module, and the second converter adjusts the output voltage to the voltage of the LED module, regulates the output current, or dims the LED module by reducing the output current.

[0054] Adapting the output voltage or output current to the requirements of an LED module enables precise control of the brightness and contributes to energy savings.

[0055] The ability to reduce the output current for dimming the LED module provides additional functionality for lighting applications and improves the user experience through customizable lighting conditions.

[0056] At very low output powers or in situations with reduced mains voltage or very high load voltage, a further 2024PF00026

[0057] 9

[0058] In this embodiment, there is no switching, and the input of the second converter remains coupled to the second potential throughout the entire mains half-wave.

[0059] This measure ensures the correct functioning of the circuit arrangement under all operating conditions.

[0060] Advantage 1: Avoiding switching at very low output powers or in situations with reduced mains voltage or high load voltage helps to reduce switching losses, which improves the efficiency of the circuit arrangement and the THD.

[0061] Advantage 2: By continuously coupling the input of the second converter with the second potential over the entire half-wave, a more stable output power is ensured, which increases the reliability of the circuit arrangement in different operating conditions.

[0062] Advantage 3: The constant connection of the input to the second potential prevents potential disturbances or current fluctuations of the load current during operation of the connected load, resulting in an improved user experience, e.g. flicker-free, constant light even with highly fluctuating input voltage.

[0063] In another preferred embodiment, the circuit arrangement is configured such that current jumps at the input during switching are detected by a signal taken from or measured at the input or at an input choke, and these undesired jumps are minimized by means of a slow control process running over several mains half-cycles or a minimization algorithm using the detected signal. This measure advantageously improves the quality of the sinusoidal mains current draw, the mains current distortion, and the mains harmonics, as well as the THD value, and enhances the electromagnetic compatibility of the circuit arrangement.

[0064] In another embodiment, the signal at the input choke is detected by means of a high-impedance capacitive tap, an auxiliary winding on the input choke, or a choke located locally near the input choke. 2024PF00026

[0065] 10

[0066] Advantage: The implementation of one of the aforementioned detection methods can be carried out without significant changes to the main structure of the input choke, which minimizes the manufacturing costs of the circuit arrangement.

[0067] A buffer capacitor, which has a capacitance in the range between a minimum of 0.5 nanofarads and a maximum of 22 nanofarads at a nominal power of the ballast or LED driver of 50W, is connected between the input terminals of the second converter to limit voltage ripple at the input.

[0068] Advantage 1: Integrating a buffer capacitor with a capacitance in the specified range limits the voltage ripple at the input of the second converter, which improves EMC and prevents interference during operation.

[0069] Advantage 2: Limiting the voltage ripple by the buffer capacitor helps to reduce voltage spikes that could damage electronic components, thus increasing the reliability of the circuit arrangement.

[0070] In another preferred embodiment, the switch-on time for the converter switch of the first converter is controlled by a control circuit such that the switch-on time is adjusted abruptly at a first switching point between the first sub-area of ​​the first sub-area and the second sub-area and at the second switching point between the second sub-area and the second sub-area of ​​the first sub-area, so that the switch-on time immediately after the first switching point is at least 30% shorter than immediately before the first switching point, and such that the switch-on time immediately before the second switching point is at least 30% shorter than immediately after the second switching point, and that the switch-on time is controlled over a mains half-cycle in such a way that the sinusoidal current draw for the mains current is ensured.This measure advantageously maintains a sinusoidal current draw without major current fluctuations across the entire mains half-cycle, including the switching times between series and parallel operation and back. 2024PF00026.

[0071] 11

[0072] A particularly advantageous implementation of the parallel connection of the inputs (alternative A) is made possible by a third bypass branch. This is implemented as a parallel upper rectifier branch using two additional mains rectifier diodes, whose anodes are connected to the AC inputs of the rectifier and whose cathodes are connected to the input of the second converter. This reduces the forward losses by eliminating the forward voltage drop of the D_P1 diode, thereby further increasing the overall efficiency.

[0073] A particularly advantageous implementation of the parallel connection of the outputs (alternative B) is made possible by a second bypass branch, which bypasses the second converter. This bypass branch connects a point between the converter inductor and the converter switch of the first converter directly to the output capacitor of the second converter.

[0074] This dynamic switching between serial and various parallel operating modes enables highly efficient use of the mains input power and represents a significant improvement over the prior art. Each of the embodiments described herein can advantageously be combined with another.

[0075] Further preferred embodiments can be found in the dependent claims and the entire disclosure, whereby the description does not always differentiate in detail between device and use aspects; in any case, the disclosure is to be read implicitly with regard to all claim categories.

[0076] Brief description of the drawings

[0077] Further advantages, features, and details of the invention will become apparent from the following description of exemplary embodiments and from the drawings, in which identical or functionally equivalent elements are provided with identical reference numerals. Figure 2024PF00026 shows:

[0078] 12

[0079] Fig. 1 shows a block diagram of a circuit arrangement according to the prior art,

[0080] Fig. 2 shows a block diagram of a tenth embodiment,

[0081] Fig. 3 shows a first embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load,

[0082] Fig. 4 shows a second embodiment of the circuit arrangement with a boost converter as a power factor corrector and a flyback converter for operating the load,

[0083] Fig. 5 shows a representation of a half-wave of the mains input voltage with other important voltage curves of the circuit arrangement.

[0084] Fig. 6 shows a representation of a half-wave of the mains input current with other important current curves of the circuit arrangement.

[0085] Fig. 7 shows the switching-on time of the converter switch of the first converter over the mains half-wave.

[0086] Fig. 8 The representation of other important voltage and current curves over a half-wave of the mains input voltage,

[0087] Fig. 9 shows the voltage and current curves of Fig. 8 in a higher temporal resolution section at the time of the first switching in the half-wave of the mains input voltage,

[0088] Fig. 10 shows a third embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load, as well as a first sensor for detecting current jumps at the mains input. Fig. 11 shows a fourth embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load, as well as a second sensor for detecting current jumps at the mains input. Fig. 12 shows a fifth embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge 2024PF00026

[0089] 13

[0090] A buck converter as a second converter for operating the load, and a third sensor for detecting current jumps at the mains input, Fig. 13 the first embodiment with the driver shown for controlling the switch of the bypass branch in an embodiment with an optocoupler for switching the switch of the bypass branch on or off and with a cascaded bootstrap circuit using bootstrap diodes D_T1 and D_T2 to provide an auxiliary voltage,

[0091] Fig. 14 shows a sixth embodiment of the circuit arrangement, which is similar to the first embodiment, but uses the converter switch in parallel with the switch of the bypass branch,

[0092] Fig. 15 shows a seventh embodiment of the circuit arrangement, which is similar to the first embodiment, but uses a MOSFET SW_P1 as a switch instead of the naturally switching diode D_P1.

[0093] Fig. 16 shows an eighth embodiment that combines the sixth and seventh embodiments to eliminate the naturally switching diode D_P1,

[0094] Fig. 17 shows a ninth embodiment of the circuit arrangement, which replaces the diode D_P1 with two additional mains rectifier diodes forming a parallel upper rectifier branch that acts as a bypass branch when the switch SW_P2 is off.

[0095] Fig. 18 shows a tenth embodiment of the circuit arrangement, which integrates an additional switch and an additional diode in the bypass path to enable a second bypass mode in which the second converter is bypassed and the power of the first converter is output directly at the output capacitor of the second converter, particularly when the required output voltage is very high. Fig. 19 shows the input power P_in and the output power P_out of the circuit arrangement over a mains half-cycle together with the input voltage, and illustrates the energy flows during the different time intervals Tsa, Tp, and Tsb with the outputs connected in parallel. 2024PF00026

[0096] 14

[0097] Preferred embodiment of the invention

[0098] Fig. 2 shows a circuit arrangement for converting mains input power into output power for operating a load. The arrangement comprises an input (L, N) for the mains AC voltage (U_in) and the mains AC current (l_in), a rectifier (BR) to provide a first potential (P1), and a first converter (PFC) that acts as a power factor corrector. A second converter (HB) provides the output power. The circuit arrangement uses a switching box SB to connect the converters in series during a first sub-region of the mains half-wave and the inputs of the converters in parallel during a second sub-region. The input currents to the two converters add up in the second sub-region and together produce a sinusoidal mains AC current received by the circuit arrangement.

[0099] In another alternative embodiment, the circuit arrangement uses a switch SW_BP2 to connect the two converters in series in a first sub-area of ​​the mains half-wave and the outputs of the converters in parallel in a second sub-area.

[0100] In a third alternative embodiment, the rectifier BR is bypassed by means of two additional rectifier diodes D_N and D_L, thus saving a forward voltage of one diode, which increases the efficiency of the circuit arrangement.

[0101] The present invention relates to a novel topology for a high-efficiency AC-DC converter, hereinafter referred to as a dynamically switchable series-parallel topology. A key embodiment of this topology is the bypass dual-rail topology, or BDR topology for short. This topology is particularly suitable for non-isolated LED drivers (non-SELV) and offers significant advantages in terms of efficiency, component count, component size, and complexity compared to existing solutions. The BDR topology 2024PF00026

[0102] 15

[0103] It combines the advantages of a boost converter and a buck converter to ensure a sinusoidal current draw from the mains while minimizing converter losses. Due to the cascaded converter design with two converters connected in series, and with good power factor correction, the operating range for the load can be very large in terms of voltage and current, and the output current can exhibit very low current modulation. Because of the smaller component sizes, the storage capacitors in the circuit arrangement can also be smaller, which means that more of these circuit arrangements can be connected to a single circuit breaker without it tripping when all circuit arrangements are switched on simultaneously. The circuit arrangement can be used, for example, as an LED driver, as will be explained further below.

[0104] The bypass dual-rail topology comprises two main converters: a boost converter (PFC, first converter) that acts as a power factor corrector, and a buck converter (HB, second converter) responsible for voltage and current matching to the load. The two converters, PFC and HB, are designed to operate partially in parallel and partially in series during a mains half-cycle. In parallel operation, depending on the specific configuration, they draw current from the mains in parallel, thereby reducing the load on the boost converter.

[0105] The bypass dual-rail topology uses two different bus voltages applied to potentials P1 and P2. P1 is connected to the input of the boost converter PFC (first converter), while P2 is connected to the output of the boost converter PFC.

[0106] In bypass mode, a portion of the current is diverted past the boost converter (PFC), and potential P1 is fed directly into the input bus of the buck converter. This allows for a reduced average input bus voltage for the buck converter, resulting in higher efficiency.

[0107] A switching box SB, which controls the switching between the bus voltages, operates virtually statically and does not require high-frequency control, 2024PF00026

[0108] 16

[0109] which simplifies the control and reduces the circuitry required for switching.

[0110] The operation of the bypass dual-rail topology can be divided into at least three time periods, which will be discussed in more detail later in Figures 5 to 9: Tsa, Tp and Tsb.

[0111] Time period Tsa: In this period, the switching box SB is permanently connected to potential P2. The boost converter PFC operates in PFC mode, i.e., as a power factor corrector, and charges capacitor C_P2, while the buck converter HB discharges capacitor C_P2. The discharge current of the buck converter HB is greater than the charging current of the boost converter PFC, resulting in a discharge of C_P2.

[0112] Time period Tp: During this period, the switching box SB is permanently connected to potential P1. The boost converter PFC continues to operate in PFC mode; however, the input current to the boost converter is significantly reduced because it no longer needs to supply load 5, but only the capacitor C_P2. The buck converter HB is no longer supplied by capacitor C_P2, but directly by the mains rectifier. Due to the lower input voltage, the buck converter HB operates with improved efficiency. The current is regulated so that the sum of the average input currents of the boost converter PFC and buck converter HB yields the desired sinusoidal input current. The averaging of the input currents of the boost converter PFC and buck converter HB is a relatively short averaging period of approximately 100 ps.

[0113] Time period Tsb: In this period, the switching box SB is permanently switched to potential P2, and the buck converter HB is switched to C_P2 again. Operation in this period is almost identical to Tsa, except that the voltage at C_P2 is modulated to a small extent by the sinusoidal current draw, with this portion being phase-shifted relative to the mains voltage half-wave. This modulation is also known as mains hum. 2024PF00026

[0114] 17

[0115] The bypass dual-rail topology can be implemented in various configurations, differing in the type of components used and the specific control of the switches. For example, the buck converter can be implemented either as a half-bridge (HB-Buck) or as a low-side or high-side buck, i.e., with the buck switching transistor located at the bottom or top.

[0116] Example 1: With an input voltage of 230V AC and an output voltage of 220V DC, the average bus voltage at C_BUF can be set to approximately 336V. This leads to a significant reduction in losses in the buck converter HB, as the switching losses are reduced by the lower average voltage and switching frequency. In one embodiment, the bypass current path can be equipped with a clamping diode whose anode is connected to P1 and whose cathode is connected to P2, in order to protect the circuit arrangement and its components from high voltages, such as those that can occur during voltage surges.

[0117] The bypass dual-rail topology offers several advantages:

[0118] Increased efficiency: The losses in the first converter, i.e. in the boost converter PFC, can be reduced by approximately 40% to 65%, resulting in higher overall energy efficiency.

[0119] Reduction of the component size of the boost converter choke L_PFC by reducing the saturation current in the boost converter choke L_PFC. This is made possible by reducing the peak currents in the boost converter choke L_PFC.

[0120] Another advantage is the reduction in the component size of the buffer capacitor or storage capacitor C_P2 by reducing its capacitance. This is achieved by reducing the amount of charge temporarily stored in C_P2 during each mains half-cycle. This significantly reduces the inrush current when the mains voltage is applied. As mentioned above, this results in a situation where many more devices can be operated from a single circuit breaker, as in 2024PF00026.

[0121] 18

[0122] Circuit topologies according to the state of the art. The capacitance of the buffer capacitor C_P2 is approximately half that of known circuit arrangements from the state of the art.

[0123] Flexibility: The topology is universally applicable for various applications, including non-isolated and isolated LED drivers.

[0124] Simple implementation: The static control of the switches in the switching box SB or the switch SW_P2 simplifies the implementation and control of the converter.

[0125] In another embodiment, instead of the inputs of the converters being connected in parallel during a partial mains half-wave, the outputs are connected in parallel, effectively bypassing the second converter. This can also increase efficiency under certain conditions, such as a low input voltage combined with a high output voltage. This embodiment is an alternative to the parallel connection of the inputs; therefore, both embodiments cannot be used in parallel. The bypass dual-rail topology represents an innovative solution to the challenges in developing highly efficient converters. By combining efficiency, reduced component size, flexibility, and ease of implementation, this invention offers a promising foundation for future developments in the field of LED drivers and other AC-DC converters.

[0126] Definitions:

[0127] The term "circuit arrangement" here refers to a specific electrical circuit designed to convert mains input power into output power for operating a load.

[0128] The term "mains half-wave" here refers to the positive or negative half-wave of an alternating voltage that occurs within a specific time interval and is important for controlling the circuit arrangement. 2024PF00026

[0129] 19

[0130] The term "converter" here refers to electronic circuit elements that convert electrical energy from one form to another, such as from alternating current to direct current or from one voltage level to another. The term "load" here refers to the electrical device or circuit that is powered by the output power of the circuit arrangement, such as an LED module.

[0131] The term "input" here refers to the terminals of the circuit arrangement where the mains input power is fed in in the form of alternating voltage and current.

[0132] The terms "input of the first converter" and "input of the second converter" refer here to the two terminals into which electrical power is fed into the converter. Since each terminal is assigned a specific potential, these are also referred to as potentials. The potentials P1 and GND form the input of the first converter, while the potentials HB_in and GND form the input of the second converter.

[0133] The term "switching" here refers to the process of changing the operating mode of the converters between serial and parallel configuration during a network half-wave in order to optimize the efficiency of energy conversion.

[0134] The terms "sub-area" and "time segment" refer here to specific time intervals within a network half-wave in which different operating modes of the circuit arrangement are active, such as the first sub-area (Ts) and the second sub-area (Tp). The term "sub-area" refers to the division of the sub-areas into two or more sub-areas, which together constitute the sub-area. For example, Tsa and Tsb are sub-areas and together form the sub-area Ts.

[0135] The term "potential" here refers to the electrical voltage levels used in the circuit arrangement for energy transfer and conversion, in particular the first DC potential (P1), the second DC potential (P2), and the AC-side alternating voltage potentials (PWa, PWb).2024PF00026

[0136] 20

[0137] The term "input choke" here refers to a passive electrical component (L_F I L1 , L_F I L2) used in the circuit arrangement to dampen current spikes at the input and improve the EMC of the circuit.

[0138] The term "operation" here refers to the active state of the circuit arrangement in which the converters operate to convert the mains input power into usable output power.

[0139] The term "PFC operation" here refers to the operation of a converter as a power factor corrector. The converter thus ensures power factor correction or reactive power compensation of the input current, resulting in a high cos φ. <p führt.

[0140] The term "spacing current" refers to an advantageous current reserve at the switching points. The spacing current ensures that the current drawn by the boost converter (l_Boost_in) always remains positive during switching, or rather, that the input current always remains sinusoidal, i.e., the current remains constant during switching. See spacing current l_HR in Figure 6.

[0141] This means that the offset current and the resulting current reserve serve to reliably maintain the switching condition for the sinusoidal current draw for the sum of the currents l_Boost_in and l_D_P 1. It also serves to generate an additional degree of freedom for the current control of l_Boost_in by allowing the offset current to be varied in order to adjust or control the current level, which is detrimental to the THD value, to very small values ​​during switching.

[0142] In the following explanations, the term "average" refers to the smoothing of the RF switching ripple caused by the high-frequency switching of the converter switches. That is, the average value is the value obtained over a period of approximately...

[0143] The average value calculated over 100 ps is meant. That is, the average value here does not refer to the average over one network half-wave. 2024PF00026

[0144] 21

[0145] The term "mains alternating voltage" here refers to the sinusoidal alternating voltage that is fed in from the power grid and serves as the input variable for the circuit arrangement.

[0146] The term "mains alternating current" here refers to the sinusoidal electric current that originates from the power grid and is processed in the circuit arrangement.

[0147] The term "mains input power" here refers to the electrical power that is fed into the circuit arrangement from the power grid, consisting of the mains AC voltage and the mains AC current.

[0148] The term "output power" here refers to the electrical power provided by the circuit arrangement to operate a connected load, such as an LED module.

[0149] The term "operate" here refers to the provision of electrical energy by the circuit arrangement to supply a connected load, such as an LED module.

[0150] The term "capacity" here refers to the ability of an electrical component to store electrical charge, typically in relation to a capacitor used in the circuit arrangement.

[0151] The term "output" here refers to the point or terminals of the circuit arrangement (LO+, LO-) where the generated output power is provided to supply the load.

[0152] The terms "output of the first converter" and "output of the second converter" refer here to the two terminals at which the converter outputs electrical power. Since each terminal is assigned a specific potential, these are also referred to as potentials. Potentials P2 and GND form the output of the first converter, while potentials LO+ and LO- form the output of the second converter. The output of the second converter is therefore also the output of the circuit arrangement.

[0153] The term "serial and parallel operation" refers here to the operating modes of the converters, whereby in serial operation the converters are connected in series, i.e. the output of the first converter with the input of the 2024PF00026

[0154] 22

[0155] is coupled to the second converter, and in parallel operation either the inputs or the outputs of the converters are connected in parallel.

[0156] The term "headroom voltage" refers here to a defined voltage difference that is taken into account when switching between operating modes. This ensures a sufficient demagnetization voltage for the first converter (PFC) and a sufficient magnetization voltage for the second converter (HB) to account for the converters' inductance and to guarantee stable converter control. This voltage is also often referred to as "headroom voltage."

[0157] The term "LED module" here refers to an electrical load consisting of one or more light-emitting diodes and supplied by the circuit arrangement with a suitable output voltage or current.

[0158] Output current: The term "output current" here refers to the electrical current l_out that is provided at the output of the second converter (HB) to operate the connected load, such as an LED module.

[0159] Current jump: The term "current jump" here refers to a sudden change in the input current l_in, which can occur at the inputs L, N of the circuit arrangement during switching between the operating modes.

[0160] Buffer capacitor: The term "buffer capacitor" here refers, for example, to a capacitor C_P2, which is connected between the output terminals (P2, GND) of the first converter PFC to limit voltage fluctuations (ripple) at the output. Other buffer capacitors in the circuit arrangement are C_P1 and C_BUF.

[0161] Operation via semiconductor switches: The term "operation via semiconductor switches" here refers to the use of semiconductor switches (SW_P2, D_P1) connected in the current path between the potentials (P1, P2) and the input (HB_in) of the second converter to enable switching between series and parallel operating modes. 2024PF00026

[0162] 23

[0163] Situation with reduced mains voltage: The term "situation with reduced mains voltage" refers here to operating conditions in which the mains voltage falls below a certain threshold, which can affect the switching between operating modes.

[0164] Semiconductor switch: The term "semiconductor switch" here refers to electronic components that function as switches and are used in the circuit arrangement to control current flow and enable switching between operating modes. The terms "switch," "semiconductor switch," and "MOSFET" are used interchangeably, merely emphasizing different meanings within the context. For example, the term "switch" focuses on the switching action as an explanation of its function, while the term "MOSFET" refers more to the actual component and its function within circuit arrangement 1. Range: The term "range" here refers to a defined range of values ​​within which certain parameters, such as the capacitance of the buffer capacitor, should lie.

[0165] The term "convert" here refers to the process of transforming one electrical power into another, e.g., converting mains alternating current into a usable output power for operating a load, or converting mains alternating current into an intermediate circuit voltage, or converting an intermediate circuit voltage into a usable output power for operating a load.

[0166] The term "rectifier" here refers to an electrical component that converts the mains AC voltage into DC voltage to provide a first potential (P1). This mathematically converts the mains AC voltage or current into a single value, since the voltage, and therefore the current, after the rectifier is always positive relative to the circuit ground (GND). To keep the input current U_in of the circuit arrangement sinusoidal, the currents within the circuit arrangement are regulated so that the overall current drawn after the rectifier is sinusoidal. This results in the current draw of the input current l_in before the rectifier being 2024PF00026

[0167] 24

[0168] The rectifier also produces a sinusoidal waveform, but as alternating current, since the voltage reverses during the negative half-waves of the mains supply. Therefore, it should always be understood in the following explanations that positive current values ​​are always used within the circuit arrangement, but these result in a real alternating current at the input of the circuit arrangement.

[0169] The term "provide" here refers to the supply of electrical energy or voltage at a specific point in the circuit arrangement. The term "average" refers to the smoothing of the RF switching ripple caused by the high-frequency switching of the converter switches. That is, "average" refers to the average value calculated over a period of approximately 100 ps. Therefore, "average" here does not refer to the average value over a single mains half-cycle.

[0170] Control circuit: An electronic unit, typically a microcontroller (pC), configured to measure relevant voltages and currents, control switches, and implement the control strategy for the circuit arrangement.

[0171] Operating mode: A specific configuration or state of the circuit arrangement in which the converters (PFC, HB) operate, such as serial operating mode or parallel operating mode.

[0172] Parallel operating mode: This refers to an operating mode in the second sub-range (Tp) of the mains half-wave, in which the converters (PFC, HB) are no longer operated purely in series. This is achieved by a bypass branch and can be accomplished either by connecting the inputs of both converters in parallel or by connecting the outputs of both converters in parallel.

[0173] Rules: The process by which the control circuit actively adjusts parameters of the circuit arrangement, such as the on-time of switches or current levels, to achieve a desired behavior or result, such as a sinusoidal input current.

[0174] Diode (e.g. D_N, D_L, D_PFC, D_BP2, DR1-DR4): A semiconductor component that allows current to flow in only one direction and is used in the circuit arrangement for 2024PF00026

[0175] 25

[0176] It is used for rectification, freewheeling, bypass functions, or as a converter diode.

[0177] Junction point: A node in the circuit arrangement where several electrical conductors or components are connected to each other.

[0178] Upper rectifier branch: A circuit arrangement of diodes that take over the function of a rectifier in a bypass path to allow a current path in parallel to an existing rectifier.

[0179] Output capacitor (C_B): A capacitor placed at the output of the second converter (HB) to smooth the output voltage, store energy, and serve as a reference for power delivery to the load.

[0180] Converter inductance: The inductance belonging to a converter (PFC or HB) and used for energy storage and transfer in the respective converter operation (e.g. L_PFC for the first converter or L_B for the second converter).

[0181] Converter switch: A semiconductor switch used in a converter (PFC or HB) to control the energy flow and enable the respective converter operation (e.g. PFC_SW for the first converter or HBH / HBL for the second converter).

[0182] Converter current: The electric current that flows through the inductor or other components of a converter.

[0183] Bypass period: A specific time interval in which a bypass mode, such as the second bypass mode, is active and part of the circuit is bypassed to allow direct power transfer.

[0184] PFC stage: Refers to the first converter (PFC) that performs the power factor correction function.

[0185] Bypass Mode 1 (BP1): This refers to the operating mode in which the inputs of the first converter (PFC) and the second converter (HB) are connected in parallel, typically by switching off switch SW_P2, to connect the first converter (PFC) directly to the first potential (P1) and the second converter (HB) also to the first potential (P1). This mode 2024PF00026

[0186] 26

[0187] This corresponds to the circuit arrangement shown in Figures 3, 4, and 10 to 16, and the switching over a mains half-wave is explained in Figures 5 to 9. This mode is used during the time interval Tp when the input voltage U_in is greater than the output voltage U_out.

[0188] Bypass mode 2 (BP2): This refers to the operating mode shown in Figure 18, in which the second converter (HB) is bypassed by activating a bypass path with an additional switch (SW_BP2) and an additional diode (D_BP2). This mode is used during the time interval Tp when the input voltage U_in is less than the output voltage U_out, and allows the power from the first converter (PFC) to be directly output to the output capacitor (C_B) of the second converter.

[0189] AC voltage potentials (PWa, PWb): Refers to the two terminals at the input of the rectifier (BR) where the mains AC voltage (U_in) is applied before it is rectified. In a preferred embodiment, these terminals serve as anode connections for the separate upper rectifier branch (BP_3).

[0190] Bypass path or bypass branch (BP_1, BP_2, BP_3): Refers to one of several alternative current paths in the circuit arrangement that allow a portion of the input power to bypass one or both converters (PFC, HB) to increase efficiency. Each bypass branch implements a specific form of parallel operation.

[0191] Fig. 3 shows a first embodiment of the circuit arrangement with a boost converter (PFC) as a power factor corrector and first converter, and a half-bridge buck converter (HB) as a second converter for operating the load. The first embodiment of the circuit arrangement is initially quite conventional in design. The circuit arrangement has an input L, N for inputting the mains AC voltage U_in and the mains AC current l_in. Together, these provide the mains input power. This power first passes through a mains filter consisting of a filter capacitor CN and two filter chokes L_F IL1 and L_FIL2, which may be magnetically coupled depending on the application. After the filter stage, the mains AC voltage is rectified in the bridge rectifier BR, consisting of four diodes DR1 to DR4. The rectified voltage is then fed into the

[0192] 27

[0193] The potential is stored in a small buffer capacitor C_P1 and fed into the first converter PFC. The voltage across this buffer capacitor C_P1 is the first potential P1. This voltage is a pulsating DC voltage that varies from nearly 0V to approximately 325V over one mains half-cycle. The first converter PFC is a boost converter and functions as a power factor corrector. It generates an input current that simulates a resistive load, i.e., it is sinusoidal, like the mains input voltage. As is known, the inductor current L_PFC of the first converter PFC is shaped over one mains half-cycle of the mains voltage in such a way that a sinusoidal mains input current results.

[0194] The first converter, PFC, operates on a large buffer capacitor C_P2, which is usually an electrolytic capacitor due to its size. A relatively constant voltage is applied to this capacitor, which in classic configurations is referred to as the intermediate circuit voltage. This voltage relative to circuit ground (GND) is the second potential, P2.

[0195] The second converter HB is connected to this output via a switch SW_P2, the function of which will be explained later. This converter transforms the intermediate circuit voltage into an output voltage U_out and an output current l_out. The second converter is designed as a current-controlled converter; it therefore delivers a predetermined current l_out to the load 5, which consists of a plurality of LEDs LED1 to LEDN, regardless of the voltage across the load.

[0196] In this embodiment, the first converter PFC is a boost converter which, together with the buck converter HB as the second converter, implements power factor correction. For this purpose, the first converter, which operates as a switching regulator, has a switch PFC_SW as a converter switch that switches the rectified input voltage at a frequency of 20 kHz to approximately 800 kHz.

[0197] The second converter HB is a buck converter in a half-bridge configuration, in which the otherwise usual converter diode or freewheeling diode is replaced by an additional switch HBL to provide a larger switching range and thus a larger range of zero-voltage switching (ZVS) for 2024PF00026

[0198] 28

[0199] to implement the two switches HBL and HBH. Each of the two converters has its own converter choke, L_PFC for the first converter and L_B for the second.

[0200] In the present embodiment, two current paths to the input of the second converter HB are provided: Firstly, the aforementioned switch SW_P2, which couples the output of the first converter, i.e., the intermediate circuit voltage or potential P2, to the input of the second converter, which is hereinafter also referred to as the first bypass mode (BP1). This switch is implemented as a semiconductor switch, here as a MOSFET, and is controlled by a signal SW_P2_C. Secondly, a diode D_P1, which couples the potential P1 at the output of the rectifier BR to the input of the second converter. The diode D_P1 acts as a natural switch that does not require any special control signal. The anode of the diode D_P1 is coupled to the first potential P1, and the cathode is coupled to the input HB_in of the second converter.

[0201] In this case, the switching box SB is implemented using the two switches SW_P2 and the diode D_P1. SW_P2 is an actively controlled switch, and the diode D_P1 switches intrinsically based on its diode functionality.

[0202] In general, the switching box can also be implemented using two active switches, e.g., MOSFETs. It is essential to prevent both switches from conducting simultaneously to avoid a short circuit between potential P1 and potential P2. Therefore, a short dead time must be observed during switching, during which both switches are briefly off.

[0203] A power-loss-efficient embodiment for the switching box SB is the use of SW_P2 and D_P1 described above, with an additional active switch connected in parallel to D_P1. This active switch only conducts when diode D_P1 would conduct anyway, thus reducing the power losses due to the forward voltage across diode D_P1 by connecting the active switch in parallel. This approach is known from active rectification or synchronous rectification. 2024PF00026

[0204] 29

[0205] An advantage for the implementation of the switching box SB with two active switches is the use of an additional N-channel MOSFET, configured so that its intrinsic diode replaces diode D_P1. This MOSFET is switched on and off synchronously, in push-pull mode, with switch SW_P2, while maintaining a dead time during switching. In this configuration, MOSFET SW_P1 is switched on after a short dead time following the switch-off of MOSFET SW_P2, and vice versa.

[0206] Circuit arrangement 1 can also include a protection diode (not shown here) which, in the event of mains overvoltages, connects them to the buffer capacitor C_P2. The anode of this diode is coupled to the anode of diode D_P1, and the cathode to potential P2, i.e., the positive terminal of buffer capacitor C_P2.

[0207] The entire circuit arrangement is controlled by a microcontroller (pC), which measures all relevant voltages and currents and, in particular, controls the active switches. The microcontroller (pC) is shown as a block in Fig. 3, with its relevant outputs. The output PFC_C is connected to the control input PFC_C of the converter switch of the first converter (PFC). The output HBL_C is connected to the control input HBL_C of the switch HBL. The next output is connected to a high-side driver (HSD1), which in turn is connected to the control input HBH_C of the switch HBH. The next output is connected to a high-side driver (HSD2), which in turn is connected to the control input SW_P2_C of the switch SW_P2.

[0208] Only either diode D_P1 or MOSFET SW_P2 is conducting at any given time. Both converters share the same reference potential, GND. Therefore, when MOSFET SW_P2 is conducting, the two converters, PFC and HB, are connected in series. This means the input HB_in of the second converter, HB, is coupled to the output of the first converter, PFC, which supplies the buffer capacitor C_P2 and represents potential P2. When MOSFET SW_P2 is off (blocking), diode D_P1 conducts. In this case, the inputs of both converters, PFC and HB, are connected in parallel, as both inputs are coupled to potential P1. The output of the first converter, PFC, continues to charge the buffer capacitor C_P2, while the second converter supplies the load as usual.

[0209] 30

[0210] The first converter only needs to consume as much power during this time period as is necessary to achieve the sinusoidal input current. Therefore, the power converted in the first converter is significantly reduced when both converters are connected in parallel.

[0211] These two switching states alternate repeatedly over a half-cycle of the mains input voltage, as explained below with reference to Fig. 5. Here, various voltages and powers of the circuit arrangement are plotted against a half-cycle of the mains voltage U_in. The half-cycle of the mains voltage U_in is 10 ms long, which corresponds to a 50 Hz mains voltage. The voltage U_B_BUS, applied across the capacitor C_BUF, is present at the input of the second converter HB. During a first time interval Tsa, from the beginning of the half-cycle until time t1 at approximately 2.6 ms, the input of the second converter HB is connected to the output of the first converter PFC via the conducting MOSFET SW_P2. The second converter HB therefore derives its input power from the buffer capacitor of the second potential C_P2, which defines the output of the first converter PFC.This is necessary because the instantaneous value of the mains input voltage U_in at this point is lower than the predetermined output voltage U_out of the second converter, which drives the load. Therefore, the first converter (PFC) must first boost the mains input voltage to a higher value so that the second converter can operate with it and drive the load. As mentioned earlier, boosting to the high DC link voltage of approximately 370V to 400V is quite lossy, and the subsequent reduction to the often significantly lower output voltage is equally inefficient.

[0212] Therefore, at time t1, the second converter is disconnected from the DC link voltage at potential P2 and connected directly to the output of rectifier BR. This means that the second converter HB is connected in parallel to the first converter PFC on its input side for the duration of the time interval designated Tp in Figure 5. Since the instantaneous voltage of the input voltage U_in is significantly lower than the DC link voltage, the second converter can operate much more efficiently. During this time interval, the first converter operates on the buffer capacitor C_P2 to ensure a sinusoidal current draw.

[0213] 31

[0214] Since the second converter draws all the power for the load directly from the rectifier's output during this period, the first converter (PFC) only needs to draw enough current from the rectifier's output to ensure a sinusoidal current draw at the circuit's input. The currents drawn, l_Boost_in and l_Buck_in, from the first and second converters essentially add up during this time interval (Tp) to the total current l_in of the circuit, which exhibits a sinusoidal waveform. The current l_Buck_in is essentially constant to deliver a consistent power to the load, and the current l_Boost_in compensates for this DC offset to achieve the sinusoidal total current required during this time interval.

[0215] The total current l_in of the circuit arrangement is thus practically defined in the first time interval Tsa solely by the current l_Boost_in into the first converter PFC, whereas the total current of the circuit arrangement in the second time interval Tp is defined by the sum of the input currents l_Boost_in of the first converter PFC and l_Buck_in of the second converter HB:

[0216] l_in = l_Boost_in + l_Buck_in [for Tp]

[0217] Strictly speaking, the total current l_in is composed of the partial currents l_Boost_in and l_D_P1 due to Kirchhoff's law. However, since the capacitor C_Buf is very small and thus adapts almost instantly to the potential P1 within the time interval Tp, the above equation is actually correct. While these currents are instantaneous values ​​with respect to the mains half-wave, they are nevertheless averaged because the superimposed RF ripple caused by the RF switching operations of the converter switches is neglected or averaged here.

[0218] The time interval Tp begins at time t1 with a phase angle cp1 of the mains voltage U_in that depends on the output voltage, at which the current mains AC voltage (U_in) in the mains half-wave is greater than the voltage U_out at the load 5 plus a predetermined offset voltage of the second converter HB, and extends beyond the maximum of the instantaneous mains voltage up to the phase angle <p2 zum Zeitpunkt t2 im sinkenden Ast der momentanen2024PF00026

[0219] 32

[0220] The mains voltage at which the current AC mains voltage U_in is approximately the same as at time t1. The time interval Tp is therefore approximately symmetrical about the midpoint of the mains half-wave. Likewise, the currents and voltages shown in Figures 5 and 6 are approximately symmetrical about the midpoint of the mains half-wave. The midpoint of the mains half-wave here refers to a phase angle of 90°. Since time t1 is at approximately 2.6 ms, time t2 is therefore at 10 ms - 2.6 ms = 7.4 ms.

[0221] Therefore, the following relationship applies: t2 = 10ms - 11. The phase angle is calculated accordingly: <p2 = 180° - <p1 ; natürlich ist diese Beziehung in der realen Schaltung nicht mathematisch exakt, sondern physikalisch realistisch zu interpretieren.

[0222] At time t2, the instantaneous voltage of the mains half-wave becomes too low to operate load 5 using the second converter HB alone, and so the MOSFET SW_P2 is switched on again. This causes diode D_P1 to switch off, and the second converter HB is again coupled to the DC link voltage at the buffer capacitor C_P2. From this time t2 onwards, it operates load 5 until the end of the mains half-wave from the buffer capacitor C_P2, which is thereby discharged.

[0223] Of course, in specific applications it can also be advantageous for phases Ts and Tp to alternate more than twice during a mains half-cycle; depending on the boundary conditions, this can occur 4, 6, or even more times. For example, if the buffer capacitor C_P2 charges too quickly, a phase Ts can be inserted to temporarily discharge the capacitor and prevent an excessively high voltage for the second potential P2.

[0224] For specific applications, a slight or greater deviation from the ideal symmetrical switching with respect to the center of the mains half-wave would also be conceivable. However, the symmetrical switching described here as preferred has the advantage of achieving the best efficiency of the circuit. The first condition for the switching times t1 and t2 is defined here by the magnitude of the instantaneous value of the input voltage, which 2024PF00026

[0225] 33

[0226] Output voltage and a headroom voltage U_HR, which the second converter HB requires to operate correctly. This voltage is used to magnetize the inductor L_B of the second converter HB.

[0227] The following applies at times t1 and t2:

[0228] |U_in| = U_out + U_HR (condition 1).

[0229] U_in is denoted with absolute value notation in the formula because condition 1 refers to the magnitude of the mains input voltage. Since U_in is normally an AC voltage, it can also be negative.

[0230] The input voltage is switched automatically by diode D_P1 as soon as switch SW_P2 is turned on or off. However, an active switch, preferably another MOSFET, can also be used instead of diode D_P1. In this configuration, the switching is always implemented with a short gap or dead time of approximately 0.1 µs to 10 µs. Even in this configuration, diode D_P1 is still necessary to conduct the current during the gap when both switches are off, from potential P1 to input HB_in of the second converter HB.

[0231] To operate the circuit correctly with a sinusoidal input current, another switching condition is necessary: ​​The instantaneous value of the input current l_in, assumed to be sinusoidal, must be equal to the input current l_buck_in of the second converter HB plus a differential current l_HR. If this condition is not met, a sinusoidal current draw of the circuit and thus a good power factor cannot be guaranteed. Therefore, the following must be true at times t1 and t2:

[0232] l_in = l_Buck_in + l_HR (condition 2).

[0233] Synchronously with the switching at times t1 and t2, the control circuit pC ensures that the on-time of the converter switch of the first converter is adjusted so that the current l_Boost_in drawn from the grid by the first converter approximately corresponds to the offset current l_HR. This means that the on-time of the PFC_SW exhibits a jump at these times t1 and t2.

[0234] 34

[0235] The curve of the on-time t_on and the jump at times t1 and t2 of t_on is shown in Fig. 7.

[0236] For correct operation, in which all boundary conditions such as power factor, output voltage, and output current are met, the system switches to the operation assigned to the time interval Tp when both conditions are met, and then switches back to the operation assigned to the time interval Ts when one of the two conditions is no longer met.

[0237] Conditions 1 and 2 make it clear that the switchover to the operation assigned to Tp can occur somewhat later in the half-wave than the minimum time t1 that would result from conditions 1 and 2. Similarly, the switchover back to the operation assigned to the time periods Tsa and Tsb can occur earlier than the maximum time t2 that would result from conditions 1 and 2. Therefore, to operate the circuit correctly with a sinusoidal input current, the switch-on time t_on is controlled by the control circuit pC so that t_on is adjusted to match the switchover times t1 and t2, ensuring that t_on is significantly smaller during the time period Tp than immediately before the switchover time t1. In other words, t_on is controlled during Tp such that the equation l_in = l_Boost_in + l_Buck_in is satisfied for the time period Tp.A corresponding waveform for controlling t_on by the control circuit pC over the period of a half-cycle is shown as an example in Fig. 7. It should be noted that the signal edges (falling and rising) at the switching times t1 and t2 are simplified in Figures 5, 6, and 7 to improve readability. In reality, the rise time of the signal edges is approximately 30 ns to approximately 50 ps, ​​but in the figures it is approximately 200 ps. Figures 8 and 9 are significantly closer to reality with regard to the representation of the signal waveforms for the currents and voltages. These signal waveforms were generated using a very precise simulation.

[0238] In the timing control for the execution of the switching at the switching times t1 or t2, the clocking of the converter switches of the first converter PFC and / or the second converter HB at the switching times 2024PF00026

[0239] 35

[0240] t1 and t2 can be executed synchronously as an option. In this case, the switching is synchronized to the clocking of the converter switches using the switching box SB or SW_P2.

[0241] Since the clocking is normally performed at a high frequency (approx. 50 kHz to 500 kHz), such synchronization can usually be omitted, for example, to save resources in the control circuit pC. The control and timing over the mains half-wave for t_on are determined by the control circuit pC using the usual equations for controlling power converters (converter equations), taking into account the voltages at potentials P1, P2, and HB_in, as well as l_in, l_out, and U_out, and considering the equation l_in = l_Boost_in + l_Buck_in for the time interval Tp.

[0242] That is, the control circuit pC knows all relevant quantities through continuous measurements of the same, such as the instantaneous currents and voltages in the circuit, as well as the relevant equations for the sinusoidal current consumption, the relevant converter equations for the first converter PFC and the second converter HB, as well as the instantaneous phase angle or time interval within the mains half-wave with reference to the zero crossing of the mains half-wave, as well as the switching times t1 and t2, and calculates the necessary switch-on time t_on from this.

[0243] The relevant converter equations are well known from the prior art. They describe the currents and voltages in the circuit as a function of the circuit arrangement, the dependence on the on and off times of the converter switches, and the dependence on the dimensioning of the circuit components, e.g., the inductance of the converter choke.

[0244] The relevant equations for sinusoidal current consumption are the following:

[0245] In general, the following equation applies to all time intervals in a network half-wave: l_in = l_Boost_in + l_D_P1

[0246] The following equations apply to the different time periods: 2024PF00026

[0247] 36

[0248] l_in = l_Boost_in + l_Buck_in [Time period Tp]

[0249] This equation applies to the time interval Tp (parallel connection of the converter inputs).

[0250] I_in = l_Boost_in + 0 [time interval Tsa and Tsb]

[0251] This equation applies to the time intervals Tsa and Tsb (converters are connected in series).

[0252] Of course, various methods can be applied to derive and calculate t_on using different computational models by the control circuit pC, in order to ultimately ensure the sinusoidal current draw l_in from the grid.

[0253] One method for the simple determination and control of t_on is to use the classic t_on control from known PFC circuits for the slow regulation of the voltage at C_P2 or at P2. This slow voltage regulation yields a preliminary t_on1. To determine t_on, this t_on1 is multiplied by the normalized curve for t_on as shown in Fig. 7. This multiplication then results in the desired curve for t_on as shown in Fig. 7 and simultaneously provides the voltage regulation of the voltage at C_P2.

[0254] Alternatively, the appropriate switch-on time t_on for each point in time or phase within the mains half-wave and for each operating state of the circuit can be determined by offline measurements in the laboratory or by calculations and provided as lookup tables or conversion tables in the control circuit pC. During operation, the control circuit pC then retrieves the appropriate values ​​for t_on from the lookup tables according to the current time or phase angle, the current output power, the current switching times t1 and t2, and depending on other relevant electrical quantities such as the input voltage U_in. The voltage regulation for controlling the voltage at C_P2 is described below.

[0255] The charge balance from the charging of C_P2 and the discharging of C_P2 must be given as a time average, so that on average the charge Q is on 2024PF00026

[0256] 37

[0257] C_P2 remains approximately constant. This is the condition for the voltage across C_P2, i.e., the potential P2, to remain approximately constant on average over several mains half-cycles. With a mains voltage U_in = 230V AC, this would ideally be approximately 370V.

[0258] The classic method for regulating the voltage of C_P2 is commonly used in boost converters with PFC functionality. It is also the preferred method in the circuit described here and is described below.

[0259] If the capacitor C_P2 discharges too much, the amplitude for the sinusoidal current draw from the mains is slowly increased by means of a suitable slow voltage regulation for the voltage at C_P2.

[0260] If capacitor C_P2 discharges too little, the amplitude of the sinusoidal current draw from the mains is gradually reduced by means of a suitable slow voltage regulation of the voltage across C_P2. Conversely, if C_P2 charges too much, the control circuit automatically and gradually reduces the voltage across C_P2 by slowly decreasing the amplitude of the sinusoidal current draw of the input current l_Boost_in. This means that the control circuit, by changing the clock frequency or reducing the on-time t_on of the switch PFC_SW, slowly and steadily reduces the input current l_Boost_in of the first converter PFC over approximately 5 to 20 mains half-cycles.

[0261] The PFC_SW switch is controlled by a control circuit (pC), such as a microcontroller, which nowadays typically controls the entire circuit arrangement, including the converter switches (SW_P2, HBL, HBH) and measures the relevant voltages and currents within the circuit to enable control. The control circuit (pC) has high-resolution timers to activate the switches at the correct times, i.e., to turn them on and off. It also determines the correct time for turning the converter switches PFC_SW, HBH (via a high-side driver HSD1), and HBL on and off in resonant mode using a ZVS input (Zero Voltage Switching input, 2024PF00026).

[0262] 38

[0263] (usually a comparator). This ZVS input is advantageously available separately for each converter stage, i.e., separate ZVS inputs exist for the first converter PFC and for the second converter HB.

[0264] For all time intervals Tsa, Tp, Tsb (and the following half-periods), the following applies: The sum of the average currents in the two converter input branches (i.e., l_Boost_in + l_D_P1) satisfies the conditions for the sinusoidal current draw of the circuit arrangement from the grid. I_D_P1 is the current in the current path of diode D_P1. The applicable regional guidelines for grid harmonics, power factor, and THD are observed.

[0265] Fig. 6 shows a representation of one half-wave of the mains input current l_in with other important current waveforms of the circuit arrangement. It should be noted that the mains input current is shown here in an idealized form, i.e., it has a desired waveform that should be achieved as closely as possible by the technical measures described here. A representation of a derivative of the real input current can be found in Fig. 8, denoted by l_L_FIL1.

[0266] The current l_Boost_in represents the input current of the first converter over the mains half-wave. The current l_Buck_in represents the input current of the second converter over the mains half-wave. The current l_out is the constant output current at the load.

[0267] The sum of the instantaneous values ​​of the currents l_Boost_in and l_D_P1 (not shown) approximately replicates the sinusoidal waveform of the mains half-wave. The sum of the average values ​​of these currents yields the input current l_L_F IL_1, which can be seen in the lower section of Fig. 8. Fig. 8 shows the representation of other important voltage and current curves over a half-wave of the mains input voltage. At the top is the inductor current l_L_B of the inductor of the second converter HB, below which are the voltages at potential P1 and the input voltage U_B_Bus of the second converter. Below that is the inductor current l_L_PFC of the inductor of the first converter. At the very bottom is the current through the input filter l_L_FIL1, which is essentially the same as the input current l_in.

[0268] 39

[0269] Figure 6 shows the signal-off current l_HR. The current l_Boost_in, which is reduced from HB_in to potential P1 shortly after switching at t1, advantageously does not go all the way to 0 (which would also be possible). This allows for some flexibility in the form of a signal-off current (l_HR) for controlling l_Boost_in, thus simplifying its control. It is also possible to control l_HR to 0, but this has disadvantages, such as making the control of l_Boost_in more complex and the THD value tending to worsen. An advantageous range for the signal-off current is approximately 5% to 30% of the maximum current draw of the circuit from the mains, i.e., approximately 5% to 30% of the maximum value of l_in.

[0270] The time intervals Tsa, Tp, and Tsb are described in more detail below. All current and voltage curves in Figures 5, 6, 7, and 8 are relevant for this purpose.

[0271] Time period Tsa

[0272] The switch SW_P2 is permanently conductive during the time interval Tsa.

[0273] Tsa goes from t = Oms to the first switching time t1.

[0274] During time interval Tsa, the first converter PFC operates in boost mode. Here, PFC_SWals acts as a boost switch in high-frequency switching mode of approximately...

[0275] 20kHz...800kHz on the intermediate circuit voltage and thereby charges the capacitor C_P2.

[0276] The input current into the first converter PFC is regulated and controlled by the control circuit pC to such an extent that, for the time interval Tsa, the current consumption for the first converter results in the desired sinusoidal input current l_in.

[0277] The voltage U_B_Bus at the buffer capacitor C_Buf essentially corresponds to the voltage at the second potential P2, i.e., the voltage across the buffer capacitor C_P2.

[0278] Simultaneously, capacitor C_P2 (and the capacitor C_Buf connected in parallel during this time period) is discharged by the second converter HB. 2024PF00026

[0279] 40

[0280] The discharge current that the second converter HB draws from capacitor C_P2 is greater than the charging current that the first converter PFC supplies to capacitor C_P2. Therefore, C_P2 is discharged during Tsa.

[0281] Time period Tp

[0282] SW_P2 is permanently locked during the time interval Tp.

[0283] The time interval Tp extends from the first switching time t1 to the second switching time t2. These two switching times were also simply described above as times t1 and t2.

[0284] During time interval Tp, the first converter PFC operates in boost mode. Here, PFC_SW functions as a boost switch in high-frequency switching mode of approximately...

[0285] 20kHz...800kHz to the intermediate circuit voltage at potential P2 and thereby feeds (charges) the capacitor C_P2.

[0286] In contrast to Tsa, however, the input current l_Boost_in to the first converter PFC is greatly reduced.

[0287] The current is only large enough to complement the input current l_in (at the input terminals L, N), so that the input current l_in becomes sinusoidal. This represents the classic power factor correction condition.

[0288] The input current into the first converter PFC is regulated and controlled by the control circuit pC to such an extent that, for the time interval T p, the combined current consumption for the first converter and for the second converter exactly results in the desired sinusoidal input current l_in.

[0289] This means that the sum of the average values ​​of the two converter input currents fulfills the conditions for the sinusoidal current draw of the input current l_in from the mains during the time interval Tp. The average value here, as defined above, is only a slightly averaged instantaneous value that merely averages out the clock cycles of the two converters, in particular the first converter PFC. 2024PF00026

[0290] 41

[0291] The voltages across the two buffer capacitors C_P2 and C_Buf are decoupled. Capacitor C_P2 is charged to the second potential P2 (~370V), while capacitor C_Buf is charged to the first potential P1, which essentially corresponds to the instantaneous value of the mains voltage. Since capacitor C_Buf has significantly less capacitance than capacitor C_P2, its voltage will rapidly drop to the value at potential P1 shortly after switching at time t1.

[0292] Time period Tsb

[0293] SW_P2 is permanently conducting during the time period Tsb.

[0294] Tsb runs from the switching time t2 until the end of the sine half-wave at t=10ms. The input of the second converter HB is switched back to the second potential P2 by SW_P2.

[0295] The operation during time interval Tsb is essentially identical to Tsa. Tsb and the operation are almost mirror-symmetrical to the imaginary center axis of the sine half-wave, except for slight differences in the voltage across C_P2. This means that, as always with power factor correction, the voltage across C_P2 is phase-shifted, i.e., lagging behind the charging current of C_P2.

[0296] The time periods following TSB

[0297] The time intervals following Tsb and the associated operation of the two converters PFC and HB result, as described for Tsa to Tsb, from the periodic continuation of the time intervals Tsa to Tsb in the next sine half-wave and so on.

[0298] Of course, the sections Ts and Tb can also alternate more often in a half-wave if special boundary conditions require this.

[0299] The use of the small storage capacitor C_BUF at the input of the second converter HB is optional but highly recommended. The capacitor 2024PF00026

[0300] 42

[0301] C_BUF is partially discharged when SW_P2 is switched. This can cause losses. Therefore, the capacitor is chosen to be as small as possible. Capacitor C_BUF thus has a relatively low capacitance. The capacitance is designed so that the voltage U_B_Bus across the capacitor increases by the following values ​​when the converter choke L_B of the second converter is fed back:

[0302] Advantageously, the voltage across capacitor C_BUF increases by approximately [amount missing] during backfeeding.

[0303] 3V...150V; particularly advantageously, the voltage across capacitor C_BUF increases by approximately 5V...50V during feedback. A favorable capacitance value for C_BUF is approximately 2.2nF to 22nF, based on a nominal output power of 50W for the circuit arrangement.

[0304] Avoidance of excessively low separation voltage U_HR and avoidance of audible switching frequencies.

[0305] The switching times at t1 and t2 are adapted by the control circuit depending on the operating conditions – e.g., input and output voltage and output current, for example, during dimming – so that sufficient separation voltage U_HR is always available for the first and second converters, typically at least 10V to 40V, and that audible switching frequencies and noise are minimized. The optimization rule that the switching frequency is always greater than 20kHz is applied here, at least at high converter currents. If the separation voltage U_HR becomes too low, the first switching time t1 must occur later and the second switching time t2 earlier. This can be clearly seen in Fig. 5, where the separation voltage U_HR is shown.

[0306] Control of switch SW_P2: Switch SW_P2 can be controlled using a known HSD2 control circuit for so-called top-mounted or high-side switches. Commercially available high-side drivers can be used for this purpose. Since the switch is turned on and off at a very low frequency, it can be turned on and off relatively slowly. Therefore, it requires 2024PF00026 for charging and discharging.

[0307] 43

[0308] Its gate requires very little current. A current in the range of approximately 0.5 mA to 50 mA is sufficient. Therefore, there are also some simpler and cheaper methods for controlling its gate, for example, using an inexpensive, slow optocoupler or, alternatively, a controlled charge pump. A simple and cost-effective implementation for gate control of switch SW_P2 using an optocoupler is shown in Figure 12.

[0309] Fig. 9 shows the voltage and current curves of Fig. 8 in a higher temporal resolution section at time t1 of the first switching in the half-wave of the mains input voltage U_in. In this figure, the voltage shown is not the mains input voltage U_in, but the voltage U_P1 at potential P1, i.e., the rectified mains input voltage, which, however, makes no significant difference in the positive half-wave of the mains input voltage U_in considered so far.

[0310] The switching frequency of the second converter HB over the half-wave of the mains input voltage has not yet been discussed. In the time interval shown in Fig. 9, it is clearly visible that the frequency before switching from potential P2 to potential P1 is significantly higher than after switching. The frequency of the inductor current l_L_B of the second converter HB before switching is approximately 110 kHz, and the frequency after switching is approximately 50 kHz. The frequency of the inductor current l_L_PFC of the first converter PFC is approximately 50 kHz before switching and 270 kHz after switching. To reduce the same power from a higher input voltage, the buck converter must operate at a significantly higher frequency than when it has to supply the power from a lower input voltage. This also explains the higher losses in conventional operation from the DC link voltage, i.e., from potential P2.It is also good to see that the rapid switching from the high potential P2 to the lower potential P1 does not pose a particular challenge for the second converter HB; the converter or the control circuit pC handles this without any problems. Fig. 4 shows a second embodiment of the circuit arrangement with a boost converter as a power factor corrector and a flyback converter to the 2024PF00026.

[0311] 44

[0312] Operating the load. Apart from this difference, the circuit arrangement is unchanged from Fig. 3; therefore, only the differences from the first embodiment are described below.

[0313] A flyback converter is used instead of a buck converter whenever the circuit arrangement as a whole is to meet the criteria of EN 61558 or IEC 61558, i.e., the output must be galvanically isolated from the input. This normally requires a transformer, which is then advantageously integrated into a flyback converter as a second converter HB. As shown in Fig. 4, the converter in the second embodiment is a flyback converter.

[0314] Similar to the buck converter, the flyback converter is controlled in such a way that it regulates the output current in the load or in the LED module to the desired current value.

[0315] Instead of the converter choke L_B of the first embodiment, a transformer T1 is provided for the second converter HB, and instead of the switch HBH of the first embodiment, a converter diode D_HB is provided. The output capacitor C_B and the filter choke L_FIL3, however, remain the same as in the first embodiment. Since the operation of a flyback converter is well known, a more detailed description is omitted here. The control strategy of circuit arrangement 1 will now be discussed, and in particular the strategy for the first converter PFC, as this is essential for its operation. There are basically two different control strategies, one somewhat simpler and one somewhat more complex. Depending on the application of circuit arrangement 1, one of the two control strategies can be selected.

[0316] The simple control concept is as follows: The control circuit pC defines the switching times using the switching conditions 1 and 2 described above, so that the phase angle of the switching times t1, t2 is suitable for all load voltages U_out. During operation, the phase angle is then not adjusted by the control circuit pC, or only within a small range. 2024PF00026

[0317] 45

[0318] The gap current l_HR (Fig. 6) during the current through the choke L_PFC of the first converter PFC in the time interval Tp is controlled by the control circuit for approximately...

[0319] The mains input current U_in is gradually increased and decreased over 5 to 500 half-cycles by a slow-acting control system to keep the current step of the mains input current U_in as small as possible at the switching times t1 and t2. This ensures an optimally low THD value and low mains harmonics for circuit arrangement 1. The offset current l_HR is not regulated to 0 during the time interval Tp, so that a current reserve always remains. This means that the minimum offset current includes a current reserve of, for example, 10% of the maximum current of the first converter PFC, so that the average current through the inductor L_PFC never reaches 0 mA during switching, thus preventing any step in the input current l_Boost_in of the first converter PFC even in the event of control deviations or inaccuracies. The voltage across the buffer capacitor C_P2 is regulated similarly to a classic power factor correction via the amplitude of the sinusoidal current draw.

[0320] The more complex control concept is used, for example, at high output voltages U_out. At high output voltages U_out, or also at low mains input voltages U_in, t1 is shifted "right," for example, to t1 = 3 ms instead of the previous t1 = 2.6 ms. Correspondingly, t2 is shifted symmetrically "left" (t2 = 7 ms instead of t2 = 7.4 ms). This increases the minimum voltage at the input HB_in of the second converter HB when it switches to the potential P1 downstream of the rectifier. This ensures that the second converter HB receives sufficient voltage and sufficient signal-to-noise ratio U_HR. The power loss savings in the first converter PFC are therefore slightly reduced, resulting in a slightly lower overall efficiency of the circuit arrangement.

[0321] Under certain extreme boundary conditions, such as a very high output voltage U_out or an extremely low mains input voltage U_in, the switching from series to parallel operation of the two converters PFC, HB of the circuit arrangement can also be completely abandoned, which then puts the circuit arrangement into the so-called "classic mode"2024PF00026

[0322] 46

[0323] The circuit operates in a manner already known from the prior art. In special operation in "classic mode," the circuit arrangement functions like a classic circuit arrangement; that is, the bypass path is inactive, and the second converter is powered exclusively by the second potential P2, which in turn means that the switch SW_P2 is permanently conducting. This operation largely corresponds, as described above, to the operation of a classic two-stage circuit arrangement with a boost converter followed by a buck converter.

[0324] In another "special operating mode," the time interval Tp is shortened, and the first switching point t1 is shifted "right," meaning it occurs later, while the second switching point t2 is shifted "left," meaning it occurs earlier. This increases the minimum voltage at the input of the second converter HB when it switches to the first potential P1. As a result, the second converter HB receives sufficient voltage and sufficient differential voltage. In terms of power loss, this operating mode falls between regular and conventional operation.

[0325] Operating with a shortened time interval Tp can also be advantageous with reduced output current or reduced output power, in order to increase the spacing current and thus simplify the control or to keep the switching frequencies in the boost converter in the advantageous range or to limit the switching frequency upwards, since otherwise excessively high switching losses would occur.

[0326] The control circuit pC may also have other special control strategies implemented. For example, if the input voltage U_in drops, operation can be immediately terminated for the time interval Tp, and the second converter HB can be switched back to the second potential P2, since the buffer capacitor C_P2, with its large capacitance, can bridge the voltage drop for some time. The same strategy can be applied in the event of a current drop in the output current l_out to ensure high-quality, uniform, and continuous light output. If the voltage or current drops at the input or output occur again, the circuit can be switched back to the second potential P2.

[0327] 47

[0328] Once they disappear, the control circuit pC can return to normal operation.

[0329] Fig. 10 shows a third embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load, as well as a first sensor as a current step sensor for detecting current steps at the mains input. The first sensor is based on a simple optocoupler. If, during switching at times t1 and t2, the input current U_in is not completely continuous, i.e., contains a current step, then this current step generates a step response at the EMI input filter L_Fil1, L_Fil2, CN of the circuit arrangement. This step response can be evaluated using the current step sensor.

[0330] With the aid of the current step sensor, the control circuit pC can minimize the step in the input current U_in during switching. This optimization is achieved in the control circuit pC through a slow or iterative optimization, adaptation, or readjustment of parameters such as the switch-on time t_on when the switch-on time t_on of the boost converter changes abruptly at times t1 and t2. "Slow" here means that this optimization takes place over several mains half-cycles, ideally over 5 to 500 half-cycles.

[0331] The parameters are continuously adjusted and optimized by the control circuit pC until the output signal of the current step sensor is minimized. This also minimizes the current jump in the input current.

[0332] The signal is tapped directly at the input filter at terminals SE1 A and SE1 B. These terminals correspond to the terminals of the first mains filter L_Fil1. The signal can also be tapped analogously at the terminals of the second mains filter L_Fil2.

[0333] The signal passes through a high-pass filter consisting of components C_S1, R_S1, R_S2, and R_S3. Following the high-pass filter is a simple optocoupler for galvanic isolation, whose output, Sens, is connected to the control circuit, pC. The current signal from the 2024PF00026 is output at the Opto output of the optocoupler.

[0334] 48

[0335] The transistor of the optocoupler Opto is converted into an output voltage using R_S4. The control circuit pC can then, for example, use an A / D converter to evaluate the signal Sens and optimize the step response, and thus the current step during switching, as described above. Since the control is based on a step response, the quality of the optocoupler is not critical, and a relatively slow and inexpensive optocoupler can be used. Because the control circuit pC knows the switching time, it can start the current step sensor measurements shortly before and stop them shortly after the switching time. This saves valuable processing power and eliminates any parasitic effects at the current step sensor.

[0336] Fig. 11 shows a fourth embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load, as well as a second sensor for detecting current jumps at the mains input. The second sensor here has an inductor L_Fil 1 B for coupling out the step response.

[0337] L_Fil 1 B is the inductance of the auxiliary winding on the EMI choke L_Fil 1. It has an inductive coupling to L_Fil1. The rectification and filtering of the coupled current-stage sensor signal is performed by R_S5, D_S1, C_S2, and R_S6. The filtered output signal Sens is again present at the output of the second sensor. The output signal is evaluated by the control circuit pC in the manner already described above.

[0338] Fig. 12 shows a fifth embodiment of the circuit arrangement with a boost converter as a power factor corrector and a half-bridge buck converter as a second converter for operating the load, as well as a third sensor for detecting current steps with capacitive coupling to point SE1B at the mains input. In this embodiment, neither an optocoupler nor an auxiliary winding on the EMI choke L_Fil1 is necessary, making this embodiment very inexpensive to manufacture. The signal is tapped at point SE1B downstream of the EMI choke or filter choke L_Fil1 and then passes through a high-pass filter consisting of components C_S3 and R_S8. The resistor R_S7 serves to limit the current of the step response to the 2024PF00026

[0339] 49

[0340] To protect the output and components from excessive currents, diode D_S3 and capacitor C_S4 form a sample & hold circuit that stores the maximum value of the sampled signal. This signal is then divided by a voltage divider consisting of resistors R_S9 and R_S10 to a voltage preferred by the control circuit pC. This voltage is then fed into the control circuit pC via the Sens output and evaluated as described above. Diode D_S2 ensures that the negative step response of the sampled signal also flows into the sample & hold circuit, thus amplifying the signal and making it easier to evaluate. This diode also protects the Sens output from overvoltages by connecting them to circuit ground (GND).Another diode can be connected to a different fixed potential in circuit arrangement 1, for example, to an auxiliary power supply, to better protect the positive signals from overvoltage. It should be noted that all diodes can be inexpensive small-signal diodes that do not need to block particularly high voltages. They can, for example, meet the 1N4148 specification, which is very inexpensive. Capacitor C_S3 can, for example, be a ceramic capacitor with a specified voltage of 630V to withstand voltage spikes such as surge pulses. R_S7 is also a resistor with a good voltage rating; it can, for example, be used in a Minimelf package. This design allows the third current-level sensor to be built particularly cost-effectively.

[0341] Fig. 13 shows the first embodiment with the driver HSD2 for controlling the switch SW_P2 of the bypass branch in an embodiment with two cascaded bootstrap diodes D_T1 and D_T2 for providing the auxiliary voltage VCC_C_SW and with an optocoupler for galvanic isolation and for switching the switch SW_P2 on and off. The driver consists of an optocoupler, a decoupling capacitor C_SW, a coupling capacitor C_HBM, and two diodes D_T1 and D_T2. The output of the optocoupler with its phototransistor is connected between the gate and the source of the MOSFET SW_P2 to control it. A series connection of resistor R_T1 and decoupling capacitor C_SW is connected in parallel to the output of the optocoupler. The coupling point of the 2024PF00026

[0342] 50

[0343] The cathode of diode D_T2 is connected to resistor R_T1 and the decoupling capacitor C_SW. Its anode is connected to the cathode of diode D_T1 on one side and to one terminal of capacitor C_HBM on the other. The anode of diode D_T1 is connected to an auxiliary voltage supply VCC_12V. The other terminal of capacitor C_HBM is connected to the midpoint of the half-bridge of the second converter HB.

[0344] The function of the HSD2 driver circuit is as follows:

[0345] When the lower transistor HBL of the half-bridge is switched on and the upper transistor HBH is switched off, the capacitor C_HBM is charged to 12V by the auxiliary voltage supply VCC_12V, since the auxiliary voltage supply VCC_12V is referenced to circuit ground. When the half-bridge is switched, the midpoint of the half-bridge jumps to the potential HB_in, and—since diode D_P1 is conducting—thus to the potential P1. At point VCC_C_SW, the 12V of capacitor C_HBM is present, because diode D_T2 is conducting and diode D_T1 is reverse-biased. When the optocoupler Opto is switched on by the control circuit pC via its two inputs pC1 and pC2, the 12V of capacitor C_HBM is present at the gate of MOSFET SW_P2, and the transistor switches on.The decoupling capacitor C_SW is also charged to 12V, so that the MOSFET SW_P2 remains switched on even when the half-bridge switches again, and the midpoint is then back at the potential of the circuit ground GND. This is because diode D_T2 then blocks, and capacitor C_SW retains its charge, while capacitor C_HBM is recharged to the 12V of the auxiliary power supply VCC_12V. In the next cycle, the decoupling capacitor C_SW is then recharged by capacitor C_HBM.

[0346] Since the SW_P2 switch does not need to be switched quickly, the HSD2 driver does not need to switch it quickly either. Because the optocoupler only operates in saturation mode here, the linearity of its characteristic curve is irrelevant, and aging effects are also negligible. Therefore, a particularly simple and cost-effective optocoupler, such as Opto.2024PF00026, can be used.

[0347] 51

[0348] Fig. 14 shows a sixth embodiment of the circuit arrangement, which is similar to the first embodiment but uses a converter switch in parallel with the bypass branch switch. Here, the MOSFET SW_P1 is used as an alternative high-side converter switch of the half-bridge. Depending on whether the time interval Ts or Tp is active, either the switch HBH or the switch SW_P1 acts as the upper converter switch. The switch HBH is permanently connected to the second potential P2, and the switch SW_P1 is permanently connected to the first potential P1. To prevent unwanted current flows from potential P2 to the lower potential P1, the diode D_P1 is still necessary as a blocking diode due to the intrinsic diode of the MOSFET SW_P1.In "classic" operation with the first converter PFC and the second converter HB connected in series, the MOSFET SW_P1 is permanently switched off, and the MOSFET HBH acts as the upper converter switch, periodically coupling the potential P2 to the midpoint of the half-bridge. As explained several times already, this occurs during the time interval Ts and thus in the sub-intervals Tsa and Tsb. During the time interval Tp, the MOSFET HBH is permanently switched off, and the MOSFET SW_P1 is used as the upper half-bridge transistor, periodically switching the midpoint of the half-bridge to the potential P1. Since the MOSFET HBH is switched off, the diode D_P1 then conducts.

[0349] This embodiment has the advantage of somewhat lower losses in the series operation of the two converters PFC and HB, but has the disadvantage of a more complex control of the MOSFET SW_P1, since it now has to be driven quickly, and a more complex high-side driver than the one in Fig.

[0350] The 13 described above must be used.

[0351] Fig. 15 shows a seventh embodiment of the circuit arrangement, similar to the first embodiment according to Fig. 3, but instead of the natural diode D_P1 as a switch, it uses an N-channel MOSFET SW_P1, whose intrinsic diode is oriented in the same direction as the natural diode D_P1 was previously. Since an N-channel MOSFET is used here, it must be connected so that its drain is connected to the potential HB_in, while its source is connected to the first potential P1. As can be clearly seen in Fig. 15, a different symbol for the MOSFET 2024PF00026 was intentionally used here.

[0352] 52

[0353] SW_P1 was chosen to show the intrinsic diode inherent in every classic MOSFET, making the circuit diagram easier to see. The MOSFET SW_P1 is therefore essentially "upside down". 1 interconnected, which is rather unusual, which is why it is explicitly pointed out here.

[0354] Since a high-side driver is required for an N-channel MOSFET, this has also been added as driver HSD3 in Figure 15. The control circuit pC therefore requires one additional output for the third high-side driver HSD3. This can, however, be implemented as a simple, slow-switching driver, as already explained in relation to Figure 13. A simple bootstrap circuit with cascaded diodes D_T1 and D_T2 and a simple optocoupler is also perfectly adequate here.

[0355] Fig. 16 shows an eighth embodiment that combines the sixth and seventh embodiments to eliminate the natural diode D_P1. Here, the circuit arrangement of the sixth embodiment in Fig. 14 is modified such that the MOSFET SW_P1 is also connected "upside down" to utilize its intrinsic diode. However, unlike Fig. 15, the drain of the MOSFET SW_P1 is now connected to the center point of the half-bridge of the second converter HB, i.e., to the drain of the MOSFET HBH and a terminal of the converter choke L_B.

[0356] This allows the intrinsic diode of the MOSFET SW_P1 to function as desired, and diode D_P1 can be omitted. This embodiment therefore exhibits further improved efficiency, as the losses at diode D_P1 are eliminated. Since the intrinsic diode of the MOSFET SW_P1 only conducts very briefly during the dead times when the MOSFET SW_P1 is either not yet switched on or already switched off, the losses due to the intrinsic diode are negligible. Because the majority of the current l_D_P1 is carried by the switched-on MOSFET SW_P1, the efficiency is improved compared to the sixth embodiment. However, as already mentioned in relation to the sixth embodiment, a fast high-side driver HSD2 is necessary here, as the MOSFET SW_P1 must be switched quickly since it now also functions as a converter transistor. 2024PF00026

[0357] 53

[0358] Fig. 17 shows a ninth embodiment of the circuit arrangement, based on the first embodiment shown in Fig. 3, but with a modification in the bypass branch. This variant consists of omitting diode D_P1 and replacing it with two additional mains rectifier diodes, D_N and D_L, connected in parallel to the inputs of rectifier BR. The anodes of these diodes D_N and D_L are each connected to the AC inputs PWa and PWb of rectifier BR (i.e., to the junction between DR1 and DR3, and DR2 and DR4, respectively). The cathodes of diodes D_N and D_L are connected to the input HB_in of the second converter HB, forming a parallel upper rectifier branch that acts in place of diode D_P1.

[0359] The key advantage of this embodiment is that the forward voltage drop occurs only once across the rectifier diodes D_N and D_L. The additional forward voltage drop across diode D_P1 is eliminated in this variant, further reducing losses and improving the overall efficiency of the circuit. It is essential to ensure sufficient buffer capacitance (C_BUF) to filter the buck-ripple current at the input of the second converter (l_Buck_in) to guarantee good electromagnetic compatibility (EMC). Furthermore, it is important that the RF ripple current generated by the converter switching remains below EMC limits at the mains terminals and in the mains current. This can be achieved with an additional buffer capacitor, C_B2.

[0360] The bypass dual-rail circuit has the advantageous property that the ripple currents of the input currents of the two converters (PFC and Buck HB) superimpose favorably during the time interval Tp, largely canceling each other out or compensating for each other. This results in low ripple currents before and after the rectifier, and consequently, a small remaining effective ripple current at the line terminals, which significantly simplifies EMC handling. In particular, the ripple currents from the buck and PFC superimpose favorably during the time interval Tp because they have different frequencies and phase angles. This is due to the fact that both converters are individually clocked (among other things, according to ZVS criteria) and are also clearly [2024PF00026]

[0361] 54

[0362] The converters are clocked at different frequencies. The "antibody" of one ripple is often compensated for by the "trough" of the other, similar to an interleaved PFC. This results in a frequency distribution and a reduction in the amplitude of the two RF current ripples from the buck converter and PFC. Another advantage is that the first converter, the PFC, is clocked at a significantly higher frequency (approximately 1.5 to 3 times higher) than the second converter, the HB (buck converter), during the time interval Tp. This allows for a further reduction in the effective buffer capacitance.

[0363] Fig. 18 shows a tenth embodiment of the circuit arrangement, which is also based on the first embodiment according to Fig. 3, but incorporates an extended bypass path. This bypass path includes an additional switch SW_BP2 and an additional diode D_BP2. The diode D_BP1 remains connected to the input (HB_in) of the second converter HB. The diode D_BP2 is connected to the junction of the converter inductor L_PFC and the converter switch PFC_SW of the first converter.

[0364] In this configuration, diode D_BP2 acts as a converter diode for the first converter (PFC) by carrying its converter current while this bypass branch is activated. Switch SW_BP2 then directs this current to the output capacitor C_B of the second converter. During this bypass phase, the output capacitor C_B of the second converter is thus treated in the same way as the output capacitor C_P2 of the first converter during the remaining time periods. The actual converter diode D_PFC and diode D_BP2 are equivalent in this configuration, with D_BP2 acting as a converter diode only during the bypass period, whereas D_PFC functions as the converter diode of the first converter during the remaining time. In principle, the first converter has two outputs: the output where capacitor C_P2 is connected in parallel, and the output where capacitor C_B is connected in parallel.However, since the SW_P2 switch is permanently switched off in this operating mode, the converter does not output any power at the output of the capacitor C_P2, but only stores it, which is why, according to the definition of a 2024PF00026 formulated at the beginning.

[0365] 55

[0366] "Output" means this branch is not an output, as it does not deliver any power in this part of the half-wave.

[0367] Bypass mode 1 (BP1): This refers to the operating mode in which the inputs of the first converter (PFC) and the second converter (HB) are connected in parallel, typically by switching off switch SW_P2, to connect the first converter (PFC) directly to the first potential (P1) and the second converter (HB) also to the first potential (P1) via diode D_P1. This mode is used during the time interval Tp when the input voltage U_in is greater than the output voltage U_out.

[0368] This circuit arrangement allows the implementation of a bypass mode 2 (BP2), which can be used as an alternative to the bypass mode 1 (BP1) of the preceding embodiments. Both bypass modes, BP1 and BP2, are activated within the same time interval Tp, which lies in the middle of the mains half-cycle and is bounded by times t1 and t2, as shown in Fig. 5 and Fig. 19. The control circuit pC is configured to decide, based on a comparison of the input voltage U_in and the output voltage U_out, which of the two bypass modes is used during the time interval Tp.

[0369] • If the input voltage U_in is greater than the output voltage U_out, bypass mode 1 (BP1) is used, in which the inputs of the first converter (PFC) and the second converter (HB) are connected in parallel (e.g. by turning off switch SW_P2).

[0370] • If the input voltage U_in is lower than the output voltage U_out, bypass mode 2 (BP2) is used, in which the second converter (HB) is bypassed or bridged. This mode is particularly advantageous when the required output voltage U_out is very high, so that the voltage generated by the boost converter (PFC) can be used directly as the output voltage.

[0371] The energy behavior of the circuit arrangement over one mains half-cycle is as follows: The output power P_out always corresponds to the input power P_in minus the losses of the circuit arrangement, which2024PF00026

[0372] 56

[0373] The excess power is typically around 5%. In both bypass modes, i.e., during the time interval Tp, the instantaneous input power P_in is greater than the instantaneous output power P_out, as illustrated in Figure 19. The excess power must therefore be temporarily stored within the circuit. This is primarily done in the electrolytic capacitor C_P2, which absorbs this excess power during the time interval Tp and releases it again during the time intervals Tsa and Tsb, when the input power P_in is less than the output power P_out. During the time interval Tp, a portion of the input power P_in is directly routed to the output, and an excess portion of the input power P_in is stored in the capacitor C_P2. This is achieved by actively clocking the switch SW_BP2 at a high frequency.When switch SW_BP2 is closed, diode D_BP2 acts as a converter diode for the first converter PFC, and the first converter PFC operates on capacitor C_B. Diode D_PFC is non-conducting due to the higher potential of P2. When switch SW_BP2 is open, the current path l_BP2 is interrupted, and diode D_BP2 is reverse-biased. Diode D_PFC is then active and operates as usual as a converter diode on capacitor C_P2.

[0374] During time period TP, the switch SW_BP2 is clocked at a high frequency using pulse-width modulation, so that the duty cycle defines the distribution of the transferred energy between the two capacitors C_P2 and C_B. Thus, during time period TP, a portion of the energy bypasses the second converter HB and is supplied directly to the output via capacitor C_B. During time periods Tsa and Tsb, the entire input power P_in is delivered to the output, and another portion of the output power is drawn from capacitor C_P2.

[0375] The integration of this second bypass mode (BP2) contributes to the further flexibility and efficiency of the overall arrangement by avoiding unnecessary conversion losses in the second converter HB under certain load and voltage conditions. Switch SW_BP2 is controlled as an active switch, while D_BP2 serves as the converter diode of the first converter PFC, particularly when U_in < U_out.

[0376] 57

[0377] Fig. 19 shows the power waveforms P_in and P_out as well as the voltage waveform U_in over a network half-cycle of 10 ms. The dashed curve U_in represents the instantaneous input voltage, which serves as a reference for the operating phases. The solid curve P_in represents the instantaneous input power drawn from the network, while the dashed horizontal line P_out represents the constant output power delivered to the load (5).

[0378] The figure illustrates the three essential time periods within a network half-wave: Tsa, Tp, and Tsb. Time t1 marks the beginning of time period Tp, in which the bypass mode is activated, and time t2 marks the end of time period Tp, at which the bypass mode is deactivated again.

[0379] During the time interval Tp, the input power P_in is significantly greater than the output power P_out. The difference between P_in and P_out during this period represents the excess energy that is absorbed and temporarily stored by the circuit. This excess energy is primarily stored in the electrolytic capacitor C_P2.

[0380] • In bypass mode 1 (BP1), as shown in Figures 3, 4, and 10 to 16 and explained in Figures 5 to 9, the area below the output power P_out during the time interval Tp is interpreted as the energy that bypasses the first converter (PFC) and is routed directly to the second converter (HB) and thus to the output. The area above the output power P_out but below the input power P_in represents the energy that is temporarily stored by the first converter (PFC) in the electrolytic capacitor C_P2.

[0381] • In bypass mode 2 (BP2), as shown in Figure 18, the area below the output power P_out during the time interval Tp represents the energy that is directly bypassed to the output, bypassing the second converter (HB). The area above the output power P_out, but below the input power P_in, is the energy that is temporarily stored in the electrolytic capacitor C_P2.

[0382] 58

[0383] where the diode D_BP2 acts as a converter diode for the first converter to supply the load, and the diode D_PFC serves as a converter diode to store the excess energy in the electrolytic capacitor C_P2.

[0384] In bypass mode 2, the switch or MOSFET SW_BP2 is clocked at a high frequency during the time interval Tp to transfer a portion of the input power P_in directly to the capacitor C_B via the bypass branch BP_2. When the MOSFET SW_BP2 is switched off, the input power P_in is stored in the electrolytic capacitor C_P2 via the diode D_PFC. The duty cycle of the MOSFET SW_BP2 ranges from 0% at time t1 to approximately 50% at a phase angle of 90°, i.e., the "midpoint" of the mains half-wave, before returning to 0% at time t2. The second converter HB remains switched off during this period.

[0385] During time intervals Tsa and Tsb, the instantaneous input power P_in is less than the constant output power P_out. During these periods, the missing energy is drawn from the buffered reservoir of the electrolytic capacitor C_P2 to maintain the constant output power P_out. This ensures a stable load supply throughout the entire half-cycle, despite dynamic fluctuations in input power. The energy flow is thus balanced over the entire half-cycle, with capacitor C_P2 acting as a buffer.

[0386] In the embodiment shown in Fig. 18, capacitor C_B is also an electrolytic capacitor to provide sufficient energy storage and to deliver high-quality, continuous output power without significant ripple. 2024PF00026

[0387] 59

[0388] Enabling characteristics:

[0389] - Use of a circuit arrangement to convert mains input power into output power for the load.

[0390] - Inputs (L, N) for inputting the mains AC voltage (U_in) and the mains AC current (l_in).

[0391] - Use of a rectifier (BR) to rectify the mains AC voltage (U_in) and provide a first potential (P1).

[0392] - Implementation of a first converter (PFC) that operates as a power factor corrector (PFC) and is coupled to the first potential (P1).

[0393] - Coupling of a capacitance (C_P2) of the first converter with its output to generate an intermediate circuit voltage (P2).

[0394] - Provision of output power by a second converter (HB) at its output (LO+, LO-) to supply the load.

[0395] - Possibility to connect the inputs (PFC_in, HB_in) of the first and second converters in series in a first sub-range (Ts) of the mains half-wave.

[0396] - Parallel operation of the inputs (PFC_in, HB_in) or the outputs in a second sub-area (Tp) of the mains half-wave, wherein both inputs are coupled to the first potential (P1) or both outputs are coupled to the output of the circuit arrangement 1.

[0397] - Possibility of bridging one of the two converters in a second sub-area of ​​the network half-wave to avoid conversion losses.

[0398] - Ensuring a sinusoidal waveform of the input mains alternating current (l_in).

[0399] - Addition of the input currents (l_Boost_in, l_Buck_in) of the first and second converters in the second part (Tp) of the mains half-wave to the sinusoidal mains alternating current (l_in).

[0400] - Possibility of dividing the first sub-area (Ts) into two or more sub-areas (Tsa, Tsb) for switching between serial and parallel operation. 2024PF00026

[0401] 60

[0402] - Symmetrical switching at the center of the mains half-wave, i.e. essentially symmetrical to the phase angle of 90°.

[0403] - Device for switching between serial and parallel operation on each half-wave of the mains supply.

[0404] - Use of semiconductor switches (SW_P2, D_P1) to perform the switching between the potentials (P1 , P2).

[0405] - Switching from parallel to series operation based on the current input current compared to the output current plus a predetermined offset current.

[0406] - Detection of switching based on the current AC mains voltage (U_in) compared to the voltage (U_out) at the load.

[0407] - Ensuring a sinusoidal sum of the current draw of the two currents l_Boost_in and l_D_P1 in each sub-segment of the mains half-wave. - Using a boost converter (PFC) as the first converter and a buck converter or flyback converter as the second converter (HB).

[0408] - The second converter (HB) adapts the output voltage (U_out) and output current (l_out) to the voltage and current of the LED module. - It avoids switching at very low output powers or in situations with reduced mains voltage, operating according to Ts, i.e., with the converters connected in series.

[0409] - Minimizing current jumps at the input (L, N) of the circuit arrangement during switching.

[0410] - Detection of current jumps at the mains input (L,N) by means of a signal taken or measured at the input or at an input choke.

[0411] - Use of a buffer capacitor (C_BUF) between the input terminals (HB_in, GND) of the second converter to limit high-frequency (RF) voltage ripple. 2024PF00026

[0412] 61

[0413] REFERENCE MARK LIST

[0414] U_in input network voltage

[0415] P_in input network power

[0416] P_out output power of the circuit arrangement

[0417] L phase of the grid connection

[0418] N Neutral conductor of the network connection

[0419] l_in Input current drawn from the grid l_D_P1 Current in the bypass branch

[0420] l_Boost_in current into the first converter

[0421] l_Buck_in current into the second converter

[0422] l_HR distance current

[0423] GND Circuit ground, negative output of the full-bridge rectifier

[0424] CN input capacitor, connected as an X-capacitor; L_Fil1, L_Fil2 filter chokes at the input

[0425] BR bridge rectifier made from diodes DR1..DR4

[0426] D_N, D_L Additional mains rectifier diodes for the third bypass branch (BP_3)

[0427] C_P1 decoupling capacitor for potential P1

[0428] P1 first potential, voltage at the output of the bridge rectifier BR

[0429] PFC first converter

[0430] L_PFC Converter inductance of the first converter

[0431] PFC_SW converter switch of the first converter

[0432] PFC_C control connection for the converter switch of the first converter

[0433] D_PFC converter diode of the first converter

[0434] C_P2 Output capacitance of the first converter, at whose positive terminal the second potential is located

[0435] P2 second potential

[0436] SW_P2 Semiconductor switch for activating bypass mode 1 (BP_1) SW_P2_C Control connection for the switch of the first bypass branch

[0437] SW_BP2 Additional semiconductor switch for the second bypass branch (BP_2)

[0438] SW_BP2_C Control connection for the switch of the second bypass branch

[0439] D_BP2 Additional diode for the second bypass branch (BP_2), which acts as a converter diode for the first converter (PFC) C_BUF Decoupling capacitor for the second potential

[0440] U_B_Bus voltage via C_BUF, also referred to as bus voltage or intermediate circuit voltage

[0441] D_P1 Diode for the first bypass branch (BP_1)

[0442] HB second converter, here a buck converter or flyback HBH converter switch of the second converter 2024PF00026

[0443] HBH_C Control connection for the converter switch of the second converter. HBL Synchronous switch of the second converter in the embodiment as a buck converter.

[0444] HBL_C Control connection for the synchronization switch of the second converter in the embodiment as a buck converter

[0445] L_B converter choke of the second converter in the embodiment as a buck converter

[0446] C_B converter capacitor of the second converter

[0447] D_HB Freewheeling diode / converter diode of the second converter in the flyback configuration

[0448] T1 Transformer of the second converter in the embodiment as a flyback

[0449] L_FIL3 filter choke at the output of the second converter

[0450] M C Control circuit

[0451] HSD1 High-Side Driver for the Converter Switch of the Second Converter

[0452] HSD2 High-Side Driver for the Bypass Branch Switch VCC_C_SW Auxiliary Voltage

[0453] VCC_12V Auxiliary power supply

[0454] C_SW decoupling capacitor

[0455] L0+ positive output terminal of the circuit arrangement LO- negative output terminal of the circuit arrangement U_out voltage at the output of the circuit arrangement

[0456] l_out Current at the output of the circuit arrangement

[0457] P_out output power of the circuit arrangement

[0458] LED1-LEDN LEDs as load of the circuit arrangement

[0459] 5 LED module with LEDs LED1 to LEDN arranged on it, which can be connected to the output of the circuit arrangement.

[0460] L+ positive input of the LED module 5

[0461] L- negative input of LED module 5

[0462] t1 Switch-on time for the bypass period Tp

[0463] t2 Switch-off time for the bypass period Tp

[0464] Tsa Time period before the bypass period Tp

[0465] Tp Time period of the bypass mode

[0466] Tsb Time period after the bypass period Tp

[0467] PWa AC voltage connection of the rectifier, phase (e.g.

[0468] (associated with L)

[0469] PWb AC voltage connection of the rectifier, neutral conductor (e.g. connected to N)

[0470] l_BP2 Current in the second bypass branch

[0471] BP_1 First bypass branch (coupling to P1)

[0472] BP_2 Second bypass branch (bypassing HB)

[0473] BP_3 Third Bypass Branch (Upper Rectifier)

[0474] R_SH Shunt resistor for measuring the output current HBL Converter switch of the second converter (lower switch or synchronous switch)

[0475] SW_P1 Semiconductor switch for the first bypass branch (BP_1) or converter switch of the second converter 2024PF00026

[0476] 63

[0477] SW P1 C Control connection for switch SW P1

[0478] HSD3 High-Side Driver for Switch SW_P1

[0479] SE1A, SE1B Connection points for current jump sensor

[0480] C_S1, R_S1, ... components of the current step sensor

[0481] Opto optocoupler (e.g. for current step sensor or driver) Sens output signal of the current step sensor L_FIL1B Auxiliary winding for current step detection

[0482] R_T1, D_T1, D_T2, C_HBM, pC1, pC2 Components of the HSD2 driver

Claims

2024PF00026 64 PATENT CLAIMS 1. Circuit arrangement (1) for converting a mains input power into an output voltage or output current for operating a load (5), comprising: - an input (L, N) for inputting the mains input power consisting of a mains AC voltage (U_in) and a mains AC current (l_in), - a rectifier (BR) for rectifying the mains AC voltage (U_in) and providing a first potential (P1), - a first converter (PFC) that operates as a power factor corrector at least in a sub-range of a mains half-wave, wherein an input (PFC_in) of the first converter is coupled to the first potential (P1), and a capacitance (C_P2) of the first converter is coupled to its output to generate an intermediate circuit voltage (U_P2) which represents a second potential (P2), - a second converter (HB) which provides the output power to operate the load at its output (LO+, LO-), characterized by the fact that The circuit arrangement further includes a control circuit (pC) configured to operate the converters (PFC, HB) in the following operating modes: - in a first sub-range (Ts) of a mains half-wave of the mains AC voltage (U_in) in a serial operating mode, wherein an input (HB_in, GND) of the second converter is coupled to the output of the first converter (P2, GND) and thus to the second potential (P2); and - in a second sub-area (Tp) of the mains half-wave of the mains AC voltage (U_in) in a parallel operating mode, wherein either the inputs of both converters (PFC, HB) are connected in parallel by coupling the input (PFC_in, GND) of the first converter to the first potential (P1) and the input (HB_in, GND) of the second converter either also to the first potential (P1) or via a 2024PF00026 65 separate upper rectifier branch (BP_3) is coupled to the AC voltage inputs (PWa, PWb) of the rectifier (BR), and the control circuit (pC) is configured to regulate the sum of the input currents (l_Boost_in, l_Buck_in) of both converters so that a sinusoidal mains AC current (l_in) results; or the outputs (P2, LO+) of both converters are at least temporarily connected in parallel and thus coupled to the output (LO+, LO-) of the circuit arrangement (1), wherein at least part of the input power (PJn) is bypassed at one of the two converters (PFC, HB) in order to generate the output power (P_out) and the control circuit (pC) is configured to regulate the input current (l_Boost_in) of the first converter (PFC) so that a sinusoidal mains alternating current (l_in) results.

2. Circuit arrangement (1) according to claim 1, characterized in that the control circuit (pC) is configured to switch between serial and parallel operating mode of the first and second converters during each half-wave of the mains supply.

3. Circuit arrangement (1) according to one of the preceding claims 1 or 2, characterized in that the control circuit (pC) is configured to divide the first sub-area (Ts) of the mains half-wave into two sub-areas (Tsa, Tsb) temporally at the beginning and at the end of the mains half-wave, and thus to perform a switching between serial and parallel operating mode twice in a mains half-wave.

4. Circuit arrangement (1) according to one of claims 1 to 3, characterized in that the control circuit (pC) is configured to perform the switching operations substantially symmetrically to the center of the mains half-wave, i.e. substantially symmetrically to the phase angle of 90° of the mains half-wave.

5. Circuit arrangement (1) according to any one of claims 1 to 4, characterized in that the control circuit (pC) is configured to accomplish the switching between the serial and the parallel operating mode by controlling semiconductor switches. 2024PF00026 66 6. Circuit arrangement (1) according to one or more of claims 1 to 5, characterized in that the control circuit (pC) is configured to switch from series to parallel operation when the magnitude of the current mains input current (l_in) of the mains half-wave becomes greater than the input current (l_Buck_in) of the second converter (HB) plus a predetermined offset current (l_HR), and to switch from parallel operation to series operation when the magnitude of the current mains input current (l_in) of the mains half-wave becomes less than the input current (l_Buck_in) of the second converter (HB) plus a predetermined offset current (l_HR).

7. Circuit arrangement (1) according to one or more of claims 1 to 6, characterized in that the control circuit (pC) is configured to switch from series to parallel operation when the magnitude of the current AC mains voltage (U_in) in the mains half-wave is greater than the voltage (U_out) at the load (5) plus a predetermined separation voltage (U_HR) of the second converter (HB), and to switch from parallel operation to series operation when the magnitude of the current AC mains voltage (U_in) again becomes less than the voltage (U_out) at the load plus a predetermined separation voltage (U_HR) of the second converter.

8. Circuit arrangement (1) according to claims 6 and 7, characterized in that the control circuit (pC) is configured to switch from serial to parallel operation when both conditions of claims 6 and 7 are met, and to switch from parallel to serial operation when one of the two conditions of claims 6 or 7 is no longer met.

9. Circuit arrangement (1) according to one or more of claims 1 to 8, characterized in that the control circuit (pC) is further configured to regulate the total current consumption from the input (L, N) in each sub-region of the mains half-wave such that the resulting mains alternating current (l_in) of the circuit arrangement (1) has a substantially sinusoidal waveform. 2024PF00026 67 10. Circuit arrangement (1) according to one of the preceding claims, characterized in that the first converter (PFC) is a boost converter, and the second converter (HB) is a buck converter or a flyback converter or another bucking potential-isolated converter or another bucking non-potential-isolated converter, and that the load (5) is an LED module, and the second converter (HB) adjusts the output voltage (U_out) to the voltage of the LED module or regulates the output current (l_out) or reduces the output current (l_out) to dim the LED module.

11. Circuit arrangement (1 ) according to one of the preceding claims, characterized in that the control circuit (pC) is configured not to perform switching at very low output powers or in situations with reduced mains voltage or in situations with very high output voltage (U_out), and to couple the input (HB_in) of the second converter with the second potential (P2) over the entire half-wave.

12. Circuit arrangement according to one of the preceding claims, characterized in that the control circuit (pC) is configured to detect current jumps at the input (L, N) of the circuit arrangement during switching by means of a signal taken from and measured at the input of the circuit arrangement, and to counteract these current jumps by means of a control or The minimization algorithm is designed to minimize the current (l_Boost_in) absorbed by the first converter (PFC) in the second sub-area (Tp) by adjusting its size according to the control requirements, and / or by adjusting or controlling the second sub-area (Tp) accordingly.

13. Circuit arrangement according to claim 12, characterized in that it is configured to detect the signal by means of a high-impedance capacitive tap at the input choke or at the mains input area of ​​the circuit arrangement before the rectifier (BR), or by means of an auxiliary winding on the input choke, or by means of a locally located 2024PF00026 68 to accomplish this by placing the throttle at the input throttle or in a corresponding manner.

14. Circuit arrangement according to one of the preceding claims, characterized in that a buffer capacitor (C_BUF) is connected between the input terminals (HB_in, GND) of the second converter to limit voltage ripple at the input, wherein the capacitance of the buffer capacitor (C_BUF) is advantageously selected proportionally to the nominal output power of the ballast and has a capacitance in the range between a minimum of 0.5nF and a maximum of 22nF per 50W of nominal output power.

15. Circuit arrangement according to one of the preceding claims, characterized in that a switch-on time (t_on) for the converter switch (PFC_SW) of the first converter (PFC) is controlled by the control circuit (pC) such that the switch-on time (t_on) is stepwise adjusted to match a first switching time (t1) between the first sub-area of ​​the first sub-area (Tsa) and the second (Tp) sub-area and the second switching time (t2) between the second (Tp) sub-area and the second sub-area of ​​the first sub-area (Tsb), so that the switch-on time (t_on) immediately after the first switching time (t1) is at least 30% shorter than immediately before the first switching time (t1) and such that the switch-on time (t_on) immediately before the second switching time (t2) is at least 30% shorter.as immediately after the second switching time (t2) and that the switch-on time (t_on) is controlled over a network half-cycle in such a way that the sinusoidal current draw for the network current (l_in) is ensured.

16. Circuit arrangement according to claim 5, characterized in that the parallel operating mode is realized by a first bypass branch (BP_1) or a third bypass branch (BP_3), wherein: - the first bypass branch (BP_1) couples the input (HB_in) of the second converter with the first potential (P1); - the third bypass branch (BP_3) as a parallel upper rectifier branch 2024PF00026 69 is realized by means of two additional mains rectifier diodes (D_N, D_L), whose anodes are connected to the AC voltage inputs (PWa, PWb) of the rectifier (BR) and whose cathodes are connected to the input (HB_in) of the second converter (HB).

17. Circuit arrangement according to claim 5, characterized in that the parallel operating mode is realized by a second bypass branch (BP_2) which bypasses the second converter (HB), wherein the second bypass branch (BP_2) has a series connection of an additional switch (SW_BP2) and an additional diode (D_BP2) and connects a connection point located between the converter inductance (L_PFC) and the converter switch (PFC_SW) of the first converter (PFC) to the output capacitor (C_B) of the second converter (HB).

Images