Method for learning an output voltage gain correction of a power factor corrector
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-01-29
- Publication Date
- 2026-08-13
Smart Images
Figure EP2026052348_13082026_PF_FP_ABST
Abstract
Description
Method for learning an output voltage gain correction of a power factor corrector Description technical field
[0001] This disclosure falls within the domain of learning processes for output voltage gain correction of a power factor corrector of an electrical circuit. Previous technique
[0002] In the field of electric vehicles, it is known that there are on-board boxes that manage the charging of electric batteries when the vehicle is connected to the electrical grid or via a charging station.
[0003] As illustrated in Figure 1, such an on-board box 2 typically includes: - a power factor corrector 4 (also called PFC for "Power Factor Corrector" in English) which ensures power transfer between its input connected to the electrical network 6, which delivers an alternating current (AC) voltage, and its output which delivers a constant direct current (DC) output voltage; and - a high voltage direct current direct current converter 8 (also called HV DCDC for "High Voltage Direct Current Direct Current" in English), electrically connected at the input to the output of the power factor corrector 4, and electrically connected at the output to a battery 8.
[0004] The on-board box 2 has the function of supplying electricity, from the electrical network 6, to the battery 10 with a substantially stable voltage, for example in the order of 400V or 800V depending on the size of the battery 10. In other words, the on-board box 2 has the function of presenting a power factor as close as possible to 1.
[0005] In this context, the 4x power factor correction requires constant monitoring of the input and output voltages to ensure there is no discrepancy between the measured and actual voltages. The 4x power factor correction performs the necessary compensation / correction.
[0006] The power factor corrector 4 includes at its output a capacitor, called DC LINK, connected to the high-voltage DC-DC converter 8, and composed of capacitors C1 and C2 arranged in series. DC LINK has a connection point, called MIDocunk, at which the connecting capacitors C1 and C2 are arranged on either side, i.e., MIDocunk is between C1 and C2.
[0007] The total voltage of the DC LINK capacitor, known as the Vocunk output voltage, is controlled by a regulation loop that adjusts the effective current under a certain voltage, thus stabilizing Vocunk. In other words, Vocunk is controlled by regulating the power drawn from the electrical grid.
[0008] The presence of a measurement error between the measured Voc unk voltage (by a voltage measuring device) and the actual Vocunk voltage introduces a bias in the regulation loop, and therefore an error in the correction provided by the power factor corrector 4. Indeed, the connection capacitors C1, C2 which make up the DC Link capacitor are designed to operate at a nominal voltage, and are not intended to operate at a different voltage.
[0009] The acquisition chain typically includes a voltage sensor (or voltage measuring device) capable of measuring the output voltage of the power factor corrector.
[0010] The actual voltage is then transformed by the voltage sensor into a voltage signal VSIGNAL within a range, typically between 0 and 5V.
[0011] Finally, the voltage signal is transferred to a microcontroller in the acquisition chain, which converts the voltage signal back into a physical voltage value according to the characteristics of the voltage sensor. This conversion is performed by multiplying the voltage signal VSIGNAL by a gain factor G.
[0012] In the end, at the end of the acquisition chain, we have VMES OUT = G * VSIGNAL + B, with B an offset (a constant voltage shift).
[0013] It has been observed that there may be a bias in the measurement of the VMES OUT voltage due to a fault in the gain factor G of the acquisition chain (relative to the theoretical gain).
[0014] However, current methods do not measure or correct any defects related to the gain factor G of the acquisition chain, which defects have an impact on the proper functioning of the power factor corrector.
[0015] Therefore, there is a need to correct a gain factor defect in a power factor correction output voltage acquisition chain. Summary
[0016] To this end, this document proposes a method for learning an output voltage gain correction of a power factor corrector of an electrical circuit, said electrical circuit comprising: A three-phase electrical network comprising three alternating voltage sources, each alternating voltage source corresponding to one phase of the three-phase electrical network, said three-phase electrical network being electrically connected to a neutral connection of the electrical circuit; the power factor corrector which includes: - a switching cell, - a first and a second connection capacity, arranged in series with each other and at the output of the power factor corrector; - a connection point arranged between said first and second connection capacities and capable of being electrically connected to the neutral connection via secondary switching means; and said power factor corrector being capable of being electrically connected to a single AC voltage source among the three AC voltage sources or to the three AC voltage sources via primary switching means, and an acquisition chain comprising a first voltage measuring device capable of measuring the output voltage of the power factor corrector and a second voltage measuring device capable of measuring the input voltage of the power factor corrector, said process includes the following steps: a) Configure the electrical circuit so that the power factor corrector is not electrically connected to the electrical grid. b) Configure the electrical circuit so that the electrical circuit has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector is electrically connected to a single AC voltage source from said at least one AC voltage source of the electrical network via the primary switching means; • A secondary configuration in which the power factor corrector is electrically connected to three AC voltage sources, including at least one AC voltage source from the electrical network, via the primary switching means, and perform an initial passive pre-charge of the power factor corrector; c) Measure an RMS input voltage VIN of the power factor corrector; d) Calculate a first output pre-charge voltage VPRECOUT 1 satisfying: • if the first configuration of the electrical circuit corresponds to the primary configuration, V PREC 0UT 1 = 2 * V IN - 2 * V d , with Vd being the predetermined voltage threshold of the diodes in the switching cell, • if the first configuration of the electrical circuit corresponds to the secondary configuration, V PREC 0UT 1 = Your * V IN - 2 * V d , e) After the first passive pre-charge, measure an output voltage of the power factor corrector, called the first measured output voltage VMESOUT -I, (f) configure the electrical circuit so that the electrical circuit has a second configuration distinct from the first configuration, said second configuration corresponding to: • a tertiary configuration if the first configuration corresponds to the secondary configuration, the tertiary configuration corresponding to a configuration in which the power factor corrector is electrically connected to all three AC voltage sources among said at least one AC voltage source of the electrical network via the primary switching means, and the connection point is electrically connected to the neutral connection via the secondary switching means; • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration, and g) Perform a second passive precharge of the power factor corrector, h) Measure and update the RMS input voltage VIN of the power factor corrector, h) Calculate a second output precharge voltage VPREC OUT 2 satisfying: • If the second configuration matches the secondary configuration, VpREC OUT 2 = 6 * V IN — 2 * V d , • If the second configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2 / 2 * V IN — 2 * V d , i) After the second passive pre-charge, measure the output voltage of the power factor corrector, referred to as the second measured output voltage VMES OUT 2, and j) Calculate a first output voltage gain correction CGAIN 1 of the power factor corrector satisfying: C GAIN 1 = (VIEWS OUT 2 ~ MY OUT I) / (NPREC OUT 2 — PREC 0UT x).
[0017] It is to be understood that step (d) can be carried out at any time in the process following step (c) and preceding step (g).
[0018] It is to be understood that step (h) can be carried out at any time in the process following step (g) and preceding step (j).
[0019] Passive preload of the power factor corrector refers to the passive preload of the first and second connection capacitors of the power factor corrector.
[0020] The term "capacitance" refers to the equivalent capacitance of electronic components. For example, a first and a second capacitor in series with capacitances CA and CB respectively have together an equivalent capacitance Ceq = (CA * CB) / (CA + CB).
[0021] The connection point is arranged between the first and second connection capacities, which are arranged in series. In particular, the at least two connection capacities and the connection point are arranged such that the equivalent capacity on one side of the connection point (the first connection capacity) and that on the other side of the connection point (the first connection capacity) are identical.
[0022] The output voltage of the power factor corrector corresponds to the sum of the voltages across each connecting capacitor.
[0023] The acquisition chain may also include a microcontroller.
[0024] The measured output voltage values from the acquisition chain can be regulated by a regulation loop.
[0025] The control loop can adapt the power factor corrector control to regulate the output voltage to a predefined setpoint (typically 800V).
[0026] The process requires the absence of offset on the acquisition of VIN, which can be obtained by a compensation strategy requiring a VIN measurement before configuration of the electrical network following the first configuration.
[0027] Following step (b), the electrical circuit has a first configuration / topology.
[0028] In the case where the first configuration corresponds to the primary configuration: - Once step (b) is completed, the power factor corrector behaves like a single-phase rectifier, and the first configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a single-phase source; - During step (d), the input voltage to the power factor corrector is an AC voltage. The rectifier converts the AC voltage into a DC voltage whose value is related to the peak value of the input AC voltage, which explains the presence of the square root of 2 term. - VPRECOUT 1 corresponds to the theoretical rectified DC voltage is equal to the peak (maximum) value of the AC voltage from which we must subtract 2 x Vd, the voltage across the two body diodes of the switching cell, which diodes are used for passive rectification; - That's why we have the following formula: V PREC 0UT ± = V2 * V IN - 2 * V d .
[0029] In the case where the first configuration corresponds to the secondary configuration: - The secondary configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a three-phase source, but without a connection to the neutral; - Therefore, the first output precharge voltage VPRECOUT 1 has a different formulation, specific to the secondary configuration. The term V6 * V IN is justified by the fact that, given that the power factor corrector is electrically connected to the three voltage sources of the three-phase electrical network, the peak voltage is equal to the square root of 3 times the term V2 * V IN present in the formulation of VPREC OUT 1. - More specifically, VPREC OUT 1 (which corresponds to the theoretical rectified DC voltage) is determined by the peak voltage between the phases in three-phase, i.e. the peak voltage (square root of 2 times the effective voltage VIN) multiplied by square root of 3.
[0030] The output voltage of the power factor corrector then increases until the natural end of the passive precharge (step (e)), the output voltage being dependent on the topology of the power factor corrector (i.e. the configuration of the electrical circuit).
[0031] These elements allow for the accurate determination of the first output pre-charge voltage VPRECOUT 1
[0032] Furthermore, the calculation (learning) of an output voltage gain correction following this method is guaranteed, regardless of the load cycle considered.
[0033] The process has a fast acquisition and calculation time: the time constant of a passive preload is on the order of a second.
[0034] The CGAIN 1 formula corresponds to the ratio between the slope of the evolution of the measurement voltage (corresponding to the measured output voltages VMES OUT -I, VMES OUT 2) and the slope of the evolution of the theoretical reference voltage (corresponding to the pre-charge voltages VPRECOUT 1, VPRECOUT 2), i.e. based on the input voltage VIN.
[0035] In other words, CGAIN 1 corresponds to the factor by which the theoretical slope must be multiplied to obtain the slope of evolution of the measured voltage.
[0036] In other words, CGAIN 1 corresponds to the factor by which the theoretical gain must be divided to compensate for the gain defect of the acquisition chain and obtain the theoretical slope.
[0037] During step (f), the electrical circuit can be configured either so that the second configuration corresponds to the secondary or tertiary configuration.
[0038] In the case where the second configuration corresponds to the tertiary configuration: - The tertiary configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a three-phase source, with connection to the neutral; - As a result, the first output precharge voltage VPRECOUT 1 has a different formulation, specific to the tertiary configuration; - When the midpoint of the connecting capacitors (the connection point) is connected to the neutral connection, each connecting capacitor has a rectified voltage of √2 times VIN from which Vd is subtracted (for the respective body diode); - Therefore, the theoretical rectified DC voltage VPREC OUT 2 is equal to the sum of the rectified voltages of the connecting capacitors, i.e., V PREC 0UT 2 = 2√2 * ^ - 2 * ^
[0039] In other words, we have the option of using secondary switching means so that the potential is either electrically connected to the neutral connection or not. This consequently influences the formulation of the second output pre-charge voltage VPREC OUT 2, since the formulas for VPREC OUT 2 respect the same electrical circuit configuration conditions as those for VPREC OUT 1.
[0040] Following step (f), the electrical circuit has a second configuration.
[0041] The VPREC OUT 2 formulas respect the same electrical circuit configuration conditions as those for VPREC OUT 1.
[0042] VPREC OUT 2 will then be used in the calculation of CGAIN 1 which will therefore depend on the configuration of the electrical circuit (i.e. the connection or not to the neutral during step (f)).
[0043] The first configuration may correspond to the primary configuration and the second configuration may correspond to the secondary configuration, the process further comprising the following steps: k) Configure the electrical circuit so that the electrical circuit has a third configuration corresponding to the tertiary configuration, and perform a third passive pre-charge of the power factor corrector, l) Measure and update the RMS input voltage VIN of the power factor corrector, m) Calculate a third output pre-charge voltage VpREcouTs satisfying: V PREC 0UT 3 = 2V2 * V IN - 2 * V d , n) At the end of the third passive pre-charge, measure an output voltage, called the third measured output voltage VMESOUT S, and 0) Calculate a second output voltage gain correction CGAIN 2 of the power factor corrector such that
[0044] It is important to understand that the VIN measurements are carried out using the second voltage measuring device, and the VMES OUT I, VMES OUT 2, and VMES OUT S measurements are carried out using the first voltage measuring device.
[0045] It is to be understood that step (m) can be carried out at any time in the process following step (I) and preceding step (0).
[0046] Following step (k), the electrical circuit has a third configuration.
[0047] The VPREC OUT 3 formulas respect the same electrical circuit configuration conditions as those for VPREC OUT 1
[0048] The process may further include the following step: p) Calculate a third output voltage gain correction CGAIN 3 of the power factor corrector such that
[0049] The process may further include the following step: q) Calculate an average output voltage gain correction CGAIN MOY which is equal to an average of CGAIN 1 , CGAIN 2 and CGAIN 3.
[0050] The formulas for VPREC OUT 3 respect the same electrical circuit configuration conditions as those for VPREC OUT 1, which explains why V PREC 0UT 3 = 2V2 * V IN - 2 * V d (formula specific to the tertiary configuration).
[0051] Step (q) improves the calculation of the output voltage gain correction by exploiting an average of the previously calculated output voltage gain corrections CGAIN 1, CGAIN 2 and CGAIN 3.
[0052] In other words, the process allows for learning the different possible scenarios (first, second, and third configurations of the electrical circuit) in order to determine the output voltage gain correction as precisely as possible. Similarly, the process incorporates the principle of experimental repeatability to minimize uncertainties in the results obtained.
[0053] Depending on the country, the sizing of the electrical power supply network for an on-board unit varies (single-phase, three-phase, supply voltage, etc.). The primary and secondary switching means allow the electrical circuit to present the first, second, and third configurations, which correspond to the different electrical network systems possible in the world.
[0054] In other words, the electrical circuit allows the determination of the output voltage gain correction to be adapted according to the power supply of the electrical network (the electrical network in single-phase mode - primary configuration -, three-phase - secondary and tertiary configurations) and according to the connection to the neutral of the power factor corrector, while exploiting this adaptability to improve the accuracy of the learning.
[0055] In the case of a data acquisition chain including a microcontroller, the process can perform the learning even if the microcontroller resets during or after the various passive preload phases, since the waiting times for the different preloads are short. The process thus exhibits greater robustness against a potential microcontroller reset.
[0056] The power factor corrector also includes: a first and a second pull-up resistor arranged in series with the first and second connecting capacitors respectively; and of the first and second tertiary switching means which are arranged in parallel with the first and second inrush resistors respectively, the process further comprising at least one of the following: between steps (a) and (b), step (a1) of opening the first and second tertiary switching means, and between steps (d) and (e), step (d1) of closing (ED1) the first and second tertiary switching means, between steps (e) and (f), step (e1) of opening the first and second tertiary switching means, and between steps (h) and (i), step (h1) of closing (EH1) the first and second tertiary switching means, and between steps (j) and (k), step (j1) of opening the first and second tertiary switching means, and between steps (m) and (n), step (m1) of closing (EM1) the first and second tertiary switching means.
[0057] When the first and second tertiary switching means are open (steps (a1), (e1) and (j1)), the first and second inrush resistors limit the inrush current through them during the electrical connection steps (steps (b), (f) and (k)), i.e., electrical circuit configuration.
[0058] Thus, the sudden increase in current caused by the transition from one configuration to another in the electrical circuit does not generally damage the power factor corrector.
[0059] In other words, the first and second inrush resistors smooth the inrush current by creating a load loss.
[0060] The measurement of the measured output voltages VMESOUT -I, VMES OUT 2 and VMEsouTs is influenced by the presence of the first and second pull-up resistors.
[0061] It is necessary to close the first and second tertiary switching means before the measured output voltages VMESOUT 1, VMESOUT2 and VMES OUT 3 are measured (steps (e), (i) and (n)).
[0062] Therefore, once the passive pre-charge is complete, or the passive pre-charge related to the transition from one configuration to another is complete, the first and second tertiary switching means (steps (d1), (h1) and (m1)) which short-circuit the first and second pull-in resistors are closed.
[0063] In other words, the current bypasses the first and second inrush resistors and passes through the first and second tertiary switching means.
[0064] The output voltage of the power factor corrector can be measured continuously, and: Step (d1) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 1, Step (h1) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 2, and Step (m1) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 3.
[0065] In this way, we ensure that we benefit from a sufficient inrush current limitation, while allowing a reliable measurement of the measured output voltages.
[0066] Continuous measurement of the output voltage of the power factor corrector can be achieved by the voltage measuring device of the acquisition chain.
[0067] The process may further include the following step: r) Configure the power factor corrector to correct the power factor corrector output voltage measurement gain according to at least one of CGAIN 1, CGAIN 2, CGAIN 3 and CGAIN MOY.
[0068] By correcting the gain of the power factor corrector's output voltage measurement according to at least one of CGAIN 1, CGAIN 2, CGAIN 3 and CGAIN MOY, we mean to define a correction on the power factor corrector's output voltage measurement VMES OUT, such that the corrected gain satisfies: GCORR = G / CGAIN with CGAIN which is equal to one of CGAIN 1, CGAIN 2, CGAIN 3 and CGAIN MOY and G the gain before correction.
[0069] Therefore, we have the measured output voltage VMES_CORR which satisfies VMES_CORR = GCORR * VsiGNAL + B.
[0070] Gain correction allows for more precise regulation of the actual output voltage.
[0071] The switching cell can comprise a plurality of MOSFET transistors.
[0072] This document may also relate to a computer intended to be installed in an on-board unit of an electric motor vehicle comprising at least one processor and at least one memory, characterized in that it is configured for the implementation of each of the steps of a process according to the aforementioned type.
[0073] This document may also concern a set including: A charging station for electric or hybrid motor vehicles which includes a three-phase electrical network comprising three alternating voltage sources, each alternating voltage source corresponding to one phase of the three-phase electrical network, said three-phase electrical network being electrically connected to a neutral connection; An on-board unit of an electric or hybrid motor vehicle, said on-board unit comprising: - the calculator according to the aforementioned type; - the power factor corrector which includes: • a switching cell, • a first and a second connection capacity, arranged in series with each other and at the output of the power factor corrector; • a connection point arranged between said first and second connection capacities and capable of being electrically connected to the neutral connection via secondary switching means; and said power factor corrector being capable of being electrically connected to a single AC voltage source among the three AC voltage sources or to the three AC voltage sources via primary switching means, and - a data acquisition chain comprising a first voltage measuring device capable of measuring the output voltage of the power factor corrector and a second voltage measuring device capable of measuring the input voltage of the power factor corrector, - a high-voltage DC-DC converter electrically connected at the input to the output of the power factor corrector, and an electric battery of the electric or hybrid motor vehicle electrically connected to the output of the DC-DC voltage converter of the on-board unit.
[0074] The connection point is arranged between the first and second connection capacities, which are arranged in series. In particular, the at least two connection capacities and the connection point are arranged such that the equivalent capacity on one side of the connection point (the first connection capacity) and that on the other side of the connection point (the first connection capacity) are identical. Brief description of the drawings
[0075] Other features, details, and advantages will become apparent upon reading the detailed description below and analyzing the attached drawings, on which:
[0076] [Fig. 1] is a schematic view illustrating an on-board unit connected to an electrical network and a battery,
[0077] [Fig. 2A] is a schematic view of an electrical circuit for measuring an output voltage gain correction of a power factor corrector according to an embodiment of this document, the electrical circuit being in an initial configuration,
[0078] [Fig. 2B] is a schematic view of the electrical circuit of figure 2A in a first configuration,
[0079] [Fig. 2C] is a schematic view of the electrical circuit of figure 2A in a second configuration,
[0080] [Fig. 2D] is a schematic view of the electrical circuit of figure 2A in a third configuration,
[0081] [Fig. 3A], [Fig. 3B] and [Fig. 3C] illustrate the different stages of a learning process for an output voltage gain correction of a power factor corrector of an electrical circuit, according to the embodiment of figures 2A to 2D,
[0082] [Fig. 4] is a graph of the evolution of the measured output voltage and the output pre-charge voltage of the power factor corrector as a function of the output signal of said power factor corrector, according to the embodiment of Figures 2A to 2D, and
[0083] [Fig. 5] represents the evolution of the measured output voltage of the power factor corrector, during a first preload, over time. Description of the implementation methods
[0084] Figure 2A illustrates an electrical circuit according to an embodiment of this document, which electrical circuit 20 comprises a three-phase electrical network 30. The electrical circuit 30 has an initial configuration.
[0085] The electrical network 30 is connected to a neutral connection N and comprises three arms 30a, 30b, 30c on which three alternating voltage sources 32a, 32b, 32c are arranged respectively. Primary switching means 34a, 34b, 34c are arranged in series with the three voltage sources 32a, 32b, 32c respectively.
[0086] The electrical circuit further includes a power factor correction 40 which comprises a switching cell. The switching cell comprises a plurality of switches S1, S2, S3, S4, S5, S6.
[0087] This plurality of switches S1, S2, S3, S4, S5, S6 are arranged so that the series pairs S1-S2, S3-S4 and S5-S6 are in parallel with each other.
[0088] Switches S1, S3 and S5 are called the upper (or top) switches and switches S2, S4 and S6 are called the lower (or bottom) switches.
[0089] The state of the switches is such that S2 is in a state opposite to S1, S4 is in a state opposite to S3 and S6 is in a state opposite to S5, i.e. the state of the upper switches is inverse to that of the lower switches.
[0090] The power factor corrector 40 further includes, at output, a first and a second connection capacitance CLINK 1, CLINK 2 in series with each other, which connection capacitances CLINK 1, CLINK 2 define between them a midpoint corresponding to a connection point MIDocLiNK which is electrically connected to the neutral connection N via secondary switching means S7.
[0091] The CLINK 1, CLINK 2 connection capabilities are arranged in parallel with the S1-S2, S3-S4 and S5-S6 switch pairs (the switching cell).
[0092] A first and a second call resistor RAPPEL 1 and RAPPEL 2 are arranged in series with the first and second connection capacitors CLINK 1, CLINK 2 respectively.
[0093] CLINK 1 and CLINK 2 here represent identical equivalent capacities on each side of the MIDDC LINK connection point.
[0094] The first and second tertiary switching means S8, S9 are arranged in parallel with the first and second pull-up resistors RAPPEL 1 and RAPPEL 2 respectively.
[0095] The power factor corrector 40 is electrically connected, at the input, to the three alternating voltage sources 32a, 32b, 32c of the three-phase electrical network 30 by the primary switching means 34a, 34b, 34c.
[0096] Although not illustrated, it is to be understood that the power factor corrector 40 is electrically connected, at output, to a high voltage DC-DC converter 8 (as shown in Figure 1).
[0097] More specifically, each voltage source 32a, 32b, 32c is electrically connected to a pair of switches S1-S2, S3-S4 and S5-S6 respectively.
[0098] In addition, power inductances Indi, Ind 2 and Ind ss are arranged in series between the corresponding primary switching means 34a, 34b, 34c and the power factor corrector 40.
[0099] The electrical circuit 20 further includes an acquisition chain 49 comprising a first voltage measuring device 50 capable of measuring the output voltage of the power factor corrector 40.
[0100] The output voltage of the power factor corrector 40 corresponds to the output voltage VocLiNK of Figure 1. VSIGNAL is the output voltage signal of the power factor corrector transformed by the first voltage measuring device, VSIGNAL being different from the measured output voltage of the power factor corrector 40.
[0101] The acquisition chain 49 further includes a second voltage measuring device 60 suitable for measuring the input voltage of the power factor corrector 40, i.e. the voltage at the connection between the primary switching means 34a, 34b, 34c and the power inductors Indi, Ind 2 and Inds.
[0102] Figures 3A to 3C illustrate the different stages of a learning process for an output voltage gain correction of a power factor corrector of the electrical circuit according to the embodiments of figures 2A to 2D.
[0103] During an EA step, the electrical circuit 20 is configured so that the power factor corrector 40 is not electrically connected to the electrical network 30. In other words, the electrical circuit 20 is configured according to the initial configuration of Figure 2A.
[0104] During an EA1 step, the first and second tertiary switching means S8, S9 are opened.
[0105] During an EB step, the electrical circuit 20 is configured so that the electrical circuit 20 has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector 40 is electrically connected to a single AC voltage source 30a among said at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c; • A secondary configuration in which the power factor corrector 40 is electrically connected to three AC voltage sources 32a, 32b, 32c among said at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c, and a first passive pre-charge of the power factor corrector 40 is carried out.
[0106] In this embodiment, the first configuration corresponds to the primary configuration: the electrical circuit 20 has a topology in which one of the switches forming the primary switching means 34a, 34b, 34c is closed. In this first configuration, the electrical network 30 is equivalent to a single-phase source.
[0107] Figure 2B illustrates the electrical circuit in the first configuration of electrical circuit 20: one of the primary switching means 34a, 34b, 34c is closed (here 34a) and the secondary switching means S7 are open. Furthermore, the other switching means 34b and 34c are configured so that their respective arms are folded down (i.e., connected) to a corresponding branch 35b, 35c connected to the neutral connection N.
[0108] During the first passive precharge, the inrush current will flow through the inrush resistors RAPPEL 1 and RAPPEL 2 (given that the first and second tertiary switching means S8, S9 are open) before flowing through the first and second connection capacitors CLINK 1, CLINK2.
[0109] The pull-up resistors RAPPEL 1 and RAPPEL 2 will create load losses and thus prevent damage to the electronic components of the passive rectification circuit of the power factor corrector 40, and prevent overcurrents.
[0110] In the remainder of this section and according to this embodiment, the first configuration is considered to be the primary configuration.
[0111] During an EC step, an effective input voltage VIN of the power factor corrector 40 is measured.
[0112] During an ED step, a first output pre-charge voltage VPREC OUT I is calculated, satisfying: • if the first configuration of the electrical circuit 20 corresponds to the primary configuration, V PREC 0UT 1 = ^2 * V IN - 2 * V d, with Vd the predetermined voltage threshold of the diodes in the switching cell S1, S2, S3, S4, S5, S6, • if the first configuration of the electrical circuit corresponds to the secondary configuration, V PREC ouri = V6 * V 1N — 2 * V d ,
[0113] This formulation of VPRECOUTI is justified by the fact that the first configuration of the electrical circuit 20 corresponds to the primary configuration.
[0114] Given that the electrical circuit configurations / topologies 20 are known in the process steps, the formulation of the output preload voltages is predictable.
[0115] During a step ED1, the first and second tertiary switching means S8, S9 are closed. In this way, the current will bypass the inrush resistors RAPPEL 1 and RAPPEL 2 which have fulfilled their function of smoothing the inrush current.
[0116] Optionally, step ED1 can be performed when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 1. According to this aspect, the output voltage of the power factor corrector 40 is measured continuously.
[0117] During an EE step, at the end of the first passive precharge, an output voltage of the power factor corrector 40 is measured, called the first measured output voltage VMESOUT 1.
[0118] Similar to step EA1, during an EE1 step, the first and second tertiary switching means S8, S9 are opened again.
[0119] This helps to protect the connection capabilities of CLINK 1, CLINK 2 from the incoming inrush current.
[0120] During an EF step, the electrical circuit 20 is configured so that the electrical circuit 20 has a second configuration distinct from the first configuration, said second configuration corresponding to: • a tertiary configuration if the first configuration corresponds to the secondary configuration, the tertiary configuration corresponding to a configuration in which the power factor corrector 40 is electrically connected to the three AC voltage sources 32a, 32b, 32c among said at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c, and the MIDDC LINK connection point is electrically connected to the neutral connection N via the secondary switching means S7; • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration, and a second passive pre-charge of the power factor corrector is performed.
[0121] In this embodiment, where the second configuration corresponds to the secondary configuration, the electrical circuit 20 has a topology in which the switches forming the primary switching means 34a, 34b, 34c are closed. In this second configuration, the electrical network 30 is equivalent to a three-phase source.
[0122] In other words, the second configuration of the electrical circuit 20 corresponds to a configuration in which the primary switching means 34a, 34b, 34c are closed and the secondary switching means S7 are open. This second configuration is shown in Figure 2C.
[0123] In the remainder of this section and according to this embodiment, the second configuration is considered to be the secondary configuration.
[0124] During an EG step, the effective input voltage VIN of the power factor corrector 40 is measured and updated.
[0125] During an EH step, a second output precharge voltage VPREC OUT 2 is calculated, satisfying: • If the second configuration matches the secondary configuration, pREC OUT 2 = o * V, N — 2 * V d , • If the second configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2V2 * V IN - 2 * V d ,
[0126] In our case, we therefore have: V PREC 0UT 2 = 6 * V IN - 2 * V d .
[0127] This formulation of VPREC OUT 2 is justified by the fact that the second configuration of the electrical circuit 20 corresponds to the secondary configuration.
[0128] Similar to step ED1, during an EH1 step, the first and second tertiary switching means S8, S9 are closed.
[0129] Optionally, step EH1 can be performed when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 2. According to this aspect, the output voltage of the power factor corrector 40 is measured continuously.
[0130] During an El stage, at the end of the second passive precharge, an output voltage of the power factor corrector 40 is measured, called the second measured output voltage VMESOUT 2.
[0131] During an EJ step, a first output voltage gain correction CGAIN 1 of the power factor corrector 40 is calculated, satisfying: C GAIN 1 = (V ME S OUT 2 ~ ^MES OUT 1) / (NPREC OUT 2 > pREC OUT 1)-
[0132] Similar to steps EA1 and EE1, during an EJ1 step, the first and second tertiary switching means S8, S9 are opened again.
[0133] During an EK step, the electrical circuit 20 is configured so that the electrical circuit 20 has a third configuration corresponding to the tertiary configuration, and a third passive pre-charge of the power factor corrector 40 is performed.
[0134] The third configuration (and therefore the tertiary configuration here) of the electrical circuit 20 corresponds to a configuration in which the primary switching means 34a, 34b, 34c are closed and the secondary switching means S7 are also closed. This third configuration is shown in Figure 2D.
[0135] During an EL step, the RMS input voltage VIN of the power factor corrector 40 is measured and updated.
[0136] During an EM step, a third output pre-charge voltage VPREC OUT 3 is calculated, satisfying: V PREC 0UT 3 = 2 2 * V IN — 2 * V d ,
[0137] Similar to steps ED1 and EH1, during an EM1 step, the first and second tertiary switching means S8, S9 are closed.
[0138] During an EN step, at the end of the third passive precharge, an output voltage is measured, called the third measured output voltage VMES OUT S.
[0139] During an EO step, a second output voltage gain correction CGAIN 2 of the power factor 40 corrector is calculated such that C GAIN 2 = (y MES 0UT 3 - V M ES OUT i) / (NPREC OUT 3 ~ pREC OUT 1) ■
[0140] During an EP step, a third output voltage gain correction CGAIN 3 of the power factor corrector 40 is calculated such that C GAIN 3 = (y MES 0UT 3 - V MES 0UT 2 ') / (NPREC OUT 3 — pREC OUT2)'
[0141] The output voltage gains CGAIN 1, CGAIN 2 and CGAIN 3 are explained in Figure 4, which is a graph of the evolution of the measured output voltage and the output pre-charge voltage of the power factor corrector as a function of the output voltage signal of said power factor corrector.
[0142] Curve 50 represents the evolution of the theoretical output voltage (i.e., based on the input voltage VIN), VPRECOUT 1, VPRECOUT 2, and VPRECOUT S, as a function of the voltage signal VSIGNAL.
[0143] Curve 52 represents the evolution of the measured output voltage VMES OUT 1, VMES OUT 2, and VMESOUT S, as a function of the voltage signal VSIGNAL.
[0144] The first configuration of the electrical circuit 20 corresponds to the case relating to the line with abscissa X1. The first output precharge voltage VPREC OUT I is the ordinate of the curve 50 at abscissa X1 and the first measured output voltage VMES OUT 1 is the ordinate of the curve 52 at abscissa X1.
[0145] The second electrical circuit configuration corresponds to the case related to the line with abscissa X2. The second output precharge voltage VPREC OUT 2 is the ordinate of the curve 50 at abscissa X2, the second output measured voltage VMES OUT 2 is the ordinate of the curve 52 at abscissa X2.
[0146] The third configuration of the electrical circuit corresponds to the case relating to the line with abscissa X3. The third output precharge voltage VPREC OUT S is the ordinate of the curve 50 at abscissa X3, the third measured output voltage VMES OUT 3 is the ordinate of the curve 52 at abscissa X3.
[0147] We observe that curve 52 has a different slope (i.e. a different gain).
[0148] The first output voltage gain correction CGAIN 1 corresponds to the coefficient by which the slope of curve 50 should be multiplied, to obtain the slope of curve 52, when taking as calculation coordinates slopes between abscissas X1 and X2.
[0149] Put another way, this corresponds to a comparison of slopes, the slopes being calculated between the second configuration and the first configuration (according to this embodiment between the secondary configuration and the primary configuration).
[0150] The second output voltage gain correction CGAIN 2 corresponds to the coefficient by which the slope of curve 50 should be multiplied, to obtain the slope of curve 52, when the abscissas X1 and X3 are taken as the calculation coordinates of the slopes.
[0151] Put another way, this corresponds to a comparison of slopes, the slopes being calculated between the third configuration and the first configuration (according to this embodiment between the tertiary configuration and the primary configuration).
[0152] The third output voltage gain correction CGAIN 3 corresponds to the coefficient by which the slope of curve 50 should be multiplied, to obtain the slope of curve 52, when the abscissas X2 and X3 are taken as the calculation coordinates of the slopes.
[0153] Put another way, this corresponds to a comparison of slopes, the slopes being calculated between the third configuration and the second configuration (according to this embodiment between the tertiary configuration and the secondary configuration).
[0154] The process and the associated electrical circuit 20 therefore allow the calculation of gain corrections with different comparisons according to the three possible configurations / topologies of the electrical circuit 20, and to obtain an average CGAIN MOY.
[0155] Indeed, during an EQ step, we calculate an average output voltage gain correction CGAIN MOY which is equal to an average of CGAIN 1, CGAIN 2 and CGAIN 3.
[0156] We therefore have: CGAIN MOY- (CGAIN 1 + CGAIN 2 + CGAIN S) / 3.
[0157] Figure 5 represents the evolution of the output voltage of the power factor corrector 40, during the first pre-charge, in the case where the tertiary switching means S8, S9 are open.
[0158] We observe that after a duration T' = 3s, the output voltage has reached its final value. The output voltage exceeds 90% of VPREC OUT 1 (0.9* VPREC OUT 1) after a duration T = 1s; it is at this moment that the first and second tertiary switching means S8, S9 are closed (step (d1)), which instantaneously brings the output voltage to its final value and terminates the pre-charge phase.
[0159] We can therefore understand the benefit of performing step (d1) when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 1.
[0160] If we take the case of performing step (d1) when the output voltage of the power factor corrector 40 is equal to 90% of VPRECOUT 1.
[0161] On the one hand, we therefore allow ourselves a 10% error on VMES OUT 1. Even though VMES OUT 1 includes a 10% error, a detection margin is present to take it into account.
[0162] On the other hand, a stable voltage at the connection point with the inrush resistors RAPPEL 1 and RAPPEL 2 short-circuited (S8 and S9 closed) improves the subsequent VMES OUT 1 measurement (step (e)). This is why RAPPEL 1 and RAPPEL 2 are short-circuited in a voltage regime with few fluctuations: a regime in which the voltage is close to its final value. Almost at the final voltage value, the currents flowing are relatively low: the inrush resistors RAPPEL 1 and RAPPEL 2 are no longer needed.
[0163] This is of course applicable to steps (h1) and (m1), and therefore to the second and third preloads.
[0164] The learning process is very fast, since it exploits the passive preload of the CLINK 1, CLINK 2 connection capabilities.
[0165] It is important to understand that the orders of magnitude of time are essentially the same for the second and third passive preloads.
[0166] During an ER step, the power factor corrector 40 is configured to correct the gain of the output voltage measurement of the power factor corrector 40 according to at least one of CGAIN 1, CGAIN 2, CGAIN S and CGAIN MOY (here we correct according to CGAIN MOY).
[0167] In other words, a correction is defined on the voltage signal, so that the corrected gain satisfies: GCORR = G / CGAIN with CGAIN which is equal to one of CGAIN 1, CGAIN 2, CGAIN 3 and CGAIN MOY and G the gain before correction.
[0168] It is to be understood that the fact that the electrical circuit presents such a sequence of electrical configurations (primary, then secondary then tertiary) allows to make three voltage measurements VMES -I, VMES2, VMES S, and thus calculate CGAIN 1, CGAIN 2, CGAIN 3 to deduce CGAIN MOY.
[0169] In the case of at least two voltage measurements (which is necessary to calculate a gain), the power factor corrector must necessarily exhibit an increasing output voltage between each electrical configuration.
[0170] Therefore, the electrical circuit can also: Present a first configuration corresponding to the primary configuration followed by a second configuration corresponding to the secondary or tertiary configuration (without a third configuration), or Present a first configuration corresponding to the secondary configuration followed by a second configuration corresponding to the tertiary configuration (without a third configuration).
Claims
Demands
1. A method for learning an output voltage gain correction of a power factor corrector (40) of an electrical circuit (20), said electrical circuit (20) comprising: A three-phase electrical network (30) comprising three alternating voltage sources (32a, 32b, 32c), each alternating voltage source corresponding to one phase of the three-phase electrical network, said three-phase electrical network (30) being electrically connected to a neutral connection (N) of the electrical circuit (20); the power factor corrector (40) which comprises: - a switching cell (S1, S2, S3, S4, S5, S6), - a first and a second connection capacity (CLINK 1, CLINK 2), arranged in series with each other and at the output of the power factor corrector (40); - a connection point (MIDDC LINK) arranged between said first and second connection capacities (CLINK 1, CLINK 2) and capable of being electrically connected to the neutral connection (N) via secondary switching means (S7); and said power factor corrector (40) being capable of being electrically connected to a single AC voltage source among the three AC voltage sources (32a, 32b, 32c) or to the three AC voltage sources (32a, 32b, 32c) via primary switching means (34a, 34b, 34c), and an acquisition chain (49) comprising a first voltage measuring device (50) capable of measuring the output voltage of the power factor corrector (40) and a second voltage measuring device (60) capable of measuring the input voltage of the power factor corrector (40), said process includes the following steps: a) Configure (EA) the electrical circuit (20) so that the power factor corrector (40) is not electrically connected to the electrical network (30), b) Configure (EB) the electrical circuit (20) so that the electrical circuit (20) has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector (40) is electrically connected to a single AC voltage source (30a) from said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via the primary switching means (34a, 34b, 34c); • A secondary configuration in which the power factor corrector (40) is electrically connected to three AC voltage sources (32a, 32b, 32c), including at least one AC voltage source (32a, 32b, 32c) from the electrical network (30) via the primary switching means (34a, 34b, 34c), and performs a first passive precharge of the power factor corrector (40); c) Measure (EC) an RMS input voltage VIN of the power factor corrector (40); d) Calculate (ED) a first output precharge voltage VPRECOUT satisfying: • if the first configuration of the electrical circuit (20) corresponds to the primary configuration, V PREC 0UT 1 = 2 * V IN - 2 * V d , with Vd the predetermined voltage threshold of the diodes in the switching cell (S1, S2, S3, S4, S5, S6), • if the first configuration of the electrical circuit corresponds to the secondary configuration, V PREC 0UT 1 = 46 * V IN— 2 * V d , e) After the first passive pre-charge, measure (EE) an output voltage of the power factor corrector (40), called the first measured output voltage VMESOUT 1, f) configure (EF) the electrical circuit (20) so that the electrical circuit (20) has a second configuration distinct from the first configuration, said second configuration corresponding to: • a tertiary configuration if the first configuration corresponds to the secondary configuration, the tertiary configuration corresponding to a configuration in which the power factor corrector (40) is electrically connected to the three AC voltage sources (32a, 32b, 32c) among said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via the primary switching means (34a, 34b, 34c), and the connection point (MIDDC LINK) is electrically connected to the neutral connection (N) via the secondary switching means (S7); • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration, and perform a second passive pre-charge of the power factor corrector (40), g) Measure and update (EG) the RMS input voltage VIN of the power factor corrector (40), h) Calculate (EH) a second output precharge voltage VPRECOUT 2 satisfying: • If the second configuration matches the secondary configuration, pREC OUT 2 = o * V, N — 2 * V d , • If the second configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2V2 * V IN - 2 * V d , i) After the second passive pre-charge, measure (El) an output voltage of the power factor corrector (40), called the second measured output voltage VMESOUT 2, and j) Calculate (EJ) a first output voltage gain correction CGAIN 1 of the power factor corrector (40) satisfying: C GAIN 1 = (4MES OUT 2 —4' ES OUT 4) / ( PREC OUT 2 ~ PREC OUT 4) ■
2. A method according to claim 1, wherein the first configuration corresponds to the primary configuration and the second configuration corresponds to the secondary configuration, the method further comprising the following steps: k) Configure (EK) the electrical circuit (20) so that the electrical circuit (20) has a third configuration corresponding to the tertiary configuration, and perform a third passive pre-charge of the power factor corrector (40), l) Measure and update (EL) the RMS input voltage VIN of the power factor corrector (40), m) Calculate (EM) a third output pre-charge voltage VPREC OUT 3 satisfying: V PREC 0UT 3 = 2^2 * V IN — 2 * V d , n) At the end of the third passive pre-charge, measure (EN) an output voltage, called the third measured output voltage VMESOUT S, and o) Calculate (EO) a second output voltage gain correction CoAiN 2 of the power factor corrector (40) such that C GAIN 2 = (V M£y 0UT 3 — VMES OUT I) / (NPREC OUT 3 — ^PR.EC OUT I) ■
3. Method according to claim 2 further comprising the step: p) Calculate (EP) a third output voltage gain correction CGAIN 3 of the power factor corrector (40) such that C GAIN 3 = ( ME s OUT 3 — MES OUT 2) / (NPREC OUT 3 — ^PREC OUT 2) ■
4. Method according to claim 3 further comprising the step: q) Calculate (EQ) an average output voltage gain correction CGAIN MOY which is equal to an average of CGAIN 1 , CGAIN 2 and CGAIN 3.
5. A method according to any one of claims 1 to 4, wherein the power factor corrector (40) further comprises: a first and a second pull-in resistor (REMINDER 1, REMINDER 2) arranged in series with the first and second connecting capacitors (CLINK 1, CLINK 2) respectively; and first and second tertiary switching means (S8, S9) which are arranged in parallel with the first and second pull-in resistors (REMINDER 1, REMINDER 2) respectively, the process further comprising at least one of the following: between steps (a) and (b), step (a1) of opening (EA1) the first and second tertiary switching means (S8, S9), and between steps (d) and (e), step (d1) of closing (ED1) the first and second tertiary switching means (S8, S9), between steps (e) and (f), step (e1) of opening (EE1) the first and second tertiary switching means (S8, S9), and between steps (h) and (i), step (h1) of closing (EH1) the first and second tertiary switching means (S8, S9), and between steps (j) and (k), step (j1) of opening (EJ1) the first and second tertiary switching means (S8, S9), and between steps (m) and (n), step (m1) of closing (EM1) the first and second tertiary switching means (S8, S9).
6. A method according to claim 5, wherein the output voltage of the power factor corrector (40) is measured continuously, and wherein: Step (d1) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 1, Step (h1) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 2, and Step (m1) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 3.
7. A method according to any one of claims 1 to 6 further comprising the step: r) Configure the power factor corrector (40) so as to correct the gain of the output voltage measurement of the power factor corrector (40) according to at least one of CGAIN 1, CGAIN 2, CGAIN 3 and CGAIN MOY.
8. A method according to any one of claims 1 to 7, wherein the switching cell comprises a plurality of MOSFET transistors (S1, S2, S3, S4, S5, S6).
9. Computer intended to be installed in an on-board box of an electric motor vehicle comprising at least one processor and at least one memory, characterized in that it is configured for the implementation of each of the steps of a method according to any one of claims 1 to 8.
10. Set comprising: A charging station for electric or hybrid motor vehicles which includes a three-phase electrical network (30) comprising three alternating voltage sources (32a, 32b, 32c), each alternating voltage source corresponding to one phase of the three-phase electrical network, said three-phase electrical network (30) being electrically connected to a neutral connection (N); An on-board unit of an electric or hybrid motor vehicle, said on-board unit comprising: - the calculator according to claim 9; - the power factor corrector (40) which comprises: • a switching cell (S1, S2, S3, S4, S5, S6), • a first and a second connection capacitor (CLINK-I, CLINK2), arranged in series with each other and at the output of the power factor corrector (40); a connection point (MIDDC LINK) arranged between said first and second connection capacitors (CLINK 1, CLINK 2) and capable of being electrically connected to the neutral connection (N) via secondary switching means (S7); and said power factor corrector (40) being capable of being electrically connected to a single AC voltage source among the three AC voltage sources (32a, 32b, 32c) or to the three AC voltage sources (32a, 32b, 32c) via primary switching means (34a, 34b, 34c), and - an acquisition chain (49) comprising a first voltage measuring device (50) capable of measuring the output voltage of the power factor corrector (40) and a second voltage measuring device (60) capable of measuring the input voltage of the power factor corrector (40), - a high-voltage DC-DC converter electrically connected at the input to the output of the power factor corrector (40), and an electric battery of the electric or hybrid motor vehicle electrically connected to the output of the DC-DC voltage converter of the on-board unit.