Method for learning measurement of an output voltage difference of a power factor corrector

Abstract

The present document relates to a method for learning an output voltage difference of a power factor corrector (40) of an electrical circuit (20), the method comprising the steps of: configuring (EA) the electrical circuit (20) such that the power factor corrector (40) is not electrically connected to an electrical network (30); configuring (EB) the electrical circuit (20) to have a first configuration; measuring (EC) an input RMS voltage VIN of the power factor corrector (40); calculating (ED) a first output precharge voltage VPREC OUT 1; measuring (EE) an output voltage of the power factor corrector (40), referred to as the first measured output voltage VMES OUT 1; and calculating (EF) a first output voltage difference VDIFF 1 corresponding to the difference between VMES OUT 1 and VPREC OUT 1.

Description

Description Method for learning to measure the output voltage difference of a power factor corrector technical field

[0001] This disclosure falls within the domain of learning processes for an output voltage difference of a power factor corrector of an electrical circuit. Previous technique

[0002] In the field of electric vehicles, it is known that on-board units allow the management of the charging of electric batteries, when the vehicle is connected to the electrical network directly or via a charging station.

[0003] As illustrated in Figure 1, such an on-board box 2 typically includes: - a power factor corrector 4 (also called PFC for "Power Factor Corrector" in English) which ensures power transfer between its input connected to the electrical network 6, which delivers an alternating current (AC) voltage, and its output which delivers a constant direct current (DC) output voltage; and - a high voltage direct current direct current converter 8 (also called HV DCDC for "High Voltage Direct Current Direct Current" in English), electrically connected at input to the output of the power factor corrector 4, and electrically connected at output to a battery 8.

[0004] The on-board box 2 has the function of supplying electricity, from the electrical network 6, to the battery 10 with a substantially stable voltage, for example in the order of 400V or 800V depending on the size of the battery 10. In other words, the on-board box 2 has the function of presenting a power factor as close as possible to 1.

[0005] In this context, the 4x power factor correction requires precise measurement of the input and output voltages to ensure there is no discrepancy between the measured and actual voltages. The 4x power factor correction then performs the necessary compensation / correction.

[0006] The power factor corrector 4 includes at its output a capacitor, called DC LINK, connected to the high-voltage DC-DC converter 8, and composed of capacitors C1 and C2 arranged in series. DC LINK has a connection point, called MIDocunk, at which the connecting capacitors C1 and C2 are arranged on either side, i.e., MIDDCunk is between C1 and C2.

[0007] The total voltage of the DC LINK capacitor, known as the Vocunk output voltage, is controlled by a regulation loop that adjusts the RMS current under a certain voltage, thus stabilizing Vocunk. In other words, Vocunk is controlled by regulating the power drawn from the electrical grid.

[0008] The presence of a voltage difference, an "offset", between the measured Vocunk voltage and the actual VDC Link voltage causes a bias in the regulation loop, and therefore an error in the correction provided by the power factor corrector 4. Indeed, the connection capacitors C1, C2 which make up the DC LINK capacitor are intended to operate at a nominal voltage, and are not intended to operate at a different voltage.

[0009] Vocunk control necessarily involves an acquisition chain which can introduce a bias on the measured voltage.

[0010] It is known from prior techniques to measure the offset of the acquisition chain by a process comprising the following steps: cut off the power transfer, wait for the natural discharge of the connection capacities C1, C2, and perform offset learning.

[0011] However, this process involves waiting for the time of a discharge cycle of the C1, C2 capacitors at the DC Link level, which cycle is a function of the time constants of the capacitors.

[0012] Furthermore, it is not guaranteed that the voltage at the MIDocunk is actually zero after waiting for the natural discharge of the connection capacitors C1, C2, which adds uncertainty to the offset measurement.

[0013] Figure 2 illustrates the measurement of the voltage Vocunk during the natural discharge of the connecting capacitors C1, C2. After a waiting time equal to the time constant T = 80s, the voltage is equal to 37% of the initial voltage V0.

[0014] We observe that, even after a waiting time of 4T = 320s, a residual voltage persists: the zero value is not strictly reached.

[0015] Therefore, there is a need to measure and correct, accurately and quickly, the offset of an output voltage acquisition chain of a power factor corrector. Summary

[0016] To this end, this document proposes a method for learning the output voltage difference of a power factor corrector in an electrical circuit, said electrical circuit comprising: A single-phase or three-phase electrical network comprising at least one alternating voltage source and optionally being electrically connected to a neutral connection of the electrical circuit; the power factor corrector which includes: -- a switching cell; -- at least one connection capacitor arranged at the output of the power factor corrector; and-- optionally, a connection point arranged in series with said at least one connection capacitor, and capable of being electrically connected to the neutral connection via secondary switching means, said power factor corrector being capable of being electrically connected to said at least one AC voltage source of the electrical network via primary switching means; and an acquisition chain comprising a first voltage measuring device capable of measuring the output voltage of the power factor corrector and a second voltage measuring device capable of measuring the input voltage of the power factor corrector, said process includes the following steps: a. Configure the electrical circuit so that the power factor corrector is not electrically connected to the electrical grid. b. Configure the electrical circuit so that the electrical circuit has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector is electrically connected to a single AC voltage source from said at least one AC voltage source of the electrical network via the primary switching means; • A secondary configuration in which the power factor corrector is electrically connected to three AC voltage sources, including at least one AC voltage source from the electrical network, via the primary switching means, provided that: or the electrical network is three-phase, and or said at least one alternating voltage source comprises at least three alternating voltage sources; and • A tertiary configuration in which the electrical network is three-phase, the power factor corrector being electrically connected to three AC voltage sources, including at least one AC voltage source of the electrical network via the primary switching means, and the connection point is electrically connected to the neutral connection via the secondary switching means, provided that: or the electrical network is three-phase, or said at least one alternating voltage source includes at least three alternating voltage sources, the electrical network is electrically connected to a neutral connection of the electrical circuit, and o the power factor corrector comprises the connection point and at least two connection capacitors, the connection point being arranged between said at least two connection capacitors, and perform an initial passive pre-charge of the power factor corrector; c. Measure an RMS input voltage VIN of the power factor corrector; d. Calculate a first output pre-charge voltage VPRECOUT 1 satisfying: • if the first configuration of the electrical circuit corresponds to the primary configuration, V PREC 0UT 1 = 2 * V IN - 2 * V d , with Vd being the predetermined voltage threshold of the switching cell, • if the first configuration of the electrical circuit corresponds to the secondary configuration, • if the first configuration of the electrical circuit corresponds to the tertiary configuration, V PREC 0UT ± = 2 2 * V IN — 2 * V d , e. After the first passive precharge, measure an output voltage of the power factor corrector, referred to as the first measured output voltage VMESOUT -I, and f. Calculate a first output voltage difference VDIFF 1 corresponding to the difference between VMES OUT 1 and VPREC OUT 1.

[0017] It is to be understood that step (d) can be carried out at any time in the process following step (c) and preceding step (f).

[0018] Passive pre-charge of the power factor corrector means the passive pre-charge of said at least one connection capacitor of the power factor corrector.

[0019] It is also important to understand that: The conditions listed for the tertiary configuration do not necessarily imply that the electrical circuit will have the tertiary configuration, but are necessary conditions for the electrical circuit to be able to have the tertiary configuration. For example, the electrical circuit under these conditions may also have the primary or secondary configuration; The conditions listed for the secondary configuration do not necessarily imply that the electrical circuit will exhibit the secondary configuration, but rather are conditions necessary for the electrical circuit to be able to exhibit the secondary configuration. For example, the electrical circuit under these conditions may also exhibit the primary configuration; therefore, there are no conditions on the electrical circuit itself that would force it to exhibit the primary configuration.

[0020] The term "capacitance" refers to the equivalent capacitance of electronic components. For example, a first and second capacitor in series with capacitances CA and CB respectively have a combined equivalent capacitance C eq = (CA * CB) / (CA + CB).

[0021] In the case where the power factor corrector includes the connection point and at least two connection capacitors (i.e., a plurality of connection capacitors), the connection point is arranged between the plurality of connection capacitors which are arranged in series.

[0022] In particular, said at least two connection capacities and the connection point are arranged so that the equivalent capacity on one side of the connection point and that on the other side of the connection point are identical.

[0023] The acquisition chain may also include a microcontroller.

[0024] The measured output voltage values ​​from the acquisition chain can be regulated by a regulation loop.

[0025] The control loop can adapt the power factor corrector control to regulate the output voltage to a predefined setpoint (typically 800V).

[0026] The process requires the absence of offset on the acquisition of VIN, which can be obtained by a compensation strategy requiring a VIN measurement before configuration of the electrical network following the first configuration.

[0027] The process also requires that the actual gain of the output voltage sensor (first voltage measuring device) is known, or determined beforehand by a dedicated strategy.

[0028] Following step (b), the electrical circuit has a first configuration / topology.

[0029] In the case where the first configuration corresponds to the primary configuration: - The first output voltage difference VDIFF 1 is the difference between a measured voltage (VMESOUT 1) and a theoretical reference voltage, i.e., based on the input voltage VIN (VPRECOUT 1), in the case of the first electrical circuit configuration. VDIFF 1 corresponds to a first offset of the acquisition chain; - Once step (b) is completed, the power factor corrector behaves like a single-phase rectifier, and the first configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a single-phase source; - During step (d), the input voltage of the power factor corrector is an AC voltage. The rectifier converts the AC voltage into a DC voltage whose value is related to the peak value of the input AC voltage, which explains the presence of the term square root of 2.- VPRECOUT 1 corresponds to the theoretical rectified DC voltage is equal to the peak (maximum) value of the AC voltage from which we must subtract 2 x Vd, the voltage across the two body diodes of the switching cell, which diodes serve for passive rectification; - That's why we have the following formula: V PREC 0UT = Ï. * V IN - 2 * V d .

[0030] In the case where the first configuration corresponds to the secondary configuration: - The secondary configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a three-phase source, but without a connection to the neutral; - Consequently, the first output precharge voltage VPREC OUT 1 has a different formulation, specific to the secondary configuration. The term Vô * V IN is justified by the fact that, given that the power factor corrector is electrically connected to the three voltage sources of the three-phase electrical network, the peak voltage is equal to the square root of 3 times the term V2 * V IN present in the formulation of VPRECOUT 1. - More specifically, VPREC OUT 1 (which corresponds to the theoretical rectified DC voltage) is determined by the peak voltage between the phases in three-phase, i.e. the peak voltage (square root of 2 times the effective voltage VIN) multiplied by square root of 3.

[0031] In the case where the first configuration corresponds to the tertiary configuration: - The tertiary configuration of the electrical circuit corresponds to a situation in which the power factor corrector is electrically connected to a three-phase source, with connection to the neutral; - As a result, the first output precharge voltage VPREC OUT 1 has a different formulation, specific to the tertiary configuration; - When the midpoint of the connecting capacitors (the connection point) is connected to the neutral connection, each connecting capacitor has a rectified voltage of √2 times VIN from which Vd is subtracted (for the respective body diode); - Therefore, the theoretical rectified DC voltage VPREC OUT 1 is equal to the sum of the rectified voltages of the connecting capacitors, i.e., V PREC0UT r = 2V2 * V IN - 2 * V d .

[0032] The output voltage of the power factor corrector then increases until the natural end of the passive precharge (step (e)), the output voltage being dependent on the topology of the power factor corrector (i.e. the configuration of the electrical circuit).

[0033] These elements allow us to determine accurately the first output precharge voltage VPRECOUT 1, and consequently the first output voltage difference VDIFF 1.

[0034] Furthermore, the calculation (learning) of a voltage difference using this method is guaranteed, regardless of the load cycle considered.

[0035] The process has a fast acquisition and calculation time: the time constant of a passive precharge is on the order of a second, and is therefore less than the time constant of a discharge which is used in conventional solutions.

[0036] In the case where the power factor corrector includes a plurality of connecting capacitors arranged in series, the output voltage of the power factor corrector corresponds to the sum of the voltages across each connecting capacitor.

[0037] The process may also include the following steps: g. Configure the electrical circuit so that the electrical circuit has a second configuration distinct from the first configuration, said second configuration corresponding to: • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration; • the tertiary configuration if the first configuration corresponds to the secondary configuration, and perform a second passive precharge of the power factor corrector, h. Measure and update the RMS input voltage VIN of the power factor corrector, i. Calculate a second output precharge voltage VPRECOUT 2 satisfying: • If the second configuration corresponds to the secondary configuration, V PREC 0UT2 = / ~6 * V IN — 2 * V d , • If the third configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2^2 * V IN — 2 * V d , j. After the second passive precharge, measure an output voltage of the power factor corrector, referred to as the second measured output voltage VMESOUT 2, and k. Calculate a second output voltage difference VDIFF 2 corresponding to the difference between VMES OUT 2 and VPREC OUT 2.

[0038] It is to be understood that step (i) can be carried out at any time in the process following step (h) and preceding step (k).

[0039] Following step (g), the electrical circuit has a second configuration.

[0040] The second output voltage difference, VDIFF 2, is the difference between a measured voltage (VMES OUT 2) and a theoretical reference voltage (VPREC OUT 2), in the case of the second electrical circuit configuration. This second output voltage difference, VDIFF 2, corresponds to a second offset in the acquisition chain.

[0041] The VPREC OUT 2 formulas respect the same electrical circuit configuration conditions as those for VPREC OUT 1.

[0042] The process may also include the following steps: l. Configure the electrical circuit so that the electrical circuit has a third configuration corresponding to the tertiary configuration, and perform a third passive pre-charge of the power factor corrector, m. Measure and update the RMS input voltage VIN of the power factor corrector. n. Calculate a third output pre-charge voltage VPREC OUT 3 satisfying: V PREC0UT 3 = 2V2 * V IN ~ 2 * V d , 0. After the third passive pre-charge, measure the output voltage of the power factor corrector, referred to as the third measured output voltage VMESOUT S, p. Calculate a third output voltage difference VDIFFS between VMESOUT S and VPREC OUT 3

[0043] It is important to understand that the VIN measurements are taken using the second voltage measuring device, and the VMES OUT 1, VMES OUT 2, and VMES OUT 3 measurements are taken using the first voltage measuring device.

[0044] It is to be understood that step (n) can be carried out at any time in the process following step (m) and preceding step (p).

[0045] Following step (I), the electrical circuit has a third configuration.

[0046] The third output voltage difference is the difference between a theoretical reference voltage (VPREC OUT 3) and a measured voltage (VMESOUTS), in the case of the third electrical circuit configuration. The third output voltage difference, VDIFF 3, corresponds to a third offset in the acquisition chain.

[0047] The VPREC OUT 3 formulas respect the same electrical circuit configuration conditions as those for VPREC OUT 1

[0048] The process may further include the following step: q. Calculate (EQ) an average output voltage difference VDIFF MOY which difference is equal to the average of VDIFF 1, VDIFF 2 and VDIFFS.

[0049] Step (q) improves the calculation of the voltage difference by exploiting, by averaging, the first, second and third output voltage differences VDIFF 1, VoiFF2 and VDIFF 3 previously calculated.

[0050] In other words, the process allows for learning the different possible scenarios (first, second, and third configurations of the electrical circuit) in order to determine as precisely as possible the difference between the measured voltage and the actual output voltage of the power factor corrector, so as to effectively compensate for any potential measurement bias. Similarly, the process incorporates the principle of experimental repeatability to minimize uncertainties in the results obtained.

[0051] Depending on the country, the sizing of the electrical power supply network for an on-board unit varies (single-phase, three-phase, supply voltage, etc.). The primary and secondary switching means allow the electrical circuit to present the first, second, and third configurations, which correspond to the different electrical network systems possible in the world.

[0052] In other words, the electrical circuit allows the determination of the output voltage difference to be adapted according to the power supply of the electrical network (the electrical network in single-phase, three-phase mode) and according to the connection to the neutral of the power factor corrector, while exploiting this adaptability to improve the accuracy of the learning.

[0053] In the case of a data acquisition chain including a microcontroller, the process can perform the learning even if the microcontroller resets during or after the various passive preload phases, since the waiting times for the different preloads are short. The process thus exhibits greater robustness against a potential microcontroller reset.

[0054] The power factor corrector also includes: a first and a second pull-up resistor arranged in series with the first and second connecting capacitors respectively; and of the first and second tertiary switching means which are arranged in parallel with the first and second inrush resistors respectively, the process further comprising at least one of the following: between steps (a) and (b), step (a1) of opening the first and second tertiary switching means, and between steps (d) and (e), step (d1) of closing the first and second tertiary switching means, between steps (f) and (g), step (f1) of opening the first and second tertiary switching means, and between steps (i) and (j), step (il) of closing the first and second tertiary switching means, and between steps (k) and (I), step (k1) of opening the first and second tertiary switching means, and between steps (n) and (o), step (n1) of closing the first and second tertiary switching means.

[0055] When the first and second tertiary switching means are open (steps (a1), (f1) and (k1)), the first and second inrush resistors limit the inrush current through them during the electrical connection steps (steps (b), (g) and (I)) i.e., electrical circuit configuration.

[0056] Thus, the sudden increase in current caused by the transition from one configuration to another in the electrical circuit does not generally damage the power factor corrector.

[0057] In other words, the first and second inrush resistors smooth the inrush current by creating a load loss.

[0058] The measurement of the measured output voltages VMES OUT 1, VMES OUT 2 and VMESOUT 3 is influenced by the presence of the first and second pull-up resistors.

[0059] It is necessary to close the first and second tertiary switching means before the measurements of the measured output voltages VMES OUT 1, VMES OUT 2 and VMES OUT 3 (steps (e), (j) and (0)).

[0060] Therefore, once the passive pre-charge is complete, or the passive pre-charge related to the transition from one configuration to another is complete, the first and second tertiary switching means (steps (d1), (il) and (n1)) which short-circuit the first and second pull-in resistors are closed.

[0061] In other words, the current bypasses the first and second inrush resistors and passes through the first and second tertiary switching means.

[0062] The output voltage of the power factor corrector can be measured continuously, and: Step (d1) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 1, Step (il) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 2, and Step (n1) can be performed when the output voltage of the power factor corrector is between 85% and 95%, preferably 90%, of VPRECOUT 3.

[0063] In this way, we ensure that we benefit from a sufficient inrush current limitation, while allowing a reliable measurement of the measured output voltages.

[0064] Continuous measurement of the output voltage of the power factor corrector can be achieved by the voltage measuring device of the acquisition chain.

[0065] The process may further include the following step: (r) configure the power factor corrector so as to compensate for at least one of VDIFF 1, VDIFF 2, VDIFF 3 and VDIFF MOY.

[0066] By compensating at least one of VDIFF 1, VDIFF 2 and VDIFF 3 and VDIFF MOY, we mean to define at least one corrective offset (adjusted or applied value to compensate for a shift i.e. an offset) on the measured output voltage of the power factor corrector VMES OUT, so that a measured corrected output voltage VouT_cor satisfies VouT_cor = VMES OUT - VDIFF, with VDIFF which is equal to one of VDIFF 1, VDIFF 2, VDIFF 3 and VDIFF MOY.

[0067] Offset compensation on the measured output voltage allows for more accurate regulation of the actual output voltage.

[0068] The switching cell can comprise a plurality of MOSFET transistors.

[0069] This document may also relate to a computer intended to be installed in an on-board unit of an electric motor vehicle comprising at least one processor and at least one memory, characterized in that the computer is configured to implement each of the steps of a process according to the aforementioned type.

[0070] This document may also concern a set including: A charging station for an electric or hybrid motor vehicle which includes an electrical network comprising at least one source of alternating voltage and being optionally electrically connected to a neutral connection; An on-board unit of an electric or hybrid motor vehicle, said on-board unit comprising: -- the calculator according to the aforementioned type; -- the power factor corrector which includes: • a switching cell, • at least one connection capacitor arranged at the output of the power factor corrector, and • optionally, a connection point arranged in series with said at least one connection capacity, and capable of being electrically connected to the neutral connection via secondary switching means, said power factor corrector being capable of being electrically connected to said at least one AC voltage source of the electrical network via primary switching means; -- a data acquisition chain comprising a first voltage measuring device capable of measuring the output voltage of the power factor corrector and a second voltage measuring device capable of measuring the input voltage of the power factor corrector; and -- a high-voltage DC-DC converter electrically connected at the input to the output of the power factor corrector, and an electric battery of the electric or hybrid motor vehicle electrically connected to the output of the DC-DC voltage converter of the on-board unit.

[0071] In the case where the power factor corrector of the on-board box includes the connection point and at least two connection capacitors (i.e. a plurality of connection capacitors), the connection point is arranged between the plurality of connection capacitors which are arranged in series.

[0072] In particular, said at least two connection capacities and the connection point are arranged so that the equivalent capacity on one side of the connection point and that on the other side of the connection point are identical. Brief description of the drawings

[0073] Other features, details, and advantages will become apparent upon reading the detailed description below and analyzing the attached drawings, on which:

[0074] [Fig. 1] is a schematic view illustrating an on-board unit connected to an electrical network and a battery,

[0075] [Fig. 2] is a graph of the evolution of the output voltage as a function of time during the natural discharge of the connecting capacitors,

[0076] [Fig. 3A] is a schematic view of an electrical circuit for measuring an output voltage difference of a power factor corrector according to an embodiment of this document, the electrical circuit being in an initial configuration,

[0077] [Fig. 3B] is a schematic view of the electrical circuit of figure 3A in a first configuration,

[0078] [Fig. 3C] is a schematic view of the electrical circuit of figure 3A in a second configuration,

[0079] [Fig. 3D] is a schematic view of the electrical circuit in Figure 3A in a third configuration,

[0080] [Fig. 4A], [Fig. 4B], [Fig. 4C] illustrate the different stages of a learning process for an output voltage difference of a power factor corrector of the electrical circuit according to the embodiments of figures 3A to 3D,

[0081] [Fig. 5] is a graph of the evolution of the measured output voltage and the output pre-charge voltage of the power factor corrector as a function of the actual output voltage of said power factor corrector, according to the embodiment of Figures 3A to 3D,

[0082] [Fig. 6] is a graph of the evolution of the output voltage difference between the measured output voltage and the output pre-charge voltage of the power factor corrector according to Figure 5, and

[0083] [Fig. 7] represents the evolution of the measured output voltage of the power factor corrector, during a first preload, over time. Description of the implementation methods

[0084] Figure 3A illustrates an electrical circuit according to an embodiment of this document, which electrical circuit 20 comprises a three-phase electrical network 30. The electrical circuit 30 has an initial configuration.

[0085] The electrical network 30 is connected to a neutral connection N and comprises three arms 30a, 30b, 30c on which three alternating voltage sources 32a, 32b, 32c are arranged respectively. Primary switching means 34a, 34b, 34c are arranged in series with the three voltage sources 32a, 32b, 32c respectively.

[0086] The electrical circuit further includes a power factor correction 40 which comprises a switching cell. The switching cell comprises a plurality of switches S1, S2, S3, S4, S5, S6.

[0087] This plurality of switches S1, S2, S3, S4, S5, S6 are arranged so that the series pairs S1-S2, S3-S4 and S5-S6 are in parallel with each other.

[0088] Switches S1, S3 and S5 are called the upper (or top) switches and switches S2, S4 and S6 are called the lower (or bottom) switches.

[0089] The state of the switches is such that S2 is in a state opposite to S1, S4 is in a state opposite to S3 and S6 is in a state opposite to S5, i.e. the state of the upper switches is inverse to that of the lower switches.

[0090] The power factor corrector 40 further includes, at output, a first and a second connection capacitance CLINK 1, CLINK 2 in series with each other, which connection capacitances CLINK-I, CLINK 2 define between them a midpoint corresponding to a connection point MIDocLiNK which is electrically connected to the neutral connection N via secondary switching means S7.

[0091] The CLINK 1, CLINK 2 connection capabilities are arranged in parallel with the S1-S2, S3-S4 and S5-S6 switch pairs (the switching cell).

[0092] The output voltage of the power factor corrector 40 corresponds to the output voltage VocLiNK of Figure 1. VREELOUT I3 is the actual output voltage of the power factor corrector 40, which is different from the measured output voltage of the power factor corrector 40.

[0093] A first and a second call resistor RAPPEL 1 and RAPPEL 2 are arranged in series with the first and second connection capacitors CLINK 1, CLINK 2 respectively.

[0094] CLINK 1 and CLINK 2 here represent identical equivalent capacities on each side of the MIDDC LINK connection point.

[0095] The first and second tertiary switching means S8, S9 are arranged in parallel with the first and second pull-up resistors RAPPEL 1 and RAPPEL 2 respectively.

[0096] The power factor corrector 40 is electrically connected, at the input, to the three alternating voltage sources 32a, 32b, 32c of the three-phase electrical network 30 by the primary switching means 34a, 34b, 34c.

[0097] Although not illustrated, it is to be understood that the power factor corrector 40 is electrically connected, at output, to a high voltage DC-DC converter 8 (as shown in Figure 1).

[0098] More specifically, each voltage source 32a, 32b, 32c is electrically connected to a pair of switches S1-S2, S3-S4 and S5-S6 respectively.

[0099] In addition, power inductances Indi, Ind 2 and Ind ss are arranged in series between the corresponding primary switching means 34a, 34b, 34c and the power factor corrector 40.

[0100] The electrical circuit 20 further includes an acquisition chain 49 comprising a first voltage measuring device 50 capable of measuring the output voltage of the power factor corrector 40.

[0101] The acquisition chain 49 further includes a second voltage measuring device 60 suitable for measuring the input voltage of the power factor corrector 40, i.e. the voltage at the connection between the primary switching means 34a, 34b, 34c and the power inductors Indi, Ind 2 and Ind 3.

[0102] Figures 4A to 4C illustrate the different stages of a learning process for an output voltage difference of a power factor corrector of the electrical circuit according to the embodiments of figures 3A to 3D.

[0103] During an EA step, the electrical circuit 20 is configured so that the power factor corrector 40 is not electrically connected to the electrical network 30. In other words, the electrical circuit 20 is configured according to the initial configuration of Figure 3A.

[0104] During an EA1 step, the first and second tertiary switching means S8, S9 are opened.

[0105] During an EB step, the electrical circuit 20 is configured so that the electrical circuit 20 has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector 40 is electrically connected to a single AC voltage source 30a among said at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c; • A secondary configuration in which the power factor corrector 40 is electrically connected to three AC voltage sources 32a, 32b, 32c, including at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c, provided that: the electrical network 30 is three-phase, and said at least one AC voltage source 32a, 32b, 32c comprises at least three AC voltage sources; and • A tertiary configuration in which the electrical network 30 is three-phase, the power factor corrector 40 being electrically connected to three AC voltage sources 32a, 32b, 32c from said at least one AC voltage source 32a, 32b, 32c of the electrical network 30 via the primary switching means 34a, 34b, 34c, and the MIDDC LINK connection point is electrically connected to the neutral connection N via the secondary switching means S7, provided that: o the electrical network 30 is three-phase, o said at least one alternating voltage source 32a, 32b, 32c comprises at least three alternating voltage sources, o the electrical network 30 is electrically connected to a neutral connection N of the electrical circuit 20, and where the power factor corrector 40 includes the MIDDC LINK connection point and at least two CLINK 1, CLINK 2 connection capacitances, the MIDDC LINK connection point being arranged between said at least two CLINK 1, CLINK 2 connection capacitances, and a first passive pre-charge of the power factor corrector 40 is performed.

[0106] In this embodiment, the first configuration corresponds to the primary configuration: the electrical circuit 20 has a topology in which one of the switches forming the primary switching means 34a, 34b, 34c is closed. In this first configuration, the electrical network 30 is equivalent to a single-phase source.

[0107] Figure 3B illustrates the electrical circuit in the first configuration of electrical circuit 20: one of the primary switching means 34a, 34b, 34c is closed (here 34a) and the secondary switching means S7 are open. Furthermore, the other switching means 34b and 34c are configured so that their respective arms are folded down (i.e., connected) to a corresponding branch 35b, 35c connected to the neutral connection N.

[0108] During the first passive precharge, the inrush current will flow through the inrush resistors RAPPEL 1 and RAPPEL 2 (given that the first and second tertiary switching means S8, S9 are open) before flowing through the first and second connection capacitors CLINK 1, CLINK2.

[0109] The pull-up resistors RAPPEL 1 and RAPPEL 2 will create load losses and thus prevent damage to the electronic components of the passive rectification circuit of the power factor corrector 40, and prevent overcurrents.

[0110] In the remainder of this section and according to this embodiment, the first configuration is considered to be the primary configuration.

[0111] During an EC step, an effective input voltage VIN of the power factor corrector 40 is measured.

[0112] During an ED step, a first output precharge voltage VPREC OUT 1 is calculated, satisfying: V PREC0UT1 = 2 * V IN - 2 * V d , with Vd the predetermined voltage threshold of the switching cell S1, S2, S3, S4, S5, S6.

[0113] This formulation of VPRECOUTI is justified by the fact that the first configuration of the electrical circuit 20 corresponds to the primary configuration.

[0114] Given that the electrical circuit configurations / topologies 20 are known in the process steps, the formulation of the output preload voltages is predictable.

[0115] During a step ED1, the first and second tertiary switching means S8, S9 are closed. In this way, the current will bypass the inrush resistors RAPPEL 1 and RAPPEL 2 which have fulfilled their function of smoothing the inrush current.

[0116] Optionally, step ED1 can be performed when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 1. According to this aspect, the output voltage of the power factor corrector 40 is measured continuously.

[0117] During an EE step, at the end of the first passive precharge, an output voltage of the power factor corrector 40 is measured, called the first measured output voltage VMESOUT 1.

[0118] During an EF step, we calculate a first output voltage difference DIFF 1 corresponding to the difference between VMESOUT 1 and VPRECOUT 1.

[0119] In other words: VDIFF 1 = VMESOUT I - VPRECOUT I

[0120] The calculation of the first output voltage difference VDIFF 1 is illustrated in Figure 5.

[0121] Curve 50 represents the evolution of the theoretical output voltage (i.e. based on the input voltage VIN), VPREC OUT I (among others, VPREC OUT 2, and VPREC OUT 3 defined later), as a function of the actual output voltage VREELOUT.

[0122] Curve 52 represents the evolution of the measured output voltage, VMES OUT I among others, VMES OUT 2, and VMES OUT 3 defined after, as a function of the actual output voltage VREELOUT.

[0123] The first configuration of the electrical circuit 20 corresponds to the case relating to the line with abscissa X1. The first output precharge voltage VPREC OUT 1 is the ordinate of the curve 50 at abscissa X1, the first output measured voltage VMES OUT 1 is the ordinate of the curve 52 at abscissa X1, and the first output voltage difference VDIFF 1 is equal to VMES OUT 1 - VPREC OUT 1.

[0124] Similar to step EA1, during a step EF1, the first and second tertiary switching means S8, S9 are opened again.

[0125] This helps to protect the connection capabilities of CLINK 1, CLINK 2 from the incoming inrush current.

[0126] During an EG step, the electrical circuit 20 is configured so that the electrical circuit 20 has a second configuration distinct from the first configuration, said second configuration corresponding to: • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration; • the tertiary configuration if the first configuration corresponds to the secondary configuration, and a second passive pre-charge of the power factor corrector is performed with a power factor of 40.

[0127] In this embodiment, where the second configuration corresponds to the secondary configuration, the electrical circuit 20 has a topology in which the switches forming the primary switching means 34a, 34b, 34c are closed. In this second configuration, the electrical network 30 is equivalent to a three-phase source.

[0128] In other words, the second configuration of the electrical circuit 20 corresponds to a configuration in which the primary switching means 34a, 34b, 34c are closed and the secondary switching means S7 are open. This second configuration is shown in Figure 3C.

[0129] In the remainder of this section and according to this embodiment, the second configuration is considered to be the secondary configuration.

[0130] During an EH step, the effective input voltage VIN of the power factor corrector 40 is measured and updated.

[0131] During step El, a second output pre-charge voltage VPREC OUT 2 is calculated, satisfying: • If the second configuration corresponds to the secondary configuration, V PREC 0UT2 = 4~6 * V IN — 2 * V d , • If the third configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2 2 * VIN - 2 * V d .

[0132] In our case, we therefore have: V PREC 0UT2 = * V IN - 2 * V d .

[0133] This formulation of VPREC OUT 2 is justified by the fact that the second configuration of the electrical circuit 20 corresponds to the secondary configuration.

[0134] Similar to step ED1, during a step EI1, the first and second tertiary switching means S8, S9 are closed.

[0135] Optionally, the EU step can be performed when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 2. According to this aspect, the output voltage of the power factor corrector 40 is measured continuously.

[0136] During an EJ step, at the end of the second passive pre-charge, an output voltage of the power factor corrector 40 is measured, called the second measured output voltage VMESOUT 2,

[0137] During an EK step, a second output voltage difference VDIFF 2 is calculated, corresponding to the difference between VMESOUT 2 and VPREC OUT 2.

[0138] The calculation of the second output voltage difference VDIFF 2 is illustrated in Figure 5.

[0139] The second configuration of the electrical circuit corresponds to the case relating to the line with abscissa X2. The second output precharge voltage VPREC OUT 2 is the ordinate of the curve 50 at abscissa X2, the second output measured voltage VMEsouT2 is the ordinate of the curve 52 at abscissa X2, and the second output voltage difference VDIFF 2 is equal to VMES OUT 2 - VPREC OUT 2.

[0140] Similar to steps EA1 and EF1, during a step EK1, the first and second tertiary switching means S8, S9 are opened.

[0141] During an EL step, the electrical circuit 20 is configured so that the electrical circuit 20 has a third configuration corresponding to the tertiary configuration, and a third passive pre-charge of the power factor corrector 40 is performed.

[0142] In this way, the electrical circuit 20 has a topology in which the switches forming the primary switching means 34a, 34b, 34c are closed. In this third configuration, the electrical network 30 is equivalent to a three-phase source.

[0143] In other words, the third configuration of the electrical circuit 20 corresponds to a configuration in which the primary switching means 34a, 34b, 34c are closed and the secondary switching means S7 are also closed. This third configuration is shown in Figure 3D.

[0144] During an EM step, the effective input voltage VIN of the power factor corrector 40 is measured and updated.

[0145] During an EN step, a third output pre-charge voltage VPREC OUT 3 is calculated, satisfying . V PREC 0UT 3 = 2 2 * V IN — 2 * V d .

[0146] Similar to steps ED1 and EI1, during an EN1 step, the first and second tertiary switching means S8, S9 are closed.

[0147] Optionally, step EN1 can be performed when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 3. According to this aspect, the output voltage of the power factor corrector 40 is measured continuously.

[0148] During an EO stage, at the end of the third passive precharge, an output voltage of the power factor corrector 40 is measured, referred to as the third measured output voltage VMES OUT 3

[0149] During an EP step, a third voltage difference VDIFF S is calculated at the output between VMES OUT 3 and VPREC OUT 3

[0150] The calculation of the third output voltage difference VDIFF S is illustrated in Figure 5.

[0151] The third configuration of the electrical circuit corresponds to the case relating to the line with abscissa X3. The third output precharge voltage VPREC OUT 3 is the ordinate of the curve 50 at abscissa X3, the third output measured voltage VMES OUT 3 is the ordinate of the curve 52 at abscissa X3, and the third output voltage difference VDIFF 3 is equal to VMES OUT 3 - VPREC OUT 3.

[0152] Figure 6 illustrates the voltage differences VDIFF 1, VDIFF 2, and VDIFF 3 as a function of the actual output voltage VREELOUT

[0153] During an EQ step, an average output voltage difference VDIFF MOY is calculated, which difference is equal to the average of VDIFF 1, VDIFF 2 and VDIFFS.

[0154] In this way, we exploit the previously obtained output voltage differences VDIFF 1, VDIFF2 and VDIFFS to improve the reliability and accuracy of learning by averaging VDIFF MOY.

[0155] Figure 7 represents the evolution of the output voltage of the power factor corrector 40, during the first pre-charge, in the case where the tertiary switching means S8, S9 are open.

[0156] We observe that after a duration T' = 3s, the output voltage has reached its final value. The output voltage exceeds 90% of VPREC OUT 1 (0.9* VPREC OUT 1) after a duration T = 1s; it is at this moment that the first and second tertiary switching means S8, S9 are closed (step (d1)), which instantaneously brings the output voltage to its final value and terminates the pre-charge phase.

[0157] We can therefore understand the benefit of performing step (d1) when the output voltage of the power factor corrector 40 is between 85% and 95%, preferably 90%, of VPREC OUT 1.

[0158] If we take the case of performing step (d1) when the output voltage of the power factor corrector 40 is equal to 90% of VPREC OUT 1.

[0159] On the one hand, we therefore allow ourselves a 10% error on VMES OUT 1. Even though VMES OUT 1 includes a 10% error, a detection margin is present to take it into account.

[0160] On the other hand, a stable voltage at the connection point with the inrush resistors RAPPEL 1 and RAPPEL 2 short-circuited (S8 and S9 closed) improves the subsequent VMES OUT 1 measurement (step (e)). Therefore, RAPPEL 1 and RAPPEL 2 are short-circuited in a voltage regime with few fluctuations: a regime in which the voltage is close to its final value. Almost reaching the final voltage value, the currents flowing are relatively low: the inrush resistors RAPPEL 1 and RAPPEL 2 are no longer needed.

[0161] This is of course transposable to steps (il) and (n1), and therefore to the second and third preloads.

[0162] The learning process is very fast, since it exploits the passive pre-charge of the CLINK 1, CLINK 2 connection capacities, unlike conventional prior art solutions which exploit the natural discharge of the connection capacities.

[0163] It is important to understand that the orders of magnitude of time are essentially the same for the second and third passive preloads.

[0164] During a final ER step, the power factor corrector 40 is configured to compensate at least one of VDIFF 1, VDIFF2, VDIFF 3 and VDIFF MOY (here we compensate VDIFF MOY).

[0165] In other words, an adjusted / corrected value is defined on the measured output voltage of the power factor corrector, VMES OUT, the corrected measured output voltage VouT_cor satisfying VoUT_cor = VlVIES OUT - VDIFF MOY

[0166] It is to be understood that the fact that the electrical circuit presents such a sequence of electrical configurations (primary, then secondary then tertiary) allows to make three voltage measurements VMES 1, VMES 2, VMES 3, and thus calculate VDIFF 1, VDIFF 2, VDIFF 3 to deduce VDIFF MOY.

[0167] In the case of at least two voltage measurements, the power factor corrector must necessarily exhibit an increasing output voltage between each electrical configuration. A learning process can also be envisioned with a single voltage measurement VMES I (and thus a single voltage difference VDIFF 1).

[0168] Therefore, the electrical circuit can also: Present a first configuration corresponding to one of the primary, secondary, and tertiary configurations (without a second or third configuration), present a first configuration corresponding to the primary configuration followed by a second configuration corresponding to the secondary configuration (without a third configuration), or, Present a first configuration corresponding to one of the primary and secondary configurations, followed by a second configuration corresponding to the tertiary configuration (without a third configuration).

Claims

Demands

1. A method for learning the output voltage difference of a power factor corrector (40) of an electrical circuit (20), said electrical circuit (20) comprising: A single-phase or three-phase electrical network (30) comprising at least one alternating voltage source (32a, 32b, 32c) and optionally being electrically connected to a neutral connection (N) of the electrical circuit (20); the power factor corrector (40) which comprises: -- a switching cell (S1, S2, S3, S4, S5, S6); -- at least one connection capacitor (CLINK 1, CLINK 2) arranged at the output of the power factor corrector (40); and -- optionally, a connection point (MIDDC LINK) arranged in series with said at least one connection capacity (CLINK 1, CLINK 2), and capable of being electrically connected to the neutral connection (N) via secondary switching means (S7), said power factor corrector (40) being capable of being electrically connected to said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via primary switching means (34a, 34b, 34c); and an acquisition chain (49) comprising a first voltage measuring device (50) capable of measuring the output voltage of the power factor corrector (40) and a second voltage measuring device (60) capable of measuring the input voltage of the power factor corrector (40), said process includes the following steps: a. Configure (EA) the electrical circuit (20) so that the power factor corrector (40) is not electrically connected to the electrical network (30), b. Configure (EB) the electrical circuit (20) so that the electrical circuit (20) has a first configuration corresponding to one of the following configurations: • A primary configuration in which the power factor corrector (40) is electrically connected to a single AC voltage source (30a) from said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via the primary switching means (34a, 34b, 34c); • A secondary configuration in which the power factor corrector (40) is electrically connected to three AC voltage sources (32a, 32b, 32c) from said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via the primary switching means (34a, 34b, 34c), provided that: the electrical network (30) is three-phase, and said at least one AC voltage source (32a, 32b, 32c) comprises at least three AC voltage sources; and • A tertiary configuration in which the electrical network (30) is three-phase, the power factor corrector (40) is electrically connected to three AC voltage sources (32a, 32b, 32c) from said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via the primary switching means (34a, 34b, 34c), and the connection point (MIDDC LINK) is electrically connected to the neutral connection (N) via the secondary switching means (S7), provided that: o the electrical network (30) is three-phase, o said at least one alternating voltage source (32a, 32b, 32c) comprises at least three alternating voltage sources, o the electrical network (30) is electrically connected to a neutral connection (N) of the electrical circuit (20), and o the power factor corrector (40) comprises the connection point (MIDDC LINK) and at least two connection capacities (CLINK 1 , CLINK 2), the connection point (MIDDC LINK) being arranged between said at least two connection capacities (CLINK 1 , CLINK 2), and perform a first passive precharge of the power factor corrector (40); c. Measure (EC) an RMS input voltage VIN of the power factor corrector (40); d. Calculate (ED) a first output precharge voltage VPRECOUT satisfying: • if the first configuration of the electrical circuit (20) corresponds to the primary configuration, V PREC 0UT 1 = 2 * V IN - 2 * V d, with Vd the predetermined voltage threshold of the switching cell (S1, S2, S3, S4, S5, S6), • if the first configuration of the electrical circuit corresponds to the secondary configuration, • if the first configuration of the electrical circuit corresponds to the tertiary configuration, V PREC 0UT ± = 2 2 * V IN — 2 * V d , e. After the first passive precharge, measure (EE) an output voltage of the power factor corrector (40), called the first measured output voltage VMESOUT -I, and f. Calculate (EF) a first output voltage difference VDIFF 1 corresponding to the difference between VMES OUT 1 and VPREC OUT 1.

2. A method according to claim 1 further comprising the steps: g. Configure (EG) the electrical circuit (20) such that the electrical circuit (20) has a second configuration distinct from the first configuration, said second configuration corresponding to: • the secondary or tertiary configuration if the first configuration corresponds to the primary configuration; • the tertiary configuration if the first configuration corresponds to the secondary configuration, and perform a second passive pre-charge of the power factor corrector (40), h. Measure and update (EH) the RMS input voltage VIN of the power factor corrector (40), i. Calculate (E1) a second output precharge voltage VPRECOUT 2 satisfying: • If the second configuration corresponds to the secondary configuration, V PREC 0UT2 = / ~6 * V IN — 2 * V d , • If the third configuration corresponds to the tertiary configuration, V PREC 0UT 2 = 2^2 * V IN — 2 * V d , j. After the second passive precharge, measure (EJ) an output voltage of the power factor corrector (40), called the second measured output voltage VMES OUT 2, and k. Calculate (EK) a second output voltage difference VDIFF 2 corresponding to the difference between VMES OUT 2 and VPRECOUT 2.

3. A method according to claim 2, wherein the first configuration corresponds to the primary configuration, and the second configuration corresponds to the secondary configuration, the method further comprising the steps: l. Configure (EL) the electrical circuit (20) so that the electrical circuit (20) has a third configuration corresponding to the tertiary configuration, and perform a third passive pre-charge of the power factor corrector (40), m. Measure and update (EM) the RMS input voltage VIN of the power factor corrector (40), n. Calculate (EN) a third output pre-charge voltage VPRECOUT S satisfying: V PREC OlJT 3 = 2V2 * V IN - 2 * V d , 0. At the end of the third passive precharge, measure (EO) an output voltage of the power factor corrector (40), called the third measured output voltage VMES OUT S, p. Calculate (EP) a third voltage difference VDIFF 3 at the output between VMES OUT S and VpREC OUT 3

4. Method according to claim 3 further comprising step q. Calculate (EQ) an average output voltage difference VDIFF MOY which difference is equal to the average of VDIFF 1 , VDIFF 2 and VDIFF 3.

5. A method according to any one of claims 1 to 4, wherein the power factor corrector (40) further comprises: a first and a second pull-in resistor (REMINDER 1, REMINDER 2) arranged in series with the first and second connecting capacitors (CLINK 1, CLINK 2) respectively; and first and second tertiary switching means (S8, S9) which are arranged in parallel with the first and second pull-in resistors (REMINDER 1, REMINDER 2) respectively, the process further comprising at least one of the following: between steps (a) and (b), step (a1) of opening (EA1) the first and second tertiary switching means (S8, S9), and between steps (d) and (e), step (d1) of closing (ED1) the first and second tertiary switching means (S8, S9), between steps (f) and (g), step (f1) of opening (EF1) the first and second tertiary switching means (S8, S9), and between steps (i) and (j), step (il) of closing (EI1) the first and second tertiary switching means (S8, S9), and between steps (k) and (I), step (k1) of opening (EK1) the first and second tertiary switching means (S8, S9), and between steps (n) and (0), step (n1) of closing (EN1) the first and second tertiary switching means (S8, S9).

6. A method according to claim 5, wherein the output voltage of the power factor corrector (40) is measured continuously, and wherein: Step (d1) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 1, Step (il) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 2, and Step (n1) is performed when the output voltage of the power factor corrector (40) is between 85% and 95%, preferably 90%, of VPRECOUT 3.

7. A method according to any one of claims 1 to 6 further comprising the step: r. Configure (ER) the power factor corrector (40) so as to compensate for at least one of VDIFF 1, VDIFF 2, VDIFF 3 and VDIFF MOY.

8. A method according to any one of claims 1 to 7, wherein the switching cell comprises a plurality of MOSFET transistors (S1, S2, S3, S4, S5, S6).

9. Computer intended to be installed in an on-board box of an electric motor vehicle comprising at least one processor and at least one memory, characterized in that the computer is configured to implement each of the steps of a method according to any one of claims 1 to 8.

10. Set comprising: A charging station for an electric or hybrid motor vehicle comprising an electrical network (30) including at least one AC voltage source (32a, 32b, 32c) and optionally electrically connected to a neutral connection (N); An on-board unit of an electric or hybrid motor vehicle, said on-board unit comprising: -- the calculator according to claim 9; -- the power factor corrector (40) which comprises: • a switching cell (S1, S2, S3, S4, S5, S6), • at least one connection capacitor (CLINK 1, CLINK 2) arranged at the output of the power factor corrector (40), and • Optionally, a connection point (MIDDC LINK) arranged in series with said at least one connection capacity (CLINK 1, CLINK 2), and capable of being electrically connected to the neutral connection (N) via secondary switching means (S7), said power factor corrector (40) being capable of being electrically connected to said at least one AC voltage source (32a, 32b, 32c) of the electrical network (30) via primary switching means (34a, 34b, 34c); -- a data acquisition chain (49) comprising a first voltage measuring device (50) capable of measuring the output voltage of the power factor corrector (40) and a second voltage measuring device (60) capable of measuring the input voltage of the power factor corrector (40); and -- a high-voltage DC-DC converter electrically connected at the input to the output of the power factor corrector (40), and an electric battery of the electric or hybrid motor vehicle electrically connected to the output of the DC-DC voltage converter of the on-board unit.

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