Audio amplifier
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-02-02
- Publication Date
- 2026-08-13
Smart Images
Figure EP2026052594_13082026_PF_FP_ABST
Abstract
Description
[0001] KF2007P-WG-0001
[0002] 1117
[0003] Audio amplifier
[0004] Description
[0005] The invention relates to an audio amplifier comprising a pulse-width modulation (PMW) unit for converting an analog signal into an analog PWM signal and a switching amplifier unit for amplifying and outputting the analog PWM signal. A digital limiting unit is connected upstream of the amplifier unit, configured to monitor and limit the analog PWM signal.
[0006] Audio amplifiers are used to amplify an input signal into an output signal, which is usually broadcast acoustically into the environment via loudspeakers. Audio amplifiers are commonly found in home stereo systems, sound systems for discotheques, cinemas, etc., and also in public buildings, schools, universities, etc., for broadcasting announcements.
[0007] In power electronics, and therefore also in audio amplifiers, power transistors are often used in switching operation, as this offers a significant efficiency advantage compared to linear operation. To obtain the desired switching signal, pulse-width modulation (PWM) is usually employed. With PWM, an input signal (e.g., an analog voltage) is converted into a PWM signal whose width depends on the amplitude of the input signal. The pulse width is thus modulated based on the amplitude of the input signal.
[0008] If pulse-width modulation (PWM) is implemented digitally, digital methods can be used in the extreme ranges to limit the modulation. However, in very sensitive systems, such as audio amplifiers, the temporal resolution offered by digital PWM is often insufficient. Therefore, when high temporal resolution is required, analog PWM is usually used. Limiting the PWM is only possible to a limited extent in analog PWM and, if at all, is usually achieved by limiting the input signal.
[0009] Such a method for limiting the input signal is known, for example, from EP 2332252 B1.
[0010] Based on this, the purpose of the present disclosure is to create an improved technique for limiting analog pulse width modulation.
[0011] This problem is solved by the audio amplifier according to claim 1.
[0012] Advantageous embodiments are described in the dependent claims, the description, and the figures.
[0013] An audio amplifier as described in the disclosure serves to amplify an input signal, which can be applied to or is present at an input terminal, into an output signal that can be output at or is output at an output terminal. The output terminal is connected to, or can be connected to, a sound transducer, such as a loudspeaker, which outputs the signal as sound to an environment.
[0014] The audio amplifier features a pulse-width modulation (PWM) unit designed to convert an analog signal into an analog PWM signal. This analog signal can correspond to the input signal applied to the input terminal. Alternatively, the analog signal can be obtained by processing the input signal. The analog PWM signal is discrete in value but continuous in time. This means that the PWM signal can change its state at any time, not just within a predetermined clock cycle.
[0015] Furthermore, the audio amplifier features a switching amplifier unit designed to amplify and output the analog PWM signal. The amplifier unit can, in particular, be a Class-D amplifier. The amplifier unit can include a so-called reconstruction filter, such as a low-pass filter, KF2007P-WG-0001
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[0017] It must be connected downstream to obtain the analog output signal, which can be processed by the loudspeaker, from the analog PWM signal.
[0018] The audio amplifier also features a digital limiting unit, which is connected upstream of the amplifier unit and is designed to monitor and limit the analog PWM signal. This means that the digital limiting unit detects the analog PWM signal and limits it when a predefined maximum threshold is exceeded or a predefined minimum threshold is undershot. The maximum and minimum thresholds can be the same value.
[0019] According to another aspect, the PWM unit can be configured to convert the analog signal into the analog PWM signal using a reference signal with a reference signal clock or frequency, also called a switching frequency. The reference signal can, in particular, be a triangle wave or a sawtooth wave. The digital limiting unit can be configured to monitor and limit the analog PWM signal with a monitoring clock or frequency whose frequency is a multiple of the reference signal clock or frequency. The monitoring clock can preferably be an integer multiple of the reference signal clock. Furthermore, it is preferred that the reference signal clock is synchronized with the monitoring clock. In this way, it is ensured that a PWM clock is always sampled or monitored with the same number of clock cycles.
[0020] According to an additional aspect, the digital limiting unit can be configured to detect a number of monitoring cycles for which the analog PWM signal has the same binary value. That is, the digital limiting unit counts, for example, the monitoring cycles for which the analog PWM signal has a binary value of "1". Likewise, the digital limiting unit can, of course, also count the monitoring cycles for which the analog PWM signal has a binary value of "0". Furthermore, the digital limiting unit can be configured to set the analog PWM signal to the other binary value, i.e., from "1" to "0" or from "0" to "1", when the number of KF2007P-WG-0001
[0021] 4 / 17
[0022] The monitoring clock reaches a predefined monitoring clock threshold. Consequently, the digital limiting unit can reduce the duty cycle and thus the modulation level of the analog PWM signal before amplification by the amplification unit.
[0023] According to an advantageous aspect, the digital limiting unit can include a fine-resolution unit comprising several gates cascaded together. The sum of the gate propagation delays of these multiple gates can correspond to the monitoring clock. Furthermore, the fine-resolution unit can include a register configured to receive the output of each of the multiple gates and output a monitoring clock component for which the analog PWM signal has the same binary value within the monitoring clock. Consequently, the PWM signal can be monitored not only with the monitoring clock but also with multiples thereof corresponding to the number of gates.
[0024] According to an additional aspect, the digital limiting unit can be configured to set the analog PWM signal to the other binary value when the number of monitoring clocks reaches the predefined monitoring clock threshold and / or the monitoring clock fraction reaches a predefined monitoring clock fraction threshold. Consequently, the digital limiting unit can limit the duty cycle and thus the modulation level with a higher temporal resolution than the monitoring clock, i.e., with a finer resolution.
[0025] According to an additional aspect, the digital limiting unit can be configured to stop setting the analog PWM signal to the other binary value when the binary value of the analog PWM signal changes at an input of the digital limiting unit or when a reference signal clock is completed. After the PWM signal has finished being set to the other binary value, the next reference signal clock or PWM clock is then monitored. KF2007P-WG-0001
[0026] 5 / 17
[0027] According to one aspect, the audio amplifier can have an output current sensing unit configured to detect the output current of the signal at the output terminal. The digital limiting unit can then be configured to control or regulate the limiting of the analog PWM signal based on the output current. For this purpose, the digital limiting unit can receive the detected output current from the output current sensing unit directly or indirectly. The directly controlled output signal quantity is a voltage, and when the output current is detected, it can be indirectly regulated or controlled.
[0028] According to an additional aspect, the digital limiting unit can be configured to control or regulate the monitoring clock threshold, taking into account a maximum output current value within a previously predetermined time period, such that the maximum output current value remains below a predefined output current threshold. Alternatively or additionally, the digital limiting unit can be configured to control or regulate the monitoring clock component threshold accordingly. Therefore, the output current can be limited by regulating or controlling the monitoring clock threshold and / or the monitoring clock component threshold, and consequently, the output voltage.
[0029] According to another aspect, the digital limiting unit can be configured to continuously increase the monitoring clock threshold after the PWM signal has been limited. In this way, the full output capability of the audio amplifier is restored as soon as the overload situation is no longer present.
[0030] According to one aspect, the audio amplifier can have an audio limiter that is connected upstream of the PWM unit. The audio limiter can process the input signal, specifically attenuate it, to preserve the analog signal that is fed into the PWM unit. In this case, the digital limiting unit can be configured to output a signal to control the audio limiter when the analog PWM signal is limited. In this way, the audio limiter can be additionally controlled, resulting in a more audiophile-grade limiting behavior overall.
[0031] Brief description of the characters
[0032] The present revelation is described below with reference to the figures. They show:
[0033] Fig. 1 shows a schematic block diagram of the audio amplifier according to the disclosure;
[0034] Fig. 2 shows a schematic view of a pulse width modulation (PWM) unit;
[0035] Fig. 3 shows exemplary waveforms of the signals at the input of the PWM unit and a PWM signal obtained from them;
[0036] Fig. 4 Time course of signals in the audio amplifier when the analog PWM signal is limited; and
[0037] Fig. 5 shows a schematic view of a fine resolution unit and time profiles when using the fine resolution unit.
[0038] Fig. 1 shows an audio amplifier 1 designed to amplify an input signal, which can be applied to or is present at an input terminal 2, into an output signal, which can be output at or is output at an output terminal 4. A loudspeaker 6 is connected to, or can be connected to, the output signal in the form of a sound wave to radiate it into the environment.
[0039] To amplify the input signal into the output signal, the audio amplifier 1 has a pulse-width modulation (PMW) unit 8, which is configured to convert an analog signal, which can be the input signal or a signal obtained by processing the input signal, into an analog PWM signal. The analog PWM signal is a discrete-value, but time-continuous signal.
[0040] 7 / 17
[0041] Understanding PWM signals. The distinction between analog and digital PWM signals is based on their time-dependent behavior. While an analog PWM signal can change its state at any time, i.e., it is continuous-time, the value of a digital PWM signal can only change at clock edges and thus at discrete points in time; the signal is therefore discrete-time.
[0042] As shown in Fig. 2, the PWM unit 8 includes a comparator. The analog signal, in this example a sine wave, is compared with a reference signal, which has a reference signal clock and in this example is a triangle wave, by means of the comparator.
[0043] As shown in Fig. 3, the reference signal clock has a significantly higher frequency than the input signal. A binary signal is generated at the comparator's output, the pulse width of which reflects the instantaneous amplitude or displacement of the input signal. This pulse-width modulated signal is called an analog PWM signal. The ratio of pulse width to pulse duration is called the duty cycle. In the example shown in Fig. 3, the input signal ranges from -5 V to +5 V. Therefore, a voltage of -5 V corresponds to a duty cycle of 0%, a voltage of 0 V to a duty cycle of 50%, and a voltage of 5 V to a duty cycle of 100%. The modulation depth is the range within which the duty cycle operates. This depends on the amplitude of the input signal. If the input signal is 0 V, the duty cycle is a constant 50%, and the modulation depth is 0%.If the input signal has the same amplitude (positive and negative) as the reference signal, the duty cycle varies between 0% and 100%, and the modulation depth is therefore 1. If the duty cycle varies between 25% (-2.5 V) and 75% (2.5 V), the modulation depth is consequently 50%. To ensure continuous modulation, it must be guaranteed that the input signal is never larger than the reference signal.
[0044] Returning to Fig. 1, the analog PWM signal is then amplified in an amplifier unit 10, which can also be referred to as a power stage. The power transistors of the amplifier unit operate in switching mode. An example of such an amplifier unit is a Class-D amplifier. KF2007P-WG-0001
[0045] 8 / 17
[0046] The amplified analog PWM signal is then fed into a reconstruction filter 12 to restore the original signal shape. The reconstruction filter 12 can, for example, be a low-pass filter.
[0047] The audio amplifier 1 has a digital limiting unit 14 which is designed to digitally monitor and limit the analog PWM signal.
[0048] This combines the resolution of analog pulse-width modulation with the diverse possibilities of digital monitoring and control. The functionality of the digital limiting unit 14 is described in detail below.
[0049] Furthermore, the audio amplifier 1 has a control unit 16, which, as indicated by an arrow in Fig. 1, is configured to obtain a control value for limiting the analog PWM signal. This control value includes, in particular, a maximum voltage and / or a maximum current. The control unit can translate these values into a monitoring clock threshold and / or a monitoring clock component threshold, which will be described in detail below. The control value can be changed at any time during operation or runtime of the audio amplifier 1 by a higher-level system (e.g., a host controller). This is a significant advantage over analog PWM limiting, where the value usually cannot be changed at all or only with considerable circuitry during runtime.
[0050] Additionally, the audio amplifier can include an audio limiter 20. The digital limiting unit 14 not only provides a very precise protection measure, but its intervention can also be signaled to the audio limiter 20 and to other units, such as a DSP, which can then perform audiophile-grade feedback with these precise limits. As shown in Fig. 1, the analog signal input to the PWM unit 8 can be provided, in particular limited, by the audio limiter 20, which processes the input signal. KF2007P-WG-0001
[0051] 9 / 17
[0052] The operation of the digital limiting unit 14 is described below with reference to Fig. 4. The digital limiting unit 14 monitors the analog PWM signal PWMJN, which has the fundamental frequency of the reference signal clock PWM-CLK, with a monitoring clock CLK. The digital limiting unit 14 monitors the analog PWM signal PWMJN for its value during each monitoring clock cycle of the digital limiting unit 14. Thus, it is possible to count how many clock cycles (count_virtual) the signal is "1" or "0". It is advantageous if the monitoring clock CLK of the digital limiting system 14 is an integer multiple of the reference signal clock (e.g., the triangle wave) and if these two clock signals, i.e., the monitoring clock and the reference signal clock, run synchronously, meaning they are derived from the same fundamental clock. This ensures that a cycle of the reference signal is always sampled with the same number of monitoring clock cycles.Therefore, if the monitoring clock has 100 times the frequency of the reference signal clock, the duty cycle of the PWM signal can be sampled with an accuracy of 1%.
[0053] A monitoring clock threshold, e.g., from the control value of the control unit 16, is specified for the digital limiting unit 14. If the monitoring clock threshold is exceeded by the described counting method, the PWM signal is forced to the other binary value. A "1" thus becomes a "0" and vice versa. This forcing can be stopped or reset when the analog PWM signal PWMJN at the input of the digital limiting unit 14 changes its value or when a clock cycle of the reference signal is completed. This limits the duty cycle and therefore also the modulation level.
[0054] Fig. 4 shows a possible signal waveform where the monitoring clock threshold is set to "5" and the digital clock (CLK) has 10 times the frequency of the reference signal (triangle is generated with PWM-CLK). As can be seen, in the first case, the value of the analog PWM signal is set from "1" to "0". For this, the FORCE_LO signal is set to "1". At the time the value of the analog PWM signal changes, the count counter also starts running to count the clock cycles for which the analog PWM signal is at the changed value and subsequently at the other binary value. This also occurs when the KF2007P-WG-0001 is forcibly changed.
[0055] 10 / 17
[0056] In the second case, the analog PWM signal is limited. In the second case, the analog PWM signal is changed to "1". This is achieved by setting the FORCE_HI signal to "1".
[0057] As described above, the duty cycle corresponds directly (or slightly delayed by the reconstruction filter) to the output voltage of the output signal. Limiting the modulation level, as described above, therefore directly corresponds to limiting the output voltage. Because this intervention is very direct and fast, the maximum output voltage can be limited much more precisely than with conventional systems, such as a pre-connected audio limiter. However, such a limiter can also be controlled by detecting the modulation limit to make the overall limiting behavior more audiophile-friendly.
[0058] Alternatively, a maximum output current of the output signal can also be specified for the control unit 16. If the direct output quantity is the output voltage, then current limiting can only be achieved indirectly by reducing the output voltage of the output signal. That is, the output current of the output signal must be measured, and if the maximum output current is exceeded, the output voltage must be reduced until the output current is again within the permissible range. For this purpose, the audio amplifier 1 can have an output current measuring unit 18 to detect the output current in the area of the output terminal 4.
[0059] It should be noted that with highly capacitive or inductive loads, the point in time of the maximum output current does not coincide with the point in time of the maximum output voltage. However, the output voltage can be limited very precisely using the procedure described above. To extend this to limiting the output current, the maximum modulation level within a previously predefined time interval is determined and used as a control variable. Upon detecting an overcurrent situation, the control unit 16 can thus limit the modulation level, and therefore the output voltage, to the maximum of the previously predefined time interval. With an ideally capacitive load, the maximum output current would occur a quarter period before this point in time, and with KF2007P-WG-0001
[0060] 11117
[0061] With an ideal inductive load, the maximum output current would occur a quarter period after this point in time. Therefore, it is important not to limit the overcurrent event to the instantaneous modulation level, but rather to the maximum modulation level in the preceding time interval.
[0062] The time constant is chosen so that all signals in the audible range are captured. If an overcurrent at output terminal 4 is detected by the output current measuring unit 18, the monitoring clock threshold is set according to the maximum modulation level in the previously predefined time interval to prevent further exceedance of the permissible maximum current. The upstream audio limiter 20 thus also intervenes automatically to reduce the current over a longer period, if necessary. After a limit is reached, the monitoring clock threshold set in this way is continuously increased again to automatically restore the full output capability of the audio amplifier 1 over time, as soon as the overload situation no longer exists.
[0063] Furthermore, an application is conceivable in which the analog PWM signal is to be sampled with a higher resolution than the monitoring clock. In this case, the digital limiting unit 14 can include a fine-resolution unit 22 as shown in Fig. 5. The fine-resolution unit 22 has several gates 24A to 24J, which are cascaded together, and a register 26 that receives the outputs of gates 24B to 24J. The sum of the gate propagation delays of gates 24A to 24J corresponds to the monitoring clock CLK.
[0064] The circuit begins with an AND gate 24A. One input of the AND gate 24A is connected to the monitoring clock CLK, and the other input is connected to the monitoring clock CLK via a negation gate to detect a rising edge of the monitoring clock CLK. The rising edge signal, pos_edge, is then passed to the subsequent gates 24B to 24J. The other input of the subsequent gate 24B is connected to the analog PWM signal PWM_IN. The subsequent gates 24C to 24J then receive an output from the respective preceding gate 24B to 24I. Register 26 then outputs a value indicating a monitoring clock segment for which the analog PWM signal has a binary value, i.e., "0" or "1", within the considered monitoring clock segment. The output of register 26 can therefore be considered like a decimal place, enabling a resolution below whole monitoring cycles.
[0065] In the example shown in Fig. 4, it is assumed that 10 gate propagation delays correspond to one clock cycle. Since in reality the gate propagation delays are usually significantly shorter in relation to the monitoring clock, considerably more gates must be used.
[0066] The setting of the more finely resolved analog PWM signal is carried out in a similar way to capturing the monitoring clock component.
[0067] The present disclosure allows the system boundaries to be exploited more effectively than in other systems, since, for example, the maximum output current of the output signal can be very precisely limited, thus reducing the safety margin to the maximum current of the reconstruction filter's output choke. Given the same requirements, this can mean that a smaller and therefore less expensive component can be used. Reference numerals
[0068] Audio amplifier
[0069] Input port Output port
[0070] Loudspeaker Pulse Width Modulation (PWM) unit Amplifier unit Reconstruction filter Limiting unit
[0071] Control unit, output current measuring unit
[0072] Audio limiter
[0073] High-resolution unit
[0074] a to 24J gate
[0075] register
Claims
KF2007P-WG-0001 14 / 17 Claims 1. Audio amplifier (1) for amplifying an input signal that can be applied to an input terminal (2) into an output signal that can be output to an output terminal (4), wherein the audio amplifier (1) comprises: a pulse width modulation, PWM, unit (8) configured to convert an analog signal into an analog PWM signal, and an amplifier unit (10) operating in switching mode, which is configured to amplify and output the analog PWM signal, characterized by a digital limiting unit (14) which is connected upstream of the amplifier unit (10) and is designed to monitor and limit the analog PWM signal.
2. Audio amplifier (1) according to claim 1, wherein the PWM unit (8) is designed to convert the analog signal into the analog PWM signal using a reference signal with a reference signal clock, and the digital limiting unit (14) is designed to monitor and limit the analog PWM signal with a monitoring clock which is a, preferably integer, multiple of the reference signal clock and is preferably synchronized with the reference signal clock.
3. Audio amplifier (1) according to claim 2, wherein the digital limiting unit (14) is configured to detect a number of monitoring clocks for which the analog PWM signal has the same binary value, and to set the analog PWM signal to the other binary value when the number of monitoring clocks reaches a predetermined monitoring clock threshold.
4. Audio amplifier (1) according to claim 2 or 3, wherein the digital limiting unit (14) has a fine resolution unit comprising several gates (24A to 24J) connected in a cascade, wherein a sum of gate times of the several gates (24A to 24J) is given to the KF2007P-WG-0001 15 / 17 monitoring clock corresponds to, and a register (26) configured to receive a respective output of the several gates (24A to 24J) and to output a monitoring clock component for which the analog PWM signal within the monitoring clock has the same binary value.
5. Audio amplifier (1) according to claim 4, wherein the digital limiting unit (14) is configured to set the analog PWM signal to the other binary value when the number of monitoring clocks reaches a predetermined monitoring clock threshold and / or the monitoring clock fraction reaches a predetermined monitoring clock fraction threshold.
6. Audio amplifier (1) according to one of claims 3 to 5, wherein the digital limiting unit (14) is configured to stop setting the analog PWM signal to the other binary value when the binary value of the analog PWM signal changes at an input of the digital limiting unit (14) or a reference signal clock is completed.
7. Audio amplifier (1) according to any one of claims 1 to 6, comprising: an output current measuring unit (18) configured to detect an output current of the output signal at the output terminal (4), wherein the digital limiting unit (14) is configured to control or regulate a limit of the analog PWM signal based on the detected output current.
8. Audio amplifier according to one of claims 3 to 6 and 7, wherein the digital limiting unit (14) is configured to control or regulate the monitoring clock threshold and / or the monitoring clock component threshold, taking into account a maximum value of the output current within a previous predetermined time period, such that the maximum value of the output current is below a predetermined output current threshold.
9. Audio amplifier (1) according to claim 8, wherein 16 / 17 the digital limiting unit (14) is designed to continuously increase the monitoring clock threshold after a limiting of the PWM signal.
10. Audio amplifier (1) according to one of claims 1 to 9, comprising: an audio limiter (20) connected upstream of the PWM unit (8), wherein the digital limiting unit (14) is configured to output a signal for controlling the audio limiter (20) when the analog PWM signal is limited.