Monitoring circuit and method for operating a monitoring circuit
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-02-06
- Publication Date
- 2026-08-13
Smart Images
Figure EP2026053199_13082026_PF_FP_ABST
Abstract
Description
[0001] P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0002] 1
[0003] Description
[0004] MONITORING CIRCUIT AND METHOD FOR OPERATING A MONITORING CIRCUIT
[0005] The disclosure is related to a monitoring circuit, a switching device with a monitoring circuit and a method for operating a monitoring circuit .
[0006] A switching device such as a circuit breaker includes logic circuits . The effect of a malfunction of a logic circuit can lead to an unsafe state in the context of a safety-relevant function .
[0007] It is an obj ective to provide a monitoring circuit, a switching device with a monitoring circuit and a method for operating a monitoring circuit which increases the safety of a switching device .
[0008] This obj ective is achieved by the subj ect matter of the independent claims . Further developments and embodiments are described in the dependent claims .
[0009] In an embodiment, a monitoring circuit comprises a first circuit . The first circuit comprises :
[0010] a first enable input configured for receiving a first enable signal,
[0011] a control enable input configured for receiving a control enable signal,
[0012] a first circuit output configured for providing a first error signal, and
[0013] a first logic circuit with a first input coupled or connected to the first enable input, a second inputP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0014] 2
[0015] coupled or connected to the control enable input and an output coupled or connected to the first circuit output .
[0016] In an embodiment of the monitoring circuit, the first logic circuit is configured to generate a first value of the first error signal in case a comparison of signals at the first and the second inputs of the first logic circuit indicates an error and to generate a second value of the first error signal in case the comparison of the signals at the first and the second inputs of the first logic circuit does not indicate an error .
[0017] Thus, the first error signal is a function of the first enable signal and the control enable signal . In case the first enable signal and the control enable signal provide information which do not correspond to each other, an error exists which is indicated by the first value of the first error signal . In case the first enable signal and the control enable signal provide information which correspond to each other, no error exists which is indicated by the second value of the first error signal .
[0018] In an embodiment of the monitoring circuit, the first logic circuit is configured to indicate errors for non-valid signal combinations of an application. An appropriate gate or gates for the first logic circuit can be found by an analysis of the monitoring circuit and of a switching device with the monitoring circuit . In an example, the first logic circuit is realized as XOR logic circuit or XNOR logic circuit . In an example, the first circuit comprises an inverter coupled or connected to the first or the second input of the first logic circuit .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0019] 3
[0020] In an embodiment of the monitoring circuit, the first circuit comprises a first input circuit . The first input circuit comprises :
[0021] a first transistor which couples the first enable input to a reference potential terminal, and
[0022] a general enable input which is coupled or connected to a control terminal of the first transistor .
[0023] In an example, the general enable input is configured to receive a general enable signal . Thus, the first error signal is a function of the first enable signal, the control enable signal and the general enable signal .
[0024] In an embodiment of the monitoring circuit, the first input circuit comprises a Zener diode which couples the second input of the first logic circuit to the reference potential terminal .
[0025] In an embodiment of the monitoring circuit, the monitoring circuit comprises a second circuit . The second circuit comprises
[0026] a second enable input configured for receiving a second enable signal,
[0027] a second circuit output configured for providing a second error signal,
[0028] an amplifier with a first input coupled or connected to the second enable input, a second input and an output, a voltage divider with a voltage divider tap coupled or connected to the second input of the amplifier, and a second logic circuit with a first input coupled or connected to the second enable input, a second input coupled or connected to the output of the amplifier and an output coupled or connected to the second circuit output .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0029] In an embodiment of the monitoring circuit, the second logic circuit is configured to generate a first value of the second error signal in case a comparison of signals at the first and the second inputs of the second logic circuit indicates an error and to generate a second value of the second error signal in case the comparison of the signals at the first and the second inputs of the second logic circuit does not indicate an error .
[0030] In an embodiment of the monitoring circuit, the second logic circuit is configured to indicate errors for non-valid signal combinations of an application. In an example, the second logic circuit is realized as XOR logic circuit or XNOR logic circuit .
[0031] In an embodiment of the monitoring circuit, the second circuit comprises a second input circuit . The second input circuit comprises a second transistor which couples the second enable input to the reference potential terminal . The general enable input is coupled or connected to a control terminal of the second transistor .
[0032] In an embodiment of the monitoring circuit, the second input circuit comprises a Zener diode which couples the first input of the amplifier to the reference potential terminal .
[0033] In an embodiment of the monitoring circuit, the monitoring circuit comprising a third circuit . The third circuit comprises
[0034] a third enable input configured for receiving a third enable signal,P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0035] 5
[0036] a third circuit output configured for providing a third error signal, and
[0037] a third logic circuit with a first input coupled or connected to the third enable input, a second input coupled or connected to the control enable input and an output coupled or connected to the third circuit output .
[0038] In an embodiment of the monitoring circuit, the first logic circuit is configured to generate a first value of the third error signal in case a comparison of signals at the first and the second inputs of the third logic circuit indicates an error and to generate a second value of the first error signal in case the comparison of the signals at the first and the second inputs of the third logic circuit does not indicate an error .
[0039] In an embodiment of the monitoring circuit, the third logic circuit is configured to indicate errors for non-valid signal combinations of an application. In an example, the third logic circuit is realized as XOR logic circuit or XNOR logic circuit .
[0040] In an embodiment of the monitoring circuit, the third circuit comprises a third input circuit . The third input circuit comprises a third transistor which couples the third enable input to the reference potential terminal . The general enable input is coupled or connected to a control terminal of the third transistor .
[0041] In an embodiment, the monitoring circuit comprises an evaluation circuit that is configured to provide a switch-off signal with a first value in case at least one error signal has the first value and to provide the switch-off signal withP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0042] 6
[0043] a second value in case each of the at least one error signal has the second value .
[0044] In an embodiment of the monitoring circuit, the evaluation circuit comprises
[0045] an output transistor with a first terminal for providing the switch-off signal, a second terminal coupled or connected to the reference potential terminal and a control terminal,
[0046] a Schmitt Trigger circuit with an output coupled or connected to the control terminal of the output transistor, and
[0047] an evaluation logic coupled or connected on its input side to at least one of to the first, second and third circuit output and comprising an output coupled or connected to an input of the Schmitt Trigger circuit .
[0048] In an embodiment of the monitoring circuit, the input side of the evaluation logic is coupled or connected to each of the first, second and third circuit outputs . In an example, the input side of the evaluation logic is coupled or connected to those of the first, second and third circuit outputs which are parts of the monitoring circuit .
[0049] In an embodiment of the monitoring circuit, the evaluation logic is implemented to realize an AND function of at least two of the error signals . For example, the error signals comprise the first, second and third error signals .
[0050] In an embodiment, a switching device comprises
[0051] the monitoring circuit,
[0052] a coil, andP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0053] 7
[0054] a control transistor which is connected in series to the coil and comprises a control terminal coupled or connected to an output side of the monitoring circuit .
[0055] In an embodiment of the switching device, the switching device further comprises a supply voltage terminal and the reference potential terminal . A series circuit of the coil and the control transistor is coupled to the supply voltage terminal and to the reference potential terminal .
[0056] In an embodiment, the switching device additionally comprises a further control transistor which is connected in series to the control transistor and to the coil .
[0057] In an embodiment of the switching device, the coil comprises a first and a second terminal .
[0058] For example, the further control transistor couples the supply voltage terminal to the first terminal of the coil and the control transistor couples the second terminal of the coil to the reference potential terminal .
[0059] Alternatively, the further control transistor couples the second terminal of the coil to the reference potential terminal and the control transistor couples the supply voltage terminal to the first terminal of the coil .
[0060] In an embodiment, the switching device is implemented as one of a group consisting of a circuit breaker, a contactor, a switch disconnector, a device with a reluctance drive, a relay and a combination of a circuit breaker and a contactor . The relay is implemented e . g. as solid-state relay. TheP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0061] 8
[0062] combination of a circuit breaker and a contactor can be named e . g. breaktor .
[0063] The monitoring circuit described above is particularly suitable for the switching device . Features described in connection with the monitoring circuit can therefore be used for the switching device and vice versa .
[0064] In an embodiment, a method for operating a monitoring circuit comprises
[0065] receiving a first enable signal by a first enable input which is part of a first circuit of a monitoring circuit, receiving a control enable signal by a control enable input which is part of the first circuit,
[0066] generating a first error signal by a first logic circuit which is part of the first circuit and comprises a first input coupled or connected to the first enable input and a second input coupled or connected to the control enable input, and
[0067] providing the first error signal at a first circuit output that is coupled or connected to an output of the first logic circuit .
[0068] In an embodiment of the method, the first logic circuit generates a first value of the first error signal in case a comparison of signals at the first and the second inputs of the first logic circuit indicates an error and generates a second value of the first error signal in case the comparison of the signals at the first and the second inputs of the first logic circuit does not indicate an error .
[0069] The monitoring circuit and the switching device described above are particularly suitable for the method for operatingP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0070] 9
[0071] a monitoring circuit . Features described in connection with the monitoring circuit and the switching device can therefore be used for the method and vice versa .
[0072] In an example, the monitoring circuit is configured for logical monitoring of digitally controlled circuits with digital transistor outputs in open-collector or push-pull configuration to determine short-circuit and open-mode fault detection of the monitored circuit section.
[0073] In an example, to recognize whether a logical function outputs an incorrect or faulty signal, the ratio of input values to output values of a logic function is compared based on the truth table of the logic function. If the ratio of input values to output values is not equal, a malfunction of the monitored function can be assumed. The transient transition from value to value is skipped and the value formed is evaluated in the static state .
[0074] A digital function with a logical input and a logical output is designed in such a way that, in binary terms, the input value corresponds to the inverted output value . An example of such a circuit is an inverter, an amplifier, a level converter, a decoupling element etc . The comparator circuit is an electronic circuit of any type with two inputs that implements e . g. a logical XOR function and has a corresponding output as a signal channel . The voltage levels of the input and output of the function can be different as long as there is a proportional relationship between the static states . To make the measured voltage values of the function evaluable for the comparator circuit, the voltage values are converted by corresponding active or passiveP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0075] 10
[0076] circuit components . These components are automatically monitored by the comparator circuit .
[0077] In standard operation, the comparator circuit detects an inverted signal state from input to output signal in the continuous state of the function. Transients are avoided by appropriate switching speeds and any remaining incorrectly detected DC signals are eliminated by appropriate filtering at the output of the monitoring circuit . In normal operation, the output of the comparator circuit is constantly HIGH (which corresponds to "1") , which means that the output signal itself can also be monitored by a downstream evaluation .
[0078] Error mode : In error mode, the comparator circuit detects an identical signal state from input signal to output signal in the continuous state of the function. The speed of error detection depends on the selected topology of the comparator circuit and the downstream filter and should be significantly faster than the maximum cycle times of the monitored circuit . In case of an error, the output of the comparator circuit is constantly LOW which corresponds to "0" . If a part of the monitoring itself is defective or a power supply to the monitoring system is faulty, the output is also constantly LOW which corresponds to "0" . This applies at the latest at the next signal change of the circuit to be monitored. An exception to this is a short circuit between the monitoring circuit and the applied power supply, which permanently sets the output to HIGH which corresponds to "1" . This small but existing possibility of faults remains latent . All other faults are detected.P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0079] 11
[0080] The following description of figures of embodiments shall further illustrate and explain aspects of the monitoring circuit and of the method for operating the monitoring circuit . Parts and components with the same structure and the same effect respectively appear with equivalent reference symbols . As far as parts and components correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the subsequent figures .
[0081] Figure 1 shows an example of a monitoring circuit;
[0082] Figure 2 shows details of a further example of a monitoring circuit; and
[0083] Figure 3 shows an example of a switching device .
[0084] Figure 1 shows an example of a monitoring circuit 10. The monitoring circuit 10 comprises a first circuit 20. The first circuit 20 comprises
[0085] a first enable input 21 at which a first enable signal EN_1 is received,
[0086] a control enable input 22 at which a control enable signal EN_C is received,
[0087] a first circuit output 23 at which a first error signal ENlErr is provided, and
[0088] a first logic circuit 24 with a first input coupled to the first enable input 21, a second input coupled to the control enable input 22 and an output coupled to the first circuit output 23.
[0089] The first logic circuit 24 generates the first error signal ENlErr having a first value in case a comparison of signalsP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0090] 12
[0091] at the first input and the second input of the first logic circuit 24 indicates an error . The first logic circuit 24 generates the first error signal ENlErr having a second value in case the comparison of the signals at the first input and the second input of the first logic circuit 24 does not indicate an error . The second value of the first error signal ENlErr is generated in case the comparison of the signals at the first input and the second input of the first logic circuit 24 indicates an absence of an error .
[0092] A monitored function 12 represents e . g. a function of a switching device . The function has to be monitored. The monitored function 12 converts an input value at an input 11 to an output value at an output 13. The monitored function 12 generates the first enable signal EN_1 as a function of the control enable signal EN_C . In case of absence of an error, the first enable signal EN_1 and the control enable signal EN_C have the same information content . In case of an error e . g. an error in the monitored function 12, the information contents of the first enable signal EN_1 and the control enable signal EN_C are different .
[0093] Optionally, the first circuit 20 comprises a first input circuit 25 which couples the first enable input 21 to the first input of the first logic circuit 24. Optionally, the first circuit 20 comprises a further first input circuit 26 which couples the control enable input 22 to the second input of the first logic circuit 24. The first and the further first input circuits 25, 26 are configured for a level adaptation of electrical signals . The first logic circuit 24 operates as a comparison circuit or comprises a comparator or an amplifier .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0094] 13
[0095] Optionally, the first circuit 20 comprises a first output circuit 27 which couples the output of the first logic circuit 24 to the first circuit output 23. A result of the first logic circuit 24 is provided to the first output circuit 27. The first output circuit 27 is implemented e . g. as a low-pass filter . The filtered result is the first error signal ENlErr which represents a status of the monitored function 12 .
[0096] A method for operating the monitoring circuit 10 comprises receiving the first enable signal EN_1 by the first enable input 21,
[0097] receiving the control enable signal EN_C by the control enable input 22,
[0098] generating the first error signal ENlErr by the first logic circuit 24 with the first input coupled to the first enable input 21 and the second input coupled to the control enable input 22, and
[0099] providing the first error signal ENlErr at the first circuit output 23 that is coupled to the output of the first logic circuit 24.
[0100] The first logic circuit 24 generates the first value of the first error signal ENlErr in case a comparison of a signal at the first input of the first logic circuit 24 and a signal at the second input of the first logic circuit 24 indicates an error . The first logic circuit 24 generates the second value of the first error signal ENlErr in case the comparison of the signal at the first input and the signal at the second input of the first logic circuit 24 does not indicate an error .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0101] 14
[0102] In an example, the ratio of input values to output values of the monitored function 12 is compared based on a truth table of a logical function. If the ratio of input values to output values is not equal, a malfunction of the monitored function 12 can be assumed. The effect of a malfunction of a logic circuit that realizes the monitored function 12 can lead to an unsafe state in the context of a safety-relevant function. If this malfunction is detected, a connected safety mechanism can react in brief time and initiate a safe state . This monitoring can be complex and expensive if based on the evaluation of analog values . The monitoring circuit 10 mainly operates digitally. The monitoring circuit 10 described here for evaluating binary states is cost-efficient .
[0103] Figure 2 shows details of a further example of a monitoring circuit 10 which is a further development of the monitoring circuit shown in Figure 1. The first logic circuit 24 is realized e . g. as XOR logic circuit . The first input circuit 25 comprises :
[0104] a first transistor 29 which couples the first enable input 21 to a reference potential terminal 18, and
[0105] a general enable input 19 which is coupled to a control terminal of the first transistor 29.
[0106] A reference potential GND is tapped at the reference potential terminal 18. A supply voltage VCC is tapped at a supply voltage terminal 93 of the monitoring circuit 10. The first transistor 29 is used as switch. The first transistor 29 is e . g. a bipolar transistor, e . g. a npn bipolar transistor . The first input circuit 25 comprises a Zener diode 28 which couples the second input of the first logic circuit 24 to the reference potential terminal 18. A general enable signal EN is applied to the general enable input 19.P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0107] - 15 -
[0108] The monitoring circuit 10 comprises smoothing capacitors C28, C43, C44, C49 to C63 which couple different nodes of the monitoring circuit 10 to the reference potential terminal 18. The monitoring circuit 10 comprises coupling resistors R34, R81, R88, R92, R108, R114, R120, R126.
[0109] The first output circuit 27 comprises a smoothing capacitor C58 which couples the output of the first logic circuit 24 to the reference potential terminal 18.
[0110] Moreover, the monitoring circuit 10 comprises a second circuit 30. The second circuit 30 comprises
[0111] a second enable input 31 for receiving a second enable signal EN_2,
[0112] a second circuit output 33 at which a second error signal EN2Err is provided,
[0113] an amplifier 34 with a first input coupled to the second enable input 31, a second input and an output,
[0114] a voltage divider 40 with a voltage divider tap coupled to the second input of the amplifier 34, and
[0115] a second logic circuit 41 with a first input coupled to the control enable input 22, a second input coupled to the output of the amplifier 34 and an output coupled to the second circuit output 33.
[0116] The voltage divider 40 comprises two voltage divider resistors R115, R116. The second logic circuit 41 generates the second error signal EN2Err with a first value in case a comparison of signals at the first and the second inputs of the second logic circuit 41 indicates an error and generates the second error signal EN2Err with a second value in case the comparison of the signals at the first and the secondP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0117] 16
[0118] inputs of the second logic circuit 41 does not indicate an error . The second logic circuit 41 is realized e . g. as XOR logic circuit .
[0119] Furthermore, the second circuit 30 comprises a second input circuit 35. The second input circuit 35 comprises a second transistor 39 which couples the second enable input 31 to the reference potential terminal 18. The general enable input 19 is coupled to a control terminal of the second transistor 39. The second transistor 39 is used as switch. The second transistor 39 is e . g. a bipolar transistor, e . g. a npn bipolar transistor . The second input circuit 35 comprises a Zener diode 38 which couples the first input of the amplifier 34 to a reference potential terminal 18.
[0120] A second output circuit 37 of the second circuit 30 comprises a smoothing capacitor C61 which couples the output of the second logic circuit 41 to the reference potential terminal 18 .
[0121] Furthermore, the monitoring circuit 10 comprises a third circuit 50. The third circuit 50 comprises
[0122] a third enable input 51 for receiving a third enable signal EN_3,
[0123] a third circuit output 53 for providing a third error signal EN3Err, and
[0124] a third logic circuit 54 with a first input coupled to the control enable input 22, a second input coupled to the third enable input 51 and an output coupled to the third circuit output 53.
[0125] The third logic circuit 54 generates the third error signal EN3Err with a first value in case a comparison of signals atP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0126] 17
[0127] the first and the second inputs of the third logic circuit 54 indicates an error and generates the third error signal EN3Err with a second value in case the comparison of the signals at the first and the second inputs of the third logic circuit 54 does not indicate an error . The third logic circuit 54 is realized e . g. as XOR logic circuit .
[0128] The third circuit 50 comprises a third input circuit 55. The third input circuit 55 comprises a third transistor 59 which couples the third enable input 51 to the reference potential terminal 18. The general enable input 19 is coupled to a control terminal of the third transistor 59. The third transistor 59 is used as switch. The third transistor 59 is e . g. a bipolar transistor, e . g. a npn bipolar transistor .
[0129] A third output circuit 57 of the third circuit 50 comprises a smoothing capacitor C63 which couples the output of the third logic circuit 54 to the reference potential terminal 18.
[0130] Additionally, the monitoring circuit 10 comprises an evaluation circuit 60 that provides a switch-off signal D_OFF with a first value in case at least one error signal ENlErr, EN2Err, EN3Err has the first value and provides the switchoff signal D_OFF with a second value in case each of the at least one error signal ENlErr, EN2Err, EN3Err has the second value . The first value of the switch-off signal D_OFF indicates an error . The second value of the switch-off signal D_OFF indicates the absence of an error .
[0131] The evaluation circuit 60 comprises
[0132] an evaluation output 61 at which the switch-off signal D_OFF is provided,P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0133] 18
[0134] an output transistor 62 with a first terminal coupled to the evaluation output 61, a second terminal coupled to the reference potential terminal 18 and a control terminal, a Schmitt Trigger circuit 63 with an output coupled to the control terminal of the output transistor 62, and
[0135] an evaluation logic 64 coupled on its input side to the first, second and third circuit output 23, 33, 53 and comprising an output coupled to an input of the Schmitt Trigger circuit 63.
[0136] The evaluation logic 64 is implemented e . g. to realize an AND function of at least two of the first, second and third error signals ENlErr, EN2Err, EN3Err . The output transistor 62 operates in an open-collector configuration.
[0137] The evaluation logic 64 comprises a first logic gate 65 having an output coupled to an input of the Schmitt Trigger circuit 63. The first logic gate 65 is realized e . g. as an AND gate . For example, the AND gate is realized by a NAND gate followed by an inverter . Two inputs of the first logic gate 65 are coupled to the second and the third circuit output 33, 53.
[0138] The monitoring circuit 10 comprises an output filter 73 which couples the output of the first logic gate 65 to the input of the Schmitt Trigger circuit 63. The output filter 73 comprises a resistor Rill and a smoothing capacitor C55.
[0139] The monitoring circuit 10 comprises a further enable input 67. A further enable signal ENA is applied to the further enable input 67 .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0140] 19
[0141] The evaluation logic 64 comprises a second logic gate 66 having an output coupled to a further input of the first logic gate 65. The second logic gate 66 is realized e . g. as an AND gate . For example, the AND gate is realized by a NAND gate followed by an inverter . An input of the second logic gate 66 is coupled to the first circuit output 23. A further input of the second logic gate 66 is coupled to the further enable input 67 .
[0142] The evaluation logic 64 comprises a third logic gate 68 having an output coupled to the further input of the second logic gate 66. The third logic gate 66 is realized e . g. as an XOR gate . An input of the third logic gate 68 is coupled to the further enable input 67. A further input of the third logic gate 68 is coupled to the control enable input 22 via a first resistor R28 and is coupled to the general enable input 19 via a second resistor R57 .
[0143] The evaluation logic 64 comprises an input transistor 69 which couples the further input of the third logic gate 68 to the reference potential terminal 18. The input transistor 69 is used as switch. The input transistor 69 is e . g. a bipolar transistor, e . g. a npn bipolar transistor . A control terminal of the input transistor 69 is coupled to the further enable input 67 .
[0144] The evaluation logic 64 comprises a fourth logic gate 70 having an output coupled to the control terminal of the input transistor 69. The fourth logic gate 70 is realized e . g. as a Schmitt Trigger circuit . An input of the fourth logic gate 70 is coupled to the further enable input 67.P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0145] 20
[0146] The evaluation logic 64 comprises a protection circuit 71 which couples the further enable input 67 to the input of the fourth logic gate 70 and to the input of the third logic gate 68. The protection circuit 71 comprises a Zener diode 74. The protection circuit 71 comprises an input filter 72 which is e . g. a low-pass filter . The input filter 72 comprises at least a resistor R86, R87, R90, R91 and at least a smoothing capacitor C43, C44.
[0147] In an alternative, not shown embodiment, the first logic circuit 24 is realized e . g. as XNOR logic circuit or another logic circuit . In an example, the first circuit 20 comprises an inverter with an output connected to the first or the second input of the first logic circuit 24.
[0148] In an alternative, not shown embodiment, the second logic circuit 41 is realized e . g. as XNOR logic circuit or another logic circuit . In an example, the second circuit 30 comprises an inverter with an output connected to the first or the second input of the second logic circuit 41.
[0149] In an alternative, not shown embodiment, the third logic circuit 54 is realized e . g. as XNOR logic circuit or another logic circuit . In an example, the third circuit 50 comprises an inverter with an output connected to the first or the second input of the third logic circuit 54.
[0150] Figure 3 shows an example of a switching device 90 which is a further development of the embodiments shown above . The switching device 90 is implemented as a circuit breaker . The switching device 90 comprises the monitoring circuit 10, a coil 91 and a control transistor 92 which is connected in series to the coil 91. The control transistor 92 comprises aP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0151] 21
[0152] control terminal coupled or connected to an output side of the monitoring circuit 10.
[0153] In an example, the control transistor 92 is a field-effect transistor, abbreviated FET . The control transistor 92 is an enhancement type FET . The control transistor 92 is a n-channel FET .
[0154] The switching device 90 further comprises the supply voltage terminal 93 and the reference potential terminal 18. A series circuit of the coil 91 and the control transistor 92 is coupled to the supply voltage terminal 93 and to the reference potential terminal 18.
[0155] Moreover, the switching device 90 comprises a further control transistor 94 which is connected in series to the control transistor 92 and to the coil 91. As shown in Figure 3, the further control transistor 94 couples the supply voltage terminal 93 to a first terminal of the coil 91 and the control transistor 91 couples a second terminal of the coil 91 to the reference potential terminal 18.
[0156] In an example, the further control transistor 94 is a FET . The further control transistor 94 is an enhancement type FET . The further control transistor 94 is a p-channel FET .
[0157] The switching device 90 comprises a control input 101, a surge protection circuit 102, a polarity protection circuit 103, a first trigger level detector 104, a timer 105 and a control circuit 117. The control input 101 is coupled via the surge protection circuit 102, the polarity protection circuit 103, the first trigger level detector 104 and the timer 105 to an input of the control circuit 117. The timer 105P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0158] 22
[0159] temporarily limits an inrush current; after that only a sealing current flows through the coil 91.
[0160] The switching device 90 comprises an emergency input 106, a further surge protection circuit 107, a further polarity protection circuit 108 and an emergency trigger level detector 109. The emergency input 106 is coupled via the further surge protection circuit 107, the further polarity protection circuit 108 and the emergency trigger level detector 109 to a further input of the control circuit 117.
[0161] An output side of the monitoring circuit 10 is coupled to the input side of the control circuit 117. The switch-off signal D_OFF is provided from the monitoring circuit 10 to the control circuit 117. A first output of the control circuit 117 is coupled or connected to the control terminal of the control transistor 92. A second output of the control circuit 117 is coupled or connected to the control terminal of the further control transistor 94. The control circuit 117 generates a first control signal SCI which is applied to a control terminal of the control transistor 92. The control circuit 117 generates a second control signal SC2 which is applied to a control terminal of the further control transistor 94. In case the switch-off signal D_OFF indicates an error, the first control signal SCI sets the control transistor 92 in a non-conducting state; in this case, the second control signal SC2 sets the further control transistor 94 in a non-conducting state
[0162] The switching device 90 comprises a first and a second fixed contact 111, 112, a contact bridge 113, and a first and a second movable contact 114, 115 which are arranged at the contact bridge 113. The switching device 10 comprises anP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0163] 23
[0164] armature 116, indicated by an arrow and a dashed line in Figure 3. The armature 116 is coupled to the coil 91 and to the contact bridge 113. The coil 91 is realized as magnetic drive . The coil 91 provides a movement to the armature 116 which directly or indirectly moves the contact bridge 113.
[0165] The monitoring circuit 102 comprises a current sensing unit 110. The current sensing unit 110 detects a value of a load current IL flowing through the switching device 90. The load current IL flows through the first fixed contact 111, the first movable contact 114, the contact bridge 113, the second movable contact 115 and the second fixed contact 112 in the holding operation of the switching device 90. The current sensing unit 110 may comprise at least a Hall sensor . The current sensing unit 110 is coupled via the emergency trigger level detector 109 to the control circuit 117.
[0166] In an example, a system controller 120 is coupled to the monitoring circuit 10. The system controller 120 provides the first to the third enable signal EN_1 to EN_3, the general enable signal EN, the control enable signal EN_C and the further enable signal ENA to the monitoring circuit 10. The system controller 120 is external to the switching device 90 or is a part of the switching device 90.
[0167] For example, the general enable signal EN and the control enable signal EN_C are inverted signals to each other . Thus, the system controller 120 comprises e . g. an inverter 118 that generates the control enable signal EN_C using the general enable signal EN or vice versa .
[0168] In an alternative, not shown embodiment, the further control transistor 94 couples the second terminal of the coil 91 toP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0169] 24
[0170] the reference potential terminal 18 and the control transistor 92 couples the supply voltage terminal 93 to the first terminal of the coil 91.
[0171] The embodiments shown in Figures 1 to 4 as stated represent example embodiments of a monitoring circuit 10 and of a switching device 90; therefore, they do not constitute a complete list of all embodiments according to the monitoring circuit 10 and the switching device 90. Actual monitoring circuits and switching devices may vary from the embodiments shown in terms of parts, devices and circuits, for example .P2024, 0894 WO N / P24-1063W001 February 6, 2026
[0172] - 25 -
[0173] Reference numerals
[0174] 10 monitoring circuit
[0175] 11 input
[0176] 12 monitored function
[0177] 13 output
[0178] 18 reference potential terminal 19 general enable input
[0179] 20 first circuit
[0180] 21 first enable input
[0181] 22 control enable input
[0182] 23 first circuit output
[0183] 24 first logic circuit
[0184] 25 first input circuit
[0185] 26 further first input circuit 27 first output circuit
[0186] 28 Zener diode
[0187] 29 first transistor
[0188] 30 second circuit
[0189] 31 second enable input
[0190] 33 second circuit output
[0191] 34 amp 1 i f i e r
[0192] 35 second input circuit
[0193] 37 second output circuit
[0194] 38 Zener diode
[0195] 39 second transistor
[0196] 40 voltage divider
[0197] 41 second logic circuit
[0198] 50 third circuit
[0199] 51 third enable input
[0200] 53 third circuit output
[0201] 54 third logic circuit
[0202] 55 third input circuitP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0203] - 26 -
[0204] 57 third output circuit
[0205] 59 third transistor
[0206] 60 evaluation circuit
[0207] 61 evaluation output
[0208] 62 output transistor
[0209] 63 Schmitt Trigger circuit
[0210] 64 evaluation logic
[0211] 65 first logic gate
[0212] 66 second logic gate
[0213] 67 further enable input
[0214] 68 third logic gate
[0215] 69 input transistor
[0216] 70 fourth logic gate
[0217] 71 protection circuit
[0218] 72 input filter
[0219] 73 output filter
[0220] 74 Zener diode
[0221] 90 switching device
[0222] 91 coil
[0223] 92 control transistor
[0224] 93 supply voltage terminal
[0225] 94 further control transistor 101 control input
[0226] 102 surge protection circuit
[0227] 103 polarity protection circuit 104 first trigger level detector 105 timer
[0228] 106 emergency input
[0229] 107 further surge protection circuit 108 further polarity protection circuit
[0230] 109 emergency trigger level detector 110 current sensing unitP2024, 0894 WO N / P24-1063W001 February 6, 2026
[0231] - 27 -
[0232] 111, 112 fixed contact
[0233] 113 contact bridge
[0234] 114, 115 movable contact
[0235] 116 armature
[0236] 117 control circuit
[0237] 118 inverter
[0238] 120 system controller C28, C43, C44 smoothing capacitor C49 to C63 smoothing capacitor D_OFF switch-off signal
[0239] EN general enable signal ENA further enable signal ENlErr first error signal EN2Err second error signal EN3Err third error signal EN_1 first enable signal EN_2 second enable signal EN_3 third enable signal EN_C control enable signal GND reference potential R28, R34, R57, R81, R86-R 8 resistor
[0240] R90-R92, R108, Rill, R114 resistor
[0241] R115, R116 voltage divider resistor R120, R126 resistor
[0242] SCI first control signal SC2 second control signal VCC supply voltage
Claims
P2024, 0894 WO N / P24-1063W001 February 6, 2026- 28 -Claims1. A monitoring circuit ( 10) comprising a first circuit (20) , wherein the first circuit (20) comprisesa first enable input (21 ) configured for receiving a first enable signal (EN_1 ) ,a control enable input (22 ) configured for receiving a control enable signal (EN_C) ,a first circuit output (23) configured for providing a first error signal (ENlErr) , anda first logic circuit (24 ) with a first input coupled to the first enable input (21 ) , a second input coupled to the control enable input (22 ) and an output coupled to the first circuit output (23) ,wherein the first logic circuit (24 ) is configured to generate a first value of the first error signal (ENlErr) in case a comparison of signals at the first input and the second input of the first logic circuit (24 ) indicates an error and to generate a second value of the first error signal (ENlErr) in case the comparison of the signals at the first input and the second input of the first logic circuit (24 ) does not indicate an error .
2. The monitoring circuit ( 10) of claim 1,wherein the first circuit (20) further comprises a first input circuit (25) ,wherein the first input circuit (25) comprises :a first transistor (29) which couples the first enable input (21 ) to a reference potential terminal ( 18 ) , and a general enable input ( 19) which is coupled to a control terminal of the first transistor (29) .
3. The monitoring circuit ( 10) of claim 2,P2024, 0894 WO N / P24-1063W001 February 6, 2026- 29 -wherein the first input circuit (25) further comprises a Zener diode (28 ) which couples the second input of the first logic circuit (24 ) to the reference potential terminal ( 18 ) .
4. The monitoring circuit ( 10) of one of claims 1 to 3, wherein the monitoring circuit ( 10) further comprises a second circuit (30) ,wherein the second circuit (30) comprisesa second enable input (31 ) configured for receiving a second enable signal (EN_2 ) ,a second circuit output (33) configured for providing a second error signal (EN2Err) ,an amplifier (34 ) with a first input coupled to the second enable input (31 ) , a second input and an output,a voltage divider (40) with a voltage divider tap coupled to the second input of the amplifier (34 ) , anda second logic circuit (41 ) with a first input coupled to the second enable input (31 ) , a second input coupled to the output of the amplifier (34 ) and an output coupled to the second circuit output (33) .
5. The monitoring circuit ( 10) of claim 4,wherein the second logic circuit (41 ) is configured to generate a first value of the second error signal (EN2Err) in case a comparison of signals at the first input and the second input of the second logic circuit (41 ) indicates an error and to generate a second value of the second error signal (EN2Err) in case the comparison of the signals at the first input and the second input of the second logic circuit (41 ) does not indicate an error .
6. The monitoring circuit ( 10) of claim 4 or 5,P2024, 0894 WO N / P24-1063W001 February 6, 202630wherein the second circuit (30) further comprises a second input circuit (35) , andwherein the second input circuit (35) comprises a second transistor (39) which couples the second enable input (31 ) to a reference potential terminal ( 18 ) , andwherein a general enable input ( 19) is coupled to a control terminal of the second transistor (39) .
7. The monitoring circuit ( 10) of one of claims 1 to 6, wherein the monitoring circuit ( 10) further comprises a third circuit (50) , andwherein the third circuit (50) comprisesa third enable input (51 ) configured for receiving a third enable signal (EN_3) ,a third circuit output (53) configured for providing a third error signal (EN3Err) , anda third logic circuit (54 ) with a first input coupled to the third enable input (51 ) , a second input coupled to the control enable input (22 ) and an output coupled to the third circuit output (53) .
8. The monitoring circuit ( 10) of claim 7,wherein the third logic circuit (54 ) is configured to generate a first value of the third error signal (EN3Err) in case a comparison of signals at the first input and the second input of the third logic circuit (54 ) indicates an error and to generate a second value of the first error signal (ENlErr) in case the comparison of the signals at the first input and the second input of the third logic circuit (54 ) does not indicate an error .
9. The monitoring circuit ( 10) of claim 7 or 8,P2024, 0894 WO N / P24-1063W001 February 6, 202631wherein the third circuit (50) further comprises a third input circuit (55) , andwherein the third input circuit (55) comprises a third transistor (59) which couples the third enable input (51 ) to a reference potential terminal ( 18 ) , andwherein a general enable input ( 19) is coupled to a control terminal of the third transistor (59) .
10. The monitoring circuit ( 10) of one of claims 1 to 9, wherein the monitoring circuit ( 10) further comprises an evaluation circuit ( 60) configured to provide a switch-off signal (D_OFF) with a first value in case at least one error signal (ENlErr, EN2Err, EN3Err) has the first value and to provide the switch-off signal (D_OFF) with a second value in case each of the at least one error signal (ENlErr, EN2Err, EN3Err) has the second value .
11. The monitoring circuit ( 10) of claim 10,wherein the evaluation circuit ( 60) comprisesan evaluation output ( 61 ) configured to provide the switch-off signal (D_OFF) ,an output transistor ( 62 ) with a first terminal coupled to the evaluation output ( 61 ) , a second terminal coupled to a reference potential terminal ( 18 ) and a control terminal, a Schmitt Trigger circuit ( 63) with an output coupled to the control terminal of the output transistor ( 62 ) , and an evaluation logic ( 64 ) coupled on its input side to at least one of the first, second and third circuit output (23, 33, 53) and comprising an output coupled to an input of the Schmitt Trigger circuit ( 63) .
12. A switching device ( 90) , comprisingthe monitoring circuit ( 10) of one of claims 1 to 11,P2024, 0894 WO N / P24-1063W001 February 6, 2026- 32 -a coil ( 91 ) , anda control transistor ( 92 ) which is connected in series to the coil ( 91 ) and comprises a control terminal coupled to an output side of the monitoring circuit ( 10) .
13. The switching device ( 90) of claim 12,wherein the switching device ( 90) is implemented as one of a group consisting of a circuit breaker, a contactor, a switch disconnector, a device with a reluctance drive, a relay and a combination of a circuit breaker and a contactor .
14. A method for operating a monitoring circuit ( 10) , wherein the method comprisesreceiving a first enable signal (EN_1 ) by a first enable input (21 ) which is part of a first circuit (20) of a monitoring circuit ( 10) ,receiving a control enable signal (EN_C) by a control enable input (22 ) which is part of the first circuit (20) , generating a first error signal (ENlErr) by a first logic circuit (24 ) having a first input coupled to the first enable input (21 ) and a second input coupled to the control enable input (22 ) , andproviding the first error signal (ENlErr) at a first circuit output (23) that is coupled to an output of the first logic circuit (24 ) ,wherein the first logic circuit (24 ) generates a first value of the first error signal (ENlErr) in case a comparison of signals at the first input and the second input of the first logic circuit (24 ) indicates an error and generates a second value of the first error signal (ENlErr) in case the comparison of the signals at the first input and the second input of the first logic circuit (24 ) does not indicate an error .