Control circuit and method for operating a control circuit

Abstract

A control circuit (10) comprises an input terminal (12) for receiving an input signal (SM), a trigger input (13) for receiving a trigger signal (ST), a first circuit (21) providing a first signal (S1) as a function of the input signal (SM) and of the trigger signal (ST), a second circuit (22) comprising a time-indicating circuit (30) and providing a second signal (S2) as a function of a derived input signal (SD) that is derived from the input signal (SM) by the time-indicating circuit (30), and a combiner circuit (23) coupled to an output of the first circuit (21) and to an output of the second circuit (22) and providing a switch-off signal (SF) as a function of the first signal (S1) and of the second signal (S2). Moreover, a method for operating a control circuit is provided.

Description

[0001] P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0002] 1

[0003] Description

[0004] CONTROL CIRCUIT AND METHOD FOR OPERATING A CONTROL CIRCUIT

[0005] The disclosure is related to a control circuit, a switching device with the control circuit and a method for operating a control circuit .

[0006] Document US 10, 018, 676 B2 describes an electromagnetic switch interlock system. A switching device comprises a power supply, a switch, a coil and a shunt resistor . A series circuit of the switch, the coil and the shunt resistor couples the power supply to ground. A coil driver circuitry of the switching device comprises a processor, a SR flipflop, a comparator and a flyback diode . A coil current is determined by measuring a voltage at the shunt resistor . The voltage and a reference voltage are applied to input terminals of the comparator . When the voltage is higher than the reference voltage, an output of the comparator is high indicating that the coil current is higher than a target . On the other hand, when the voltage is equal or lower than the reference voltage, the output of the comparator is low indicating that the coil current is equal or lower than the target . The result of the comparison is applied to a R terminal of the SR flip-flop . At the S terminal of the SR flip-flop, the processor applies a trigger signal which periodically set the SR flip-flop .

[0007] It is an obj ective to provide a control circuit, a switching device with the control circuit and a method for operating a control circuit which takes a duration of the current flow into account .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0008] 2

[0009] This obj ective is achieved by the subj ect matter of the independent claims . Further developments and embodiments are described in the dependent claims .

[0010] In an embodiment, a control circuit comprises

[0011] an input terminal configured for receiving an input signal ,

[0012] a trigger input configured for receiving a trigger signal, a first circuit coupled or connected to the input terminal and to the trigger terminal and configured to provide a first signal as a function of the input signal and of the trigger signal,

[0013] a second circuit coupled or connected to the input terminal, comprising a time-indicating circuit and configured to provide a second signal as a function of a derived input signal that is derived from the input signal by the time-indicating circuit, and

[0014] a combiner circuit coupled or connected to an output of the first circuit and to an output of the second circuit and configured for providing a switch-off signal as a function of the first signal and of the second signal .

[0015] In an embodiment of the control circuit, the time-indicating circuit is realized as a circuit out of a group consisting of a delay circuit and a low-pass filter .

[0016] In an embodiment of the control circuit, the first circuit is configured to control whether the input signal obtains a value which is too high in case the trigger signal indicates that no current should flow through or to a load connected to the control circuit and thus the input signal should be low or zero . In this case, the first circuit generates a value of the switch-off signal that interrupts the current flowP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0017] 3

[0018] through or to the load connected to the control circuit . When the trigger signal indicates that a switching device is in a closing operation or a holding operation, the first circuit generates a value of the switch-off signal that does not interrupt the current flow through or to the load.

[0019] In an embodiment of the control circuit, the first circuit is configured to provide a first value of the first signal in case the input signal is higher than a predetermined value and the trigger signal has a first value . Furthermore, the first circuit is configured to provide a second value of the first signal in case the input signal is equal or lower than the predetermined value or the trigger signal has a second value .

[0020] In an embodiment of the control circuit, in case of the first value of the trigger signal, no current is expected to flow through or to the load connected to the control circuit . In case of the second value of the trigger signal, current is expected to flow through or to the load connected to the control circuit .

[0021] In an embodiment of the control circuit, the first circuit is configured to compare the value of the trigger signal with the value of the input signal . Thus, the first circuit is designed to detect an error in other parts of the control circuit . Thus, the first circuit increases the safety.

[0022] In an embodiment of the control circuit, the second circuit is configured to control whether the input signal obtains a value which is too high over a duration which is too large . In this case, the switch-off signal obtains a value that interrupts a current flow through or to the load connected toP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0023] 4

[0024] the control circuit . During short durations, for example during a closing operation of a switching device, a high value of the input signal is allowed by the second circuit . During long durations, for example during a holding operation of a switching device after the closing operation of the switching device, the second circuit generates a value of the switch-off signal that does not interrupt the current flow to the load in case of a low value of the input signal, but the second circuit generates a value of the switch-off signal that interrupts the current flow to the load in case of a high value of the input signal .

[0025] In an embodiment of the control circuit, the second circuit is configured to provide a first value of the second signal in case the derived input signal is higher than a first reference value for a duration longer than a predetermined duration. The second circuit is configured to provide a second value of the second signal in case the derived input signal is equal or lower than the first reference value . The second value of the second signal is provided for any duration in which the derived input signal is equal or lower than the first reference value . A short duration in which the derived input signal is equal or lower than the first reference value is sufficient for providing the second value of the second signal .

[0026] In an embodiment of the control circuit, the time-indicating circuit is realized as a circuit out of a group consisting of a time-measurement circuit, a low-pass filter, a delay circuit and a saw-tooth circuit .

[0027] In an embodiment of the control circuit, the combiner circuit is configured for providing a first value of the switch-offP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0028] 5

[0029] signal in case at least one signal of a group consisting of the first signal and the second signal has the first value . The combiner circuit is configured for providing a second value of the switch-off signal in case the first signal has the second value and the second signal has the second value .

[0030] In an embodiment of the control circuit, in case of the first value of the switch-off signal, a current that flows through the load connected to the control circuit is switched-of f . In case of the second value of the switch-off signal, a current can flow through the load connected to the control circuit .

[0031] In an embodiment of the control circuit, the first circuit comprises an output comparator, a reference voltage circuit and a transistor . An output of the reference voltage circuit is coupled or connected to a first input of the output comparator . The input terminal is coupled or connected to a second input of the output comparator . A first terminal of the transistor is coupled or connected to the second input of the output comparator . A second terminal of the transistor is coupled or connected to a reference potential terminal . The trigger terminal is coupled or connected to a control terminal of the transistor .

[0032] In an embodiment of the control circuit, the first circuit further comprises a further time-indicating circuit that is coupled to the input terminal and to the second input of the output comparator . The first terminal of the transistor is coupled e . g. to a node of the further time-indicating circuit . Thus, the first terminal of the transistor is coupled via a part of the further time-indicating circuit to the second input of the output comparator .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0033] 6

[0034] In an embodiment of the control circuit, the further timeindicating circuit is realized as a circuit out of a group consisting of a low-pass filter, a time-measurement circuit, a delay circuit and a saw-tooth circuit .

[0035] In an embodiment of the control circuit, the output comparator is implemented as comparator with open collector output .

[0036] In an embodiment of the control circuit, the second circuit comprises a first comparator and a first reference voltage circuit . The input terminal is coupled or connected to a first input of the first comparator . An output of the first reference voltage circuit is coupled or connected to a second input of the first comparator . The first reference value is provided at the output of the first reference voltage circuit . An output of the first comparator is coupled to the output of the second circuit .

[0037] In an embodiment of the control circuit, the first comparator is implemented as comparator with open collector output .

[0038] Alternatively, the first comparator is realized as transconductance amplifier .

[0039] In an embodiment of the control circuit, the second circuit comprises a second comparator and a second reference voltage circuit . An output of the second reference voltage circuit is coupled or connected to a first input of the second comparator . A second reference value is provided at the output of the second reference voltage circuit . The output of the first comparator is coupled via the time-indicating circuit to a second input of the second comparator . An outputP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0040] 7

[0041] of the second comparator is coupled or connected to the output of the second circuit .

[0042] In an embodiment of the control circuit, the second comparator is implemented as comparator with open collector output .

[0043] In an embodiment of the control circuit, the combiner circuit comprises a combiner output, a first resistor that couples the output of the first circuit to the combiner output and a second resistor that couples the output of the second circuit to the combiner output .

[0044] In an embodiment of the control circuit, the combiner circuit additionally comprises a pull-up resistor that is coupled or connected to a supply voltage terminal and to one of a group consisting of the combiner output, the output of the first circuit and the output of the second circuit .

[0045] In an alternative embodiment of the control circuit, the combiner circuit is realized as a logic gate, e . g. a AND gate or an OR gate . For example, the AND gate is realized by a NAND gate followed by an inverter . The OR gate is realized e . g. by a NOR gate followed by an inverter .

[0046] In an embodiment, a switching device comprises

[0047] the control circuit,

[0048] a coil, wherein the input terminal is coupled to the coil, and

[0049] a control transistor which is connected in series to the coil and comprises a control terminal coupled or connected to an output side of the control circuit .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0050] 8

[0051] For example, the control terminal of the control transistor is coupled or connected to the combiner output . The combiner circuit comprises the combiner output .

[0052] In an embodiment, the switching device comprises a supply voltage terminal and a reference potential terminal . A series circuit of the coil and the control transistor is coupled to the supply voltage terminal and to the reference potential terminal .

[0053] In an embodiment, the switching device additionally comprises a further control transistor which is connected in series to the control transistor and to the coil .

[0054] In an embodiment of the switching device, the coil comprises a first and a second terminal .

[0055] For example, the further control transistor couples the supply voltage terminal to the first terminal of the coil and the control transistor couples the second terminal of the coil to the reference potential terminal .

[0056] Alternatively, the further control transistor couples the second terminal of the coil to the reference potential terminal and the control transistor couples the supply voltage terminal to the first terminal of the coil .

[0057] In an embodiment of the switching device, the input terminal is coupled or connected to the first or the second terminal of the coil .

[0058] In an alternative embodiment, the switching device comprises a current measurement device . The current measurement deviceP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0059] 9

[0060] is e . g. a Hall sensor or a shunt resistor . The Hall sensor is in vicinity to a conducting line that is connected to the first terminal or the second terminal of the coil . The shunt resistor is connected in series to the coil and the control transistor or in series to the further control transistor, the coil and the control transistor .

[0061] In an embodiment, the switching device is implemented as one of a group consisting of a circuit breaker, a contactor, a switch disconnector and a combination of a circuit breaker and a contactor . A combination of a circuit breaker and a contactor can be named breaktor .

[0062] The control circuit described above is particularly suitable for the switching device . Features described in connection with the control circuit can therefore be used for the switching device and vice versa .

[0063] In an embodiment, a method for operating a control circuit comprises :

[0064] receiving an input signal at an input terminal, receiving a trigger signal at a trigger input, providing a first signal as a function of the input signal and of the trigger signal by a first circuit, providing a second signal as a function of a derived input signal that is derived from the input signal by a timeindicating circuit of a second circuit, and

[0065] providing a switch-off signal as a function of the first signal and of the second signal by a combiner circuit .

[0066] For example, an input side of the combiner circuit is coupled or connected to an output of the first circuit and to an output of the second circuit . An input side of the firstP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0067] 10

[0068] circuit is coupled or connected to the input terminal and to the trigger terminal . An input side of the second circuit is coupled or connected to the input terminal .

[0069] The control circuit and the switching device described above are particularly suitable for the method for operating a control circuit . Features described in connection with the control circuit and the switching device can therefore be used for the method and vice versa .

[0070] In an example, the control circuit is configured for voltagedependent short-circuit, open-mode and operator fault detection for transistors in high-side configuration for controlling inductive loads with power-dependent trip characteristic .

[0071] In an example, the control circuit is designed to replace a fuse, because the fuse does not work voltage and temperature independent in a switching device . A release time of the fuse is too long to prevent the switching device from an unintended close . The control circuit is implemented to shut off the switching device in case of a short or fault control of a high side driver of a coil of the switching device . The control circuit is implemented for protection of the switching device from an unintended close .

[0072] In an example, the effect of an incorrectly actuated or defective transistor in high-side configuration can lead to permanent incorrect loading and thus possibly to overloading of the operated load. This may be the case if the load is designed for pulse operation only, or if the transistor in high-side configuration is able to control the current in normal operation by a linear control or a PWM control, or theP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0073] - 11 -

[0074] voltage is regulated at the connected load. PWM is the abbreviation for pulse-width modulation. The control circuit is configured to detect an overload and to report the overload in a suitable time depending on the overload and to end the overload by a switch-off mechanism.

[0075] The following description of figures of embodiments shall further illustrate and explain aspects of the control circuit and of the method for operating the control circuit . Parts and components with the same structure and the same effect respectively appear with equivalent reference symbols . As far as parts and components correspond to one another in terms of their function in different figures, the description thereof is not repeated for each of the subsequent figures .

[0076] Figure 1 shows an example of a control circuit;

[0077] Figure 2 shows details of an example of a control circuit;

[0078] Figure 3 shows electrical circuits of an example of a switching device; and

[0079] Figure 4 shows an example of a switching device .

[0080] Figure 1 shows an example of a control circuit 10. The control circuit 10 comprises an input terminal 12, a trigger input 13, a first circuit 21 coupled or connected to the input terminal 12 and to the trigger terminal 13, a second circuit 22 coupled or connected to the input terminal 12 and a combiner circuit 23 coupled or connected to an output of the first circuit 21 and to an output of the second circuit 22. The second circuit 22 comprises a time-indicating circuit 30. The time-indicating circuit 30 is realized as a circuitP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0081] 12

[0082] out of a group consisting of a time-measurement circuit, a delay circuit, a low-pass filter and a saw-tooth circuit . An input of the time-indicating circuit 30 is coupled to the input of the second circuit 22 and an output of the timeindicating circuit 30 is coupled to the output of the second circuit 22 .

[0083] An input signal SM is received at the input terminal 12. For example, the input signal SM has the form of a voltage . For example, the input signal SM indicates a value of a current flowing through a load 24. The load 24 is e . g. a coil 25 of a switching device 60 as shown in Figures 3 and 4. A trigger signal ST is received at the trigger input 13. For example, the trigger signal SM has the form of a voltage . The trigger signal SM is e . g. a digital signal .

[0084] A first signal SI is generated by the first circuit 21 as a function of the input signal SM and of the trigger signal ST . A derived input signal SD is derived from the input signal SM by the time-indicating circuit 30. A second signal S2 is generated by the second circuit 22 as a function of the derived input signal SD. For example, the first and the second signals SI, S2 have the form of voltages . The first and the second signals SI, S2 are e . g. digital signals .

[0085] A switch-off signal SF is generated by the combiner circuit 23 as a function of the first signal SI and of the second signal S2 . The switch-off signal SF is provided at a combiner output 50 of the control circuit 10. The switch-off signal SF has the form e . g. of a voltage . The switch-off signal SF is e . g. a digital signal .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0086] 13

[0087] The first circuit 21 provides a first value of the first signal SI in case the input signal SM is higher than a predetermined value SP and the trigger signal ST has a first value . The first circuit 21 provides a second value of the first signal SI in case the input signal SM is equal or lower than the predetermined value SP or the trigger signal ST has a second value .

[0088] In case of the first value of the trigger signal ST, no current is expected to flow through the load 24 connected to the control circuit 10. Thus, an unintended close of the switching device 60 is avoided. An unintended close means that a high current flows through the load 24 despite that the trigger signal ST has the first value and the current is expected to be zero . In case of the second value of the trigger signal ST, current is expected to flow through the load 24 connected to the control circuit 10.

[0089] The second circuit 22 provides a first value of the second signal S2 in case the derived input signal SD is higher than a first reference value SRI during or for a duration D longer than a predetermined duration PD. The second circuit 22 provides a second value of the second signal S2 in case the derived input signal SD is equal or lower than the first reference value SRI, e . g. for any duration besides short spikes of the input signal SM.

[0090] The combiner circuit 23 provides a first value of the switchoff signal SF in case the first signal SI or the second signal S2 has the first value . In other words, the combiner circuit 23 provides the first value of the switch-off signal SF in case at least one of the first signal SI or the second signal S2 has the first value . In case of the first value ofP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0091] 14

[0092] the switch-off signal SF, the current that flows through the load 24 is interrupted that means switched-of f .

[0093] Moreover, the combiner circuit 23 provides a second value of the switch-off signal SF in case the first signal SI has the second value and the second signal S2 has the second value . In case of the second value of the switch-off signal SF, a current flows through the load 24.

[0094] A conversion block 26 symbolizes a conversion of an analog signal which is to be supervised into the input signal SM. The conversion block 26 and the load 24 couple an input 27 to an output 28 .

[0095] Figure 2 shows details of an example of a control circuit 10 which is a further development of the control circuit 10 shown in Figure 1. The first circuit 21 comprises an output comparator 41, a reference voltage circuit 42 and a transistor 43. An output of the reference voltage circuit 42 is connected to a first input of the output comparator 41. The input terminal 12 is coupled to a second input of the output comparator 41. A first terminal of the transistor 43 is coupled to the second input of the output comparator 41. A second terminal of the transistor 43 is connected to a reference potential terminal 40. The trigger terminal 13 is coupled or connected to a control terminal of the transistor 43, e . g. via a resistor 92. A reference potential GND is tapped at the reference potential terminal 40.

[0096] The reference voltage circuit 42 comprises a voltage divider with a first resistor 44 and a second resistor 45 forming a series circuit . The series circuit couples a supply voltage terminal 54 to the reference potential terminal 40. A nodeP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0097] 15

[0098] between the first resistor 44 and the second resistor 45 is coupled via the output of the reference voltage circuit 42 to the first input of the output comparator 41. For example, the first input of the output comparator 41 is a non-inverting input and the second input of the output comparator 41 is an inverting input .

[0099] The first circuit 21 additionally comprises a further timeindicating circuit 46 that couples the input terminal 12 to the second input of the output comparator 41.

[0100] The first terminal of the transistor 43 is coupled via a node of the further time-indicating circuit 46 to input terminal 12 and to the second input of the output comparator 41. The further time-indicating circuit 46 is realized as RC filter . The further time-indicating circuit 46 comprises at least one resistor 47, 73 and at least one capacitor 48, 49, 49' , 71. The further time-indicating circuit 46 is a low pass filter . The low-pass filter is realized by the at least one resistor 48, 72, 73 and the at least one capacitor 48, 49, 49' , 71. A response time of the further time-indicating circuit 46 is in a range between 5 ms and 20 ms or in a range between 10 ms and 15 ms .

[0101] The further time-indicating circuit 46 comprises a Zener diode 74 which is coupled to the input terminal 12 and to the reference potential terminal 40. The Zener diode 74 is configured for input protection, e . g. in case of high values of the input signal SM.

[0102] The second circuit 22 comprises a first comparator 32 and a first reference voltage circuit 33. The input terminal 12 is coupled to a first input of the first comparator 32. AnP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0103] 16

[0104] output of the first reference voltage circuit 33 is connected to a second input of the first comparator 32. An output of the first comparator 32 is coupled to the output of the second circuit 22. For example, the first input of the first comparator 32 is a non-inverting input and the second input of the first comparator 32 is an inverting input .

[0105] The first comparator 32 is implemented as comparator with open collector output or as a transconductance amplifier .

[0106] The first reference voltage circuit 33 comprises a first voltage divider with a first resistor 34 and a second resistor 35 forming a series circuit . A node between the first resistor 34 and the second resistor 35 is coupled via the output of the first reference voltage circuit 33 to the second input of the first comparator 32.

[0107] Furthermore, the second circuit 22 comprises a second comparator 36 and a second reference voltage circuit 37. An output of the second reference voltage circuit 37 is connected to a first input of the second comparator 36. The output of the first comparator 32 is coupled via the timeindicating circuit 30 to a second input of the second comparator 36. An output of the second comparator 36 is coupled or connected to the output of the second circuit 22. For example, the first input of the second comparator 36 is a non-inverting input and the second input of the second comparator 36 is an inverting input .

[0108] The time-indicating circuit 30 comprises a timing resistor 84 and a first, second and third timing capacitor 81 to 83. The timing resistor 84 couples the supply voltage terminal 54 to a first electrode of the first, second and third timingP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0109] 17

[0110] capacitor 81 to 83. The first electrode of the first, second and third timing capacitor 81 to 83 is connected to the output of the first comparator 32 and to the second input of the second comparator 36. A second electrode of the first, second and third timing capacitor 81 to 83 is coupled or connected to the reference potential terminal 40.

[0111] The second reference voltage circuit 37 comprises a second voltage divider with a first resistor 38 and a second resistor 39 forming a series circuit . A node between the first resistor 38 and the second resistor 39 is coupled via the output of the second reference voltage circuit 37 to the first input of the second comparator 36.

[0112] A first reference value SRI is provided by the first reference voltage circuit 33. A second reference value SR2 is provided by the second voltage divider 37.

[0113] In an example, the first comparator 32 comprises an open collector output . In case the input signal SM obtains a value lower than the first reference value SRI, the first comparator 32 is configured such that current flows from the output of the first comparator 32 to the reference potential terminal 40. Thus, the derived input signal SD has a low value and the second signal S2 obtains the second value which is 1 or high in this example .

[0114] In case the input signal SM obtains a value higher than the first reference value SRI, the first comparator 32 is configured such that no current flows from the output of the first comparator 32 to the reference potential terminal 40. The output of the first comparator 32 is in a high-ohmic state . Thus, a current flows through the timing resistor 84P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0115] 18

[0116] to the at least a first timing capacitor 81 (in the example of figure 2 to the first, second and third timing capacitor 81 to 83) . Thus, the derived input signal SD increases from the ground value GND. The derived input signal SD has e . g. a saw-tooth form. In an example, the derived input signal SD increases linearly. When the derived input signal SD has a value higher than a value of the second reference value SR2, the second comparator 36 changes its value at the output, namely the second comparator 36 provides the second signal S2 with the first value which is 0 or low in this example .

[0117] The value of the derived input signal SD represent a duration D. The duration D is the time how long the input signal SM is above the first reference value SRI . A predetermined duration PD is a function of the resistance values of the resistors 38, 39 of the second reference voltage circuit 37, a resistance value of the timing resistor 84 and a capacitance value of the at least a first timing capacitor 81 (in Figure 2 of the sum of the capacitance values of the first, second and third capacitor 81 to 83) . Since these resistance and capacitance values are constant, the predetermined duration PD has a set value .

[0118] The second circuit 22 comprises an input protection circuit 70. The input protection circuit 70 comprises a low-pass filter . The low-pass filter comprises a capacitor 71' and at least one resistor 72' , 73' . The input protection circuit 70 comprises a Zener diode 74' which is coupled to the input terminal 12 and to the reference potential terminal 40. The Zener diode 74' is configured for protecting the first comparator 32 and other parts of the control circuit 10 in case of high values of the input signal SM.P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0119] 19

[0120] The combiner circuit 23 comprises the combiner output 50, a first resistor 51 and a second resistor 52. The first resistor 51 couples the output of the first circuit 21 to the combiner output 50. The second resistor 52 couples the output of the second circuit 22 to the combiner output 50.

[0121] Optionally, the combiner circuit 23 comprises a pull-up resistor 53 that is coupled or connected to a supply voltage terminal 54 and to one of a group consisting of the combiner output 50, the output of the first circuit 21 and the output of the second circuit 22. For example, the pull-up resistor 53 couples the supply voltage terminal to the output of the first circuit 21. Optionally, the combiner circuit 23 comprises a further pull-up resistor 55. For example, the further pull-up resistor 55 couples the supply voltage terminal to the output of the second circuit 22.

[0122] The control circuit 10 comprises smoothing capacitors 85 to 91 which couple different nodes of the control circuit 10 to the reference potential terminal 40.

[0123] A method for operating the control circuit 10 comprises receiving the input signal SM at the input terminal 12, receiving the trigger signal ST at the trigger input 13, providing the first signal SI as a function of the input signal SM, of the trigger signal ST and of the further timeindicating circuit 46 by the first circuit 21,

[0124] providing the second signal S2 as a function of the derived input signal SD that is derived from the input signal by the time-indicating circuit 30 of the second circuit 22, and

[0125] providing the switch-off signal SF as a function of the first signal SI and of the second signal S2 by the combiner circuit 23.P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0126] - 20 -

[0127] The first circuit 21 comprises the further time-indicating circuit 46.

[0128] In case the input signal SM is higher than the first reference value SRI provided by the first reference voltage circuit 33, a current through a transistor at the output of the first comparator 32 is zero . The first reference value SRI is a voltage . The transistor is comprised by the first comparator 32. Thus, the timing resistor 84 provides current from the supply voltage terminal 54 to the first, second and third timing capacitor 81 to 83. Thus, a voltage at the second input of the second comparator 36 rises . The derived input signal SD is equal to this voltage . If the derived input signal SD is lower than a second reference value SR2, the second signal S2 is high or "1" . The second reference value SR2 is a voltage .

[0129] If the derived input signal SD is higher than the second reference value SR2 provided by the second voltage divider 37, the second signal S2 is low or "0" . In this case, the switch-off signal SF has the first value which is low or "0" .

[0130] In an alternative embodiment, not shown, the time-indicating circuit 30 comprises only the first timing capacitor 81 or only the first and the second timing capacitors 81, 82 or at least the first timing capacitor 81.

[0131] In an alternative, not shown embodiment, the combiner circuit 23 is realized as a logic gate, e . g. having the functionality of an AND gate or an OR gate . For example, the AND gate is realized by a NAND gate followed by an inverter .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0132] 21

[0133] Figure 3 shows electrical circuits of an example of a switching device 60 which is based on the embodiments of the control circuit 10 shown in Figures 1 and 2. The switching device 60 comprises the control circuit 10, the load 24 and a control transistor 61. The load 24 is realized as a coil 25. The input terminal 12 is coupled to the coil 25. The control transistor 61 is connected in series to the coil 25. The control transistor 61 comprises a control terminal coupled or connected to an output side of the control circuit 10, e . g. to the combiner output 50.

[0134] In an example, the control transistor 61 is an enhancement type field-effect transistor, abbreviated enhancement type FET . The control transistor 64 is e . g. a n-channel FET .

[0135] The coil 25 comprises a first terminal 62 and a second terminal 63. The input terminal 12 is coupled or connected to the first terminal 62. The switching device 60 comprises the supply voltage terminal 54 and the reference potential terminal 40. A series circuit of the coil 25 and the control transistor 61 is coupled to the supply voltage terminal 54 and to the reference potential terminal 40.

[0136] Moreover, the switching device 60 comprises a further control transistor 64 which is connected in series to the control transistor 61 and to the coil 25. As shown in Figure 3, the further control transistor 64 couples the supply voltage terminal 54 to the first terminal 62 of the coil 25 and the control transistor 61 couples the second terminal 63 of the coil 25 to the reference potential terminal 40.P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0137] 22

[0138] In an example, the further control transistor 64 is an enhancement type FET . The further control transistor 64 is a p-channel FET .

[0139] The switching device 60 comprises a driver circuit 65 that couples the control circuit 10 to the further transistor 64. The driver circuit 65 comprises a driver capacitor 66 for stabilizing a voltage at a control terminal of the further transistor 64 and a driver resistor 67 that is coupled to an output of the control circuit 10 and to the control terminal of the further transistor 64. The driver circuit 65 receives the trigger signal ST or a signal derived from the trigger signal ST . The switching device 60 comprises a protection circuit 68 that couples the second terminal 63 of the coil 24 to the reference potential terminal 40. The protection circuit 68 comprises at least a Zener diode 69.

[0140] The input signal SM is tapped between the first terminal of the coil 25 and the reference potential terminal 40.

[0141] In an alternative, not shown embodiment, the further control transistor 64 couples the second terminal 63 of the coil 25 to the reference potential terminal 40 and the control transistor 61 couples the supply voltage terminal 54 to the first terminal 62 of the coil 25.

[0142] Figure 4 shows an example of a switching device 60 which is a further development of the switching device 60 shown in the Figures above . The switching device 60 comprises a control input 101, a surge protection circuit 102, a polarity protection circuit 103, a first trigger level detector 104 and a timer 105. The control input 101 is coupled via the surge protection circuit 102, the polarity protection circuitP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0143] 23

[0144] 103, the first trigger level detector 104 and the timer 105 to an input of the control circuit 10. The timer 105 temporarily limits a pick-up current; after that only a sealing current flows through the coil 25. The control input 101 is implemented e . g. as enable input . The trigger signal ST or a signal ST' which is generated by the control circuit 10 as a function of the trigger signal ST is applied to the control terminal of the further control transistor 64.

[0145] The switching device 60 comprises a first and a second fixed contact 111, 112, a contact bridge 113, and a first and a second movable contact 114, 115 which are arranged at the contact bridge 113. The switching device 60 comprises an armature 116, indicated by an arrow and a dashed line . The armature 116 is coupled to the coil 25 and to the contact bridge 113. The coil 25 is realized as magnetic drive . The coil 25 provides a movement to the armature 116 which directly or indirectly moves the contact bridge 113.

[0146] The switching device 60 realizes a voltage-dependent short-circuit, open-mode and operating fault detection for transistors in high-side configuration for controlling inductive loads with power-dependent tripping characteristics .

[0147] To detect whether a transistor (e . g. the further control transistor 64 ) in high-side configuration for controlling an inductive load 24 has a defect during operation, the voltage level SM at the input of the load 24 is monitored and compared with the first reference value SRI . Depending on the measured voltage SM, a voltage-dependent timer is used to switch off the suspected defective load 24 from the set reference value . The suspected defective circuit section isP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0148] 24

[0149] switched off . To extend the operating range of the monitoring system, the monitoring system can be deactivated for particular cases .

[0150] The effect of an incorrectly controlled or defective transistor 64 in high-side configuration may result in a permanent incorrect load 24 and thus possibly results in an overload of the operated load 24. This may be the case if the load 24 is only designed for pulse operation or the further control transistor 64 in high-side configuration is controlled by a linear control or a PWM control to regulate the current or voltage at the load 24. The control circuit 10 is configured to recognize an overload and to report it at a suitable time depending on the overload and to terminate the overload by a downstream mechanism.

[0151] The operating voltage SM of the load 24 driven by the further control transistor 64 in high-side configuration is measured resistively decoupled from the load 24 via a corresponding electrical network. The network is connected to the output comparator 41 with a set reference value to report a fault status at a defined voltage level . To define a tripping time, the network contains a single or multi-stage RC element before the output comparator 41. This results in a voltagedependent timing element that protects the load 24 depending on the voltage SM but allows load peaks . A tolerance analysis and corresponding tests can be used to validate the protective circuit for the operating cases under temperature .

[0152] To increase the operating range of the control circuit 10, for example if the load 24 operates with voltage peaks in the range of milliseconds and in exceptional cases is operated with a higher energy for several seconds, the overload-P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0153] - 25 -

[0154] dependent monitoring may be switched off via a digital input which is e . g. the trigger input 13. For this purpose, the given RC element is short-circuited for the time of a defined exception .

[0155] In an example, to ensure that monitoring still takes place, a second time-dependent monitoring path (realized by the second circuit 22 ) exists in parallel to the overload-dependent monitoring (realized by the first circuit 21 ) . The second time-dependent monitoring path also measures the voltage SM at the load 24 and, if the voltage SM increases, at best at the same level as the overload-dependent monitoring, by a delay time detects a fault . The delay time for detecting faults should correspond to the maximum possible exception period that does not result in an overload of the monitored load 24. This results in fast fault detection for normal cases with an optional inertia for particular cases and continuous monitoring of the load 24 for a large dynamic range . In an example, the control circuit 10 is internal within the switching device 60. The switching device 60 comprises e . g. a housing or enclosure as indicated by the outer dashed line in Figure 4. The housing encloses e . g. at least the parts of the switching device 60 surrounded by the outer dashed line in Figure 4.

[0156] In an example, the switching device 60 is configured e . g. for motor control . The switching device 60 is implemented to break the connection between a high voltage battery and a battery electric system in electric vehicles . The switching device 60 is implemented as circuit breaker .

[0157] The embodiments shown in Figures 1 to 4 as stated represent example embodiments of a control circuit 10 and of aP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0158] - 26 -

[0159] switching device 60; therefore, they do not constitute a complete list of all embodiments of the control circuit 10 and of the switching device 60. Actual control circuits and switching devices may vary from the embodiments shown in terms of parts, devices and circuits, for example .P2024, 0924 WO N / P24-1067W001 February 6, 2026

[0160] - 27 -

[0161] Reference numerals

[0162] 10 control circuit

[0163] 12 input terminal

[0164] 13 trigger input

[0165] 21 first circuit

[0166] 22 second circuit

[0167] 23 combiner circuit

[0168] 24 load

[0169] 25 coil

[0170] 26 conversion block

[0171] 27 input

[0172] 28 output

[0173] 30 time-indicating circuit

[0174] 32 first comparator

[0175] 33 first reference voltage circuit 34, 35 resistor

[0176] 36 second comparator

[0177] 37 second reference voltage circuit 38, 39 resistor

[0178] 40 reference potential terminal

[0179] 41 output comparator

[0180] 42 reference voltage circuit

[0181] 43 transistor

[0182] 44, 45 resistor

[0183] 46 further time-indicating circuit 47 resistor

[0184] 48, 49, 49' capacitor

[0185] 50 combiner output

[0186] 51, 51' first resistor

[0187] 52 second resistor

[0188] 53 pull-up resistor

[0189] 54 supply voltage terminalP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0190] - 28 -

[0191] 55 further pull-up resistor

[0192] 60 switching device

[0193] 61 control transistor

[0194] 62 first terminal

[0195] 63 second terminal

[0196] 64 further control transistor 65 driver circuit

[0197] 66 driver capacitor

[0198] 67 driver resistor

[0199] 68 protection circuit

[0200] 69 Zener diode

[0201] 70 input protection circuit 71, 71' capacitor

[0202] 72, 72' resistor

[0203] 73, 73' resistor

[0204] 74, 74' Zener diode

[0205] 81 to 83 timing capacitor

[0206] 84 timing resistor

[0207] 85 to 91 smoothing capacitor

[0208] 92 resistor

[0209] 101 control input

[0210] 102 surge protection circuit 103 polarity protection circuit 104 first trigger level detector 105 timer

[0211] 111, 112 fixed contact

[0212] 113 contact bridge

[0213] 114, 115 movable contact

[0214] 116 armature

[0215] duration

[0216] GND reference potential

[0217] PD predetermined duration

[0218] SC control signalP2024, 0924 WO N / P24-1067W001 February 6, 2026

[0219] - 29 -

[0220] SD derived input signal SM input signal

[0221] SF switch-off signal

[0222] SP predetermined value SRI first reference value SR2 second reference value ST trigger signal

[0223] 51 first signal

[0224] 52 second signal

Claims

P2024, 0924 WO N / P24-1067W001 February 6, 2026- 30 -Claims1. A control circuit ( 10) comprisingan input terminal ( 12 ) configured for receiving an input signal (SM) ,a trigger input ( 13) configured for receiving a trigger signal (ST) ,a first circuit (21 ) coupled to the input terminal ( 12 ) and to the trigger terminal ( 13) and configured to provide a first signal (SI ) as a function of the input signal (SM) and of the trigger signal (ST) ,a second circuit (22 ) coupled to the input terminal ( 12 ) , comprising a time-indicating circuit (30) and configured to provide a second signal (S2 ) as a function of a derived input signal (SD) that is derived from the input signal (SM) by the time-indicating circuit (30) , anda combiner circuit (23) coupled to an output of the first circuit (21 ) and to an output of the second circuit (22 ) and configured for providing a switch-off signal (SF) as a function of the first signal (SI ) and of the second signal (S2 ) ,wherein the time-indicating circuit (30) is realized as a circuit out of a group consisting of a delay circuit and a low-pass filter .

2. The control circuit ( 10) of claim 1,wherein the first circuit (21 ) is configured to provide a first value of the first signal (SI ) in case the input signal (SM) is higher than a predetermined value (SP) and the trigger signal (ST) has a first value, andwherein the first circuit (21 ) is configured to provide a second value of the first signal (SI ) in case the inputP2024, 0924 WO N / P24-1067W001 February 6, 202631signal (SM) is equal or lower than the predetermined value (SP) or the trigger signal (ST) has a second value .

3. The control circuit ( 10) of claim 1 or 2,wherein the second circuit (22 ) is configured to provide a first value of the second signal (S2 ) in case the derived input signal (SD) is higher than a first reference value (SRI ) for a duration (D) longer than a predetermined duration (PD) ; andwherein the second circuit (22 ) is configured to provide a second value of the second signal (S2 ) in case the derived input signal (SD) is equal or lower than the first reference value ( SRI ) .

4. The control circuit ( 10) of claim 2 and 3,wherein the combiner circuit (23) is configured for providing a first value of the switch-off signal (SF) in case at least one signal of a group consisting of the first signal (SI ) and the second signal (S2 ) has the first value; andwherein the combiner circuit (23) is configured for providing a second value of the switch-off signal (SF) in case the first signal (SI ) has the second value and the second signal (S2 ) has the second value .

5. The control circuit ( 10) of one of claims 1 to 4, wherein the first circuit (21 ) comprises an output comparator (41 ) , a reference voltage circuit (42 ) and a transistor (43) , wherein an output of the reference voltage circuit (42 ) is coupled to a first input of the output comparator (41 ) , wherein the input terminal ( 12 ) is coupled to a second input of the output comparator (41 ) ,wherein a first terminal of the transistor (43) is coupled to the second input of the output comparator (41 ) ,P2024, 0924 WO N / P24-1067W001 February 6, 202632wherein a second terminal of the transistor (43) is coupled to a reference potential terminal (40) (GND) , andwherein the trigger terminal ( 13) (ST) is coupled to a control terminal of the transistor (43) .

6. The control circuit ( 10) of claim 5,wherein the first circuit (21 ) further comprises a further time-indicating circuit (46) that couples the input terminal ( 12 ) to the second input of the output comparator (41 ) .

7. The control circuit ( 10) of one of claims 1 to 6, wherein the second circuit (22 ) comprises a first comparator (32 ) and a first reference voltage circuit (33) ;wherein the input terminal ( 12 ) is coupled to a first input of the first comparator (32 ) ;wherein an output of the first reference voltage circuit (33) is coupled to a second input of the first comparator (32 ) ; andwherein an output of the first comparator (32 ) is coupled via the time-indicating circuit (30) to the output of the second circuit ( 22 ) .

8. The control circuit ( 10) of claim 7,wherein the first comparator (32 ) is implemented as comparator with open collector output .

9. The control circuit ( 10) of claim 7 or 8,wherein the second circuit (22 ) further comprises a second comparator (36) and a second reference voltage circuit (37 ) , wherein an output of the second reference voltage circuit (37 ) is coupled to a first input of the second comparatorP2024, 0924 WO N / P24-1067W001 February 6, 2026- 33wherein the output of the first comparator (32 ) is coupled via the time-indicating circuit (30) to a second input of the second comparator (36) , andwherein an output of the second comparator (36) is coupled to the output of the second circuit (22 ) .

10. The control circuit ( 10) of one of claims 1 to 9, wherein the combiner circuit (23) comprisesa combiner output (50) ;a first resistor (51 ) that couples the output of the first circuit (21 ) to the combiner output (50) ;a second resistor (52 ) that couples the output of the second circuit (22 ) to the combiner output (50) ; anda pull-up resistor (53) that is coupled to a supply voltage terminal (54 ) and to one of a group consisting of the combiner output (50) , the output of the first circuit (21 ) and the output of the second circuit (22 ) .

11. A switching device ( 60) , comprisingthe control circuit ( 10) of one of claims 1 to 10, a coil (25) , wherein the input terminal ( 12 ) is coupled to the coil (25) , anda control transistor ( 61 ) which is connected in series to the coil (25) and comprises a control terminal coupled to a combiner output (50) of the combiner circuit (23) .

12. The switching device ( 60) of claim 11,wherein the switching device ( 60) further comprises a supply voltage terminal (54 ) and a reference potential terminal (40) and a series circuit of the coil (25) and the control transistor ( 61 ) is coupled to the supply voltage terminal (54 ) and to the reference potential terminal (40) .P2024 , 0924 WO N / P24- 1067W001 February 6 , 2026- 34 -13 . The switching device ( 60 ) of claim 11 or 12 ,wherein the switching device ( 60 ) further comprisesa first and a second fixed contact ( 111 , 112 ) ,a contact bridge ( 113 ) ,a first and a second movable contact ( 114 , 115 ) which are arranged at the contact bridge 113 ) , andan armature ( 116 ) , coupled to the coil ( 25 ) and to the contact bridge ( 113 ) .14 . The switching device ( 60 ) of one of claims 11 to 13 , wherein the switching device ( 60 ) is implemented as one of a group consisting of a circuit breaker, a contactor, a switch disconnector and a combination of a circuit breaker and a contactor .15 . A method for operating a control circuit ( 10 ) , comprising receiving an input signal ( SM) at an input terminal ( 12 ) ,receiving a trigger signal ( ST ) at a trigger input ( 13 ) , providing a first signal ( S I ) as a function of the input signal ( SM) and of the trigger signal ( ST ) by a first circuit ( 21 ) ,providing a second signal ( S2 ) as a function of a derived input signal ( SD) that is derived from the input signal by a time-indicating circuit ( 30 ) of a second circuit ( 22 ) , andproviding a switch-of f signal ( SF) as a function of the first signal ( S I ) and of the second signal ( S2 ) by a combiner circuit ( 23 ) ,wherein the time-indicating circuit ( 30 ) is reali zed as a circuit out of a group consisting of a delay circuit and a low-pass filter .

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