Semiconductor device

Abstract

Provided is a novel semiconductor device. This semiconductor device has a substrate, a first circuit unit provided on a first-surface side of the substrate, and a second circuit unit provided on a second-surface side of the substrate and electrically connected to the first circuit unit. The second circuit unit has a first power supply circuit, a level shift circuit, and a second power supply circuit. The first power supply circuit has a function in which the on / off state of a switch is controlled and a first voltage supplied to the first power supply circuit is supplied to the first circuit unit as a second voltage. The level shift circuit has a function in which a third voltage is supplied to the level shift circuit and the amplitude voltage of a first clock signal, which is supplied to the level shift circuit and which is for controlling the on / off state of the switch, is level-shifted. The second power supply circuit has a function in which a second clock signal is supplied to the second power supply circuit and a fourth voltage supplied to the second power supply circuit is supplied to the level shift circuit as the third voltage.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, methods for driving them, or methods for manufacturing them.

[0003] With advancements in transistor microfabrication technology, a technology called Backside Power Delivery Network (BSPDN) is attracting attention (see, for example, Non-Patent Documents 1, 2, and 3).

[0004] H. Lin et al. , “2021 Symposium on VLSI Technology”, T9-2. X. Sun et al. , “2020 IEEE Symposium on VLSI Technology”, TH1.2J. Myers, “2024 IEEE VLSI Symposium on Technology and Circuits”, SC2.4

[0005] In the BSPDN technology described in Non-Patent Documents 1 to 3, the power supply circuit is provided on the back side of the substrate along with the power lines. In this power supply circuit, the desired voltage is obtained through the switching operation of transistors. If the current driving capability of the transistors performing the switching operation is low, a problem arises in that the power supply circuit cannot be operated with sufficient performance.

[0006] One aspect of the present invention aims to provide a semiconductor device capable of stable voltage supply. Alternatively, it aims to provide a power-saving semiconductor device, etc. Alternatively, it aims to provide a semiconductor device with improved operating speed. Alternatively, it aims to provide a semiconductor device with good reliability. Alternatively, it aims to provide a novel semiconductor device, etc.

[0007] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, which are described below. Those not mentioned in this section can be deduced by those skilled in the art from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention solves at least one of the problems listed above and / or other problems.

[0008] One aspect of the present invention is a semiconductor device comprising a substrate, a first circuit section provided on the first side of the substrate, and a second circuit section provided on the second side of the substrate and electrically connected to the first circuit section, wherein the second circuit section comprises a first power supply circuit, a level shift circuit, and a second power supply circuit, the first power supply circuit having the function of boosting a first voltage supplied to the first power supply circuit to a second voltage and supplying it to the first circuit section when the on or off of a switch is controlled, the level shift circuit having the function of level shifting the amplitude voltage of a first clock signal that controls the on or off of a switch supplied to the level shift circuit when a third voltage is supplied, and the second power supply circuit having the function of supplying a fourth voltage supplied to the second power supply circuit as a third voltage to the level shift circuit when a second clock signal is supplied.

[0009] In one embodiment of the present invention, the switch, the level shift circuit, and the second power supply circuit each have a first transistor having a first semiconductor layer, the first transistor being of n-channel type, and the first semiconductor layer having indium and oxygen, which are preferred semiconductor devices.

[0010] In one aspect of the present invention, the switch, the level shift circuit, and the second power supply circuit each have a second transistor having a second semiconductor layer, the second transistor is a p-channel type, and the second semiconductor layer has a material containing tellurium and oxygen, and a semiconductor device is preferable.

[0011] In one aspect of the present invention, the first circuit section has a functional circuit having a third transistor, the third transistor has a third semiconductor layer, and the second semiconductor layer has silicon, and a semiconductor device is preferable.

[0012] In one aspect of the present invention, the semiconductor substrate is a silicon substrate, and the silicon substrate has a through electrode for making the first circuit section and the second circuit section conductive, and a semiconductor device is preferable.

[0013] In one aspect of the present invention, the first power supply circuit is preferably a charge pump circuit having a switch.

[0014] In one aspect of the present invention, the second power supply circuit is preferably a charge pump circuit having a diode.

[0015] According to one aspect of the present invention, a semiconductor device capable of providing a stable voltage supply can be provided. Or, a semiconductor device with power saving can be provided. Or, a semiconductor device with an improved operating speed can be provided. Or, a semiconductor device with good reliability can be provided. Or, a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions.

[0017] Figures 1(A) and 1(B) illustrate semiconductor devices. Figures 2(A) and 2(B) illustrate semiconductor devices. Figures 3(A) and 3(B) illustrate semiconductor devices. Figures 4(A) to 4(C) illustrate semiconductor devices. Figures 5(A) to 5(D) illustrate semiconductor devices. Figures 6(A) and 6(B) illustrate semiconductor devices. Figures 7(A) and 7(B) illustrate semiconductor devices. Figure 8 illustrates semiconductor devices. Figures 9(A) and 9(B) illustrate semiconductor devices. Figure 10 illustrates semiconductor devices. Figures 11(A) and 11(B) illustrate semiconductor devices. Figure 12 illustrates semiconductor devices. Figures 13(A) to 13(C) illustrate semiconductor devices. Figure 14 illustrates semiconductor devices. Figures 15(A) and 15(B) illustrate semiconductor devices. Figures 16(A) to 16(C) illustrate semiconductor devices. Figures 17(A) to 17(C) illustrate semiconductor devices. Figures 18(A) and 18(B) are schematic perspective views of semiconductor devices. Figure 19 is an illustration of a semiconductor device. Figure 20 is an illustration of a semiconductor device. Figure 21 is an illustration of a semiconductor device. Figures 22(A) to 22(C) illustrate semiconductor devices. Figure 23 is an illustration of a semiconductor device. Figures 24(A) and 24(B) illustrate semiconductor devices. Figures 25(A) and 25(B) are schematic perspective views of semiconductor devices. Figures 26(A) and 26(B) illustrate a method for manufacturing a semiconductor device. Figures 27(A) and 27(B) illustrate a method for manufacturing a semiconductor device. Figures 28(A) to 28(C) illustrate a method for manufacturing a semiconductor device. Figures 29(A) and 29(B) illustrate a method for manufacturing a semiconductor device. Figure 30 is a diagram illustrating a semiconductor device. Figure 31 is a diagram illustrating a semiconductor device. Figure 32 is a diagram illustrating a semiconductor device. Figures 33(A) and 33(B) are diagrams illustrating a semiconductor device. Figures 34(A) and 34(B) are diagrams illustrating a semiconductor device. Figure 35 is a diagram illustrating a semiconductor device. Figures 36(A) and 36(B) are diagrams illustrating a semiconductor device.Figures 37(A) to 37(C) are diagrams illustrating semiconductor devices. Figures 38(A) and 38(B) are diagrams illustrating semiconductor devices. Figures 39(A) and 39(B) are diagrams illustrating semiconductor devices. Figure 40 is a diagram illustrating a semiconductor device. Figures 41(A) and 41(B) are diagrams illustrating semiconductor devices. Figure 42 is a diagram illustrating a semiconductor device. Figure 43 is a diagram illustrating a semiconductor device. Figure 44 is a diagram illustrating a semiconductor device. Figure 45 is a diagram illustrating a semiconductor device. Figure 46 is a diagram illustrating a semiconductor device. Figure 47 is a diagram illustrating a semiconductor device. Figure 48 is a block diagram illustrating an example configuration of a semiconductor device. Figures 49(A) to 49(F) are diagrams illustrating an example circuit configuration of a memory cell. Figures 50(A) and 50(B) are diagrams illustrating an example circuit configuration of a memory cell. Figure 51 is a diagram illustrating an example configuration of a semiconductor device. Figures 52(A) to 52(D) are diagrams illustrating an example circuit configuration of a pixel. Figures 53(A) to 53(D) illustrate examples of pixel circuit configurations. Figures 54(A) to 54(D) illustrate examples of transistor configurations. Figures 55(A) and 55(B) illustrate examples of transistor configurations. Figures 56(A) and 56(B) illustrate examples of transistor configurations. Figures 57(A) and 57(B) illustrate examples of transistor configurations. Figures 58(A) and 58(B) show examples of electronic components. Figures 59(A) and 59(B) show examples of electronic equipment, and Figures 59(C) to 59(E) show examples of large-scale computers. Figure 60(A) shows an example of space equipment. Figure 60(B) shows an example of a storage system applicable to data centers.

[0018] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0019] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may also contain semiconductor devices.

[0020] In the drawings and other illustrations relating to this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited to those shown. Furthermore, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0021] In the configuration of the embodiment of the invention, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the same hatching pattern may be used, and no reference numerals may be assigned. Furthermore, in order to make the drawings easier to understand, the description of some components may be omitted in plan views, cross-sectional views, perspective views, etc.

[0022] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Furthermore, even if a term in this specification does not have an ordinal number, an ordinal number may be added in the claims to avoid confusion of constituent elements. Also, even if a term in this specification has an ordinal number, a different ordinal number may be added in the claims. Furthermore, even if a term in this specification has an ordinal number, the ordinal number may be omitted in the claims.

[0023] In this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases described in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0024] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0025] In this specification, terms such as "overlapping" and "overlapping" do not limit the stacking order or stacking direction of the constituent elements. For example, the expression "electrode B overlapping insulating layer A" does not exclude not only the state in which electrode B is formed on top of insulating layer A, but also the state in which electrode B is formed below insulating layer A or the state in which electrode B is formed to the right (or left) of insulating layer A.

[0026] In this specification, the terms "adjacent" or "proximity" are not limited to direct contact between components. For example, the expressions "B adjacent to A" or "B in proximity to A" do not require A and B to be directly in contact, nor do they exclude cases where other components are included between A and B.

[0027] In this specification, terms such as "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Alternatively, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" can be replaced with terms such as "region" or "conductive layer."

[0029] In this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other as appropriate or depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line," and vice versa. Terms such as "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line," and vice versa. Furthermore, the term "potential" applied to wiring may be changed to the term "signal," and vice versa.

[0030] In this specification, "source" refers to a source region, a source electrode, or a source wiring. A source region refers to one of two regions adjacent to a channel formation region in a semiconductor layer. A source electrode refers to a conductive layer that includes the portion connected to the source region. In some cases, a portion of the source wiring may function as a source electrode. Furthermore, source wiring may be composed of multiple conductive layers.

[0031] In this specification, "drain" refers to a drain region, a drain electrode, or drain wiring. A drain region refers to the other of two regions adjacent to a channel formation region in a semiconductor layer. A drain electrode refers to a conductive layer that includes the portion connected to the drain region. In some cases, a portion of the drain wiring may function as a drain electrode. Furthermore, drain wiring may be composed of multiple conductive layers.

[0032] The "source" and "drain" functions of a transistor may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0033] In this specification, "gate" refers to the gate electrode or gate wiring. The gate electrode is an electrode that overlaps with the semiconductor layer of a transistor and has the function of controlling the resistance between the source and drain of the transistor by the supplied voltage. In some cases, a portion of the gate wiring may function as the gate electrode. Furthermore, the gate wiring may be composed of multiple conductive layers.

[0034] In this specification, one of the sources or drains of a transistor may be referred to as the "first terminal of the transistor," and the other of the sources or drains of a transistor may be referred to as the "second terminal of the transistor."

[0035] In this specification, "parallel" means a state in which two lines are positioned at a relative angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at a relative angle of -15° or more and 15° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at a relative angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at a relative angle of 60° or more and 120° or less.

[0036] In this specification, when count values ​​and measured values ​​are referred to as "identical," "same," "equal," or "uniform" (including synonyms thereof), unless otherwise explicitly stated, this shall include an error margin of plus or minus 10%.

[0037] Voltage often refers to the potential difference between a given potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0038] In this specification, the voltage VDD (hereinafter also simply referred to as "VDD") and the voltage VSS (hereinafter also simply referred to as "VSS") refer to the power supply voltage or a voltage equal to the power supply voltage. Furthermore, when compared with a reference potential, the potential of VDD is higher than that of VSS. It is also possible to use the ground potential GND (hereinafter also simply referred to as "GND") as VDD or VSS. For example, if the potential of VDD is equal to that of GND, then VSS is lower than that of GND.

[0039] In this specification, the "on state" of a transistor means that the source and drain of the transistor are conductive (a state in which current can be conducted). The "off state" of a transistor means that the source and drain of the transistor are non-conductive (a state in which it can be considered electrically blocked).

[0040] Furthermore, in this specification, "on-current" refers to the current that flows between the source and drain when the transistor is in the "on" state. "Off-current" refers to the current that flows between the source and drain when the transistor is in the "off" state.

[0041] In this specification, potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, and the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Similarly, potential L is the potential that turns an n-type transistor off, and the potential that turns a p-type transistor on. Therefore, potential H is higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS.

[0042] Furthermore, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, there is no distinction between the forward and reverse directions. The same applies to the "Y direction" and "Z direction." Also, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0043] Generally, "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, "capacitive element" includes the case of the aforementioned "capacitance". That is, in this specification, "capacitive element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between. In this specification, one electrode of a capacitive element may be referred to as the "first terminal of the capacitive element". The other electrode of a capacitive element may be referred to as the "second terminal of the capacitive element". A capacitive element is sometimes called a capacitor.

[0044] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, the symbols may be accompanied by identifying symbols such as "A", "b", "_1", "[n]", and "[m,n]".

[0045] In this specification, "connection" includes "electrical connection." The term "electrical connection" is sometimes used to describe the connection relationships of circuit elements as physical objects. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements.

[0046] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0047] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0048] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0049] (Embodiment 1) An example of the configuration of a semiconductor device according to one aspect of the present invention will be described.

[0050] <Configuration Example> Figure 1(A) is an example of a schematic cross-sectional view of a semiconductor device 100 applicable to a semiconductor device according to one aspect of the present invention. Figure 1(B) is an example of a block diagram illustrating each of the components shown in Figure 1(A).

[0051] The semiconductor device 100 shown in Figure 1(A) includes an element layer 10 including a substrate 51 and an element layer 20. An element layer is a layer on which semiconductor elements such as transistors and capacitive elements are provided.

[0052] If the substrate 51 can be considered as a flat plate, the substrate 51 has two surfaces that are much larger in area than the other surfaces of the substrate 51. These two surfaces can be said to be opposing surfaces or surfaces that face each other. In this specification, one of these two surfaces may be referred to as the front surface or the first surface, and the other as the back surface or the second surface. Furthermore, surfaces other than the first and second surfaces may be referred to as side surfaces.

[0053] The element layer 10 has a circuit section 110 (also called the first circuit section). The element layer 10 is formed on the first surface (front side) of the flat substrate 51. The element layer 20 has a circuit section 120 (also called the second circuit section). The element layer 20 is formed on the second surface (back side) of the flat substrate 51. The circuit section 110 and the circuit section 120 are connected by a conductive layer 92 that functions as a through-electrode provided in the substrate 51. If the substrate 51 is a semiconductor substrate, for example a silicon substrate, the conductive layer 92 may be called a TSV (Through Silicon Via).

[0054] The circuit unit 110 has multiple functional circuits controlled by a control signal SEN supplied from an external source via a signal line. These functional circuits may include, for example, digital circuits such as FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), DSP (Digital Signal Processor), and semiconductor memory (hereinafter referred to as memory), as well as analog circuits, analog-to-digital converters (ADCs), and communication circuits.

[0055] The element layer 10 having the circuit section 110 preferably has a silicon-containing transistor (also called a "Si transistor") in the semiconductor layer where the channel is formed. Since Si transistors can increase field-effect mobility, it is possible to improve the operating speed, increase the mounting density, and reduce power consumption of the semiconductor device 100. Furthermore, since the Si transistor can also be a p-channel type transistor, the degree of freedom in circuit design can be increased. In addition, if the substrate 51 is a semiconductor substrate, for example a silicon substrate, it is also possible to configure the Si transistor to be provided in a part of the substrate 51.

[0056] The circuit unit 120 has the function of generating a power supply voltage to be supplied to the circuit unit 110 based on the signal CLK supplied from the outside via a clock signal line and the power supply voltage (VDD-GND) supplied via a power supply line. The signal CLK is, for example, a clock signal, an inverted clock signal, etc. The circuit unit 120 includes a power supply circuit 121, a level shift circuit 122, and a power supply circuit 123.

[0057] In this specification, the term "voltage VDD-GND" refers to the voltage that is the potential difference between VDD and GND. For example, "voltage VDD2-GND" means the voltage that is the potential difference between VDD2 and GND. In drawings, the circuit supplying "voltage VDD2-GND" may only show VDD2, and the diagram of GND may be omitted.

[0058] In the configuration shown in Figure 1(A), the power lines provided on the second side of the substrate 51 can be arranged separately from the signal lines that supply the control signal SEN, which are provided on the first side of the substrate 51. This prevents interference between the power lines and the signal lines. Furthermore, by arranging the power lines and signal lines separately, the width of the power lines can be increased, which reduces wiring resistance and mitigates factors such as heat generation and voltage drop. In addition, signal delay in the signal lines can be suppressed.

[0059] The element layer 20 having the circuit section 120 preferably has a transistor (also called an "OS transistor") containing an oxide semiconductor, which is a type of metal oxide, in the semiconductor layer in which the channel is formed. In particular, it is preferable to use an OS transistor in which one or both of In and Zn are included in the semiconductor layer of the transistor. OS transistors using In oxide in the semiconductor layer are particularly suitable for the circuit section 120 because they can achieve high field-effect mobility.

[0060] Furthermore, OS transistors maintain their characteristics well even in high-temperature environments, enabling stable operation. Therefore, even when the element layer 20 containing OS transistors is superimposed on the element layer 10 containing Si transistors, the circuit is less affected by the heat generated by the Si transistors, resulting in stable circuit operation. Consequently, the reliability of the semiconductor device 100 can be improved.

[0061] The transistors in each circuit of the circuit section 120, which functions as power supply circuits 121, 123, or level shift circuit 122, are required to have high dielectric strength. OS transistors have high dielectric strength between the source and drain. In addition, since the transistors in the element layer 20 can be manufactured at a different process node than the element layer 10, a configuration in which the gate insulating film can be made thicker is possible. Therefore, OS transistors in the element layer 20 can be transistors with superior dielectric strength compared to Si transistors.

[0062] According to one aspect of the present invention, an element layer 20 having a circuit section 120 with an OS transistor can be formed on the back side of a substrate 51 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 100 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0063] By forming the element layer 20 using thin-film formation technology, photolithography technology, etc., high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the circuit section 110 over extremely short distances. Therefore, the necessary voltage can be supplied to the necessary locations of the circuit section 110. In addition, in the semiconductor device 100 according to one aspect of the present invention, since the connection distance between the circuit section 120 and the circuit section 110 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0064] Figure 1(B) is a diagram illustrating the power supply circuit 121, level shift circuit 122, and power supply circuit 123 of the circuit section 120 in Figure 1(A).

[0065] The power supply circuit 121 is a charge pump circuit that has the function of boosting or stepping down an externally supplied voltage to a voltage necessary to operate the load circuit unit 110 by controlling the conduction state (on) or non-conduction state (off) of a transistor that functions as a switch. The power supply circuit 121 is controlled to be on or off by the clock signals HCLK1-HCLK2 supplied by the level shift circuit 122. The clock signal HCLK2 is, for example, the inverted signal of the clock signal HCLK1. The power supply circuit 121 can supply the externally supplied voltage VDD1-GND as the voltage VDD2-GND necessary to operate the load circuit unit 110.

[0066] The voltage VDD1-GND is the voltage corresponding to the potential difference between the reference potential GND (earth potential, ground potential, reference voltage, or sometimes simply referred to as GND) and the potential VDD1. The potential VDD1 may sometimes be read as voltage VDD1 in the explanation. The same applies to voltage VDD2-GND, and the voltages VDD3-GND and VDD4-GND described later.

[0067] The level shift circuit 122 is a circuit that has the function of performing a level shift of the amplitude voltage of the externally supplied clock signals CLK1-CLK2 based on the voltage VDD3-GND supplied from the power supply circuit 123, and supplying it to the power supply circuit 121 as clock signals HCLK1-HCLK2. Clock signal CLK2 is, for example, the inverted signal of clock signal CLK1. The level shift circuit 122 can supply the power supply circuit 121 with clock signals HCLK1-HCLK2 that have a higher amplitude voltage than clock signals CLK1-CLK2, based on a voltage VDD3-GND that is greater than the amplitude voltage of clock signals CLK1-CLK2.

[0068] The notation CLK1-CLK2 indicates that clock signal CLK1 and its inverted signal, clock signal CLK2, are input. Therefore, clock signal CLK1 and clock signal CLK2 are signals with the same clock frequency and amplitude voltage. The same applies to clock signals HCLK1-HCLK2 and clock signals CLK3-CLK4, which will be discussed later.

[0069] The level shift circuit 122 can also be configured to perform a level shift of the amplitude voltage of an externally supplied control signal. An externally supplied control signal could be, for example, a power gating signal for power gating a functional circuit in the circuit unit 110. The level shifted power gating signal can be supplied to the gate of a transistor that functions as a switch for power gating. The level shift circuit 122 can supply a power gating signal with an increased amplitude voltage to the transistor gate based on a voltage VDD3-GND that is greater than the amplitude voltage of the power gating signal.

[0070] The power supply circuit 123 is a charge pump circuit that has a transistor that functions as a rectifier element (diode) and a capacitive element, and supplies the clock signal CLK3-CLK4 to one electrode of the capacitive element to boost or lower the voltage VDD4-GND supplied from an external source and supply it to the level shift circuit 122. In the following description, the power supply circuit 123 will be described as boosting the voltage VDD4 to the voltage VDD3, but it is also possible to configure it to lower the voltage VSS1, which is lower than the reference potential GND, to a voltage VSS2 that is even lower than the voltage VSS1.

[0071] In one embodiment of the present invention, the power supply circuit 123 may be omitted from the element layer 20. In this case, the voltage VDD3 supplied to the level shift circuit 122 can be supplied to the level shift circuit 122 located in the element layer 20 from outside the semiconductor device 100. Even with a configuration in which the power supply circuit 123 is omitted from the element layer 20, the level shift of the clock signal in the level shift circuit 122 is still possible, and the power supply circuit 121 can be operated with sufficient performance. The circuit size of the circuit section 120 on the second side (back side) of the substrate 51 can be reduced, thus reducing the area occupied by the circuit section 120. As a result, a semiconductor device with excellent manufacturing yield can be obtained. Furthermore, since the voltage VDD3 can be supplied from an external power supply circuit, a power supply circuit using an inductor such as a linear regulator or a switching regulator can be used. As a result, a power supply circuit 123 with excellent performance in terms of conversion efficiency and current supply capability can be obtained.

[0072] Figure 2(A) is a diagram that adds schematic diagrams to the block diagram of Figure 1(B) to explain the functions of the power supply circuit 121, the level shift circuit 122, and the power supply circuit 123.

[0073] As shown in Figure 2(A), the power supply circuit 123 boosts the voltage VDD4 to the voltage VDD3. The power supply circuit 123 can be configured as a charge pump circuit that boosts the voltage VDD4 to the voltage VDD3 using a capacitive element to which the clock signals CLK3-CLK4 are supplied and a diode-connected transistor. Therefore, the power supply circuit 123 can achieve voltage boosting or de-boiling without switching the transistor.

[0074] The level shift circuit 122 shown in Figure 2(A) level shifts the clock signals CLK1-CLK2 to HCLK1-HCLK2, which have a higher amplitude voltage. The level shift circuit 122 can increase the amplitude voltage of the clock signals CLK1-CLK2 using the voltage VDD3 boosted by the power supply circuit 123.

[0075] The power supply circuit 121 shown in Figure 2(A) boosts the voltage VDD1 to the voltage VDD2. The power supply circuit 121 can be configured as a charge pump circuit that boosts the voltage VDD1 to the voltage VDD2 using a transistor to which the amplitude voltage of the clock signal HCLK1-HCLK2, which has been increased by the level shift circuit 122, is supplied, and a capacitive element. As a result, the power supply circuit 121 enables the transistor acting as a switch to perform a switching operation with improved performance. Specifically, the amount of current flowing in the ON state of the transistor functioning as a switch can be increased, or the amount of current flowing in the OFF state of the transistor functioning as a switch can be made extremely small. As a result, the power supply circuit 121 can be operated with sufficient performance.

[0076] Furthermore, as shown in Figure 2(B), the power supply circuit 121 can also step down the voltage VDD1 to the voltage VDD2b. The power supply circuit can be configured as a charge pump circuit that steps down the voltage VDD1 to the voltage VDD2b according to the capacitance of the capacitive element connected to the output terminal. Therefore, as in Figure 2(A), the transistor acting as a switch can perform switching operations with improved performance.

[0077] In one aspect of the present invention, the circuit section 120 provided on the second side of the substrate 51 is configured to include a power supply circuit 121, a level shift circuit 122, and a power supply circuit 123. The transistor functioning as a switch in the power supply circuit 121 can be controlled by the level shift circuit 122 provided on the second side of the substrate 51 using a clock signal with an increased amplitude voltage. Furthermore, the voltage used to increase the amplitude voltage of the clock signal can be a boosted voltage provided by the power supply circuit 123 on the second side of the substrate 51. As a result, the power supply circuit 121 can operate with sufficient performance. Consequently, the circuit section 120 can supply a stable voltage to the circuit section 110 provided on the first side of the substrate 51.

[0078] One embodiment of the present invention allows the amplitude voltage of the clock signal to be increased within the circuit unit 120, and a stable voltage to be generated in the power supply circuit. Compared to a configuration in which a high-amplitude clock signal is supplied from an external source and a stable voltage is generated in the power supply circuit, this configuration reduces the effect of increased wiring resistance due to increased wiring length, thus enabling lower power consumption. Furthermore, compared to a configuration in which a boosted voltage is supplied from an external source to increase the amplitude voltage of the clock signal, this configuration reduces the effect of voltage drop due to increased wiring resistance, thus enabling a stable voltage supply.

[0079] As described above, the circuit section 120 provided on the second side of the substrate 51 requires high dielectric strength. OS transistors with thick gate insulating films have excellent dielectric strength, but their on-current may decrease. Therefore, by incorporating a configuration within the circuit section 120 that increases the on-current of transistors that function as switches in the power supply circuit 121, such as voltage boosting in the power supply circuit 123 without switching operation and level shifting of the amplitude voltage of the clock signal in the level shift circuit 122, the power supply circuit 121 can be operated with sufficient performance.

[0080] Furthermore, since the circuit section 120 provided on the second surface side of the substrate 51 can be integrally formed (also called monolithic stacking) with the circuit section 110 provided on the first surface side of the substrate 51, it is possible to reduce the manufacturing cost of the semiconductor device. In addition, by providing circuits such as a level shift circuit 122 and a power supply circuit 123 in the element layer 20 having the circuit section 120 to operate the power supply circuit 121 with sufficient performance, it is possible to reduce the number of external circuits of the semiconductor device, thereby enabling miniaturization of the device including the semiconductor device.

[0081] Next, Figures 3(A) to 7(B) describe an example of a circuit configuration applicable to the power supply circuit 121, the level shift circuit 122, and the power supply circuit 123.

[0082] The circuit 121A shown in Figure 3(A) is an example of a circuit configuration applicable to the power supply circuit 121. Circuit 121A is a boost-type charge pump circuit having a transistor that functions as a switch. By supplying a voltage VDD1 to terminal IN of circuit 121A, a voltage VDD2 higher than VDD1 can be output from terminal OUT of circuit 121A.

[0083] The circuit 121A shown in Figure 3(A) includes switches SWn1, SWn2, SWp1, SWp2, and a capacitive element C11. Note that switches SWn1, SWn2, SWp1, and SWp2 can each be composed of OS transistors. Switches SWn1 and SWn2 are controlled to be on or off by the clock signal HCLK1. Switches SWp1 and SWp2 are controlled to be on or off by the clock signal HCLK2, which is the inverted signal of the clock signal HCLK1. Switches SWn1 and SWn2, and switches SWp1 and SWp2, are controlled to be on or off alternately.

[0084] In circuit 121A, the capacitive element C11 is charged and discharged via switches SWn1, SWn2, SWp1, and SWp2. As a result, a voltage VDD2 higher than VDD1 can be output from terminal OUT of circuit 121A.

[0085] Figure 4(A) is a circuit diagram in which switches SWn1, SWn2, SWp1, and SWp2 are represented by OS transistors M11 to M14. In Figure 4(A), the clock signal HCLK1 is supplied to the gates of transistors M11 and M12 via terminal CL. In Figure 4(A), the clock signal HCLK2 is supplied to the gates of transistors M13 and M14 via terminal CLB.

[0086] Circuit 121A can generate voltage VDD2 by alternately turning transistors M11, M12 and M13, M14 on or off simply by supplying clock signals HCLK1 and HCLK2. Since clock signals HCLK1 and HCLK2 are clock signals with increased amplitude voltage, transistors M11 to M14 can operate with sufficient performance.

[0087] The circuit 121B shown in Figure 3(B) is an example of a circuit configuration applicable to the power supply circuit 121. Circuit 121B is a step-down charge pump circuit having a transistor that functions as a switch. By supplying the voltage VDD1 to terminal IN of circuit 121B, a voltage VDD2_L lower than VDD1 can be output from terminal OUT of circuit 121A.

[0088] The circuit 121B shown in Figure 3(B) includes switches SWn1, SWn2, SWp1, SWp2, and a capacitive element C11. Note that switches SWn1, SWn2, SWp1, and SWp2 can each be composed of OS transistors. Switches SWn1 and SWn2 are controlled to be on or off by the clock signal HCLK1. Switches SWp1 and SWp2 are controlled to be on or off by the clock signal HCLK2, which is the inverted signal of the clock signal HCLK1. Switches SWn1 and SWn2, and switches SWp1 and SWp2, are controlled to be on or off alternately.

[0089] In circuit 121B, the capacitive element C11 is charged and discharged via switches SWn1, SWn2, SWp1, and SWp2. This allows a voltage VDD2_L lower than VDD1 to be output from terminal OUT of circuit 121A.

[0090] Figure 4(B) is a circuit diagram in which switches SWn1, SWn2, SWp1, and SWp2 are represented by OS transistors M11 to M14. In Figure 4(B), the clock signal HCLK1 is supplied to the gates of transistors M11 and M12 via terminal CL. In Figure 4(B), the clock signal HCLK2 is supplied to the gates of transistors M13 and M14 via terminal CLB.

[0091] Circuit 121B can generate the voltage VDD2_L by alternately turning on or off transistors M11, M12 and M13, M14 simply by supplying clock signals HCLK1 and HCLK2. Since clock signals HCLK1 and HCLK2 are clock signals with increased amplitude voltage, transistors M11 to M14 can operate with sufficient performance.

[0092] It is possible to use transistors with back gates as transistors M11 to M14 shown in Figures 4(A) and 4(B). When using transistors with back gates in the transistors that make up circuits 121A and 121B, it is preferable to connect the gate and the back gate. Figure 4(C) shows the circuit symbol of a transistor with the gate and back gate connected.

[0093] Here, we will explain transistors with a back gate. The gate and back gate of a transistor are positioned so as to sandwich the channel formation region of the semiconductor layer. Both the gate and the back gate are formed from a conductive layer or a semiconductor layer with low resistivity. The back gate can function in the same way as the gate. When the gate is used to control the on and off states of the transistor, the potential of the back gate can be the same as the gate potential. Alternatively, it can be set to the reference potential GND or any arbitrary potential.

[0094] For example, when turning on a transistor, supplying the potential to both the gate and the back gate increases the on-current compared to supplying it to only one. Connecting the gate and back gate allows them to always be at the same potential. Furthermore, controlling the back gate's potential independently of the gate's allows for adjustment of the transistor's threshold voltage.

[0095] Furthermore, it is possible to supply a fixed potential, such as a reference potential GND, to the back gate. Since the gate and back gate are formed by conductive layers, the channel formation region of the semiconductor layer is sandwiched between the gate and back gate, making it difficult for electromagnetic fields generated outside the transistor and electric fields related to the drain voltage to act on the channel formation region (also known as the "electromagnetic shielding effect"). For this reason, providing a back gate to a transistor stabilizes its operation. In addition, providing a back gate to a transistor reduces the variation in characteristics between multiple transistors. Providing a back gate to a transistor can improve the reliability of the transistor. Therefore, the reliability of the semiconductor device containing the transistor can be improved. Note that the electromagnetic shielding effect can be obtained even if one or both of the gate and back gate are electrically floating (also known as the "floating state"), but the effect can be enhanced by supplying potential to the gate and back gate.

[0096] The circuit 122A shown in Figure 5(A) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122A is a level shift circuit supplied with the power supply voltage VDD3-GND. By supplying the clock signal CLK1 to terminal CL of circuit 122A and the clock signal CLK2 to terminal CLB of circuit 122A, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122A. Although not shown in the figure, by supplying the clock signal CLK2 to terminal CL of circuit 122A and the clock signal CLK1 to terminal CLB of circuit 122A, a clock signal HCLK2 with a higher amplitude voltage than the clock signal CLK2 can be output from terminal OUT of circuit 122A.

[0097] As shown in Figure 5(A), circuit 122A includes transistors M21, M22, M23, M24, and a capacitive element C21. Note that transistors M21, M22, M23, and M24 can each be composed of OS transistors. Transistors M21, M22, M23, and M24 are controlled according to clock signals CLK1 and CLK2.

[0098] For example, during the period when clock signal CLK1 is at a high level (high potential level) and clock signal CLK2 is at a low level (low potential level), transistor M24 is in the off state and transistor M23 is in the on state. Transistor M23 is turned off when the potential of the gate of transistor M21, that is, the potential of the source of transistor M23, rises. The gate of transistor M21 becomes floating. As the potential of the gate of transistor M21 rises, current flows through transistor M21, and the potential of terminal OUT rises to the potential based on voltage VDD3. At this time, by utilizing the fact that the gate of transistor M21 is floating, the gate of transistor M21 can be boosted by capacitive coupling in the capacitive element C21. Therefore, a clock signal HCLK1 with a higher amplitude voltage than clock signal CLK1 can be output more reliably from terminal OUT of circuit 122A.

[0099] The circuit 122B shown in Figure 5(B) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122B is a level shift circuit supplied with voltage VDD4 in addition to the power supply voltage VDD3-GND. By supplying the clock signal CLK1 to terminal CL of circuit 122B and the clock signal CLK2 to terminal CLB of circuit 122B, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122B. Although not shown in the figure, by supplying the clock signal CLK2 to terminal CL of circuit 122B and the clock signal CLK1 to terminal CLB of circuit 122B, a clock signal HCLK2 with a higher amplitude voltage than the clock signal CLK2 can be output from terminal OUT of circuit 122B.

[0100] Circuit 122B, as shown in Figure 5(B), includes transistors M21, M22, M23, and a capacitive element C21. Note that transistors M21, M22, and M23 can each be composed of OS transistors. Transistors M21, M22, and M23 are controlled according to clock signals CLK1 and CLK2.

[0101] For example, when the clock signal CLK1 is at a high level (high potential level) and the clock signal CLK2 is at a low level (low potential level), transistor M23 is ON. Transistor M23 is turned OFF when the potential of the gate of transistor M21 rises. The gate of transistor M21 becomes floating. As the potential of the gate of transistor M21 rises, current flows through transistor M21, and the potential of terminal OUT rises to the potential based on voltage VDD3. At this time, by utilizing the fact that the gate of transistor M21 is floating, the gate of transistor M21 can be boosted by capacitive coupling in the capacitive element C21. Therefore, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122B more reliably.

[0102] The circuit 122C shown in Figure 5(C) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122C is a level shift circuit supplied with the power supply voltage VDD3-GND. By supplying the clock signal CLK2 to terminal CLB of circuit 122C, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122C. Although not shown in the figure, by supplying the clock signal CLK1 to terminal CLB of circuit 122C, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK2 can be output from terminal OUT of circuit 122C.

[0103] The circuit 122C shown in Figure 5(C) has transistors M21 and M22. Note that transistors M21 and M22 can each be composed of OS transistors. Transistors M21 and M22 are controlled according to the clock signal CLK2 (or CLK1).

[0104] For example, when the clock signal CLK2 is at an L level (low potential level), transistor M22 is in the OFF state. Current flows through transistor M21, and the potential at terminal OUT rises to a potential based on voltage VDD3. This allows a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 to be output from terminal OUT. Figure 5(C) shows that the number of transistors can be reduced compared to the configurations of circuit 122A shown in Figure 5(A) and circuit 122B shown in Figure 5(B).

[0105] The circuit 122D shown in Figure 5(D) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122D is a level shift circuit supplied with the power supply voltage VDD3-GND, and as shown in Figure 5(D), it is a configuration in which transistors M23 and M24 are added to the configuration of circuit 122C shown in Figure 5(C). In the configuration shown in Figure 5(D), by supplying the clock signal CLK2 to terminal CLB, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122D. Although not shown in the figure, by supplying the clock signal CLK1 to terminal CLB of circuit 122D, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK2 can be output from terminal OUT of circuit 122D.

[0106] The circuit 122D shown in Figure 5(D) includes transistors M21 to M24 and a capacitive element C21. Note that each of the transistors M21 to M24 can be an OS transistor. The transistors M21 to M24 are controlled according to the clock signal CLK2 (or CLK1).

[0107] For example, during the period when the clock signal CLK2 is at an L level (low potential level), transistors M22 and M24 are in the off state, and current flows through transistor M23, causing the gate potential of transistor M21 to rise. Transistor M23 is turned off by the rise in the gate potential of transistor M21. The gate of transistor M21 becomes floating. As the gate potential of transistor M21 rises, current flows through transistor M21, and the potential of terminal OUT rises to the potential based on voltage VDD3. At this time, by utilizing the fact that the gate of transistor M21 is floating, the gate of transistor M21 can be boosted by capacitive coupling in the capacitive element C21. Therefore, a clock signal HCLK2 with a higher amplitude voltage than the clock signal CLK2 can be output more reliably from terminal OUT of circuit 122D.

[0108] The circuit 123A shown in Figure 6(A) is an example of a circuit configuration applicable to the power supply circuit 123. Circuit 123A is a boost-type charge pump circuit having a transistor that functions as a diode and a capacitive element. By supplying a voltage VDD4 to terminal IN of circuit 123A, a voltage VDD3 higher than VDD4 can be output from terminal OUT of circuit 123A.

[0109] Circuit 123A has transistors M41, M42, M43, M44, M45 and capacitive elements C41, C42, C43, C44, C45 connected as shown in Figure 6(A). Figure 6(A) shows an example where the basic circuit constituting the charge pump circuit has 5 stages, but it is not limited to this and the charge pump circuit can be constructed with any number of stages. Transistors M41 to M45 can each be made up of OS transistors. Capacitive elements C41 to C44 are supplied with a clock signal CLK3 or CLK4 via terminal CL or terminal CLB as shown in Figure 6(A). Charge can be accumulated in capacitive element C45 by charge transitions via capacitive elements C41 to C44 and transistors M41 to M45. Therefore, a desired voltage can be output at terminal OUT according to the capacitance of capacitive element C45.

[0110] The configuration in Figure 6(A) allows the use of transistors with back gates as transistors M41 to M45, as shown in circuit 123B in Figure 6(B). Each of the transistors M41 to M45 shown in Figure 6(B) has a back gate, and the gate and back gate are connected as shown in Figure 6(A).

[0111] The circuit 123C shown in Figure 7(A) is an example of a circuit configuration applicable to the power supply circuit 123. Circuit 123C is a step-down charge pump circuit having a transistor that functions as a diode and a capacitive element. By supplying a voltage VSS1 to terminal IN of circuit 123C, a voltage VSS2 lower than VSS1 can be output from terminal OUT of circuit 123C. Voltage VSS1 is, for example, a voltage lower than the reference potential GND (reference voltage).

[0112] Circuit 123C has transistors M41, M42, M43, M44, M45 and capacitive elements C41, C42, C43, C44, C45 connected as shown in Figure 7(A). Figure 7(A) shows an example where the basic circuit constituting the charge pump circuit has 5 stages, but it is not limited to this and the charge pump circuit can be constructed with any number of stages. Note that transistors M41 to M45 can each be made up of OS transistors. Capacitive elements C41 to C44 are supplied with a clock signal CLK3 or CLK4 via terminal CL or terminal CLB as shown in Figure 7(A). Charge can be accumulated in capacitive element C45 by charge transitions via capacitive elements C41 to C44 and transistors M41 to M45. Therefore, a desired voltage can be output at terminal OUT according to the capacitance of capacitive element C45.

[0113] The configuration in Figure 7(A) allows the use of transistors with back gates as transistors M41 to M45, as shown in circuit 123D in Figure 7(B). Each of the transistors M41 to M45 shown in Figure 7(B) has a back gate, and the gates and back gates are connected to each other.

[0114] Figure 8 shows circuit configurations in which the circuit configuration of the power supply circuit 121 in Figure 1(B) is replaced with the circuit 121A in Figure 4(A), the circuit configuration of the level shift circuit 122 in Figure 1(B) is replaced with the circuit 122A in Figure 5(A), and the circuit configuration of the power supply circuit 123 in Figure 1(B) is replaced with the circuit 123A in Figure 6(A). In Figure 8, the level shift circuit 122 shows a level shift circuit 122_1 that supplies a clock signal HCLK1 obtained by level shifting the clock signal CLK1, and a level shift circuit 122_2 that supplies a clock signal HCLK2 obtained by level shifting the clock signal CLK2.

[0115] Level shift circuit 122_1 has transistors M21_1 to M24_1 and a capacitive element C21_1. Level shift circuit 122_2 has transistors M21_2 to M24_2 and a capacitive element C21_2. Level shift circuits 122_1 and 122_2 can have the same circuit configuration as circuit 122A described above. The power supply circuit 121, level shift circuits 122_1 and 122_2, and power supply circuit 123 shown in Figure 8 can each be made of OS transistors and can be connected via wiring having a conductive layer. Therefore, the functions of the circuits according to the transmission and reception of signals can be realized.

[0116] Figure 9(A) shows a circuit configuration in which the power supply circuit 121 of Figure 1(B), to which voltage VDD1, reference potential GND, clock signal HCLK1, and HCLK2 are supplied, is arranged in parallel. In Figure 9(A), as an example, a circuit configuration is shown in which circuits 121a to 121d, which function as four power supply circuits, are arranged in parallel. Circuits 121a to 121d can have the same circuit configuration as power supply circuit 121. This configuration makes it possible to stabilize the output voltage VDD2.

[0117] Figure 9(A) shows a configuration in which the power supply circuit 121 is connected in parallel, but it is also possible to configure the level shift circuit 122 and the power supply circuit 123 to be connected in parallel. Figure 9(B) shows, as an example, a circuit configuration in which circuits 122a to 122d that function as four level shift circuits and circuits 123a to 123d that function as four power supply circuits are arranged in parallel. This configuration makes it possible to stabilize the output clock signals HCLK1 and HCLK2, and the voltage VDD3.

[0118] Figure 10 shows a block diagram illustrating a variation of the block diagram shown in Figure 1(B). To reduce repetition, the explanation of Figure 10 will primarily focus on the differences from the block diagram shown in Figure 1(B). For parts of Figure 10 not explained, the explanation in Figure 1(B) can be referenced.

[0119] Figure 10 includes a power supply circuit 124 in addition to the configuration shown in Figure 1(B). The power supply circuit 124 includes a transistor that functions as a rectifier element (diode) and a capacitive element. The power supply circuit 124 can be provided in the circuit section 120 of the element layer 20, similar to the power supply circuit 123. The circuit configuration of the power supply circuit 124 can be the same as the circuit configuration of Figure 7(A) or Figure 7(B) described above. The power supply circuit 124 has the function of supplying the clock signals CLK3-CLK4 to one electrode of the capacitive element, thereby stepping down the externally supplied voltage VSS1 and supplying it as the voltage VSS2 to the power supply circuit 121. The power supply circuit 124 can achieve voltage step-down without using a charge pump circuit that performs step-down by switching transistors.

[0120] Although Figure 10 describes a configuration in which the externally supplied voltage VSS1 is stepped down, other configurations are also possible. For example, it is also possible to step down the voltage VDD4 supplied to the power supply circuit 123, or the voltage VDD3 boosted by the power supply circuit 123, and supply it as the voltage to the power supply circuit 121. By adopting this configuration, it is possible to reduce the number of voltages supplied to the circuit section 120, reduce the number of wires, etc.

[0121] The voltage VSS2 generated by the power supply circuit 124 is supplied to the power supply circuit 121. The voltage VSS2 can be, for example, the voltage applied to the back gates of transistors M11 to M14 as described in Figures 4(A) and 4(B). For example, the circuit 121C shown in Figure 11(A) is a modified example of the circuit 121A shown in Figure 4(A) described above, and is an example of a circuit configuration applicable to the power supply circuit 121 to which the voltage VSS2 from the power supply circuit 124 is supplied. Similarly, the circuit 121D shown in Figure 11(B) is a modified example of the circuit 121B shown in Figure 4(B) described above, and is an example of a circuit configuration applicable to the power supply circuit 121 to which the voltage VSS2 from the power supply circuit 124 is supplied.

[0122] Circuits 121C and 121D use transistors M11 to M14 that have back gates. In circuits 121C and 121D, it is preferable to connect the back gates of transistors M11 to M14 to the wiring that supplies the voltage VSS2. This configuration makes it possible to supply the voltage VSS2 to the back gates of the transistors. As a result, the threshold voltage of the transistors can be shifted to the positive side, and the operation of the transistors becomes more stable. Furthermore, the variation in characteristics between multiple transistors is reduced. In addition, the reliability of the transistors can be improved.

[0123] In one embodiment of the present invention, the power supply circuit 124 may be omitted from the element layer 20. In this case, the voltage VSS2 supplied to the power supply circuit 121 can be supplied to the power supply circuit 121 located in the element layer 20 from outside the semiconductor device 100. Even with a configuration in which the power supply circuit 124 is omitted from the element layer 20, it is possible to shift the threshold voltage of the transistor with a back gate in the power supply circuit 121 to the positive side, allowing the power supply circuit 121 to operate with sufficient performance. The circuit size of the circuit section 120 located on the second side (back side) of the substrate 51 can be reduced, thus reducing the area occupied by the circuit section 120. As a result, a semiconductor device with excellent manufacturing yield can be obtained. Furthermore, since the voltage VSS2 can be supplied from an external power supply circuit, a power supply circuit using an inductor such as a linear regulator or a switching regulator can be used. As a result, a power supply circuit 124 with excellent performance in terms of conversion efficiency and current supply capability can be obtained.

[0124] Figure 12 shows circuit configurations in which the circuit configuration of power supply circuit 121 in Figure 10 is replaced with the circuit 121C in Figure 11(A), the circuit configuration of level shift circuit 122 in Figure 10 is replaced with the circuit 122A in Figure 5(A), the circuit configuration of power supply circuit 123 in Figure 1(B) is replaced with the circuit 123A in Figure 6(A), and the circuit configuration of power supply circuit 124 in Figure 10 is replaced with the circuit 123C in Figure 7(A). In Figure 12, as in Figure 8, level shift circuit 122_1 and level shift circuit 122_2 are shown as level shift circuit 122.

[0125] The power supply circuit 121, level shift circuits 122_1 and 122_2, and power supply circuits 123 and 124 shown in Figure 12 can each be constructed using OS transistors and connected via wiring with a conductive layer. Therefore, the functions of the circuits can be realized in accordance with the transmission and reception of signals.

[0126] Figures 13(A) to 13(C) illustrate variations of the block diagram shown in Figure 1(B). To reduce repetition, the explanations of Figures 13(A) to 13(C) primarily focus on the differences from the block diagram shown in Figure 1(B). For parts of Figures 13(A) to 13(C) that are not explained, the explanation in Figure 1(B) can be referenced.

[0127] Figure 13(A) shows a modified example of the configuration shown in Figure 1(B), in which the voltage supplied to the power supply circuit 123 is the same as the voltage supplied to the power supply circuit 121, VDD1. This configuration allows for a reduction in the number of voltages supplied to the circuit section 120, a reduction in the number of wires, and so on.

[0128] Figure 13(B) shows a modified example of the configuration shown in Figure 1(B), in which the clock signal supplied to the power supply circuit 123 is the same as the clock signal CLK1-CLK2 supplied to the level shift circuit 122. This configuration allows for a reduction in the number of clock signals supplied to the circuit section 120, a reduction in the number of wires, and so on.

[0129] Figure 13(C) is a modified example of the configuration shown in Figure 1(B), combining the configurations of Figures 13(A) and 13(B). This configuration allows for a reduction in the number of voltages supplied to the circuit section 120, a reduction in the number of clock signals, a reduction in the number of wires, and so on.

[0130] Figure 14 is a circuit diagram that shows the configuration of the block diagram described in Figure 13(A), similar to Figures 8 and 12.

[0131] The power supply circuit 121, level shift circuits 122_1 and 122_2, and power supply circuit 123 shown in Figure 14 can each be constructed using OS transistors and connected via wiring having a conductive layer. The number of wires supplying power to power supply circuits 121 and 123 can be reduced as shown in Figure 14. Therefore, it is possible to reduce the number of voltages supplied to the circuit section 120, reduce the number of wires, and so on.

[0132] In Figure 1(B), the clock signal is explained assuming a clock signal with a duty cycle of 50%, but other configurations are also possible. For example, multiple clock signals with small duty cycles, specifically the clock signals CLK1_1 to CLK1_4 shown in Figure 15(A), can be used. By using this configuration, voltage stabilization can be achieved in the circuit section 120.

[0133] Figure 15(B) shows that clock signals CLK1_1 to CLK1_4 can be applied as clock signals corresponding to clock signal CLK1 in Figure 1(B), clock signals CLK2_1 to CLK2_4 as clock signals corresponding to clock signal CLK2 in Figure 1(B), clock signals CLK3_1 to CLK3_4 as clock signals corresponding to clock signal CLK3 in Figure 1(B), and clock signals CLK4_1 to CLK4_4 as clock signals corresponding to clock signal CLK4 in Figure 1(B). Also shown are clock signals HCLK1_1 to HCLK1_4 as clock signals corresponding to clock signal HCLK1 in Figure 1(B), and clock signals HCLK2_1 to HCLK2_4 as clock signals corresponding to clock signal HCLK2 in Figure 1(B). With this configuration, voltage stabilization can be achieved in the circuit section 120.

[0134] Figures 16(A) to 16(C) illustrate variations of the block diagram shown in Figure 1(B). To reduce repetition, the explanations of Figures 16(A) to 16(C) primarily focus on the differences from the block diagram shown in Figure 1(B). For parts of Figures 16(A) to 16(C) that are not explained, the explanation in Figure 1(B) can be referenced.

[0135] Figure 16(A) shows a modified example of the configuration shown in Figure 1(B) in which the clock signal CLK2 supplied to the level shift circuit 122 is reduced. Clock signal CLK2 is the inverted signal of clock signal CLK1. Therefore, by inverting clock signal CLK1 inside the level shift circuit 122, it is possible to reduce the clock signal CLK2, which is the inverted signal of clock signal CLK1. This configuration makes it possible to reduce the number of clock signals supplied to the circuit section 120, reduce the number of wires, and so on.

[0136] Figure 16(B) shows a modified example of the configuration shown in Figure 1(B) in which the clock signal CLK4 supplied to the power supply circuit 123 is reduced. Clock signal CLK4 is the inverted signal of clock signal CLK3. Therefore, by inverting and using clock signal CLK3 inside the power supply circuit 123, it is possible to reduce the clock signal CLK4, which is the inverted signal of clock signal CLK3. This configuration makes it possible to reduce the number of clock signals supplied to the circuit section 120, reduce the number of wires, and so on.

[0137] Figure 16(C) shows a modified example of the configuration shown in Figure 1(B), combining the configurations of Figures 16(A) and 16(B). This configuration allows for a reduction in the number of voltages supplied to the circuit section 120, a reduction in the number of clock signals, a reduction in the number of wires, and so on.

[0138] Figures 17(A) to 17(C) illustrate variations of the block diagram shown in Figure 1(A). To reduce repetition, the explanations of Figures 17(A) to 17(C) primarily focus on the differences from the block diagram shown in Figure 1(A). For parts of Figures 17(A) to 17(C) that are not explained, the explanation in Figure 1(A) can be referenced.

[0139] Figure 17(A) illustrates a plurality of functional circuits 111 to 113 as circuits of the circuit section 110 in Figure 1(A). The circuits of the circuit section 110 are not limited to functional circuits 111, 112, and 113, and one or more of these can be used. It is also possible to include circuits with other functions. For example, it is possible to include digital circuits such as FPGA, CPU, GPU, and memory, analog circuits, analog-to-digital converters (ADCs), communication circuits, etc.

[0140] Digital circuits include logic gates such as NOT gates, NAND gates, and NOR gates, as well as flip-flops, shift registers, adders, and multipliers. Analog circuits include amplifiers, oscillators, modulation circuits, filters, and high-frequency circuits.

[0141] As described above, the power supply circuit 121 of the circuit unit 120 can be configured to generate voltage using a clock signal that has been level-shifted by the level shift circuit 122, based on the voltage boosted by the power supply circuit 123. The generated voltage can be supplied to the functional circuits 111, 112, and 113 of the circuit unit 110 via the wiring within the circuit unit 120, the conductive layer 92 of the substrate 51, etc.

[0142] Figure 17(B) shows a plurality of element layers 20A to 20C as element layers 20 on which the circuit section 120 is provided. Element layers 20A to 20C are stacked on the second surface of the substrate 51. A power supply circuit 121 is provided in element layer 20A, a level shift circuit 122 in element layer 20B, and a power supply circuit 123 in element layer 20C. Element layers 20A to 20C can be stacked by making them element layers having OS transistors. Therefore, the element layer 20 having element layers 20A to 20C can be an element layer having OS transistors from different process nodes.

[0143] In Figure 17(C), a plurality of power supply circuits 121_1 to 121_3, level shift circuits 122_1 to 122_3, and power supply circuits 123_1 to 123_3 are shown as element layers 20 on which the circuit section 120 is provided. Voltages supplied from power supply circuit 121_1, level shift circuit 122_1, and power supply circuit 123_1 are supplied to functional circuit 111. Voltages supplied from power supply circuit 121_2, level shift circuit 122_2, and power supply circuit 123_2 are supplied to functional circuit 112. Voltages supplied from power supply circuit 121_3, level shift circuit 122_3, and power supply circuit 123_3 are supplied to functional circuit 113. With this configuration, it is possible to supply different voltages to functional circuits 111 to 113.

[0144] Figure 18(A) is an example of a schematic cross-sectional view of a semiconductor device 100A applicable to the semiconductor device 100 described above. Figure 18(B) is a schematic perspective view of a part of the semiconductor device 100A shown in Figure 18(A). Figure 19 is a schematic perspective view showing the configuration of each layer provided in the element layers 10 and 20 in the semiconductor device 100A shown in Figure 18(A).

[0145] In Figures 18(A), 18(B), and 19, the semiconductor device 100A, as an example, has an element layer 20 below the element layer 10. The element layer 10 includes a substrate 51 on which a conductive layer 92 is provided. The semiconductor device 100A, as an example, also has an insulating layer 89 on the element layer 10, and a support substrate 90 on the insulating layer 89. The element layer 10 has a plurality of transistors 50 that constitute the circuit section 110 as described above. The element layer 20 has a plurality of transistors 60 that constitute the circuit section 120 as described above. The element layer 20 also has a plurality of conductive layers 41 for connecting the circuit section 110 and the circuit section 120.

[0146] At least some of the transistors 50 included in circuit section 110 are connected to at least some of the conductive layers 41 via the conductive layer 92. Similarly, at least some of the transistors 60 included in circuit section 120 are connected to at least some of the conductive layers 41. Therefore, at least some of the transistors 50 included in circuit section 110 can be connected to at least some of the transistors 60 included in circuit section 120 via the conductive layer 92 and at least some of the conductive layers 41.

[0147] In Figure 19, the circuit section 110 is illustrated by the functional circuits 111, 112, and 113 described in Figures 17(A) to 17(C). In addition, the circuit section 120 is illustrated by the power supply circuit 121, level shift circuit 122, and power supply circuit 123 described in Figures 1(A) and 1(B).

[0148] Figure 20 shows a block diagram illustrating an example configuration of semiconductor device 100A. Figure 20 shows an external power supply PW that supplies multiple potentials connected to power supply circuit 121, level shift circuit 122, and power supply circuit 123 via conductive layer 35[1]. Figure 20 also shows an external clock generation circuit CK that supplies multiple potentials connected to level shift circuit 122 and power supply circuit 123 via conductive layer 35[2].

[0149] The power supply circuit 121 is connected to the functional circuits 111, 112, and 113, respectively, via a conductive layer 41[1] that supplies voltage VDD2 and a conductive layer 41[2] that supplies reference potential GND.

[0150] The external power supply PW can be used as a power source to supply different voltages to the power supply circuit 121, the level shift circuit 122, and the power supply circuit 123. For example, the external power supply PW can supply the voltages VDD1, VDD4, and the reference potential GND as described above.

[0151] The external clock generation circuit CK can be used as a clock generation circuit to supply clock signals to the level shift circuit 122 and the power supply circuit 123. For example, the external clock generation circuit CK can supply the clock signals CLK1, CLK2, CLK3, and CLK4 described above.

[0152] The circuit section 120 is not limited to the power supply circuit 121, the level shift circuit 122, and the power supply circuit 123. The circuit section 120 may also include circuits with other functions. For example, the circuit section 120 may be provided with a clock signal generation circuit or the like.

[0153] The multiple conductive layers 41 (conductive layers 41[1], 41[2]) of the element layer 20 can, at least a portion thereof, function as power lines. By providing a conductive layer 41 that functions as a power line supplying a constant potential between circuit section 110 and circuit section 120, the propagation of noise caused by the electric field or magnetic field emitted by circuit section 120 to circuit section 110 can be reduced. Similarly, the propagation of noise emitted by circuit section 110 to circuit section 120 can be reduced. In other words, the conductive layer 41 can function as an electromagnetic shielding layer (also called a "shielding layer"). In this specification, "electromagnetic shielding layer" refers to a layer that has the function of inhibiting the propagation of at least one of an electric field and a magnetic field. By providing a conductive layer 41 between circuit section 110 and circuit section 120, the operation of the semiconductor device 100A can be stabilized and its reliability can be increased. It is also possible to provide a shielding layer other than the conductive layer 41 between circuit section 110 and circuit section 120.

[0154] Furthermore, by providing a conductive layer 41 between circuit section 110 and circuit section 120, the conductive layer 41 provides a heat dissipation effect that allows heat to escape from both circuit section 110 and circuit section 120. The heat dissipation effect of the conductive layer 41 stabilizes the operation of the semiconductor device 100A and improves its reliability.

[0155] The wiring width of the conductive layer 41 is preferably larger than the size of the transistors in the circuit section 110 when viewed from above. By making the wiring width of the conductive layer 41 larger than the size of the transistors in the circuit section 110 when viewed from above, the electromagnetic shielding effect (also called "shielding effect") can be enhanced. In addition, the heat dissipation effect of the conductive layer 41 can be enhanced.

[0156] Furthermore, as shown in the perspective schematic of Figure 21, it is preferable to provide the conductive layer 41 in a mesh pattern. By providing the conductive layer 41 in a mesh pattern, the in-plane uniformity of the power supply voltage can be further improved. In addition, the power supply capacity of the circuit section 120 can be increased. Furthermore, the shielding effect of the conductive layer 41 can be further enhanced. In addition, the heat dissipation effect of the conductive layer 41 can be further enhanced. As a result, the operation of the semiconductor device 100A can be stabilized and its reliability can be increased.

[0157] Figure 22(A) shows a block diagram illustrating an example configuration of semiconductor device 100B, which is a modified version of semiconductor device 100A. In this embodiment, to reduce repetition of explanations, we will mainly explain the differences between semiconductor device 100B and semiconductor device 100A. Unless otherwise specified, the example configuration of semiconductor device 100A can be interpreted as the example configuration of semiconductor device 100B. Therefore, for parts of semiconductor device 100B that are not explained, you can refer to the explanation of semiconductor device 100A.

[0158] One aspect of the present invention, the semiconductor device 100B, can be configured to include a transistor that functions as a power switch in the circuit portion 120 of the element layer 20. Figure 22(B) shows a state in which transistor PS1 is provided between the terminal that supplies the voltage VDD2 of the power supply circuit 121 and the conductive layer 41[1]. Figure 22(C) shows a state in which transistor PS2 is provided between the terminal that supplies the reference potential GND of the power supply circuit 121 and the conductive layer 41[2]. Figures 22(B) and 22(C) illustrate the control signals HSPG1 and HSPG2 supplied to the gates of transistors PS1 and PS2. Control signals HSPG1 and HSPG2 are control signals whose amplitude voltages have been increased by performing a level shift of the amplitude voltage of control signals SPG1 and SPG2 in the level shift circuit 122.

[0159] Figure 22(A) also illustrates a power gating control circuit PG that outputs control signals SPG1 and SPG2 (also called power gating control signals) that control the on or off state of transistors PS1 and PS2.

[0160] One of the sources or drains of transistor PS1 is connected to the power supply circuit 121. The other of the sources or drains of transistor PS1 is connected to the functional circuit 111 via the conductive layer 41[1]. One of the sources or drains of transistor PS2 is connected to the power supply circuit 121. The other of the sources or drains of transistor PS2 is connected to the functional circuit 112 via the conductive layer 41[2].

[0161] The control signals SPG1 and SPG2 are supplied to the level shift circuit 122. The level shift circuit 122 performs a level shift on the amplitude voltage of the control signals SPG1 and SPG2, and can supply the increased amplitude voltage of the control signals HSPG1 and HSPG2 to the gates of transistors PS1 and PS2. As a result, transistors PS1 and PS2 can operate with improved switching performance. Specifically, the amount of current flowing when the transistors are ON can be increased, or the amount of current flowing when they are OFF can be made extremely small.

[0162] By providing transistors PS1 and PS2, which function as power switches to control the supply or cessation of power, between the power supply circuit 121 and the circuit section 110, power gating can be achieved to reduce power consumption by stopping the power supply to the standby functional circuit. Power gating can reduce the power consumption of the semiconductor device 100B.

[0163] OS transistors have a high dielectric strength between their source and drain, making them suitable for use as power switches. Therefore, it is preferable to use OS transistors for transistors PS1 and PS2. Furthermore, because OS transistors have extremely low off-currents, they exhibit low leakage current even when power supply and clock signal supply are stopped, making them suitable for power saving.

[0164] The transistors PS1 and PS2 used as power switches require high on-current and low off-current. Therefore, it is preferable to use an oxide semiconductor containing a large amount of indium as the semiconductor layer of these transistors. In particular, it is preferable to use indium oxide (also called "indium oxide").

[0165] Furthermore, the transistor PS1 in the element layer 20 shown in Figure 22(A) can also be formed using the Si transistor transistor 50 in the circuit section 110. In this case, since the transistor PS1 can be a p-channel Si transistor, it is suitable as a power switch for the high power supply voltage VDD2.

[0166] Furthermore, the transistor PS2 in the element layer 20 shown in Figure 22(A) can also be formed using the Si transistor transistor 50 in the circuit section 110. In this case, the transistor PS2 is an n-channel Si transistor. Compared to OS transistors, Si transistors have superior current capability, making it possible to supply a sufficiently large amount of current from the power supply circuit 121.

[0167] Figure 23 shows circuit configurations in which the circuit configuration of the level shift circuit 122 in Figure 22(A) is applied to the circuit 122A in Figure 5(A), and the circuit configuration of the power supply circuit 121 in Figure 22 is applied to the circuit 121A in Figure 4(A). In Figure 23, as with Figures 8 and 12, level shift circuit 122_1 and level shift circuit 122_2 are shown as level shift circuit 122.

[0168] Level shift circuits 122_1 and 122_2 are supplied with control signals SPG1 and SPG2. Level shift circuits 122_1 and 122_2 perform a level shift of the amplitude voltage of the control signals SPG1 and SPG2, and can supply the increased amplitude voltage of the control signals HSPG1 and HSPG2 to the gates of transistors PS1 and PS2.

[0169] The power supply circuit 121, level shift circuits 122_1 and 122_2, and transistors PS1 and PS2 shown in Figure 23 can each be constructed using OS transistors and connected via wiring with a conductive layer. Therefore, the circuit functions can be realized in accordance with the transmission and reception of signals.

[0170] Furthermore, Figure 24(A) shows a block diagram illustrating an example configuration of semiconductor device 100C, which is a modified version of semiconductor device 100A, and Figure 24(B) shows a block diagram illustrating an example configuration of semiconductor device 100D, which is also a modified version of semiconductor device 100A. Figure 25(A) shows a schematic perspective view of semiconductor device 100C, and Figure 25(B) shows a schematic perspective view of semiconductor device 100D. In this embodiment, to reduce repetition of explanations, we will mainly explain the differences between semiconductor device 100C and semiconductor device 100D and semiconductor device 100A. Unless otherwise specified, the configuration examples of semiconductor device 100A can be interpreted as the configuration examples of semiconductor device 100C and semiconductor device 100D, respectively. Also, semiconductor device 100C and semiconductor device 100D are also modified versions of semiconductor device 100B. Therefore, for parts of semiconductor device 100C and semiconductor device 100D that are not explained, you can refer to the explanations of semiconductor device 100A and semiconductor device 100B.

[0171] As shown in Figures 24(A) and 25(A), the semiconductor device 100C can have an element layer 30 superimposed below the element layer 20. The semiconductor device 100C shows an example in which the element layer 10 and the element layer 30 are superimposed via the element layer 20. The element layer 30 has a plurality of transistors 70 that constitute the circuit section 130 (also called the third circuit section).

[0172] Furthermore, the element layer 30, which is superimposed on the element layer 20, is preferably formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 70 included in the element layer 30 is preferably a thin-film transistor. It is possible to use a transistor similar to the transistor 60 as the transistor 70.

[0173] At least some of the multiple transistors 70 included in the circuit section 130 are connected to at least some of the multiple conductive layers 41. Figure 24(A) shows an example configuration in which the circuit section 130 has memory 131 and memory 132. In Figure 24(A), an example is shown in which memory 131 is connected to the power supply circuit 121 via the conductive layer 41[1]. An example is also shown in which memory 132 is connected to an external power supply PW without going through the conductive layer 41.

[0174] As memory 131 and memory 132, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash memory, ferroelectric memory (FeRAM), magnetoresistive Random Access Memory (MRAM), phase-change memory (PCM), resistive random access memory (ReRAM), etc. can be used.

[0175] The circuits in the circuit unit 130 are not limited to memory 131 and memory 132. The circuit unit 130 may also include circuits with functions other than memory. For example, the circuit unit 130 may include a CPU, GPU, FPGA, digital circuits, analog circuits, etc. The circuit unit 130 may include one or more of these.

[0176] Similar to the integration of element layers 10 and 20 described above, it is possible to fabricate element layers 20 and 30 separately and mechanically bond them together using three-dimensional integration technology. On the other hand, it is preferable to form the element layer 30 to be superimposed on element layer 20 using thin-film formation technology, photolithography technology, etc. By forming the element layer 30 using thin-film formation technology, photolithography technology, etc., high-precision alignment at the photolithography level can be achieved. Furthermore, when forming element layer 20 using thin-film formation technology, photolithography technology, etc., element layer 30 can be formed immediately after element layer 20. Therefore, the productivity of semiconductor devices can be increased.

[0177] By providing an element layer 20 containing a power supply circuit between element layer 10 and element layer 30, the length of the wiring connecting circuit section 110 and circuit section 120, and the length of the wiring connecting circuit section 130 and circuit section 120 can both be shortened. As a result, IR drop (voltage drop due to the product of current and resistance) is reduced, and power supply to both circuit section 110 and circuit section 130 becomes stable. In addition, the power consumption of semiconductor device 100C is reduced.

[0178] Furthermore, the shielding and heat dissipation effects of the conductive layer 41 reduce the propagation of noise and heat emitted from both the circuit section 110 and the circuit section 130. As a result, the operation of the semiconductor device 100C becomes more stable and its reliability is improved.

[0179] Furthermore, the element layer 20, which includes the power supply circuit, handles the power supply, specifically performing power conversion and power control. Therefore, materials with high insulation, high heat dissipation, and high heat resistance are required around the element layer 20. Accordingly, it is preferable to use a material with high thermal conductivity near the element layer 20. Typical materials with high thermal conductivity include diamond-like carbon (DLC), aluminum nitride (AlNx, where x is any number), and silicon nitride (SiNx, where x is any number).

[0180] As shown in Figures 24(B) and 25(B), the semiconductor device 100D can also be configured by stacking n layers of element layers 30 (where n is an integer of 2 or more). In Figure 24(B), the first element layer 30 is shown as element layer 30[1], and the nth element layer 30 is shown as element layer 30[n]. The circuit section 130, memory 131, and memory 132 included in element layer 30[1] are shown as circuit section 130[1], memory 131[1], and memory 132[1], respectively. The circuit section 130, memory 131, and memory 132 included in element layer 30[n] are shown as circuit section 130[n], memory 131[n], and memory 132[n], respectively.

[0181] Furthermore, Figure 24(B) shows an example in which memory 131 (memory 131[1] to memory 131[n]) and memory 132 (memory 132[1] to memory 132[n]) are connected to the conductive layer 41, but it is also possible to configure them to be connected to other power supply circuits or conductive layers.

[0182] By stacking multiple element layers 30, it becomes possible to increase the functionality of the semiconductor device 100D without increasing its occupied area. For example, by stacking multiple element layers 30 that include memory, it becomes possible to increase the storage capacity without increasing the occupied area of ​​the semiconductor device 100D.

[0183] <Example of Manufacturing Method> Next, an example of a manufacturing method for the semiconductor device 100A will be described. First, an element layer 10 on which transistors 50 are formed is prepared on the surface of a substrate 51 (see Figure 26(A)).

[0184] In this embodiment, a single-crystal semiconductor substrate is used as the substrate 51. The transistor 50 has a semiconductor region 51c formed on a part of the substrate 51. Typically, single-crystal silicon can be used as the substrate 51. In addition, semiconductors made of elemental elements such as germanium, compound semiconductors made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride can be used. Furthermore, a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, can also be used. Alternatively, a substrate in which a thin semiconductor film is provided on an insulating substrate such as a glass substrate, quartz substrate, sapphire substrate, YSZ substrate, or resin substrate can be used.

[0185] The transistor 50 includes a conductive layer 53 that functions as a gate, an insulating layer 52 that functions as a gate insulating layer, a semiconductor region 51c that is part of the substrate 51, and a pair of low-resistance regions 54 that function as a source region or drain region. The transistor 50 can be a p-type transistor or an n-type transistor. In addition, an element isolation layer 81 is provided between two adjacent transistors 50.

[0186] The transistor 50 has a convex (fin-shaped) semiconductor region 51c in which the channel is formed. Although not shown in Figure 26(A), in the depth direction, the conductive layer 53 covers the side and top surfaces of the semiconductor region 51c via an insulating layer 52. Such a transistor 50 is also called a FIN-type transistor.

[0187] Furthermore, an insulating layer 82 is formed on the element isolation layer 81, and an insulating layer 83a is formed on the insulating layer 82. Next, a plurality of plugs 61a are formed that penetrate the insulating layer 83a and the insulating layer 82. Next, an insulating layer 83b and a plurality of conductive layers 71a are formed on the insulating layer 83a. The plurality of conductive layers 71a are formed to be embedded in the insulating layer 83b. At least one of the plurality of conductive layers 71a is connected to the low-resistance region 54 via a plug 61a.

[0188] An insulating layer 83c is formed on the conductive layer 71a and the insulating layer 83b. Next, a plurality of plugs 61b are formed that penetrate the insulating layer 83c. At least one of the plurality of plugs 61b is connected to one of the plurality of conductive layers 71a. Next, an insulating layer 83d and a plurality of conductive layers 71b are formed on the insulating layer 83c. The plurality of conductive layers 71b are formed to be embedded in the insulating layer 83b. At least one of the plurality of conductive layers 71b is connected to one of the plugs 61b.

[0189] An insulating layer 83e is formed on the conductive layer 71b and the insulating layer 83d. Next, a plurality of plugs 61c are formed that penetrate the insulating layer 83e. At least one of the plurality of plugs 61c is connected to one of the plurality of conductive layers 71b. Next, an insulating layer 83f and a plurality of conductive layers 71c are formed on the insulating layer 83e. The plurality of conductive layers 71c are formed to be embedded in the insulating layer 83f. At least one of the plurality of conductive layers 71c is connected to one of the plugs 61c.

[0190] An insulating layer 83g is formed on the conductive layer 71c and the insulating layer 83f. Next, a plurality of plugs 61d are formed that penetrate the insulating layer 83g. At least one of the plurality of plugs 61d is connected to one of the plurality of conductive layers 71c. Next, an insulating layer 83h and a plurality of conductive layers 71d are formed on the insulating layer 83g. The plurality of conductive layers 71d are formed to be embedded in the insulating layer 83h. At least one of the plurality of conductive layers 71d is connected to one of the plugs 61d. Next, an insulating layer 85 is formed on the insulating layer 83h and the conductive layer 71d.

[0191] Plugs 61a to 61d can be made of a conductive material. The insulating layers 83a to 83h, conductive layers 71a to 71d, and plugs 61a to 61d can be partially omitted as needed. It is also possible to provide other insulating layers, conductive layers, or plugs.

[0192] Next, the support substrate 90 on which the insulating layer 89 is formed is joined to the element layer 10 (see Figure 26(B)). The support substrate 90 and the element layer 10 are joined by placing the support substrate 90 on top of the element layer 20 so that the insulating layer 89 and the insulating layer 85 face each other. The same material as the substrate 51 can be used for the support substrate 90. For example, the support substrate 90 can be a semiconductor substrate made of a semiconductor material such as silicon, a glass substrate, a resin substrate, etc. It is preferable to use a glass substrate as the support substrate 90. Glass substrates are cheaper than semiconductor substrates and have better high-temperature resistance than resin substrates. Therefore, the productivity of the semiconductor device according to one aspect of the present invention can be increased. It is preferable that the insulating layer 89 is made of a material with the same composition as the insulating layer 85. By making the insulating layer 89 and the insulating layer 85 from materials with the same composition, the joining of the support substrate 90 and the element layer 10 becomes easier.

[0193] Typically, silicon oxide can be used as the insulating layer 89 and insulating layer 85. Alternatively, insulating materials such as silicon oxynitride, silicon oxide nitride, silicon nitride, aluminum oxide, and hafnium oxide can be used. The insulating layer 89 can be formed by the same film deposition method as the insulating layer 85, such as sputtering or CVD. Furthermore, to improve flatness, the upper surfaces of the insulating layer 89 and insulating layer 85 can be planarized by CMP (Chemical Mechanical Polishing) or etching.

[0194] After stacking the support substrate 90 on the element layer 10, pressing one point on the support substrate 90 or the element layer 10 allows van der Waals bonds, hydrogen bonds, etc., to spread from that point to the entire bonding surface. If one or both of the bonding surfaces have a hydrophilic surface, hydroxyl groups, water molecules, etc., act as adhesives, and subsequent heat treatment causes the water molecules to diffuse, leaving residual components to form silanol groups (Si-OH) and form a bond through hydrogen bonding. Furthermore, as hydrogen is removed from this bonding area, siloxane bonds (O-Si-O) are formed, becoming a covalent bond and resulting in an even stronger bond.

[0195] Next, the element layer 10 to which the support substrate 90 is bonded is inverted (see Figure 27(A)). After inverting, the back surface of the substrate 51 is subjected to CMP treatment or etching treatment to thin the substrate 51 to the extent that the low-resistance region 54 is not exposed (see Figure 27(B)).

[0196] Next, an insulating layer 91 is provided on the back side of the substrate 51 (see Figure 28(A)). Subsequently, in the region overlapping with one of the pair of low-resistance regions 54 of the transistor 50, an opening 93 is formed by removing the insulating layer 91 and a part of the substrate to reach one of the low-resistance regions 54 (see Figure 28(B)).

[0197] Next, a conductive layer 92 is provided on the insulating layer 91 and the opening 93 (see Figure 28(C)). The conductive layer 92 is also formed inside the opening 93 and has a region that is in contact with one of the low-resistance regions 54.

[0198] Next, the conductive layer 92 is subjected to CMP treatment or etching treatment to expose the insulating layer 91 (see Figure 29(A)). At this time, a portion of the insulating layer 91 may also be removed, making the insulating layer 91 thinner. The conductive layer 92 formed inside the opening 93 remains inside the opening 93 and functions as a contact plug. In this way, the element layer 10 can be formed.

[0199] Next, an element layer 20, which includes circuit elements such as a transistor 60, is formed on the back side of the substrate 51 on which the element layer 10 is located (see Figure 29(B)). The element layer 20 has an insulating layer 25, an insulating layer 31, an insulating layer 32, insulating layers 33a to 33h, plugs 34a to 34f, conductive layers 35a to 35e, a conductive layer 41, an insulating layer 42, and an insulating layer 43.

[0200] The transistor 60 has a semiconductor layer 21, an insulating layer 22 that functions as a gate insulating layer, a conductive layer 23 that functions as a gate, and a pair of conductive layers 24 that function as a source or drain.

[0201] Multiple conductive layers 41 are formed on the insulating layer 91. At least one of the multiple conductive layers 41 has a region in contact with the conductive layer 92. Next, an insulating layer 42 is formed on the conductive layer 41. After forming the insulating layer 42, it is preferable to perform CMP treatment or etching treatment to improve the flatness of the insulating layer 42 surface. By improving the flatness of the insulating layer 42 surface, the coverage of the insulating layer, conductive layer, etc. formed in subsequent steps can be improved.

[0202] Next, a plurality of plugs 34a are formed that penetrate the insulating layer 42. At least one of the plurality of plugs 34a is connected to one of the plurality of conductive layers 41. Next, an insulating layer 43 and a plurality of conductive layers 35a are formed on the insulating layer 42. The plurality of conductive layers 35a are formed to be embedded in the insulating layer 43. At least one of the plurality of conductive layers 35a is connected to one of the plugs 34a. Next, an insulating layer 31 is formed on the insulating layer 43 and the conductive layers 35a, and an insulating layer 25 is formed on top of the insulating layer 31.

[0203] As the insulating layer 25, insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and hafnium aluminate can be used as a single layer or in a laminated form. The insulating layer 25 can be formed using film deposition methods such as sputtering, CVD, or ALD.

[0204] Next, a semiconductor layer 21 is formed on the insulating layer 25. It is preferable to use an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer 21. In particular, it is preferable to use an oxide mainly composed of indium, tin, or zinc. Among these, indium oxide is preferred because it combines high mobility and high reliability. The semiconductor layer 21 can be formed by methods such as atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), or wet methods.

[0205] Furthermore, the oxide semiconductor used as the semiconductor layer 21 is preferably indium oxide with a polycrystalline or single-crystal structure. In particular, using indium oxide with a single-crystal structure can suppress carrier scattering at grain boundaries, enabling the realization of a transistor with high field-effect mobility. It also enables the realization of a highly reliable transistor.

[0206] When using indium oxide with a polycrystalline structure, it is preferable that no grain boundaries are observed, at least in the channel-forming region. This allows indium oxide with a polycrystalline structure to achieve the same effects as indium oxide with a single-crystal structure.

[0207] It is preferable to deposit the semiconductor layer 21 while the surface to be formed is heated. That is, it is preferable to deposit the insulating layer 25 while it is heated. This makes it possible to obtain a single crystal film with few defects. Furthermore, it is preferable to heat the surface to be formed to 100°C or higher in order to reduce moisture content. Higher heating temperatures are preferable because they allow for cleaner surface and reduction of lattice defects. On the other hand, if the heating temperature is too high, oxygen in the insulating layer 25 is more likely to be desorbed. Also, if the heating temperature is too high, the constituent elements of the deposited film are more likely to be desorbed, increasing the possibility that a film with the desired composition cannot be obtained. For this reason, the processing temperature during the deposition of the semiconductor layer 21 is preferably between 100°C and 600°C.

[0208] As mentioned above, it is particularly preferable to use indium oxide as the semiconductor layer 21. The higher the ratio of indium atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Furthermore, by using indium oxide having a polycrystalline or single-crystal structure in the channel formation region of the transistor, an extremely reliable transistor can be realized. The band gap of indium oxide is 2.5 eV to 3.7 eV. By using indium oxide with a large band gap in the channel formation region of the transistor, the off-current of the transistor can be reduced, and the power consumption of the semiconductor device can be significantly reduced.

[0209] Next, a conductive layer 24 is formed on the semiconductor layer 21. For the conductive layer 24, for example, a conductive material that does not easily diffuse oxygen, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, can be used. This prevents the conductive layer 24 from being oxidized by oxygen contained in the semiconductor layer 21, etc., and prevents a decrease in conductivity. The conductive layer 24 can be formed by sputtering, ALD, CVD, etc.

[0210] For example, a conductive film to form a conductive layer 24 can be deposited on top of a semiconductor film to form a semiconductor layer 21, a resist mask can be formed on the conductive film to form the conductive layer 24 by photolithography, and unnecessary portions of the conductive film to form the conductive layer 24 and the semiconductor film to form the semiconductor layer 21 can be removed by etching to form island-shaped conductive layers 24 and semiconductor layers 21. The resist mask is then removed. Dry etching or wet etching can be used for etching, but dry etching is preferred because it allows for easy fine processing.

[0211] Next, an insulating layer 32 having a region covering the semiconductor layer 21 and the conductive layer 24 is formed, and an insulating layer 33a is formed on the insulating layer 32. The insulating layer 32 and the insulating layer 33a can be formed by sputtering, ALD, CVD, or the like.

[0212] The insulating layer 32 functions as a barrier layer. Preferably, the insulating layer 32 is made of insulating material such as silicon nitride, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Because these materials have barrier properties against oxygen, hydrogen, and water, they can prevent these impurities from diffusing into the semiconductor layer 21.

[0213] The insulating layer 33a functions as an interlayer insulating film. It is preferable to use an insulating material such as silicon oxide, silicon oxynitride, or silicon oxide nitride as the insulating layer 33a. By using a material with a low dielectric constant as the interlayer insulating film, parasitic capacitance can be reduced.

[0214] Next, the insulating layer 33a, the insulating layer 32, and a portion of the conductive layer 24 are removed to form a groove reaching the semiconductor layer 21. At this time, the conductive layer 24 is divided into two parts at the groove. Subsequently, an insulating film that will become the insulating layer 22 is formed along the groove, and then a conductive film that will become the conductive layer 23 is formed on the insulating layer 22 so as to fill the groove. Subsequently, a planarization process is performed by the CMP method until the insulating layer 33a is exposed, thereby forming the insulating layer 22 and the conductive layer 23 within the groove. The insulating layer 22 functions as a gate insulating layer, and the conductive layer 23 functions as a gate electrode. The pair of conductive layers 24 divided on the semiconductor layer 21 function as a source electrode and a drain electrode, respectively. In this way, a transistor 60 can be fabricated.

[0215] As the insulating layer 22, insulating materials such as silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and hafnium aluminate can be used as a single layer or in a laminated form. The insulating layer 22 can be formed using film deposition methods such as sputtering, CVD, and ALD, but the ALD method, which has high step coverage, is preferable from the viewpoint of pressure resistance because it can be formed with a uniform thickness even inside the grooves.

[0216] It is preferable to use a low-resistance conductive material such as tungsten, molybdenum, copper, or aluminum for the conductive layer 23. It is also preferable to have a laminated structure for the conductive layer 23 and to provide a film of an oxygen-resistant conductive material that can be used for the conductive layer 24 on the side in contact with the insulating layer 22. This prevents the conductive layer 23 from oxidizing due to oxygen diffusing from the insulating layer 22 and other components, thereby preventing a decrease in conductivity.

[0217] Subsequently, an insulating layer 33b is formed on the transistor 60. Next, a plurality of plugs 34b that penetrate the insulating layer 33b, insulating layer 33a, insulating layer 32, insulating layer 25 and insulating layer 31, and a plurality of plugs 34c that penetrate the insulating layer 33b, insulating layer 33a and insulating layer 32 are formed. At least one of the plurality of plugs 34b is connected to one of the plurality of conductive layers 35a. At least one of the plurality of plugs 34c is connected to one of the plurality of conductive layers 24.

[0218] Next, an insulating layer 33c and a plurality of conductive layers 35b are formed on the insulating layer 33b. The plurality of conductive layers 35b are formed so as to be embedded in the insulating layer 33c. At least one of the plurality of conductive layers 35b is connected to one or both of the plug 34b or plug 34c.

[0219] Next, an insulating layer 33d is formed on the conductive layer 35b and the insulating layer 33c. Next, a plurality of plugs 34d are formed that penetrate the insulating layer 33d. At least one of the plurality of plugs 34d is connected to one of the plurality of conductive layers 35b. Next, an insulating layer 33e and a plurality of conductive layers 35c are formed on the insulating layer 33d. The plurality of conductive layers 35c are formed to be embedded in the insulating layer 33e. At least one of the plurality of conductive layers 35c is connected to one of the plugs 34d.

[0220] Next, an insulating layer 33f is formed on the conductive layer 35c and the insulating layer 33e. Next, a plurality of plugs 34e are formed that penetrate the insulating layer 33f. At least one of the plurality of plugs 34e is connected to one of the plurality of conductive layers 35c. Next, an insulating layer 33g and a plurality of conductive layers 35d are formed on the insulating layer 33f. The plurality of conductive layers 35d are formed to be embedded in the insulating layer 33g. At least one of the plurality of conductive layers 35d is connected to one of the plugs 34e.

[0221] Next, an insulating layer 33h is formed on the conductive layer 35d and the insulating layer 33g. Next, a plurality of plugs 34f are formed that penetrate the insulating layer 33h. At least one of the plurality of plugs 34f is connected to one of the plurality of conductive layers 35d. Next, a plurality of conductive layers 35e are formed on the insulating layer 33h. At least one of the plurality of conductive layers 35e is connected to one of the plugs 34f. In this way, a semiconductor device according to one aspect of the present invention can be manufactured. Figure 29(B) is a schematic cross-sectional view of the completed semiconductor device 100A before it is returned to its original orientation.

[0222] Furthermore, it is also possible to construct a circuit by combining the transistor 50 formed on the element layer 10 and the transistor 60 formed on the element layer 20. For example, it is possible to form a CMOS type circuit by using a p-type transistor 50 and an n-type transistor 60 and combining them.

[0223] Furthermore, as shown in Figure 30, an element layer 40 containing circuit elements can be provided between the element layer 10 and the support substrate 90, as in the semiconductor device 100E. Note that since the semiconductor device 100E is a modified example of the semiconductor device 100A, the differences between the semiconductor device 100E and the semiconductor device 100A will be explained in detail.

[0224] Figures 31 and 32 are a perspective schematic and a block diagram illustrating the configuration of the semiconductor device 100E. The element layer 40 has a plurality of transistors 80 that constitute the circuit section 140. At least some of the plurality of transistors 80 included in the circuit section 140 are connected to at least some of the plurality of conductive layers 41. In addition, at least some of the plurality of transistors 80 included in the circuit section 140 are connected to at least some of the plurality of transistors 60 included in the circuit section 120 via at least some of the plurality of conductive layers 41.

[0225] In Figure 30, the circuit section 140 is illustrated with functional circuits 141, 142, and 143. The circuit section 140 is supplied with the power necessary for its operation from the circuit section 120. The circuit section 120 can also supply the optimal power supply voltage to each of the functional circuits 141, 142, and 143 of the circuit section 140. For example, the functional circuit 141 can be a logic operation circuit, the functional circuit 142 an analog-to-digital conversion circuit, and the functional circuit 143 a communication circuit.

[0226] Figure 31 shows a block diagram illustrating an example configuration of the semiconductor device 100E. Figure 31 shows an example in which the power supply circuit 121 is connected to the functional circuits 111 to 113 via conductive layers 41[1] and 41[2]. For other configurations related to Figure 31, please refer to the explanation in Figure 20 and other documents.

[0227] The circuit section 140 of the element layer 40 shown in Figures 30 and 31 can also be configured to include a part of the circuit section 110 of the element layer 10 by making the transistor 80 of the circuit section 140 an OS transistor. For example, the functional circuit 111 of the circuit section 110 can be provided in the circuit section 140.

[0228] The circuit section 140 of the element layer 40 shown in Figures 30 and 31 can also be configured to include a part of the circuit section 120 of the element layer 20 by making the transistor 80 of the circuit section 140 an OS transistor. For example, the power supply circuit 121 of the circuit section 120 can be provided in the circuit section 140.

[0229] Furthermore, the circuit section 140 of the element layer 40 shown in Figures 30 and 31 can also be configured such that the transistor 80 in the circuit section 140 is an OS transistor, and a part of the circuit section 110 of the element layer 10 and a part of the circuit section 120 of the element layer 20 are provided. For example, the power supply circuit 121 of the circuit section 120 and the functional circuit 111 of the circuit section 110 can be provided in the circuit section 140. Also, for example, the power supply circuit 121 and level shift circuit 122 of the circuit section 120 and the functional circuit 111 of the circuit section 110 can be provided in the circuit section 140.

[0230] Furthermore, the circuit section 140 of the element layer 40 shown in Figures 30 and 31 can also be configured to include the transistor PS1 of the element layer 20 shown in Figures 22(A) and 22(B) by making the transistor 80 of the circuit section 140 an OS transistor. Furthermore, the circuit section 140 of the element layer 40 shown in Figures 30 and 31 can also be configured to include the transistor PS2 of the element layer 20 shown in Figures 22(A) and 22(B) by making the transistor 80 of the circuit section 140 an OS transistor.

[0231] As described above, the configuration in which a part of the circuits of element layers 10 and 20 are provided on the element layer 40 on the first surface (front) side of the substrate 51 results in the arrangement of circuits with transistors on top of each other, thereby increasing the transistor density per unit area. Therefore, it becomes possible to miniaturize the semiconductor device without reducing its performance.

[0232] Figure 32 shows an example of the cross-sectional configuration of the semiconductor device 100E. For example, the element layer 40 can have the same configuration as the element layer 20. In the semiconductor device 100E illustrated in Figure 32, an example configuration is shown in which the element layer 40 is provided between the insulating layer 85 and the insulating layer 89.

[0233] The following describes the method for manufacturing the semiconductor device 100E illustrated in Figure 32. In the semiconductor device 100E illustrated in Figure 32, an insulating layer 26 is formed on the insulating layer 85. The insulating layer 26 can be formed using the same materials and methods as the insulating layer 25. Next, a semiconductor layer 27 is formed on the insulating layer 26. The semiconductor layer 27 can be formed using the same materials and methods as the semiconductor layer 21. Next, a conductive layer 28 is formed on the semiconductor layer 27. The conductive layer 28 can be formed using the same materials and methods as the conductive layer 24.

[0234] Next, an insulating layer 29 having a region covering the semiconductor layer 27 and the conductive layer 28 is formed, and an insulating layer 33i is formed on the insulating layer 29. The insulating layer 29 can be formed using the same materials and methods as the insulating layer 32. The insulating layer 33i can be formed using the same materials and methods as the insulating layer 33a.

[0235] Next, the insulating layer 33i, the insulating layer 29, and a portion of the conductive layer 28 are removed to form a groove that reaches the semiconductor layer 27. At this time, the conductive layer 28 is divided into two parts at the groove.

[0236] Subsequently, an insulating film that will become an insulating layer 72 is formed along the groove, and then a conductive film that will become a conductive layer 73 is formed on the insulating layer 72 so as to fill the groove. Next, a planarization process is performed by the CMP method until the insulating layer 33i is exposed, thereby forming the insulating layer 72 and the conductive layer 73 in the groove. The insulating layer 72 functions as a gate insulating layer, and the conductive layer 73 functions as a gate electrode. In addition, the pair of conductive layers 28 separated on the semiconductor layer 27 function as a source electrode and a drain electrode, respectively. In this way, a transistor 80 can be fabricated.

[0237] The insulating layer 72 can be formed using the same materials and methods as the insulating layer 22. The conductive layer 73 can be formed using the same materials and methods as the conductive layer 23.

[0238] Subsequently, an insulating layer 33j is formed on the transistor 80. Next, a plurality of plugs 34g that penetrate the insulating layer 33j, insulating layer 33i, insulating layer 29, insulating layer 26 and insulating layer 85, and a plurality of plugs 34h that penetrate the insulating layer 33j, insulating layer 33i and insulating layer 29 are formed. At least one of the plurality of plugs 34g is connected to one of the plurality of conductive layers 71d. At least one of the plurality of plugs 34h is connected to one of the plurality of conductive layers 28.

[0239] Next, an insulating layer 33k and a plurality of conductive layers 35f are formed on the insulating layer 33j. The plurality of conductive layers 35f are formed to be embedded in the insulating layer 33k. At least one of the plurality of conductive layers 35f is connected to one or both of the plug 34g or plug 34h.

[0240] Next, an insulating layer 33l is formed on the conductive layer 35f and the insulating layer 33k. Next, a plurality of plugs 34i are formed that penetrate the insulating layer 33l. At least one of the plurality of plugs 34i is connected to one of the plurality of conductive layers 35f. Next, an insulating layer 33m and a plurality of conductive layers 35g are formed on the insulating layer 33l. The plurality of conductive layers 35g are formed to be embedded in the insulating layer 33m. At least one of the plurality of conductive layers 35g is connected to one of the plugs 34i.

[0241] Next, an insulating layer 86 is formed on the insulating layer 33m and the conductive layer 35g. The insulating layer 86 can be formed using the same material and method as the insulating layer 85. Subsequently, the support substrate 90 on which the insulating layer 89 is formed is joined to the element layer 40. It is preferable that the insulating layer 86 be made of the same material composition as the insulating layer 89. By using the same material composition for the insulating layer 89 and the insulating layer 85, the joining of the support substrate 90 and the element layer 10 becomes easier.

[0242] Next, the element layer 40 and element layer 10 to which the support substrate 90 is bonded are inverted to form the element layer 20. In this way, a semiconductor device 100E according to one embodiment of the present invention can be manufactured. Figure 32 is a schematic cross-sectional view of the completed semiconductor device 100E with its orientation reversed. Figure 33(A) is a schematic perspective view corresponding to Figure 32.

[0243] By adding an element layer 40 on top of the element layer 10, the functionality of the semiconductor device can be increased without increasing the occupied area. Furthermore, as shown in Figure 33(B) for the semiconductor device 100F, it is also possible to add n layers of element layers 40. In Figure 33(B), the first element layer 40 is shown as element layer 40[1], and the nth element layer 40 is shown as element layer 40[n]. By adding multiple element layers 40 on top of the element layer 10, the functionality of the semiconductor device can be further increased without increasing the occupied area.

[0244] Furthermore, as shown in Figures 34(A) and 34(B), it is possible to form an element layer 40 having a circuit portion 140 on a support substrate 90 and bond the support substrate 90 to the element layer 10 via the circuit portion 140 using three-dimensional integration technology. Figure 34(A) shows a schematic cross-sectional view of the element layer 40 provided on the support substrate 90. The semiconductor device 100G is a modified example of the semiconductor device 100E. Therefore, the semiconductor device 100G is also a modified example of the semiconductor device 100A. To reduce repetition in the explanation, a detailed explanation of the element layer 40 is omitted here.

[0245] The element layer 40 shown in Figure 34(A) has an insulating layer 89 provided on top of an insulating layer 33m and a conductive layer 35g. A plug 34j is provided that penetrates the insulating layer 89 so as to be embedded in the insulating layer 89. The plug 34j is connected to the conductive layer 35g. By inverting the support substrate 90 on which the element layer 40 is formed and bonding it to the insulating layer 85 of the element layer 10, the semiconductor device 100G can be formed (see Figure 34(B)). In addition, the plug 34g and plug 34j are connected by this bonding.

[0246] Furthermore, it is possible to stack multiple element layers 40 on the support substrate 90. By providing a support substrate 90 having a circuit section 140 on top of the element layer 10, the functionality of the semiconductor device can be increased without increasing the occupied area. It is also possible to use a support substrate 90 having a circuit section 140 as the support substrate 90 for the semiconductor device 100 (semiconductor device 100A to semiconductor device 100G).

[0247] Furthermore, as shown in Figure 35, the semiconductor device 100H can be formed on an element layer 10 having an element layer 340 having light-emitting elements 361A and 361B.

[0248] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements and light-emitting elements can be replaced with display devices and light-emitting devices, respectively.

[0249] As light-emitting elements 361A and 361B, organic EL devices such as OLEDs or QOLEDs (Quantum-dot Organic Light Emitting Diodes) can be applied. Examples of light-emitting materials for EL elements include fluorescent materials and phosphorescent materials. Not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used as light-emitting materials for EL elements.

[0250] In this specification, examples using light-emitting elements as display elements are given, but other display elements can also be used. Examples include liquid crystal elements, light-emitting diodes, and electrophoretic elements.

[0251] The light-emitting elements 361A and 361B are provided on an insulating layer 362 on which a conductive layer 363 is provided. The conductive layer 363 functions as wiring connecting the transistor 50 of the element layer 10 and the light-emitting elements 361A and 361B of the element layer 340. The light-emitting elements 361A and 361B have a conductive layer 371 that functions as a pixel electrode and a conductive layer 373 that functions as a common electrode.

[0252] The light-emitting elements 361A and 361B have an EL layer 372A and 372B between a conductive layer 371 that functions as a pixel electrode and a conductive layer 373 that functions as a common electrode. The EL layers 372A and 372B contain a light-emitting organic compound that emits light having a peak in at least the red, green, or blue wavelength range. In addition to the layer containing the light-emitting substance (light-emitting layer), the EL layers 372A and 372B may also have one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0253] In this specification, we have provided examples of structures in which different light-emitting layers are created or painted on each light-emitting element. However, it is also possible to apply a structure that combines a light-emitting element capable of emitting white light with a colored layer (for example, a color filter).

[0254] A conductive layer 371, which functions as a pixel electrode, is provided for each light-emitting element 361A and 361B. A conductive layer 373, which functions as a common electrode, is provided as a continuous layer common to both light-emitting elements 361A and 361B. A conductive film that is transparent to visible light can be used for one of the conductive layers 371, which functions as a pixel electrode, or the conductive layer 373, which functions as a common electrode, and a conductive film that is reflective can be used for the other. For example, if the light-emitting elements 361A and 361B are of the top-emission type, the light 375A and 375B emitted from the light-emitting elements 361A and 361B is emitted towards the conductive layer 373.

[0255] An insulating layer 374 is provided to cover the ends of the conductive layer 371, which functions as a pixel electrode. The ends of the insulating layer 374 can be tapered or inversely tapered (inverse triangular). The insulating layer 374 is provided to prevent adjacent light-emitting elements 361A and 361B from unintentionally short-circuiting and emitting false light.

[0256] The EL layers 372A and 372B can be differentiated using methods such as vacuum deposition with a shadow mask like a metal mask. Alternatively, they can be differentiated using photolithography. By using photolithography, it is possible to realize a display device with high resolution that is difficult to achieve when using a metal mask.

[0257] The protective layer 376 can be, for example, a single-layer structure or a multi-layer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxide nitride films, silicon nitride films, silicon nitride films, aluminum oxide films, aluminum oxide nitride films, and hafnium oxide films.

[0258] The substrate 90A is preferably a translucent substrate or a layer made of a translucent material. For example, a glass substrate can be used as the substrate 90A.

[0259] [Insulating Layer] Unless otherwise specified, various inorganic insulators can be used for the insulating layer (insulating layer 22, insulating layer 25, insulating layer 26, insulating layer 29, insulating layer 31, insulating layer 32, insulating layer 33 (insulating layer 33a to insulating layer 33m), insulating layer 42, insulating layer 43, insulating layer 52, insulating layer 82, insulating layer 83 (insulating layer 83a to insulating layer 83h), insulating layer 85, insulating layer 86, insulating layer 89, insulating layer 91, insulating layer 362, insulating layer 374, etc.) in a semiconductor device according to one embodiment of the present invention. For example, oxide insulators, nitride insulators, oxidized nitride insulators and nitrided oxide insulators can be used.

[0260] Examples of oxide insulators include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitride insulators include silicon nitride and aluminum nitride. Examples of oxidative nitride insulators include silicon oxidative nitride, aluminum oxidative nitride, gallium oxidative nitride, yttrium oxidative nitride, and hafnium oxidative nitride. Examples of nitride oxide insulators include silicon nitride and aluminum nitride. Furthermore, organic insulators can also be used in the insulating layer of a semiconductor device according to one embodiment of the present invention.

[0261] In this specification, "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content. The content of each element can be measured using methods such as Rutherford backscattering (RBS).

[0262] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as increased leakage current. By using a high-k material for the insulating layer that functions as the gate insulating layer, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. It also becomes possible to thin the equivalent oxide film thickness (EOT) of the gate insulating layer. On the other hand, by using a material with a low relative permittivity for the insulating layer that functions as an interlayer insulating film (e.g., insulating layer 33, insulating layer 83, etc.), parasitic capacitance that occurs between conductive layers such as wiring can be reduced. Therefore, it is important to select the material according to the function of the insulating layer. It should be noted that materials with a low relative permittivity also have high dielectric strength.

[0263] Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0264] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Also, for example, silicon oxide with voids is another example. These silicon oxides may contain nitrogen.

[0265] [Conductive Layer] Unless otherwise specified, the conductive layers (conductive layer 23, conductive layer 24, conductive layer 28, plug 34 (plug 34a to plug 34j), conductive layer 35 (conductive layer 35a to conductive layer 35g), conductive layer 41 (conductive layer 41[1] to conductive layer 41[4]), conductive layer 53, plug 61 (plug 61a to plug 61d), conductive layer 71 (conductive layer 71a to conductive layer 71d), conductive layer 73, conductive layer 92, etc.) in a semiconductor device according to one aspect of the present invention may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal elements, or an alloy combining the aforementioned metal elements.

[0266] As alloys composed of the aforementioned metal elements, nitrides or oxides of the alloys can also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can be used. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0267] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, silicon-added indium tin oxide (also called ITSO), indium zinc oxide (also called IZO®), and indium zinc oxide containing tungsten oxide.

[0268] Furthermore, it is possible to use multiple conductive layers formed from the above materials in a laminated structure. For example, a laminated structure can be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure can be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, a laminated structure can be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0269] When an oxide semiconductor, a type of metal oxide, is used as the semiconductor layer 21, the conductive layer 24 is a conductive layer in contact with the semiconductor layer 21. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide (also called an "oxide conductive layer"), or a conductive material that has the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layer 24.

[0270] By using an oxide conductive layer as the conductive layer 24, conductivity can be maintained even if the conductive layer 24 absorbs oxygen. For example, even when an insulating layer containing oxygen that is desorbed by heating (also called "excess oxygen") is used as the insulating layer in contact with the conductive layer 24, the conductive layer 24 can maintain its conductivity, making it suitable. For example, ITO, ITSO, IZO (registered trademark), etc., can be used as the conductive layer 24.

[0271] [Semiconductor Layer] As the semiconductor layer, single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, etc., can be used individually or in combination. Using a single-crystal semiconductor or a crystalline semiconductor in the semiconductor layer where the channel is formed is preferable because it can suppress the degradation of transistor characteristics.

[0272] As semiconductor materials, for example, semiconductors composed of elemental elements such as silicon and germanium can be used. Alternatively, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can be used. As compound semiconductors, organic materials with semiconductor properties (also called "organic semiconductors"), metal nitrides with semiconductor properties (also called "nitride semiconductors"), or metal oxides with semiconductor properties (also called "oxide semiconductors") can be used. These semiconductor materials may contain impurities as dopants.

[0273] When silicon is used as a semiconductor layer, examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon.

[0274] It is also possible to use a two-dimensional material that functions as a semiconductor as the semiconductor layer of a transistor. Two-dimensional materials, also called layered materials, are a general term for a group of materials that have a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity as the semiconductor layer, it is possible to provide a transistor with a large on-current.

[0275] Examples of the above layer material include graphene, silicene, chalcogenide, etc. Chalcogenide is a compound containing a chalcogen (an element belonging to Group 16). Examples of chalcogenide also include transition metal chalcogenide, Group 13 chalcogenide, etc. Specifically, as the transition metal chalcogenide applicable to the semiconductor layer of the transistor, there are molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten telluride (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ), etc.

[0276] [Metal Oxide Layer] Transistor 60 preferably has an oxide semiconductor, which is a kind of metal oxide, on the semiconductor layer 21 including the channel formation region. That is, it is preferable to use an OS transistor as the transistror 60.

[0277] When oxygen deficiency (V Ｏ ) and impurities exist in the channel formation region in the metal oxide functioning as a semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. In addition, defects in which hydrogen enters the oxygen deficiency (hereinafter sometimes referred to as V Ｏ H) may be formed, and electrons serving as carriers may be generated. Therefore, when the channel formation region in the metal oxide contains oxygen deficiency, the OS transistor tends to have normally-on characteristics. Therefore, in the channel formation region in the metal oxide, it is preferable that oxygen deficiency and impurities are reduced as much as possible. In other words, it is preferable that the channel formation region in the metal oxide has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0278] On the other hand, the source and drain regions in the metal oxide that function as the semiconductor of the OS transistor have more oxygen vacancies than the channel formation region. Ｏ It is preferable that the region has a high concentration of H or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements, which increases the carrier concentration and lowers the resistance. In other words, it is preferable that the source region and drain region of an OS transistor are n-type regions with a higher carrier concentration and lower resistance compared to the channel formation region.

[0279] The band gap of the metal oxide that functions as a semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide that functions as a semiconductor and has a larger band gap than silicon in the semiconductor layer 21, the off-current of the transistor 60 can be reduced. Because the off-current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. In addition, because the frequency characteristics of the OS transistor are high, the semiconductor device can be operated at high speed.

[0280] The metal oxide that can be used in the semiconductor layer of an OS transistor preferably contains at least indium (In). Furthermore, it is preferable that the metal oxide contains at least one of indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is a metal or metalloid element with a high bond energy with oxygen, for example, a metal or metalloid element with a higher bond energy with oxygen than indium.

[0281] Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0282] For example, indium oxide (In oxide) can be used as a metal oxide for the semiconductor layer of an OS transistor. Other metal oxides include zinc oxide (Zn oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), and indium a Aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0283] Examples of crystal structures for metal oxides that function as semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0284] Furthermore, by increasing the ratio of zinc atoms to the sum of the atoms of other metal elements in a metal oxide that functions as a semiconductor, a highly crystalline metal oxide can be obtained, suppressing the diffusion of impurities within the metal oxide. Consequently, fluctuations in the electrical properties of the transistor can be suppressed, improving reliability.

[0285] Furthermore, by increasing the ratio of element M atoms to the sum of the atoms of metal elements among the main constituent elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0286] The field-effect mobility of a transistor can be increased by increasing the ratio of indium atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide. Typically, using single-crystal or polycrystalline indium oxide in the semiconductor layer can significantly increase the field-effect mobility of a transistor. Furthermore, transistors using single-crystal or polycrystalline indium oxide in the semiconductor layer can achieve good frequency characteristics.

[0287] By varying the composition of the semiconductor layer of a transistor according to the characteristics required for each of the multiple circuits constituting the semiconductor device, the performance of the semiconductor device can be efficiently improved. Furthermore, the reliability of the semiconductor device can be enhanced. For example, in a semiconductor device having circuit section 110 and circuit section 120, by using a Si transistor in circuit section 110 where operating speed is required, and an OS transistor in circuit section 120 where source-drain dielectric breakdown voltage is required, the performance of the semiconductor device can be efficiently improved. Furthermore, the reliability of the semiconductor device can be enhanced.

[0288] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0289] (Embodiment 2) This embodiment describes an example of a transistor configuration applicable to a semiconductor device according to one aspect of the present invention, and an example of a level shift circuit 122 to which the transistor is applied. In the following, mainly the parts that differ from Embodiment 1 will be described. Therefore, explanations of parts that overlap with Embodiment 1 may be omitted.

[0290] In this embodiment, we will describe a configuration in which, in addition to an OS transistor that functions as an n-channel transistor, an OS transistor that functions as a p-channel transistor is used as the transistor applied to the element layer 20 having the circuit section 120 described in Embodiment 1 above.

[0291] In an OS transistor that functions as a p-channel transistor, tellurium oxide, which contains tellurium and oxygen, is used in the semiconductor layer where the channel is formed. By having tellurium oxide, which is a metal oxide, in the semiconductor layer where the channel is formed, an OS transistor that functions as a p-channel transistor can be created.

[0292] Furthermore, the semiconductor layer in which the channel of a p-channel transistor is formed contains cuprous oxide (Cu) ２ O), copper aluminate (CuAlO) ２ ), copper gallium oxide (CuGaO ２It is also possible to use metal oxides such as stannous oxide (SnO). Furthermore, a mixture of tellurium oxide and tellurium can be used in the semiconductor layer where the channel of the OS transistor, which functions as a p-channel transistor, is formed.

[0293] In addition to the transistor having a metal oxide provided on the element layer 20 described in Embodiment 1 above, a transistor having a different metal oxide can be used to create a circuit configuration that combines n-channel transistors and p-channel transistors, a so-called CMOS circuit. This CMOS circuit, composed of OS transistors, can be applied to each circuit of the element layer 20. Therefore, according to one aspect of the present invention, an element layer 20 equipped with a circuit section 120 to which a CMOS circuit is applied can be formed on the back side of the substrate 51 using thin-film formation technology, photolithography technology, etc. Thus, the semiconductor device 100 according to one aspect of the present invention can be a semiconductor device having a monolithically stacked CMOS circuit.

[0294] Although this configuration increases the manufacturing process, it allows for more reliable blocking of the current flow path using a CMOS circuit, thereby reducing the leakage current flowing between power lines. Furthermore, it eliminates the need for the configuration described in Embodiment 1, where a negative potential is applied to the back gate to reduce leakage current, which is preferable.

[0295] Figures 36(A) and 36(B) show examples of circuit configurations for OS transistor CMOS circuits applicable to the level shift circuit 122 of the element layer 20 described in Embodiment 1. The OS transistor CMOS circuit is applicable to circuit configurations such as the Cross Couled Level Shifter (CCLS) shown in Figures 36(A) and 36(B).

[0296] The circuit 122E shown in Figure 36(A) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122E is a level shift circuit supplied with the power supply voltage VDD3-GND. By supplying the clock signal CLK1 to terminal CL of circuit 122E and the clock signal CLK2 to terminal CLB of circuit 122E, a clock signal HCLK1 with a higher amplitude voltage than the clock signal CLK1 can be output from terminal OUT of circuit 122E, and a clock signal HCLK2 with a higher amplitude voltage than the clock signal CLK2 can be output from terminal OUTB of circuit 122E.

[0297] As shown in Figure 36(A), circuit 122E has transistors M25, M26, M27, and M28. Transistors M25 and M26 are p-channel OS transistors, and transistors M27 and M28 are n-channel OS transistors.

[0298] For example, during the period when clock signal CLK1 is at a high level (high potential level) and clock signal CLK2 is at a low level (low potential level), transistor M27 is ON and transistor M28 is OFF. Also, transistor M26 turns ON as the potential of its gate decreases, and the potential of terminal OUT rises to the potential based on voltage VDD3. Transistor M25 turns OFF as the potential of the gate of transistor M25, which is connected to terminal OUT, rises. Therefore, a clock signal HCLK1 with a higher amplitude voltage than clock signal CLK1 can be output from terminal OUT of circuit 122E. Similarly, a clock signal HCLK2 with a higher amplitude voltage than clock signal CLK2 can be output from terminal OUTB of circuit 122E.

[0299] The circuit 122F shown in Figure 36(B) is an example of a circuit configuration applicable to the level shift circuit 122. Circuit 122F is a level shift circuit supplied with the power supply voltage VDD3-GND, similar to circuit 122E.

[0300] As shown in Figure 36(B), circuit 122F has transistors M25, M26, M27, M28, M29, and M30. Transistors M25, M26, M29, and M30 are p-channel OS transistors, while transistors M27 and M28 are n-channel OS transistors.

[0301] Figure 36(B) represents a circuit configuration in which transistors M29 and M30 have been added compared to Figure 36(A). The presence of transistors M29 and M30 allows for the alternating on and off states of transistors M27 and M29, and the alternating on and off states of transistors M28 and M30. Therefore, it becomes possible to keep at least one transistor in the off state between power lines, thereby more reliably suppressing leakage current flowing between power lines.

[0302] The circuit configuration using the OS transistor CMOS circuit as in this embodiment can also be applied to inverter circuits. The circuit 122E shown in Figure 37(A) illustrates a configuration in which the inverter circuit INV is located between terminals CL and CLB of the circuit 122E described in Figure 36(A). With this configuration, the supply of the clock signal CLK2, which is the inverted signal of the clock signal CLK1, can be eliminated, and thus the number of terminals in the circuit 122E can be reduced.

[0303] The inverter circuit INV uses the CMOS circuit of the OS transistor described above, as shown in Figure 37(B). Specifically, it has a configuration with an n-channel transistor MN1 and a p-channel transistor MP1. As a result, the number of clock signals supplied to the level shift circuit 122 can be reduced, and the wiring supplying the clock signals can be reduced.

[0304] The circuit configuration with the inverter circuit INV shown in Figure 37(A) is also applicable to the circuit 122F in Figure 36(B). Figure 37(C) shows an example of the configuration of the circuit 122F with the inverter circuit INV. With this configuration, the supply of the clock signal CLK2, which is the inverted signal of the clock signal CLK1, can be eliminated, and thus the number of terminals in the circuit 122F can be reduced.

[0305] Furthermore, the level shift circuit using the OS transistor CMOS circuit configuration of this embodiment can also be applied to a level shift circuit supplied with the power supply voltage VDD-VSS2. Voltage VSS2 is a voltage obtained by stepping down voltage VSS1, which is lower than the reference potential GND, to voltage VSS2, as explained in Figure 10 of Embodiment 1 above.

[0306] The circuit 122G shown in Figure 38(A) is an example of a level shift circuit to which the power supply voltage VDD-VSS2 is supplied in the configuration shown in Figure 36(A). Similarly, the circuit 122H shown in Figure 38(B) is an example of a level shift circuit to which the power supply voltage VDD-VSS2 is supplied in the configuration shown in Figure 36(B).

[0307] The circuit configuration with the inverter circuit INV shown in Figure 37(A) is also applicable to the circuit 122G in Figure 38(A). Figure 39(A) shows an example of the configuration of the circuit 122G with the inverter circuit INV. With this configuration, the supply of the clock signal CLK2, which is the inverted signal of the clock signal CLK1, can be eliminated, and thus the number of terminals in the circuit 122G can be reduced.

[0308] The circuit configuration with the inverter circuit INV shown in Figure 37(A) is also applicable to the circuit 122H in Figure 38(B). Figure 39(B) shows an example of the configuration of the circuit 122H with the inverter circuit INV. With this configuration, the supply of the clock signal CLK2, which is the inverted signal of the clock signal CLK1, can be eliminated, and thus the number of terminals in the circuit 122H can be reduced.

[0309] Figure 40 is a block diagram showing the application of the level shift circuit, to which the power supply voltage VDD-VSS2 shown in Figures 38(A) and 38(B), is supplied, to the level shift circuit 122 of the element layer 20. As shown in Figure 40, the level shift circuit 122 is configured to receive the voltage VSS2 from the power supply circuit 124.

[0310] Furthermore, the level shift circuit 122 in Figure 40 is shown to be configured in which voltage VDD3 is supplied in addition to voltage VSS2. Using both voltage VDD3 and voltage VSS2 is preferable because it allows for the output of a clock signal HCLK1 with a higher amplitude voltage.

[0311] Figure 41(A) shows an example of a level shift circuit having a circuit 122E to which the power supply voltage VDD3-GND is supplied, and a circuit 122G to which the power supply voltage VDD3-VSS2 is supplied. In the configuration of Figure 41(A), the voltage on the high-potential side of the clock signal CLK1 is boosted in circuit 122E. Then, in circuit 122G, the voltage on the low-potential side can be lowered using the signal whose high-potential side voltage has been boosted in circuit 122E.

[0312] The clock signal HCLK1 generated in Figure 41(A) can be a clock signal in which the high-potential and low-potential voltages have been converted compared to the clock signal CLK1 of amplitude voltage VDD-GND. Figure 41(B) is a diagram illustrating the amplitude voltages of the clock signals CLK1 and CLK2 of amplitude voltage VDD-GND and the clock signals HCLK1 and HCLK2 generated in Figure 41(A). As shown in Figure 41(B), the amplitude voltages of the clock signals HCLK1 and HCLK2 can be clock signals with amplitude voltages based on voltage VDD3 and voltage VSS2. Therefore, the power supply circuit 121 to which the clock signals HCLK1 and HCLK2 are supplied can more reliably control the on or off state of the switches in the power supply circuit 121.

[0313] Figure 42 shows an example of a level shift circuit having a plurality of circuits 122E (122E_1, 122E_2) to which the power supply voltage VDD3-GND is supplied, and a circuit 122G to which the power supply voltage VDD3-VSS2 is supplied. Circuit 122E_1 boosts the voltage on the high potential side of the clock signal CLK1, and circuit 122E_2 boosts the voltage on the high potential side of the clock signal CLK2. Circuit 122G can obtain the clock signals HCLK1 and HCLK2 of amplitude voltage voltage VDD3-VSS2 using the clock signals boosted by circuits 122E_1 and 122E_2.

[0314] This embodiment can be implemented in appropriate combination with other embodiments described herein. For example, the circuit 122E in Figure 36(A) described in this embodiment can be replaced with the level shift circuits 122_1 and 122_2 shown in Figure 8 of Embodiment 1. The circuit diagram in this case is shown in Figure 43. Also, for example, the circuit 122E in Figure 36(A) described in this embodiment can be replaced with the level shift circuits 122_1 and 122_2 shown in Figure 12 of Embodiment 1. The circuit diagram in this case is shown in Figure 44. For example, the circuit 122E in Figure 36(A) described in this embodiment can be replaced with the level shift circuits 122_1 and 122_2 shown in Figure 14 of Embodiment 1. The circuit diagram in this case is shown in Figure 45. For example, the circuits 122E and 122G in Figure 41(A) described in this embodiment can be replaced with the level shift circuits 122_1 and 122_2 shown in Figure 23 of Embodiment 1. The circuit diagram in this case is shown in Figure 46.

[0315] In this embodiment, since it is possible to apply a CMOS circuit of an OS transistor, it is possible to use an inverter circuit that inverts the logic. Therefore, the clock signals HCLK1 and HCLK2 supplied from the level shift circuit 122 to the power supply circuit 121 can also be supplied via the inverter circuit. A modified example of Figure 43 with this configuration applied is shown in Figure 47. The inverter circuit INV shown in Figure 47 can be provided in the element layer 20 by using a CMOS circuit of an OS transistor.

[0316] (Embodiment 3) In this embodiment, an example of the configuration of a storage device 900 and an example of the configuration of a display device 800 applicable to a semiconductor device according to one aspect of the present invention will be described. The storage device 900 can be used as the memory 131, memory 132, etc. shown in the above embodiment.

[0317] <Example of Storage Device Configuration> Figure 48 shows a block diagram illustrating an example of the configuration of a storage device 900. The storage device 900 shown in Figure 48 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 48 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0318] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912 (Control Circuit), and a voltage generation circuit 928.

[0319] In the storage device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside or from the circuit unit 110, and signal RDA is an output signal to the outside or to the circuit unit 110. Signal CLK is a clock signal.

[0320] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can also be generated by the control circuit 912.

[0321] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the storage device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0322] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage. Any of the circuits in the circuit section 120 can be applied as the voltage generation circuit 928.

[0323] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0324] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0325] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the storage device 900. The data output from the output circuit 926 is the signal RDA.

[0326] PSW931 has the function of controlling the supply of VDD to the peripheral circuit 915. PSW932 has the function of controlling the supply of VHM to the row driver 923. Here, the high power supply voltage of the storage device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 48, the number of power supply domains to which VDD is supplied in the peripheral circuit 915 is set to 1, but it can be multiple. In this case, it is preferable to provide a power switch for each power supply domain.

[0327] Using Figures 49(A) to 49(F), 50(A), and 50(B), other examples of memory cell configurations applicable to the memory cell 950 will be described.

[0328] [DOSRAM] Figure 49(A) shows an example of the circuit configuration of a DRAM memory cell. In this specification and elsewhere, a DRAM using an OS transistor is called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 has a transistor M1 and a capacitive element CA.

[0329] Furthermore, transistor M1 may also have a gate and a back gate. The back gate can be connected to the gate. It is also possible to connect the back gate to a wire to which a constant potential or signal is supplied.

[0330] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0331] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0332] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0333] Furthermore, the memory cell that can be used in memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed. For example, a memory cell 952 configuration as shown in Figure 49(B) can also be used. Memory cell 952 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0334] In the memory cell 952, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0335] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of memory cell refresh can be reduced. Alternatively, the memory cell refresh operation can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 951 and 952.

[0336] [NOSRAM] Figure 49(C) shows an example of a circuit configuration of a gain cell type memory cell with two transistors and one capacitance element. The memory cell 953 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0337] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0338] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0339] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0340] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0341] Furthermore, it is possible to implement the functions of both the WBL and RBL wirings with a single wiring. An example of the circuit configuration of such a memory cell is shown in Figure 49(D). The memory cell 954 has a configuration that implements the functions of both the WBL and RBL wirings of the memory cell 953 with a single wiring BIL. Specifically, the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 has a configuration that uses a single wiring BIL for both the write bit line and the read bit line.

[0342] The memory cell 955 shown in Figure 49(E) is an example where the capacitive element CB and wiring CAL in the memory cell 953 are omitted. Similarly, the memory cell 956 shown in Figure 49(F) is an example where the capacitive element CB and wiring CAL in the memory cell 954 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0343] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

[0344] Because the OS transistor has the characteristic of having an extremely low off-current, the data written to it can be held by transistor M2 for a long time. This reduces the frequency of memory cell refreshes, or even eliminates the need for memory cell refresh operations altogether. Furthermore, because the OS transistor has a very low current, it can hold multi-level data or analog data in memory cells 953, 954, 955, and 956.

[0345] Memory cells 953, 954, 955, and 956, which use an OS transistor as transistor M2, represent one form of NOSRAM.

[0346] Furthermore, a Si transistor can be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0347] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0348] Figure 50(A) also shows a gain cell type memory cell 957 with three transistors and one capacitance element. The memory cell 957 has transistors M4 to M6 and a capacitance element CC.

[0349] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0350] Wiring BIL functions as a bit line, wiring WOL functions as a write word line, and wiring RWL functions as a read word line. Wiring GNDL is a wire that provides a low level potential.

[0351] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and the first terminal of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0352] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0353] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0354] Furthermore, Si transistors can be used as transistors M5 and M6. As mentioned above, depending on the crystal state of the silicon used in the semiconductor layer, Si transistors may have a higher field-effect mobility than OS transistors.

[0355] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0356] [OS-SRAM] Figure 50(B) shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 958 shown in Figure 50(B) is a memory cell of a backup-capable SRAM.

[0357] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0358] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0359] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0360] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0361] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0362] Wires BIL and BILB function as bit lines, wire WOL functions as a word line, and wire BRL controls the on and off states of transistors M9 and M10.

[0363] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0364] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0365] Incidentally, since the memory cell 958 is configured in an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0366] Data is read by first precharging wiring BIL and wiring BILB to a predetermined potential, then applying a high-level potential to wiring WOL and wiring BRL, thereby refreshing the potential of the first terminal of capacitive element CD1 by the inverter loop of memory cell 958 and outputting it to wiring BILB. Similarly, the potential of the first terminal of capacitive element CD2 is also refreshed by the inverter loop of memory cell 958 and outputting it to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively, so the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0367] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes, or even eliminating the need for memory cell refresh operations altogether.

[0368] Furthermore, Si transistors can be used as transistors MS1 to MS4.

[0369] For example, when the storage device 900 is provided in the element layer 30, both the drive circuit 910 and the memory array 920 can be provided in the element layer 30. Alternatively, the drive circuit 910 can be provided in the circuit section 110 of the element layer 10, and the memory array 920 can be provided in the circuit section 130 of the element layer 30.

[0370] The memory cells using OS transistors, such as DOSRAM, NOSRAM, and OS-SRAM, as shown in this embodiment (also called "OS memory"), do not involve structural changes at the atomic level, unlike ferroelectric memory (FeRAM) or resistive random-access memory (ReRAM), and therefore have excellent rewrite endurance. Furthermore, OS memory does not exhibit the instability caused by an increase in electron trapping centers due to repeated rewrite operations, as seen in flash memory.

[0371] Since OS memory can be constructed using thin-film transistors, it can be superimposed on Si transistors. Therefore, high integration of semiconductor devices is easily achieved. For example, it is possible to use OS transistors in the element layer 10. Furthermore, OS transistors used in OS memory can be manufactured using the same manufacturing equipment as Si transistors. Therefore, OS memory can be manufactured at low cost.

[0372] <Example of Display Device Configuration> Figure 51 shows a block diagram illustrating a display device to which one aspect of the present invention can be applied. The display device 800 shown in Figure 51 includes, as an example, a display unit 820, a power supply circuit 830, a display control circuit 840, a gate line drive circuit 850, and a data line drive circuit 860.

[0373] The display unit 820 has a plurality of pixels 959 arranged in a matrix. Each pixel 959 corresponds to a sub-pixel that controls the brightness of each color, such as red (R), green (G), and blue (B). Each pixel 959 has an light-emitting element.

[0374] Pixel 959 is connected to one of the data lines DL (data lines DL_1 to DL_3 are shown in Figure 51) and one of the gate lines GL (gate lines GL_1 and GL_2 are shown in Figure 51).

[0375] The data line DL is arranged in the column direction and connected to the data line drive circuit 860. The data line DL is the wiring that supplies the image data output by the data line drive circuit 860 to the pixel 959. The data line DL may also be called a source line, signal line, or wiring.

[0376] The data line drive circuit 860 is a drive circuit that outputs image data for displaying an image in the display unit 820 to the data line DL. The data line drive circuit 860 can be provided in the circuit section 110 of the element layer 10 described in Embodiment 1 above. The data line drive circuit 860 may also be called a source line drive circuit, source line side drive circuit, source driver, or simply a drive circuit. The data line drive circuit 860 can be placed in the display device 800 as an integrated circuit.

[0377] Image data is an analog voltage. Image data is data for displaying an image in the display device 800, and may be called video data, image signal, or video voltage. The display device 800, which has pixels 959, controls the current flowing through the light-emitting elements according to the analog voltage, and can display an image based on a desired grayscale.

[0378] The gate line GL is arranged extending in the row direction and connected to the gate line drive circuit 850. The gate line GL is a wiring that supplies the selection signal or deselection signal (hereinafter referred to as the gate signal) output by the gate line drive circuit 850 to the pixel 959. The gate line GL may also be called a scan line, signal line, or wiring. The gate signal supplied to the gate line GL controls the on or off state of a transistor in the pixel 959 that functions as a switch.

[0379] The gate line drive circuit 850 is a drive circuit that outputs a gate signal to the gate line GL for displaying an image in the display unit 820. The gate line drive circuit 850 can be provided in the circuit section 110 of the element layer 10 described in Embodiment 1 above. The gate line drive circuit 850 may also be called a scan line drive circuit, scan line side drive circuit, gate driver, or simply a drive circuit. The gate line drive circuit 850 can be placed in the display device 800 as an integrated circuit.

[0380] The power supply circuit 830 can be provided in the circuit section 120 of the element layer 20 described in Embodiment 1 above. The power supply circuit 830 has the function of supplying power voltage to drive the display control circuit 840, the gate line drive circuit 850, and the data line drive circuit 860. Since the power supply circuit 830 can be placed on the back side of the display section 820, a display device with excellent convenience can be made.

[0381] The display control circuit 840 has the function of outputting various control signals for controlling the gate line drive circuit 850 and the data line drive circuit 860. Since the various control signals for controlling the gate line drive circuit 850 and the data line drive circuit 860, such as the start pulse and clock signal, can be level-shifted using the power supply voltage supplied from the circuit section 120 of the element layer 20 as described in Embodiment 1 above, a display device with excellent convenience can be made.

[0382] Each of the pixels 959 in the display unit 820 can use an OS transistor and / or a Si transistor. The transistors in the pixels 959 can be provided in the element layer 10 or in the element layer 40 on the element layer 10. The light-emitting elements in the pixels 959 can be provided in the upper layer of the element layer 10 or in the upper layer of the element layer 40.

[0383] Figures 52(A) to 52(D) show an example of a circuit (also called a pixel circuit) that can be applied to the pixels 959 of the display device 800.

[0384] The pixel 959A shown in Figure 52(A) illustrates transistors PT1 and PT2, a capacitive element PC1, and a light-emitting element PEL. The pixel 959A is also connected to data lines DL, gate line GL, power line ANO, and power line VCOM. Each transistor in the pixel 959A is connected to its respective wiring as shown in Figure 52(A) as an example. Power lines ANO and VCOM are supplied with voltage to allow current to flow through the light-emitting element PEL.

[0385] Transistor PT1 has its gate connected to the gate line GL, one of its source and drain connected to the data line DL, and the other connected to the gate of transistor PT2 and one electrode of capacitive element C1. Transistor PT2 has its source and drain connected to the power line ANO, and the other connected to the anode of the light-emitting element PEL. Capacitive element C55 has its other electrode connected to the anode of the light-emitting element PEL. The cathode of the light-emitting element PEL is connected to the power line VCOM.

[0386] Pixel 959B, shown in Figure 52(B), is configured by adding transistor PT3 to pixel 959A. Power line V0 is also connected to pixel 959B.

[0387] The pixel 959C shown in Figure 52(C) is an example where transistors having a pair of gates are applied to transistors PT1 and PT2 of the above-mentioned pixel 959A. Similarly, the pixel 959D shown in Figure 52(D) is an example where the same transistors are applied to pixel 959B. This increases the current that the transistors can supply. While transistors having a pair of gates were used for all transistors here, this is not the only option. Furthermore, transistors having a pair of gates, but connected to different wiring, may also be used. For example, reliability can be improved by using a transistor in which one of the gates is connected to the source.

[0388] The pixel 959E shown in Figure 53(A) is configured by adding a transistor PT4 to the above-mentioned pixel 959B. In addition, three wires that function as gate lines (gate line GL1, gate line GL2, and gate line GL3) are connected to the pixel 959E.

[0389] Transistor PT4 has its gate connected to gate line GL3, and one of its source and drain is connected to the gate of transistor PT2, while the other is connected to power line V0. Transistor PT1's gate is connected to gate line GL1, and transistor PT3's gate is connected to gate line GL2.

[0390] By simultaneously making transistors PT3 and PT4 conduct, the source and gate of transistor PT2 become at the same potential, making transistor PT2 non-conductive. This allows the current flowing through the light-emitting element PEL to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0391] The pixel 959F shown in Figure 53(B) is an example in which a capacitive element PC2 is added to the above-mentioned pixel 959E. The capacitive element PC2 functions as a retaining capacitor.

[0392] Pixel 959G shown in Figure 53(C) and pixel 959H shown in Figure 53(D) are examples of cases where a transistor having a pair of gates is applied to the above-mentioned pixel 959E or pixel 959F, respectively. Transistors PT1, PT3, and PT4 are transistors with a pair of gates connected, while transistor PT2 is a transistor in which one gate is connected to the source.

[0393] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0394] (Embodiment 4) This embodiment describes an example of a transistor configuration applicable to a semiconductor device according to one aspect of the present invention.

[0395] Various transistor structures can be used as transistors constituting a semiconductor device according to one aspect of the present invention. For example, various transistor structures can be used, such as top-gate type (planar type, staggered type, etc.), bottom-gate type (inverse planar type, inverse staggered type, etc.), dual-gate type (structure in which gates are arranged on both sides (e.g., top and bottom) of the channel formation region), FIN type, TRI-GATE type, and GAA type (gate all-around type). In addition, for example, a vertical transistor (a transistor whose channel length direction has a component in the vertical direction (also called the height direction or the direction perpendicular to the surface to which it is formed)) can be used.

[0396] <Transistor Configuration Example 1> Figures 54(A) to 54(D) are plan views and cross-sectional views of transistor 200A. Figure 54(A) is a plan view of transistor 200A, and Figures 54(B) to (D) are schematic cross-sectional views corresponding to the cutting lines A1-A2, A3-A4, and A5-A6 in Figure 54(A), respectively. Figure 54(B) corresponds to the cross-section of transistor 200A in the channel length direction, and Figures 54(C) and (D) correspond to the cross-section in the channel width direction, respectively. Figures 55(A) and (B) are cross-sectional views of transistor 200A, corresponding to enlarged views of Figure 54(B). As mentioned above, in order to make the drawings easier to understand, some components may be omitted from the plan views, cross-sectional views, etc.

[0397] The transistor 200A includes a semiconductor layer 230 provided on an insulating layer 201 provided on a substrate (not shown), a conductive layer 242 (conductive layer 242a and conductive layer 242b) on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. An insulating layer 275 is provided covering the semiconductor layer 230 and the conductive layer 242, and an insulating layer 280 is provided on the insulating layer 275. The insulating layer 280 and the insulating layer 275 are provided with grooves that reach the semiconductor layer 230, and the conductive layer 242a and the conductive layer 242b are separated by these grooves. The insulating layer 250 is provided inside the grooves along the surfaces of the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, and the semiconductor layer 230. The conductive layer 260 is provided on the insulating layer 250 so as to fill the grooves. Furthermore, insulating layers 282 and 285 are provided in order, covering insulating layer 280, insulating layer 250, and conductive layer 260.

[0398] For example, the insulating layer 201 corresponds to the insulating layer 25 shown in the above embodiment. The semiconductor layer 230 corresponds to the semiconductor layer 21 shown in the above embodiment. The conductive layer 242 corresponds to the conductive layer 24 shown in the above embodiment. The insulating layer 275 corresponds to the insulating layer 32 shown in the above embodiment. The insulating layer 280 corresponds to the insulating layer 33a shown in the above embodiment. The insulating layer 250 corresponds to the insulating layer 22 shown in the above embodiment. The conductive layer 260 corresponds to the conductive layer 23 shown in the above embodiment.

[0399] The semiconductor layer 230 includes a region that functions as a channel formation region of the transistor 200A. The conductive layer 260 functions as a gate electrode of the transistor 200A. The insulating layer 250 functions as a gate insulator of the transistor 200A. The region of the semiconductor layer 230 that overlaps with the conductive layer 260 via the insulating layer 250 functions as a channel formation region.

[0400] The conductive layer 242a functions as either the source electrode or the drain electrode of the transistor 200A, while the conductive layer 242b functions as the other.

[0401] It is preferable that the conductive layers 242a and 242b have a laminated structure. It is preferable to use a conductor that is resistant to oxidation, such as a metal nitride, on the side that is in contact with the semiconductor layer 230. This prevents the conductive layers 242a and 242b from being excessively oxidized by the oxygen contained in the semiconductor layer 230. It is also preferable to use a metal or alloy with higher conductivity than the layer in contact with the semiconductor layer 230 on the side that is not in contact with the semiconductor layer 230. This allows the conductive layers 242a and 242b to function as highly conductive wiring or electrodes.

[0402] In conductive layers 242a and 242b, it is preferable to use a metal nitride on the side in contact with the semiconductor layer 230. For example, it is preferable to use nitrides containing tantalum, titanium, molybdenum, tungsten, ruthenium, tantalum and aluminum, or titanium and aluminum. Alternatively, for example, ruthenium, ruthenium oxides, strontium and ruthenium oxides, or lanthanum and nickel oxides can be used. These materials are preferable because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0403] The insulating layer 201 is a film that is in contact with the semiconductor layer 230, and it is preferable to use an oxide insulating film. For example, it is preferable to use silicon oxide or silicon oxynitride as the insulating layer 201.

[0404] It is also possible to provide an insulating layer that functions as a barrier layer (also called a "barrier insulating layer") between the insulating layer 201 and the semiconductor layer 230. Preferably, this insulating layer has barrier properties against hydrogen. Examples of hydrogen barrier insulating layers include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. In particular, when silicon oxide is used for the insulating layer 201, it is especially preferable to provide an insulating layer that has barrier properties against hydrogen because it has the characteristic of easily diffusing hydrogen. This makes it possible to keep the hydrogen concentration in the semiconductor layer 230 low, thereby improving the reliability of the transistor 200A.

[0405] To stabilize the electrical characteristics of transistor 200A, it is effective to reduce the impurity concentration in the semiconductor layer 230. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the semiconductor layer 230 refer to elements other than the main components that make up the semiconductor layer 230. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0406] As shown in the above embodiment, it is preferable to use an oxide semiconductor for the semiconductor layer 230. It is preferable to use indium oxide as the semiconductor layer 230. In particular, it is preferable to use a single-crystal indium oxide film. It is preferable to use a crystalline film for the semiconductor layer 230, and it is particularly preferable to use indium oxide with a single-crystal structure. By using indium oxide with a single-crystal structure, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0407] Furthermore, indium oxide having a polycrystalline or microcrystalline structure can also be used for the semiconductor layer 230. When using indium oxide having a polycrystalline structure, it is preferable that no grain boundaries are observed, at least in the channel formation region (the region superimposed with the conductive layer 260). This allows the same effects as when using indium oxide having a single-crystal structure to be achieved, even when using indium oxide having a polycrystalline structure.

[0408] When an oxide semiconductor is used for the semiconductor layer 230, the film thickness of the semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the film thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved. However, if the film thickness of the semiconductor layer 230 is made too thick, the density of grain boundaries in the semiconductor layer 230 will increase, and the field-effect mobility of the transistor may decrease due to the influence of carrier scattering at the grain boundaries. In addition, the productivity of the semiconductor device will decrease. On the other hand, if the film thickness of the semiconductor layer 230 is made too thin, the crystallinity of the semiconductor layer 230 will vary within the substrate surface, and the electrical properties may vary.

[0409] The insulating layer 250, which functions as a gate insulating layer, preferably has the function of capturing and fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the semiconductor layer 230. This makes it possible to make the channel formation region i-type or substantially i-type.

[0410] Here, the insulating layer 250 is preferably a laminated structure comprising a first layer in contact with the semiconductor layer 230, a second layer on the first layer, and a third layer on the second layer. In this case, it is preferable that the first layer has the function of capturing and fixing hydrogen.

[0411] Examples of insulators having the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. For the first layer, it is preferable to use a metal oxide such as magnesium oxide, or an oxide containing one or both of aluminum and hafnium. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides have a high ability to capture or fix hydrogen.

[0412] Furthermore, it is preferable to use a high-k material for the first layer. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material as the first layer, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it becomes possible to thin the EOT of the insulator that functions as a gate insulator.

[0413] It is preferable to use an oxide containing one or both of aluminum and hafnium as the first layer, and it is more preferable to use an oxide having an amorphous structure that contains one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0414] Next, it is preferable to use an insulator with a thermally stable structure, such as silicon oxide or silicon oxide-nitride, for the second layer.

[0415] Furthermore, a structure can be provided in which a fourth layer is placed on top of the second layer. In this case, the fourth layer can be an insulator that can be used for the first layer. For example, hafnium oxide can be used as the fourth layer. By providing the fourth layer between the third layer and the second layer, hydrogen contained in the second layer and the like can be captured and fixed more effectively.

[0416] The third layer preferably has a barrier property against oxygen. The third layer is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260, and between the insulating layer 280 and the conductive layer 260. With this configuration, it is possible to suppress oxygen contained in the channel formation region of the semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen deficiency in the channel formation region of the semiconductor layer 230. In addition, it is possible to suppress oxygen contained in the semiconductor layer 230 and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The third layer preferably has at least a lower oxygen permeability than the insulating layer 280. For example, it is preferable to use a silicon nitride film as the third layer. In this case, the third layer becomes an insulator having at least nitrogen and silicon.

[0417] Furthermore, the third layer preferably has a barrier property against hydrogen. Thereby, it is possible to prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0418] The insulating layer 275 preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a, and between the insulating layer 280 and the conductive layer 242b. With this configuration, it is possible to suppress oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. Therefore, it is possible to suppress the conductive layer 242a and the conductive layer 242b from being oxidized by oxygen contained in the insulating layer 280, increasing the resistivity, and reducing the on-current.

[0419] The insulating layer 275 preferably has at least a lower oxygen permeability than the insulating layer 280. In addition, it preferably has a low hydrogen permeability. For example, it is preferable to use silicon nitride as the insulating layer 275. In this case, the insulating layer 275 becomes an insulator having at least nitrogen and silicon.

[0420] Also, in the present embodiment, it is preferable to adopt a configuration that suppresses hydrogen from being mixed into the transistor 200A and the like from the outside. For example, it is preferable to provide an insulator having a function of suppressing the diffusion of hydrogen so as to cover the transistor 200A. In the semiconductor device described in the present embodiment, the insulator is, for example, the insulating layer 282 or the like. Also, as shown in FIG. 55(B), it is also possible to provide a similar film under the transistor 200A. FIG. 55(B) shows an example in which an insulating layer 283 is provided under the insulating layer 201.

[0421] The insulating layer 282 and the insulating layer 283 preferably function as a barrier insulating layer that suppresses the diffusion of impurities such as water and hydrogen from the outside into the transistor 200A. Therefore, the insulating layer 282 and the insulating layer 283 are preferably made of an insulating material having a function of suppressing the diffusion of impurity atoms such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ２ O, NO, NO ２ etc.) and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferably made of an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0422] The insulating layer 282 and insulating layer 283 preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as the insulating layer 283. Also, for example, it is preferable that the insulating layer 282 has aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulating layer 283 to the transistor 200A, etc. Also, it is possible to suppress the diffusion of oxygen contained in the insulating layer 280, etc., upward from the transistor 200A, etc. via the insulating layer 282, etc. Furthermore, by providing a film similar to one or both of the insulating layers 282 and 283 below the transistor 200A, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200A, etc.

[0423] Furthermore, as shown in Figures 55(A) and (B), an insulating layer 271a can be provided between the conductive layer 242a on the conductive layer 242a and the insulating layer 275, and an insulating layer 271b can be provided between the conductive layer 242b on the conductive layer 242b and the insulating layer 275. The insulating layers 271a and 271b function as etching stoppers during processing of the conductive layers 242a and 242b, and have the function of protecting the conductive layers 242a and 242b. In addition, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, it is preferable that they be inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, the insulating layers 271a and 271b can be arranged in a laminated structure, with silicon nitride used on the side in contact with the conductive layers 242a and 242b, and silicon oxide used elsewhere.

[0424] In Figures 55(A) and (B), openings reaching the conductive layer 242a are formed in insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 280, insulating layer 275, and insulating layer 271a, and the conductive layer 240a and insulating layer 241a are provided within these openings. The insulating layer 241a is provided in contact with the side wall of the opening, and the conductive layer 240a is provided inside the insulating layer 241a. In addition, openings reaching the conductive layer 242b are formed in insulating layer 285, insulating layer 283, insulating layer 282, insulating layer 280, insulating layer 275, and insulating layer 271b, and the conductive layer 240b and insulating layer 241b are provided within these openings. The insulating layer 241b is provided in contact with the side wall of the opening, and the conductive layer 240b is provided inside the insulating layer 241b. The conductive layers 240a and 240b function as vias connecting the conductive layer provided on the transistor 200A to the source or drain of the transistor 200A. The conductive layer 240 (conductive layers 240a and 240b) corresponds to the plug 34c shown in the above embodiment.

[0425] The conductive layers 240a and 240b are preferably made of conductive materials mainly composed of, for example, tungsten, copper, or aluminum. Furthermore, the conductive layers 240a and 240b can be arranged in a laminated structure.

[0426] For example, as shown in Figures 55(A) and (B), it is also possible to have a two-layer laminated structure of conductive layer 240a and conductive layer 240b. Conductive layer 240a has conductive layer 240a1 formed along the opening and conductive layer 240a2 formed inside conductive layer 240a1. Conductive layer 240b has conductive layer 240b1 formed along the opening and conductive layer 240b2 formed inside conductive layer 240b1.

[0427] It is preferable to use conductive materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide for the conductive layers 240a1 and 240b1, which have the function of suppressing the permeation of impurities such as water and hydrogen. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen can be used in a single layer or a laminate. By providing conductive layers 240a1 and 240b1, it is possible to suppress the mixing of impurities such as water and hydrogen into the semiconductor layer 230 through conductive layers 240a2 and 240b2. The conductive layers 240a2 and 240b2 may be conductive materials that can be used for conductive layers 240a and 240b described above.

[0428] Furthermore, as shown in Figure 54(B), the upper surfaces of the conductive layer 240a and conductive layer 240b may be formed to coincide with or substantially coincide with the upper surface of the insulating layer 285. Also, as shown in Figures 55(A) and (B), the lower part of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0429] As insulating layers 241a and 241b, barrier insulating layers that can be used for insulating layer 275 and the like may be used. For example, silicon nitride may be used as insulating layer 241a and insulating layer 241b. Insulating layers 241a and 241b are provided in contact with insulating layers 285, 283, 282, 275, 271a, and 271b. This makes it possible to suppress the mixing of impurities such as water and hydrogen contained in insulating layer 280 and the like into semiconductor layer 230 through conductive layer 240a and conductive layer 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulating layer 280 from being absorbed by conductive layer 240a and conductive layer 240b.

[0430] The conductive layer 260 functions as the gate electrode of the transistor 200A. Here, it is preferable that the conductive layer 260 extends in the channel width direction, as shown in Figures 54(A) and 54(C). With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0431] The conductive layer 260 may also have a laminated structure. Figures 55(A) and (B) show an example in which the conductive layer 260 has a conductive layer 260a located on the side in contact with the insulating layer 250 and a conductive layer 260b above it. In this case, it is preferable to use a conductive material that is resistant to oxidation, such as titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, or a conductive material that has the function of suppressing oxygen diffusion, for the conductive layer 260a. It is also preferable to use a low-resistance conductive material such as tungsten, copper, or aluminum for the conductive layer 260b.

[0432] The insulating layer 280 and insulating layer 285 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, the insulating layer 280 and insulating layer 285 preferably contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with vacancies. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0433] <Transistor Configuration Example 2> Below, we will describe a configuration example of transistor 200B, which differs in some aspects from transistor 200A. Note that the following mainly describes the differences from the above. Therefore, explanations of parts that overlap with the above may be omitted.

[0434] Transistor 200B is a modified version of transistor 200A, and Figures 56(A) and (B) are enlarged cross-sectional views of transistor 200B. Transistor 200B has a conductive layer 205 that functions as a back gate. Transistor 200B shown in Figure 56(A) has a conductive layer 205 and an insulating layer 202 beneath an insulating layer 201.

[0435] In the transistor 200B shown in Figure 56(A), the conductive layer 205 is provided so as to be embedded in the insulating layer 202. The insulating layer 201 is provided so as to cover the insulating layer 202 and the conductive layer 205.

[0436] The conductive layer 260 functions as the first gate of transistor 200B, and the conductive layer 205 functions as the second gate (back gate) of transistor 200B. The conductive layer 260 and the conductive layer 205 have overlapping regions via the semiconductor layer 230. The conductive layer 205 can be made of the same material as the conductive layer 260. The conductive layer 205 can also have a layered structure.

[0437] Furthermore, the insulating layer 250 functions as a first gate insulating layer, and the insulating layer 201 functions as a second gate insulating layer. In this case, the insulating layer 201 can be made into a laminated structure, and a high dielectric constant material such as hafnium oxide, aluminum oxide, or hafnium aluminate can be used in part thereof. For example, silicon oxide can be used as the insulating layer 202.

[0438] Furthermore, it is preferable to provide an insulating film, such as silicon nitride or aluminum oxide, which has oxygen barrier properties, between the insulating layer 202 and the conductive layer 205, as this can suppress oxidation of the conductive layer 205.

[0439] Furthermore, as shown in Figure 56(B) for transistor 200B, it is also possible to provide an insulating layer 283 that functions as a barrier insulating layer between the insulating layer 201 and the conductive layer 205.

[0440] <Transistor Configuration Example 3> Figure 57(A) is a plan view of transistor 200C, which has a different configuration from transistors 200A and 200B. Figure 57(B) is a cross-sectional view corresponding to the cutting line shown A1-A2 in Figure 57(A). In the following, we will mainly explain the parts that differ from the above. Therefore, explanations of parts that overlap with the above may be omitted.

[0441] Transistor 200C has a conductive layer 255 on top of an insulating layer 201. It also has an insulating layer 257 on top of the conductive layer 255, an insulating layer 258 on top of the insulating layer 257, and an insulating layer 259 on top of the insulating layer 258. In this specification, insulating layers 257, 258, and 259 may be collectively referred to as an insulating layer 256 or a spacer layer. It also has a conductive layer 261 on top of the insulating layer 259.

[0442] Furthermore, an opening 262 is provided in a region that overlaps with a part of the conductive layer 255, penetrating the conductive layer 261, the insulating layer 259, the insulating layer 258, and the insulating layer 257. A semiconductor layer 230 is also provided covering the inner wall of the opening 262.

[0443] The semiconductor layer 230 has a region that overlaps with the bottom of the opening 262 and a region that overlaps with the side of the opening 262. That is, the semiconductor layer 230 has a region that is in contact with the insulating layer 256 inside the opening 262. The semiconductor layer 230 also has a region that is in contact with the conductive layer 255 and a region that is in contact with the conductive layer 261 inside the opening 262.

[0444] Furthermore, an insulating layer 250 is provided on top of the insulating layer 259, the conductive layer 261, and the semiconductor layer 230. A conductive layer 265 is also provided on top of the insulating layer 250. The conductive layer 265 has a region that overlaps with the semiconductor layer 230. The conductive layer 265 has a region that overlaps with the semiconductor layer 230 via the insulating layer 250. The conductive layer 265 functions as a gate electrode. Therefore, the conductive layer 265 corresponds to the conductive layer 260 in transistors 200A and 200B.

[0445] Furthermore, each of the insulating layer 250 and the conductive layer 265 has a region that overlaps with the opening 262. Also, each of the insulating layer 250 and the conductive layer 265 has a region that overlaps with the inside of the opening 262. Inside the opening 262, the semiconductor layer 230 has a region that overlaps with the conductive layer 265 via the insulating layer 250, and a region that overlaps with the side surface of the opening 262 (the side surface of the insulating layer 256).

[0446] Furthermore, an insulating layer 285 is provided on top of the insulating layer 250. It is preferable that the upper surface of the insulating layer 285 is flat. Alternatively, it is preferable that the heights (positions in the Z-direction) of the upper surfaces of the insulating layer 285 and the conductive layer 265 coincide or substantially coincide. For example, the flatness of the upper surface of the insulating layer 285 can be improved by performing chemical mechanical polishing (CMP) treatment. Also, by performing CMP treatment, the positions of the upper surfaces of the insulating layer 285 and the conductive layer 265 can be made to coincide or substantially coincide. By performing CMP treatment, surface irregularities of the sample can be reduced, thereby improving the coverage of the insulating layer and conductive layer formed thereafter.

[0447] Furthermore, when an oxide semiconductor is used for the semiconductor layer 230, it is preferable that the conductive layer 255 and the conductive layer 261 in contact with the semiconductor layer 230 use a conductive material that converts the oxide semiconductor to n-type. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. It is also possible to provide other conductive materials on top of the conductive material containing nitrogen.

[0448] Furthermore, when an oxide semiconductor is used for the semiconductor layer 230, it is preferable to use a material with reduced hydrogen and containing oxygen for the insulating layer 258. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in oxide semiconductors, the contact between the oxide semiconductor semiconductor layer 230 and the hydrogen-reduced insulating layer 258 makes it less likely for the semiconductor layer 230 to become n-type. In addition, the contact between the oxide semiconductor semiconductor layer 230 and the oxygen-containing insulating layer 258 reduces oxygen vacancies in the semiconductor layer 230, stabilizing the transistor's characteristics and improving reliability.

[0449] Furthermore, when an oxide semiconductor is used for the semiconductor layer 230, the insulating layer 258 may contain excess oxygen. In this specification, excess oxygen refers to oxygen that is desorbed by heating. A material that desorbs oxygen by heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ by TDS (Thermal Desorption Spectroscopy) analysis. １８ atoms / cm ３ Preferably 1.0 × 10 １９ atoms / cm ３ More preferably 2.0 × 10 １９ atoms / cm ３ The above or 3.0 x 10 ２０ atoms / cm ３ The material is as described above. Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C or 100°C to 400°C. Performing TDS analysis in the range of 100°C to 700°C allows for evaluation of the amount of oxygen released in accordance with the transistor manufacturing process.

[0450] Also, when using a material containing excess oxygen for the insulating layer 258, it is preferable to use a material with low oxygen permeability for the insulating layer 257 and the insulating layer 259. As the material with low oxygen permeability, for example, an oxide containing one or both of aluminum and hafnium, silicon nitride, etc. can be used. By using a material with low oxygen permeability for the insulating layer 257 and the insulating layer 259, the excess oxygen contained in the insulating layer 258 is less likely to desorb into the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, a configuration having an insulating layer (insulating layer 258) containing silicon and oxygen between two insulating layers (insulating layer 257, insulating layer 259) containing silicon and nitrogen is preferable.

[0451] Also, when using an oxide semiconductor for the semiconductor layer 230, by using a material containing hydrogen for the insulating layer 257 and the insulating layer 259, hydrogen is supplied to the region of the semiconductor layer 230 in contact with the insulating layer 257 and the region of the semiconductor layer 230 in contact with the insulating layer 259. Depending on the composition of the oxide semiconductor used for the semiconductor layer 230, each region becomes n-type. Therefore, the region of the semiconductor layer 230 in contact with the conductive layer 261 and the region of the semiconductor layer 230 in contact with the insulating layer 259 function as one of the source region or the drain region. Also, the region of the semiconductor layer 230 in contact with the conductive layer 255 and the region of the semiconductor layer 230 in contact with the insulating layer 257 function as the other of the source region or the drain region.

[0452] The conductive layer 261 functions as one of the source electrode or the drain electrode of the transistor 200C. The conductive layer 255 functions as the other of the source electrode or the drain electrode of the transistor 200C. Therefore, the conductive layer 261 functions as one of the conductive layer 242a and the conductive layer 242b in the transistors 200A and 200B. Also, the conductive layer 255 functions as the other of the conductive layer 242a and the conductive layer 242b in the transistors 200A and 200B.

[0453] Transistor 200C is a transistor in which the source electrode and drain electrode are arranged in the Z direction. That is, the source and drain of transistor 200C are positioned at different heights. In other words, the source and drain of transistor 200C are positioned at different locations in the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0454] In the above configuration, for the VFET transistor 200C, the length of the side surface of the insulating layer 158 viewed from the X or Y direction becomes the channel length L (channel length L1) (see Figure 57(B)). Therefore, the channel length L of the transistor 200C is determined according to the thickness t1 of the insulating layer 258.

[0455] Furthermore, it is possible to use materials that do not contain hydrogen or contain very little hydrogen for the insulating layer 257 and insulating layer 259. When silicon nitride or silicon nitride oxide with very little hydrogen is used for the insulating layer 257 and insulating layer 259, the regions of the semiconductor layer 230 that are in contact with the insulating layer 257 and the regions of the semiconductor layer 230 that are in contact with the insulating layer 259 are not n-type. Therefore, the region of the semiconductor layer 230 that is in contact with the conductive layer 261 functions as either a source region or a drain region. Also, the region of the semiconductor layer 230 that is in contact with the conductive layer 255 functions as either a source region or a drain region. Furthermore, the region of the semiconductor layer 230 that is in contact with the insulating layer 258 functions as a channel-forming region.

[0456] In this case, the sum of the lengths of the sides of insulating layers 257, 258, and 259 as viewed from the X or Y direction becomes the channel length L (channel length L2). Therefore, the channel length L of transistor 200C is determined according to the thickness t2 obtained by adding the thicknesses of insulating layers 257, 258, and 259. Thus, transistor 200C has a channel formation region that is aligned with the side surface of insulating layer 256.

[0457] Furthermore, since the semiconductor layer 230 is provided in the opening 262, the length of the perimeter of the opening 262 when viewed from the Z direction becomes the channel width W of the transistor 200C (see Figure 57(A)). The length of the perimeter can be determined, for example, at a point where the thickness t1 of the insulating layer 258 is halfway, or at a point where the thickness t2 is halfway. If necessary, the length of the perimeter at any position of the opening 262 can be used as the channel width W. For example, the length of the perimeter at the bottom of the opening 262 can be used as the channel width W, or the length of the perimeter at the top of the opening 262 can be used as the channel width W. Also, in Figure 57(A), the contour (planar shape) of the opening 262 when viewed from the Z direction is shown as a circle, but it is not limited to this. For example, the contour of the opening 262 when viewed from the Z direction can be an ellipse, a rectangle, etc.

[0458] Furthermore, in order to improve the coverage of the semiconductor layer 230, insulating layer 250, and conductive layer 265 formed inside the opening 262, it is preferable that the side surface of the opening 262 has a slope. Specifically, it is preferable that the side surfaces of the insulating layer 257, insulating layer 258, and insulating layer 259, which are exposed by the formation of the opening 262, have a slope. In this specification, the angle between the bottom surface and the side surface of a layer (insulating layer, conductive layer, or semiconductor layer) is referred to as the "taper angle θ" (see Figure 57(B)).

[0459] By reducing the taper angle θ of insulating layers 257, 258, and 259, the coverage of the semiconductor layer 230, insulating layer 250, and conductive layer 265 formed later can be improved. In other words, the formation of the semiconductor layer 230, insulating layer 250, and conductive layer 265 on the inner wall of the opening 262 becomes easier. On the other hand, the smaller the taper angle θ, the larger the area occupied by the opening 262. Therefore, the area occupied by the transistor 200C increases, making miniaturization and high integration of the transistor 200C more difficult. Also, the larger the taper angle θ of insulating layers 257, 258, and 259, the lower the coverage of the semiconductor layer 230, insulating layer 250, and conductive layer 265, reducing the manufacturing yield and reliability of the transistor 200C. For these reasons, there is an appropriate range for the taper angle θ. The taper angle θ on the sides of each of the insulating layers 257, 258, and 259 is preferably 45° or more and less than 90°, and more preferably 50° or more and 75° or less.

[0460] Vertical transistors can reduce the area occupied by a transistor (also called a "horizontal transistor") in which the channel formation region, source region, and drain region are separately located on the XY plane. Therefore, by using vertical channel transistors in semiconductor devices, the area occupied by the semiconductor device can be reduced. Furthermore, by using vertical channel transistors in semiconductor devices, high integration of the semiconductor device can be achieved.

[0461] Furthermore, in lateral transistors, the channel length was limited by the exposure limit of photolithography. In one aspect of the present invention, the channel length can be set by the thickness of the insulating layer 256 or insulating layer 258. Therefore, the channel length of the transistor can be made into an extremely fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more). This increases the on-current of transistor 200C, and improves the frequency characteristics. By using a vertical channel transistor, a semiconductor device with a high operating speed can be provided.

[0462] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0463] (Embodiment 5) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor according to one aspect of the present invention.

[0464] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0465] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0466] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0467] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0468] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0469] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0470] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0471] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0472] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0473] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0474] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0475] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0476] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0477] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0478] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0479] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0480] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0481] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0482] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0483] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0484] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0485] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0486] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0487] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0488] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0489] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0490] (Embodiment 6) This embodiment describes electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DCs) that can use the semiconductor device described in the above embodiment. Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device according to one aspect of the present invention are effective in improving performance such as miniaturization and low power consumption.

[0491] [Electronic Components] Figure 58(A) shows a perspective view of a substrate (mounted substrate 704) on which an electronic component 709 is mounted. The electronic component 709 shown in Figure 58(A) has a semiconductor device 710 inside a mold 711. Some details are omitted in Figure 58(A) to show the inside of the electronic component 709. The electronic component 709 has a land 712 on the outside of the mold 711. The land 712 is connected to an electrode pad 713, and the electrode pad 713 is connected to the semiconductor device 710 via a wire 714. The electronic component 709 is mounted on a printed circuit board 702, for example. Multiple such electronic components are combined and connected on the printed circuit board 702 to complete the mounted substrate 704.

[0492] Furthermore, a semiconductor device 100 according to one aspect of the present invention can be used as the semiconductor device 710. Therefore, the semiconductor device 710 can have a monolithic stacked configuration in which multiple element layers are stacked. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV and bonding technology such as Cu-Cu direct bonding. By arranging multiple element layers in a monolithic stacked configuration, it becomes possible to increase the speed of operation of the interface portions between the multiple element layers in particular.

[0493] Furthermore, by adopting a monolithic stacked configuration, it is possible to reduce the size of connection wiring and other components compared to technologies using through-electrodes such as TSVs, thus increasing the number of connection pins.

[0494] Next, a perspective view of the electronic component 730 is shown in Figure 58(B). The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 710 and a plurality of semiconductor devices 720 are provided on the interposer 731. As the semiconductor device 710 and the plurality of semiconductor devices 720, a semiconductor device 100 according to one aspect of the present invention can be used.

[0495] Electronic component 730 shows an example in which a semiconductor device 720 using a semiconductor device 100 according to one aspect of the present invention is used as a high-bandwidth memory (HBM). Furthermore, electronic component 730 shows that a semiconductor device 710 using a semiconductor device 100 according to one aspect of the present invention can be used in integrated circuits such as CPUs, GPUs, and FPGAs.

[0496] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0497] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also has the function of connecting integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0498] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0499] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0500] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers, TSVs, etc., space is required, such as the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as described above, a monolithic stacked configuration using OS transistors is preferable. It is possible to create a composite structure that combines a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0501] Furthermore, it is preferable to provide a heat sink (heat dissipation plate) on top of the electronic component 730. Providing a heat sink stabilizes the operation of the electronic component and improves its reliability. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 720.

[0502] To mount the electronic component 730 onto another substrate, electrodes 733 can be provided at the bottom of the package substrate 732. Figure 58(B) shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. It is also possible to form the electrodes 733 with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0503] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0504] [Electronic Device] Next, a perspective view of the electronic device 6500 is shown in Figure 59(A). The electronic device 6500 shown in Figure 59(A) is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The control device 6509 has one or more functions selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device 100 according to one aspect of the present invention can be used as a control device 6509, etc.

[0505] The electronic device 6600 shown in Figure 59(B) is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, and the like. The control device 6616 has one or more functions selected from, for example, a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6615, the control device 6616, etc. Furthermore, a semiconductor device 100 according to one aspect of the present invention can be used as the control device 6616, etc.

[0506] [Large-scale computer] Next, a perspective view of the large-scale computer 5600 is shown in Figure 59(C). The large-scale computer 5600 shown in Figure 59(C) has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0507] The computer 5620 can have the configuration shown in the perspective view in Figure 59(D), for example. In Figure 59(D), the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0508] The PC card 5621 shown in Figure 59(E) is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. In one aspect of the present invention, the semiconductor device 100 can be used as, for example, at least one of the semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629.

[0509] Note that Figure 59(E) shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628. For information on these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 provided below.

[0510] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0511] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0512] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0513] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0514] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 709 can be used as the semiconductor device 5628.

[0515] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0516] [Space Equipment] A semiconductor device according to one aspect of the present invention can be used in space equipment such as devices for processing and storing information.

[0517] A semiconductor device according to one aspect of the present invention may include an OS transistor. This OS transistor exhibits minimal fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and is therefore suitable for environments where radiation may be incident. For example, an OS transistor is suitable for use in outer space.

[0518] Figure 60(A) shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 60(A), a planet 6804 is shown as an example in outer space. Outer space refers to, for example, an altitude of 100 km or more, but as described herein, outer space includes the thermosphere, mesosphere, and stratosphere.

[0519] Furthermore, although not shown in Figure 60(A), it is possible to provide a battery management system (also called "BMS") or a battery control circuit with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0520] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0521] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0522] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0523] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 has one or more functions selected from, for example, a CPU, a GPU, and a memory device. Compared to Si transistors, OS transistors exhibit less fluctuation in electrical characteristics due to radiation exposure. In other words, they are highly reliable even in environments where radiation may be incident, making them suitable for the control device 6807. A semiconductor device 100 according to one aspect of the present invention can be used, for example, in the control device 6807.

[0524] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0525] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention is suitable for space equipment such as spacecraft, space capsules, and space probes.

[0526] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0527] [Data Center] One aspect of the present invention is suitable for storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring the immutability of data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, and securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0528] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. As a result, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. Consequently, it is possible to save space in the data center.

[0529] Furthermore, since the semiconductor device according to one aspect of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0530] Figure 60(B) shows a storage system applicable to a data center. The storage system 7000 shown in Figure 60(B) has multiple servers 7001sb as hosts 7001 (indicated as Host Computer) and multiple storage devices 7003md as storage 7003 (indicated as Storage). The host 7001 and the storage 7003 are connected via a storage area network 7004 (SAN: Storage Area Network) and a storage control circuit 7002 (indicated as Storage Controller).

[0531] Host 7001 corresponds to a computer that accesses data stored in storage 7003. Hosts 7001 can connect to each other via a network.

[0532] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and retrieval in order to solve the problem of the long access speed of storage 7003.

[0533] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0534] By using OS transistors as the transistors for storing the data in the aforementioned cache memory, and by maintaining a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking memory cell arrays.

[0535] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that power consumption will be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention will reduce carbon dioxide (CO2). ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0536] This embodiment can be implemented in appropriate combination with other embodiments described herein.

[0537] 10: Element layer, 20: Element layer, 100: Semiconductor device, 110: Circuit section, 111: Functional circuit, 112: Functional circuit, 113: Functional circuit, 120: Circuit section, 121: Power supply circuit, 122: Level shift circuit, 123: Power supply circuit

Claims

circuit board and A first circuit section provided on the first surface side of the substrate, The substrate has a second circuit section provided on the second surface side and electrically connected to the first circuit section, The second circuit section comprises a first power supply circuit, a level shift circuit, and a second power supply circuit. The first power supply circuit has the function of boosting or lowering the first voltage supplied to the first power supply circuit to a second voltage and supplying it to the first circuit section by controlling the on / off state of a switch. The level shift circuit has the function of level shifting the amplitude voltage of the first clock signal that controls the on or off state of the switch supplied to the level shift circuit when a third voltage is supplied to it. The second power supply circuit has the function of supplying the fourth voltage supplied to the second power supply circuit as the third voltage to the level shift circuit when a second clock signal is supplied to it. Semiconductor equipment. 　 In claim 1, The switch, the level shift circuit, and the second power supply circuit each have a first transistor having a first semiconductor layer. The first transistor is of the n-channel type, The first semiconductor layer comprises indium and oxygen, Semiconductor equipment. 　 In claim 2, The switch, the level shift circuit, and the second power supply circuit each have a second transistor having a second semiconductor layer. The second transistor is a p-channel type, The second semiconductor layer comprises a material having tellurium and oxygen. Semiconductor equipment. 　 In claim 1, The first circuit section has a functional circuit having a third transistor, The aforementioned third transistor has a third semiconductor layer, The third semiconductor layer has silicon, Semiconductor equipment. 　 In claim 4, The substrate is a silicon substrate, The silicon substrate has through electrodes for electrically connecting the first circuit section and the second circuit section. Semiconductor equipment. 　 In claim 1, The first power supply circuit is a charge pump circuit having the switch. Semiconductor equipment. 　 In claim 1, The second power supply circuit is a charge pump circuit having a diode. Semiconductor equipment.

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