Drive circuit and semiconductor device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-04
- Publication Date
- 2026-08-13
Smart Images
Figure JP2025003626_13082026_PF_FP_ABST
Abstract
Description
Drive circuits and semiconductor devices
[0001] This disclosure relates to a drive circuit and a semiconductor device.
[0002] Patent Document 1 discloses a power converter for reducing switching delay time and switching loss while suppressing noise during recovery and voltage spikes during turn-off operation. In this power converter, for turn-on, the gate resistance is reduced compared to other turn-on periods when an ON signal is input and the gate voltage is below a certain set voltage, and when the collector voltage is below a certain set voltage. Similarly, for turn-off, the gate resistance is reduced compared to other turn-off periods when an ON signal is input and the gate voltage is below a certain set voltage, and when the collector voltage is above a certain set voltage.
[0003] Japanese Patent Publication No. 2009-054639
[0004] Generally, in a switching element drive circuit, switching loss and surge voltage are in a trade-off relationship. Similarly, the period td(off) from the start of turn-off operation until the output current begins to decrease is also in a trade-off relationship with the surge voltage. Patent Document 1 describes a method for optimally adjusting the trade-off relationship between switching loss, td(off), and surge voltage by changing the gate drive conditions during the turn-off operation. Specifically, the output terminal voltage V during the turn-off operation of the switching element is... ＣＥ When the threshold is exceeded, the gate resistance value is switched.
[0005] Here, if the switching of the gate drive condition is delayed from the optimal timing, the surge voltage will increase or the switching loss will increase. According to measured waveforms, the gate drive condition needs to be switched within, for example, ±50 ns from the optimal switching timing. In contrast, in a typical analog comparator, there is a propagation delay time of several hundred ns to several microseconds from when the input signal exceeds the threshold until the output signal inverts. Therefore, the output terminal voltage V of the switching element ＣＥIt may be difficult to detect when a certain threshold is reached using an analog comparator and switch the gate drive conditions accordingly.
[0006] Thus, with conventional technology, it is difficult to accurately set the timing of switching gate drive conditions, and there is a risk that switching losses and TD (off) and surge voltages cannot be sufficiently suppressed.
[0007] This disclosure aims to provide a drive circuit and semiconductor device that can suppress switching losses, TD (off), and surge voltage.
[0008] The drive circuit according to this disclosure includes a first buffer connected to the gate terminal of a switching element having a first terminal, a second terminal, and a gate terminal for switching the on / off state between the first terminal and the second terminal, with the gate drive voltage as input; a first resistor connected between the first buffer and the gate terminal; a selection circuit configured to output the higher of a tracking voltage that follows the output terminal voltage between the first terminal and the second terminal of the switching element and the gate drive voltage; a second buffer connected to the gate terminal with the output of the selection circuit as input; and a second resistor connected between the second buffer and the gate terminal, wherein the gate threshold voltage of the switching element is higher than the output terminal voltage when the rated current of the switching element is supplied.
[0009] In the drive circuit according to this disclosure, the gate drive conditions can be changed by changing the gate current. This makes it possible to suppress switching losses, td(off), and surge voltage.
[0010] A diagram showing the configuration of the semiconductor device according to Embodiment 1. A diagram showing the configuration of the semiconductor device according to the first comparative example. A diagram showing the waveforms during the turn-off operation of the semiconductor device according to the first comparative example. A diagram showing the configuration of the semiconductor device according to the second comparative example. A diagram explaining the influence of the timing of switching of the gate drive conditions. A diagram showing the measured waveforms during the turn-off operation when the gate drive conditions are fixed. A diagram showing the measured waveforms during the turn-off operation of the semiconductor device according to Embodiment 1. A diagram showing an example of the first buffer according to Embodiment 1. A diagram showing an example of the first buffer according to Embodiment 1. A diagram showing an example of the second buffer according to Embodiment 1. A diagram showing an example of the second buffer according to Embodiment 1. A diagram showing an example of the second buffer according to Embodiment 1. A diagram showing an example of the second buffer according to Embodiment 1. A diagram showing the configuration of the semiconductor device according to Embodiment 2. A diagram showing the configuration of the semiconductor device according to Embodiment 3. A diagram showing the configuration of the semiconductor device according to Embodiment 4. A diagram showing the measured waveforms during the turn-off operation of the semiconductor device according to Embodiment 4. A diagram showing the configuration of the semiconductor device according to Embodiment 5.
[0011] The drive circuit and semiconductor device according to the present embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the description thereof may be omitted.
[0012] Embodiment 1. FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to Embodiment 1. The semiconductor device 100 includes a drive circuit 10 and a switching element Q1. The switching element Q1 is a semiconductor switching element to be driven by the drive circuit 10. For example, an inductive load L1 is driven by the switching element Q1. A freewheeling diode D4 for freewheeling the load current flowing through the load L1 when the switching element Q1 is turned off is connected to the switching element Q1. A power supply V1 supplies power to the load L1.
[0013] The switching element Q1 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching element Q1 may be an IGBT (Insulated Gate Bipolar Transistor). The switching element Q1 has a first terminal, a second terminal, and a gate terminal for switching on and off between the first terminal and the second terminal. When the switching element Q1 is a MOSFET, the first terminal is a drain terminal and the second terminal is a source terminal. When the switching element Q1 is an IGBT, the first terminal is a collector terminal and the second terminal is an emitter terminal.
[0014] The drive signal is a signal for controlling the on and off of the switching element Q1, and is also called a gate drive voltage. The voltage of the drive signal when on is equal to the voltage applied to the gate of the switching element Q1. Generally, the voltage of the power supply VCC of the drive circuit 10 is provided as the voltage of the drive signal when on.
[0015] The first buffer Buf1 is connected to the gate terminal of the switching element Q1 with the gate drive voltage as an input. A resistor R4 is connected between the first buffer Buf1 and the gate terminal. The second buffer Buf2 is connected to the gate terminal of the switching element Q1 with the output of a selection circuit 14 described later as an input. A resistor R5 is connected between the second buffer Buf2 and the gate terminal.
[0016] The first buffer Buf1 and the second buffer Buf2 are circuits with broadband frequency characteristics, a voltage amplification factor = 1, that is, they output the input voltage without amplification and have a current amplification ability. The first buffer Buf1 is, for example, a current buffer that can output the current required for turning on and off the gate of the switching element Q1 with the gate drive voltage as an input. The second buffer Buf2 is, for example, a current buffer that can sink the current required for turning off the gate of the switching element Q1 with the output voltage of the selection circuit 14 as an input. The resistors R4 and R5 are resistors for adjusting the switching speed of the switching element Q1.
[0017] The cathode of diode D1 is connected to the first terminal, which is the output terminal of switching element Q1. In other words, the cathode of diode D1 is connected to the output terminal voltage V ＣＥ A bias voltage or current source is connected to the anode of diode D1. In this embodiment, the bias voltage is the voltage at the connection point of resistors R6 and R7, which are connected in series between the power supply VCC and GND. The output voltage detection circuit 12 outputs the voltage at the anode of diode D1.
[0018] Hereafter, the output terminal voltage V between the first and second terminals of the switching element Q1 will be described. ＣＥ A voltage that follows a curve is sometimes called a tracking voltage. In this embodiment, the voltage at the anode of diode D1, that is, the output voltage of the output voltage detection circuit 12, corresponds to the tracking voltage.
[0019] The selection circuit 14 is configured to output the higher of the tracking voltage output from the output voltage detection circuit 12 and the gate drive voltage. Specifically, the selection circuit 14 has a diode D2 to which the tracking voltage is supplied as the anode and a second buffer Buf2 is connected as the cathode, and a diode D3 to which the gate drive voltage is supplied as the anode and a second buffer Buf2 is connected as the cathode. A pull-down resistor R3 is connected to the cathode of diode D2 and the cathode of diode D3. The selection circuit 14 is also called a diode OR circuit. Note that the configuration of the selection circuit 14 is not limited to that shown in Figure 1.
[0020] Next, in order to explain the functions and effects of the drive circuit 10 and the semiconductor device 100 according to the present embodiment, first, the prior art will be described. FIG. 2 is a diagram showing the configuration of a semiconductor device according to a first comparative example. In the first comparative example, a resistor R11 and a resistor R12 are provided as means for setting gate drive conditions for adjusting the switching characteristics of the switching element Q1 to appropriate characteristics. The resistor R11 and the resistor R12 are gate resistors connected during the turn-on operation and the turn-off operation, respectively. The control circuit 81 controls the switches S1 and S2 to switch the resistors R11 and R12. When the gate resistance value is increased, the switching speed of the switching element Q1 decreases. Also, when the gate resistance value is decreased, the switching speed of the switching element Q1 increases.
[0021] FIG. 3 is a diagram showing waveforms during the turn-off operation of the semiconductor device according to the first comparative example. During the turn-off operation of the switching element Q1, the gate drive voltage becomes off at time t1, and the gate voltage V ＧＥ starts to decrease. Next, at time t2, the output terminal voltage V ＣＥ starts to increase gently, and the gate voltage V ＧＥ stops decreasing. The period during which the gate voltage V ＧＥ is constant from time t2 is called the mirror period. At time t3, the output terminal voltage V ＣＥ starts to increase rapidly. At time t4, the output terminal voltage V ＣＥ reaches the power supply voltage, and the output current Ic starts to decrease. At time t5, the output current Ic becomes zero. Also, between time t4 and time t5, the gate voltage V ＧＥ starts to decrease again, and at time t6, the gate voltage V ＧＥ becomes zero.
[0022] During the period from time t3 to t5, switching loss of the output terminal voltage V ＣＥ × output current Ic occurs. Also, during the period t4 to t5 when the output current Ic decreases, a surge voltage is generated due to the parasitic inductance of the output current path. Since the switching loss is a factor in the heat generation of the switching element Q1, it is preferably low. Also, it is necessary to suppress the sum of the surge voltage and the power supply voltage below the breakdown voltage of the switching element Q1, and the surge voltage is also preferably low.
[0023] Here, if the resistance value of the turn-off resistor R12 shown in Figure 2 is reduced, the turn-off switching speed of the switching element Q1 increases. This shortens the time from t3 to t5 and reduces switching losses. On the other hand, the rate of change ΔIc / Δt of the output current Ic of the switching element Q1 during the period from t4 to t5 increases. Therefore, the surge voltage = L × ΔIc / Δt generated by the parasitic inductance L in the path of the output current Ic increases. Conversely, if the resistance value of resistor R12 is increased, the surge voltage decreases, but the switching losses increase. Thus, there is a trade-off relationship between switching losses and surge voltage.
[0024] Furthermore, the period td(off), i.e., t1 to t4, from the start of the turn-off operation until the output current Ic begins to decrease, is also affected by the gate drive conditions. Lowering the resistance value of resistor R12 shortens td(off), while increasing the resistance value of resistor R12 lengthens td(off). Thus, td(off) also has a trade-off relationship with the surge voltage.
[0025] In a bridge configuration where switching elements are connected in series, it is necessary to prevent the upper and lower switching elements from being simultaneously turned on and causing a short circuit. Therefore, after one of the switching elements starts turning off, a certain time t is required. ｄｅａｄ Later, the other switching element is turned off. If td(off) is prolonged, t is adjusted in accordance with td(off). ｄｅａｄ It also needs to be made longer. ｄｅａｄ If td(off) is extended, the effective output voltage decreases when an H-bridge or three-phase inverter is configured. For this reason, a shorter td(off) is preferable.
[0026] Figure 4 shows the configuration of a semiconductor device according to the second comparative example. In the semiconductor device according to the second comparative example, the gate drive conditions are changed during the turn-off operation period in order to optimally adjust the switching loss and td(off) and surge voltage, which are in a trade-off relationship. Specifically, two resistors R12 and R13 for turn-off are provided. The control circuit 82 controls switches S1, S2, and S3 to switch resistors R11, R12, and R13. The control circuit 82 controls the output terminal voltage V during the turn-off operation of the switching element Q1. ＣＥ When the threshold is exceeded, resistors R12 and R13 are switched. Output terminal voltage V ＣＥ This is detected in the output voltage detection circuit 83 by dividing the voltage with resistors R14 and R15.
[0027] The optimal timing for switching the gate drive conditions is t4 in Figure 3. That is, the gate resistance is reduced before t4 and increased after t4. This results in td (off) and the output terminal voltage V between t3 and t4. ＣＥ This can reduce switching losses during periods of increasing voltage and reduce surge voltages that occur during periods t4 to t5.
[0028] If the gate drive condition is switched after t4, the surge voltage will increase, and the switching element Q1 may fail due to voltage breakdown. Conversely, if the gate drive condition is switched before t4, the switching loss will increase. Therefore, it is important to bring the timing of the gate drive condition switch as close as possible to the optimal switching timing of t4.
[0029] Figure 5 illustrates the effect of the timing of switching the gate drive conditions. Figure 5 shows measured waveforms obtained by changing the timing of switching the gate drive conditions. The second waveform from the top, waveform 2, is the waveform when the gate drive conditions are switched at the optimal timing t4. The top waveform, waveform 1, is the waveform when the gate drive conditions are switched approximately 50 ns earlier than t4. The third waveform from the top, waveform 3, is the waveform when the gate drive conditions are switched approximately 50 ns later than t4. The bottom waveform, waveform 4, is the waveform when the gate drive conditions are switched approximately 100 ns later than t4. From the waveforms in Figure 5, it can be estimated that the gate drive conditions need to be switched within ±50 ns of the optimal switching timing.
[0030] Here, for example, as shown in Figure 4, the output terminal voltage V of the switching element Q1 during the period t3 to t4. ＣＥ One possibility is to use an analog comparator U11 to detect when the input signal reaches an arbitrary threshold voltage and switch the gate drive conditions. However, in general, analog comparators have a propagation delay time of several hundred nanoseconds to several microseconds from the time the input signal exceeds the threshold until the output signal inverts. In addition, the delay of the control circuit 82 connected to the analog comparator U11 for switching the gate drive conditions must also be taken into consideration.
[0031] Therefore, considering the total delay time of the switching circuit, including the propagation delay time of the analog comparator U11, in relation to the switching timing t4 of the optimal gate drive conditions, the output terminal voltage V that triggers the switching is determined. ＣＥ The threshold voltage needs to be determined. However, the output terminal voltage V ＣＥ Reducing the gate resistance to minimize switching losses during the rise time t3-t4 shortens this period. Therefore, in a circuit like the one shown in Figure 4, it may become difficult to accurately set the timing for switching the gate drive conditions.
[0032] Furthermore, in a circuit like the one shown in Figure 4, the shorter the total delay time of the switching circuit, the lower the output terminal voltage V that triggers the switching. ＣＥThe threshold can be set higher. This reduces variations in operating timing due to external noise. Due to variations in the characteristics of the switching element Q1, the output terminal voltage V ＣＥ If the rise time fluctuates, the discrepancy between the gate drive condition switching timing and the optimal timing t4 increases. However, the shorter the total delay time of the switching circuit, the less the influence of characteristic variations in the switching element Q1 can be reduced. Therefore, the shorter the total delay time of the switching circuit, the more stably and accurately the circuit in Figure 4 can operate.
[0033] Figure 6 shows the measured waveform during turn-off operation when the gate drive conditions are fixed. Figure 6 shows the turn-off waveform of the IGBT when the gate drive conditions are not switched. In the example of Figure 6, since the gate drive conditions are fixed, optimization is performed to slow down the turn-off switching speed so that the surge voltage generated when the collector current Ic falls below the breakdown voltage. However, despite slowing down the turn-off switching speed, the output terminal voltage V ＣＥ The time it takes for the voltage to rise from 10% of the power supply voltage to the full power supply voltage is 180 ns. This time is shorter than the propagation delay time of a typical analog comparator.
[0034] For example, if the gate drive conditions are switched and the rise time of the collector voltage is set to 90 ns, the total delay time of the switching circuit must be shorter than 90 ns. Also, as mentioned above, considering that the shorter the total delay time of the switching circuit, the more stably the circuit operates, the total delay time in the example in Figure 6 must be kept below 50 ns. In this case, a typical analog comparator with a propagation delay time of several hundred ns cannot be used. Therefore, it is necessary to use an expensive discrete-type high-speed comparator. For this reason, in the comparative example shown in Figure 4, the cost and mounting area of the drive circuit may increase.
[0035] Thus, by switching the gate drive conditions precisely and at the optimal timing during the turn-off operation, it is possible to suppress the trade-off relationship between switching loss and td(off) and surge voltage. However, in conventional technology, considering variations in the characteristics of the switching element Q1, various operating conditions, and the total delay time of the switching circuit, it was difficult to accurately set the timing at which the switching circuit started operating.
[0036] Next, the functions and effects of the drive circuit 10 and semiconductor device 100 according to this embodiment will be described. During turn-off operation, the gate drive voltage becomes 0V. Also, when a negative bias voltage is applied when the switching element Q1 is turned off, the gate drive voltage drops to the negative bias voltage. This gate drive voltage is input to the first buffer Buf1 and the selection circuit 14.
[0037] During turn-off operation, gate drive voltage < output terminal voltage V ＣＥ Therefore, the output terminal voltage V is output from the selection circuit 14. ＣＥ The output is generated and input to the second buffer Buf2. At this time, the output currents of the first buffer Buf1 and the second buffer Buf2 are as follows: Output current of first buffer Buf1 = (gate voltage V ＧＥ Output current of second buffer Buf2 = (gate voltage V) / R4 ＧＥ - Output terminal voltage V ＣＥ ) / R5
[0038] Figure 7 shows the measured waveform during the turn-off operation of the semiconductor device 100 according to Embodiment 1. In Figure 7, IGsink is the gate current of the switching element Q1. IGsink is the sum of the output currents of the first buffer Buf1 and the second buffer Buf2. IGsink is defined with the direction in which the gate current flows from the gate to the first buffer Buf1 and the second buffer Buf2, i.e., the sink direction, as negative, and the direction in which the gate current flows from the first buffer Buf1 and the second buffer Buf2 to the gate, i.e., the source direction, as positive.
[0039] As described above, after the start of the turn-off operation of the switching element Q1, the gate voltage V is the same as during the turn-on operation. ＧＥ There exists a Miller period during which the gate voltage V remains constant. ＧＥ It is proportional to the gate threshold voltage. The gate threshold voltage of switching element Q1 is the output terminal voltage V when the rated current of switching element Q1 is applied. ＣＥ In other words, it is set higher than the on-voltage. Therefore, the following equation holds during the Miller period: Gate voltage V ＧＥ > Output terminal voltage V ＣＥ (= ON voltage) Therefore, the second buffer Buf2 can output sink-in current even during the Miller period.
[0040] In Figure 7, the output terminal voltage V ＣＥ is time - 2.0 × 10 －７ It begins to gradually increase from the vicinity. As a result, the output current of the second buffer Buf2 decreases, and IGsink also decreases to time -2.0 × 10 －７ The voltage V at the output terminal of the switching element Q1 begins to gradually decrease after peaking in the vicinity. ＣＥ As the IGsink gradually decreases with increasing IGsink, the gate drive conditions can be changed in this embodiment.
[0041] In other words, the output terminal voltage V ＣＥ Until the voltage starts to increase, the gate of switching element Q1 is sunk in both the first buffer Buf1 and the second buffer Buf2. This allows the output terminal voltage V to start increasing from the time the switching element Q1 turns off. ＣＥ The time until the increase begins can be shortened. Output terminal voltage V ＣＥ As the voltage increases, the output current of the second buffer Buf2 decreases. This makes the falling edge slope of the output current of the switching element Q1 gentler, thereby reducing the surge voltage generated in the inductance of the main circuit wiring. The main wiring circuit consists of a power supply V1, a freewheeling diode D4, and a switching element Q1.
[0042] Thus, in this embodiment, the output terminal voltage V during the turn-off operation ＣＥAn active gate drive function can be realized that varies the gate drive conditions to follow the rise in voltage. Therefore, switching losses, TD (off), and surge voltage can be suppressed.
[0043] At the start of the turn-on operation, the output terminal voltage V of the switching element Q1, which is in the off state, ＣＥ This is equal to the power supply V1. Then, when the switching element Q1 turns on, the output terminal voltage V ＣＥ This voltage is lower than the gate drive voltage. The gate drive voltage is the voltage applied to the gate of the switching element Q1 when the switching element Q1 is turned on. Therefore, during turn-on operation, the output voltage of the selection circuit 14, that is, the input voltage of the second buffer Buf2, is greater than or equal to the gate voltage of the switching element Q1. Thus, during turn-on operation, the gate of the switching element Q1 can be driven by the output currents of the first buffer Buf1 and the second buffer Buf2.
[0044] Furthermore, high-speed switching diodes can be used as diodes D2 and D3 in the selection circuit 14. In this case, the output delay relative to the input of the selection circuit 14 can be reduced to a few nanoseconds to a few tens of nanoseconds.
[0045] Next, the first buffer Buf1 and the second buffer Buf2 will be described in detail. There are no particular restrictions on the configuration of the first buffer Buf1. Figures 8A and 8B show an example of the first buffer Buf1 according to Embodiment 1. As shown in Figure 8A, the first buffer Buf1 may be configured by connecting two common-source inverter circuits using MOSFETs in stages. The first buffer Buf1 may also be configured by connecting two common-emitter inverter circuits using bipolar transistors instead of MOSFETs. As shown in Figure 8B, the first buffer Buf1 may be a source-follower type buffer using MOSFETs. The first buffer Buf1 may also be an emitter-follower type buffer using bipolar transistors instead of MOSFETs.
[0046] The source-common buffer shown in Figure 8A has only two input voltages, GND level and power supply voltage level. In the source-follower buffer shown in Figure 8B, the output voltage Out = input voltage In, ignoring the gate threshold voltage of the MOSFET. The range of the input voltage In is from GND to the power supply voltage. The first buffer Buf1 is input with a gate drive voltage that is either GND level or power supply voltage level. Therefore, buffers with either configuration in Figures 8A or 8B can be used.
[0047] In contrast, the output voltage of the selection circuit 14, which ranges from the GND level to the power supply voltage level of the VCC, is input to the second buffer Buf2. In order to make the output voltage of the second buffer Buf2 follow the input voltage, it is preferable that the second buffer Buf2 be of the source follower type or emitter follower type.
[0048] Figures 9A, 9B, 10A, and 10B show examples of the second buffer Buf2 according to Embodiment 1. The second buffer Buf2 may have only a sink current output function during turn-off operation and may not have a source current output function during turn-on operation. Figures 9A and 9B show examples of the second buffer Buf2 having only a sink current output function. Figure 9A shows a source follower type buffer using a MOSFET, and Figure 9B shows an emitter follower type buffer using a bipolar transistor.
[0049] Figures 10A and 10B show examples of a second buffer Buf2 having sink current output and source current output functions. Figure 10A shows a source follower type buffer using a MOSFET, and Figure 10B shows an emitter follower type buffer using a bipolar transistor. The second buffer Buf2, which has a source current output function, also functions during turn-on operation. In this case, during turn-on operation, source current is supplied to the gate of the switching element Q1 from both the first buffer Buf1 and the second buffer Buf2.
[0050] Whether the second buffer Buf2 is a source follower or emitter follower, a high-speed buffer can be used. This allows the delay between the input and output to be reduced to a few nanoseconds.
[0051] The values of resistors R4 and R5 change depending on whether the turn-on operation is performed using only the first buffer Buf1 or using both the first buffer Buf1 and the second buffer Buf2. The combined resistance value of resistors R4 and R5 is adjusted so that the switching speed of the switching element Q1 falls within the required speed.
[0052] Alternatively, the first buffer Buf1 may have only a sink current output function, while the second buffer Buf2 may have both a sink current output function and a source current output function. In this case, the first buffer Buf1 will have the configuration shown in Figure 9A or Figure 9B, and the second buffer Buf2 will have the configuration shown in Figure 10A or Figure 10B. In this case, during turn-on operation, the gate is driven only by the source output current of the second buffer Buf2. During turn-off operation, the gate is driven by the sink currents of both the first buffer Buf1 and the second buffer Buf2.
[0053] In this embodiment, the output terminal voltage V ＣＥ An example was described in which the tracking voltage that follows is the voltage at the anode of diode D1. In contrast, the tracking voltage input to the selection circuit 14 is the output terminal voltage V ＣＥ The functionality of this embodiment can be realized as long as the voltage follows the response. Other examples of the response voltage will be discussed later.
[0054] Furthermore, the diode D1 of the output voltage detection circuit 12 is supplied with a bias current from the power supply VCC via resistor R6. This bias current can be supplied from a constant current source, and the circuit can operate in the same manner as in this embodiment.
[0055] The switching element Q1 may be formed from a wide-bandgap semiconductor. Wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. For example, the switching element Q1 may be a MOSFET formed from SiC.
[0056] The modifications described above can be appropriately applied to the drive circuit and semiconductor device according to the following embodiments. Since the drive circuit and semiconductor device according to the following embodiments have many similarities with Embodiment 1, the differences from Embodiment 1 will be the focus of this explanation.
[0057] Embodiment 2. Figure 11 shows the configuration of the semiconductor device 200 according to Embodiment 2. The semiconductor device 200 includes a drive circuit 210. In the drive circuit 210, the configuration of the output voltage detection circuit 212 differs from that of Embodiment 1. The other configurations are the same as those of Embodiment 1. The output voltage detection circuit 212 detects the output terminal voltage V ＣＥ The system includes a resistive voltage divider circuit that divides the voltage by resistors and outputs it as a tracking voltage. The resistive voltage divider circuit consists of resistors R1 and R2 connected in series between the output terminal of the switching element Q1 and GND.
[0058] In this embodiment, the output terminal voltage V ＣＥ The voltage obtained by dividing the voltage is input to the selection circuit 14 as the tracking voltage. The selection circuit 14 is configured to output the higher of the tracking voltage output from the output voltage detection circuit 212 and the gate drive voltage.
[0059] The voltage of the power supply V1 increases depending on the power supplied to the load L1, and may exceed 1kV. In this case, the reverse bias breakdown voltage of diode D1 in Embodiment 1 needs to be higher than the voltage of power supply V1. In contrast, in this embodiment, inexpensive resistors R1 and R2 can be connected in series as needed, depending on the voltage of power supply V1. Therefore, component costs can be reduced. Furthermore, in Embodiment 1, since the reverse bias breakdown voltage can be ensured by diode D1, the mounting area can be reduced compared to Embodiment 2.
[0060] Embodiment 3. Figure 12 shows the configuration of the semiconductor device 300 according to Embodiment 3. The semiconductor device 300 includes a drive circuit 310. The drive circuit 310 includes a DeSAT detection circuit 320, a control circuit 324, and a gate voltage monitoring circuit 322 instead of an output voltage detection circuit 12.
[0061] In the DeSAT detection circuit 320, a constant current source I1 is connected to the anode of diode D1. A capacitor C1 is connected between the constant current source I1 and GND. The DeSAT detection circuit 320 further includes a switching element Q2, a comparator U1, and a reference voltage source V31. The gate voltage monitoring circuit 322 consists of a comparator U2 that compares the gate voltage of the switching element Q1 with the reference voltage source V32.
[0062] The control circuit 324 takes an on / off instruction signal that instructs the switching element Q1 to be turned on or off, a DeSAT detection signal which is the output of comparator U1, and a gate monitoring signal which is the output of comparator U2 as input signals, and outputs a drive signal and a clamp signal. The selection circuit 14 outputs the higher voltage of the drive signal voltage and the anode voltage of diode D1. The other configurations are the same as those of the first embodiment.
[0063] First, let's explain general protection operations. Suppose that during the ON period of switching element Q1, a short circuit in load L1 causes the output current of switching element Q1 to exceed its rating. This condition is represented by the output terminal voltage V of switching element Q1. ＣＥ This is called the DeSAT state, where the voltage increases. The anode potential of diode D1 is equal to the output terminal voltage V of Q1. ＣＥ It follows this. When the anode potential of diode D1 exceeds the voltage of the reference voltage source V31, the output voltage of comparator U1, i.e., the DeSAT detection signal, changes from Low to High. This allows the control circuit 324 to be notified that the switching element Q1 is in an overcurrent or overload condition. When an overcurrent or overload condition is detected, the control circuit 324 lowers the drive signal to the GND level and starts a protection operation to turn off the switching element Q1. This prevents failure of the switching element Q1.
[0064] Even during this protective turn-off operation, the selection circuit 14, the first buffer Buf1, and the second buffer Buf2 operate in the same manner as in Embodiment 1. This makes it possible to shorten the turn-off time and reduce surge voltages in the main circuit wiring.
[0065] When switching element Q1 is in the off state, the output terminal voltage V ＣＥ This is equal to the power supply V1. When the switching element Q1 is turned on, the output terminal voltage V ＣＥ The voltage drops to an on-voltage corresponding to the load current. The voltage of the reference voltage source V31 of the DeSAT detection circuit 320 is set to be higher than the on-voltage of the switching element Q1 at the maximum load current. This allows the DeSAT detection signal to be kept low when the load current is below the maximum load current.
[0066] Here, during the turn-on operation when the switching element Q1 transitions from the off state to the on state, the output terminal voltage V ＣＥ It takes a certain amount of time for the voltage to drop to an ON voltage corresponding to the load current. During this period, it is necessary to mask the DeSAT detection for a certain period of time so that the DeSAT detection circuit 320 does not falsely detect the DeSAT state. This mask is controlled by the Clamp signal output by the control circuit 324.
[0067] When the on / off instruction signal is off, the Clamp signal becomes high. This turns on the switching element Q2, and the input terminal voltage of comparator U1 drops to GND level. In other words, when the on / off instruction signal is off, DeSAT detection is masked. When the on / off instruction signal becomes on, the Clamp signal becomes low. This turns off the switching element Q2, and capacitor C1 is charged by the output current of constant current source I1. The output terminal voltage of switching element Q1 V is measured from the start of charging of capacitor C1 until Tmask = C1(F) × V31(V) / I1(A) seconds later. ＣＥ If the value does not fall below V31, the DeSAT detection signal becomes High. This initiates a protection operation that turns off the switching element Q1.
[0068] Thus, in a typical DeSAT detection circuit, the Clamp signal becomes High at the same time as the turn-off operation begins, the switching element Q2 turns on, and the input voltage of comparator U1, i.e., the anode potential of diode D1, is lowered to the GND level. In contrast, in this embodiment, the anode potential of diode D1 is maintained at the output terminal voltage V even during the turn-off operation period. ＣＥTo accommodate this, the gate drive conditions must be made variable by the second buffer Buf2. Therefore, the switching element Q2 must be kept in the off state even during the turn-off operation.
[0069] Therefore, in this embodiment, a gate voltage monitoring circuit 322 is used to determine the timing for turning on the switching element Q2 and enabling the mask. After the turn-off operation starts, when the gate voltage of the switching element Q1 drops below the voltage of the reference voltage source V32, the control circuit 324 determines that the turn-off operation of the switching element Q2 is complete and it is in the off state, and sets the Clamp signal to High. This turns on the switching element Q2. The gate voltage monitoring circuit 322 is often implemented in the drive circuit to monitor the on / off state of the switching element Q1. For this reason, it is not necessary to add a new gate voltage monitoring circuit 322 to realize this embodiment.
[0070] From the above, the drive circuit 310 of this embodiment has an output terminal voltage V ＣＥ The control circuit 324 includes a comparator U1 as a detection circuit configured to detect whether the output terminal voltage V31 is greater than a predetermined first threshold voltage V31. ＣＥ When it is detected that the gate drive voltage is greater than the first threshold voltage V31, the drive circuit 310 reduces the gate drive voltage. The drive circuit 310 also reduces the gate drive voltage when the output terminal voltage V input to the comparator U1 is received during the turn-off operation of the switching element Q1. ＣＥ The switching element Q2 is provided as a mask circuit configured to mask the output terminal voltage V input to the comparator U1 during a predetermined period from the start of the turn-off operation. ＣＥ It does not mask. Specifically, when the voltage at the gate terminal of switching element Q1 falls below a predetermined second threshold voltage V32 after the start of the turn-off operation of switching element Q2, the output terminal voltage V input to comparator U1 is not masked. ＣＥ Mask it.
[0071] From the above, according to this embodiment, the DeSAT detection circuit 320 performs a protective operation, and the output terminal voltage V during the turn-off operation is... ＣＥThis embodiment allows for the simultaneous implementation of an active gate drive function that varies the gate drive conditions to follow the increase in voltage. Furthermore, in this embodiment, since a portion of the output voltage detection circuit 12 of Embodiment 1 is also used as the DeSAT detection circuit 320, additional circuits can be suppressed.
[0072] Embodiment 4. Figure 13 shows the configuration of a semiconductor device 400 according to Embodiment 4. The semiconductor device 400 includes a drive circuit 410. The drive circuit 410 has a selection circuit 414. The selection circuit 414 differs from the selection circuit 14 in that it further has a capacitor C2 connected in parallel with a resistor R3, which is a pull-down resistor. The other configurations are the same as those of Embodiment 1.
[0073] In this embodiment as well, the output terminal voltage V of the switching element Q1 during the turn-off operation. ＣＥ As the value increases, the gate drive conditions can be changed by the second buffer Buf2. Furthermore, the timing of changing the gate drive conditions of the second buffer Buf2 can be arbitrarily delayed by the capacitor C2. Therefore, active gate driving under more optimal conditions than in Embodiment 1 becomes possible.
[0074] The output of the selection circuit 414 during turn-off operation is the output terminal voltage V of the switching element. ＣＥ It follows this. However, the capacitance of the added capacitor C2 causes a delay in the tracking. As a result, the start of the change in the gate drive conditions by the second buffer Buf2 is also delayed.
[0075] Figure 14 shows the measured waveform during the turn-off operation of the semiconductor device 400 according to Embodiment 4. When the capacitance of capacitor C2 is small, the output terminal voltage V ＣＥ As the IGsink increases, the time is -2.0 × 10 －７ It gradually decreases from the vicinity. On the other hand, the larger the capacitance of capacitor C2, the later the timing at which IGsink begins to decrease. In other words, the larger the capacitance of capacitor C2, the later the start of the change in the gate drive conditions by the second buffer Buf2.
[0076] Furthermore, the larger the capacitance of capacitor C2, the lower the output terminal voltage V. ＣＥThe slope of the rising edge and the slope of the output current Ic become larger. In other words, the switching speed increases. Thus, the capacitance of capacitor C2 can be adjusted to increase the switching speed. Therefore, it becomes possible to optimize the switching conditions.
[0077] Embodiment 5. Figure 15 shows the configuration of a semiconductor device 500 according to Embodiment 5. The semiconductor device 500 includes a drive circuit 510. The drive circuit 510 has a voltage detection circuit 512. In this embodiment, the diode D1 is provided inside the package or case of the switching element Q1. That is, the anode of the diode D1 is provided as one of the signal terminals of the package of the switching element Q1. The other configurations are the same as those of Embodiment 1.
[0078] Depending on the amount of power supplied to the load L1, the voltage of the power supply V1 becomes greater than the power supply VCC of the drive circuit 510, for example, several tens of volts to several kV. At this time, the output terminal voltage of the switching element Q1 V ＣＥ The voltage also reaches several tens of volts to several kV. In Embodiment 1, diode D1 is placed inside the drive circuit 10. In this case, the output terminal voltage V ＣＥ Depending on the maximum value, creepage distance must be ensured between the wiring connecting the output terminal of the switching element Q1 and the cathode of the diode D1, and between the cathode of the diode D1 and other components and wiring in the drive circuit 10. For example, if the voltage of the power supply V1 is 800V, a creepage distance of about 8mm is required.
[0079] In this embodiment, the drive circuit 510 is not subjected to a voltage higher than that of the power supply VCC, eliminating the need to secure a large creepage distance as in Embodiment 1. Therefore, the mounting area of the drive circuit 510 can be reduced.
[0080] The technical features described in each embodiment may be used in combination as appropriate.
[0081] 10 Drive circuit, 12 Output voltage detection circuit, 14 Selection circuit, 81, 82 Control circuit, 83 Output voltage detection circuit, 100, 200 Semiconductor device, 210 Drive circuit, 212 Output voltage detection circuit, 300 Semiconductor device, 310 Drive circuit, 320 DeSAT detection circuit, 322 Gate voltage monitoring circuit, 324 Control circuit, 400 Semiconductor device, 410 Drive circuit, 414 Selection circuit, 500 Semiconductor device, 510 Drive circuit, 512 Voltage detection circuit, Buf1 First buffer, Buf2 Second buffer, C1, C2 Capacitors, D1, D2, D3, D4 Freewheeling diode, I1 Constant current source, L1 Load, Q1, Q2 Switching elements: R1, R2, R3, R4, R5, R6, R7, R11, R12, R13, R14, R15, S1, S2, S3 Switch, U1 Comparator, U11 Analog comparator, U2 Comparator
Claims
1. A drive circuit comprising: a first buffer connected to the gate terminal of a switching element having a first terminal, a second terminal, and a gate terminal for switching the on / off state between the first terminal and the second terminal, with the gate drive voltage as input; a first resistor connected between the first buffer and the gate terminal; a selection circuit configured to output the higher of a tracking voltage that follows the output terminal voltage between the first terminal and the second terminal of the switching element and the gate drive voltage; a second buffer connected to the gate terminal with the output of the selection circuit as input; and a second resistor connected between the second buffer and the gate terminal, wherein the gate threshold voltage of the switching element is higher than the output terminal voltage when the rated current of the switching element is energized.
2. The drive circuit according to claim 1, characterized in that the output terminal voltage is supplied to the cathode, a bias voltage or current source is connected to the anode, and the first diode outputs the voltage of the anode as the tracking voltage.
3. The drive circuit according to claim 1, further comprising a resistive voltage divider circuit that resistively divides the output terminal voltage and outputs it as the tracking voltage.
4. The drive circuit according to any one of claims 1 to 3, characterized in that the selection circuit comprises a second diode to which the tracking voltage is supplied to the anode and the second buffer is connected to the cathode, and a third diode to which the gate drive voltage is supplied to the anode and the second buffer is connected to the cathode.
5. The drive circuit according to claim 4, characterized in that the selection circuit comprises a pull-down resistor connected to the cathode of the second diode and the cathode of the third diode, and a capacitor connected in parallel with the pull-down resistor.
6. The drive circuit according to claim 2, characterized in that the first diode is provided within the package of the switching element.
7. A drive circuit according to any one of claims 1 to 6, comprising: a detection circuit configured to detect whether the output terminal voltage is greater than a predetermined first threshold voltage; a control circuit that reduces the gate drive voltage when it is detected that the output terminal voltage is greater than the first threshold voltage; and a mask circuit configured to mask the output terminal voltage input to the detection circuit when the switching element is turned off, wherein the mask circuit does not mask the output terminal voltage input to the detection circuit for a predetermined period from the start of the turn-off operation.
8. The drive circuit according to claim 7, characterized in that the mask circuit masks the output terminal voltage input to the detection circuit when the voltage at the gate terminal falls below a predetermined second threshold voltage after the start of the turn-off operation.
9. A semiconductor device comprising: a drive circuit according to any one of claims 1 to 8; and the switching element.
10. The semiconductor device according to claim 9, characterized in that the switching element is formed of a wide-bandgap semiconductor.
11. The semiconductor device according to claim 10, characterized in that the wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.