Memory system and method

Abstract

This memory system comprises a temperature sensor, a capacitor, a power supply circuit, a volatile first memory, a nonvolatile second memory, and a controller. At the time of a power interruption, the power supply circuit starts generating power by using electric energy stored in the capacitor. The controller executes a capacitance test operation one or more times at different timings. In the capacitance test operation, the controller acquires a capacitance measurement value and a temperature detection value of the capacitor. When the temperature detection value is a first value, the controller sets a second value as a capacitance threshold, and when the temperature detection value is a third value lower than the first value, the controller sets a fourth value smaller than the second value as the capacitance threshold. The controller transitions from a first operation mode to a second operation mode in response to the capacitance measurement value becoming smaller than the capacitance threshold value.

Description

Memory System and Method

[0001] This embodiment relates to a memory system and method.

[0002] A memory system is known that includes a non-volatile memory that functions as storage and a volatile memory that functions as a buffer for data transfer between a host and the non-volatile memory.

[0003] The memory system may be configured to perform a PLP (Power Loss Protection) operation. The PLP operation is an operation to save the data stored in the volatile memory to the non-volatile memory in response to a power loss. By the PLP operation, the data buffered in the volatile memory is prevented from being lost from the memory system.

[0004] Such a memory system is equipped with a capacitor used as a power supply source after a power failure. The PLP operation is executed using the electrical energy stored in the capacitor. However, mounting a large-capacity capacitor in the memory system contributes to an increase in the cost of the memory system.

[0005] US Patent Application Publication No. 2016 / 0239235, US Patent Application Publication No. 2021 / 0074336, US Patent Application Publication No. 2020 / 0064430, US Patent No. 10020723

[0006] One embodiment aims to provide a memory system and method that enable suppressing the set capacitance of the mounted capacitor.

[0007] According to one embodiment, the memory system is connectable to a host. The memory system comprises a temperature sensor, a capacitor, a power supply circuit, a volatile first memory, a non-volatile second memory, and a controller. The power supply circuit charges the capacitor and generates the second power using the first power while the first power is supplied from an external source. The power supply circuit starts generating the second power using the electrical energy stored in the capacitor in response to a power interruption of the first power. The power supply circuit measures the capacitance of the capacitor. The controller is driven by the second power. The controller performs a write operation, writing data received from the host to the second memory. In the first operating mode, the controller uses the first memory as a buffer to perform the write operation. The controller performs a capacitance test operation one or more times at different timings. In the capacitance test operation, the controller has the power supply circuit measure the capacitance of the capacitor to obtain a capacitance measurement value, which is the measured value of the capacitor's capacitance, and obtains a temperature detection value from the temperature sensor. In the capacity test operation, the controller sets the second value as the capacity threshold if the detected temperature is the first value, and sets the fourth value, which is smaller than the second value, as the capacity threshold if the detected temperature is the third value, which is lower than the first value. In the capacity test operation, the controller further compares the measured capacity with the capacity threshold. In the capacity test operation, the controller transitions from the first operating mode to the second operating mode as the measured capacity becomes smaller than the capacity threshold. In response to a power outage, the controller stops the write operation and writes any data from the first memory that has not yet been written to the second memory to the second memory.

[0008] A diagram showing an example of the configuration of the memory system according to the first embodiment. A diagram showing the flow of data and power in the memory system according to the first embodiment while power is supplied from the host. A diagram showing the flow of data and power in the memory system according to the first embodiment when a power outage occurs. A diagram showing an example of the correspondence between the capacitance threshold and temperature according to the first embodiment. A diagram showing another example of the correspondence between the capacitance threshold and temperature according to the first embodiment. A diagram showing an example of the configuration of the controller according to the first embodiment. A flowchart showing an example of the operation of the PLP capacitor health check according to the first embodiment. A flowchart showing an example of the operation of outputting the PLP capacitor health status of the memory system according to the first embodiment. A diagram for explaining the method of transitioning between operating modes of the memory system according to the second embodiment. A diagram for explaining the trigger for transitioning to an abnormal mode according to the third embodiment. A flowchart showing an example of the operation of measuring the capacitance of the PLP capacitor according to the third embodiment. A flowchart showing an example of the operation of the memory system when temperature is detected according to the third embodiment. A diagram for explaining an example of the method of acquiring the capacitance estimation line according to the fourth embodiment.

[0009] The memory system and method according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0010] (First Embodiment) Figure 1 is a diagram showing an example of the configuration of a memory system according to the first embodiment.

[0011] As shown in Figure 1, the memory system SYS may be connected to the host HS via signal lines and power lines. The host HS may be, for example, a personal computer, a portable information terminal, or a server. The memory system SYS can receive various requests from the host HS via signal lines. These requests may include write requests or read requests. The memory system SYS also receives power from the host HS via power lines. The power source does not necessarily have to be built into the host HS. The memory system SYS may also receive power from an external device, different from the host HS.

[0012] The memory system SYS comprises a controller 1, NAND flash memory (NAND memory) 2, DRAM (Dynamic Random Access Memory) 3, PLP-IC (Power Loss Protection-Integrated Circuit) 4, PLP capacitor 5, power supply IC (Power Management Integrated Circuit) 6, and a temperature sensor 7.

[0013] Furthermore, the NAND flash memory 2, DRAM 3, PLP-IC 4, and temperature sensor 7 are each connected to the controller 1 by signal lines. The PLP-IC 4 is connected to the host HS by power lines. The PLP capacitor 5 is connected to the PLP-IC 4 by power lines. The power supply IC 6 is connected to the PLP-IC 4 by power lines. The controller 1, NAND flash memory 2, and DRAM 3 are each connected to the power supply IC 6 by power lines.

[0014] The temperature sensor 7 detects temperature. In this specification, the temperature detected by the temperature sensor 7 is considered to be the temperature of the memory system SYS. The controller 1 obtains the temperature detection value from the temperature sensor 7 and uses the obtained temperature detection value for various controls.

[0015] NAND flash memory 2 is a storage device that stores data requested to be written from the host HS. Note that any non-volatile memory can be used as storage, not just NAND flash memory. NAND flash memory 2 is an example of a second memory.

[0016] DRAM3 is a volatile memory used as buffer memory, cache memory, and a storage area where firmware programs are loaded. DRAM3 is an example of the first memory.

[0017] Furthermore, the volatile memory is not limited to DRAM 3; any memory can be used. For example, the memory system SYS may include SRAM (Static Random Access Memory) instead of DRAM 3, or in addition to DRAM 3. Some or all of the volatile memory may be integrated into the controller 1.

[0018] Controller 1 controls the memory system SYS. As part of controlling the memory system SYS, Controller 1 performs write and read operations. A write operation is the operation of writing data requested to be written from the host HS and received from the host HS to the NAND flash memory 2. A read operation is the operation of reading data requested to be read from the host HS from the NAND flash memory 2 and transferring that data to the host HS. Hereafter, write and read operations will be collectively referred to as host transfer operations. Data requested to be written from the host HS will be referred to as write data. Data requested to be read from the host HS will be referred to as read data. Controller 1 may be implemented as a SoC (System-on-a-Chip).

[0019] Furthermore, in response to a power outage, controller 1 stops the host transfer operation and performs a PLP operation. A power outage occurs when the power supply from host HS is interrupted. The PLP operation is the operation of writing data that has been buffered in DRAM 3 and has not yet been written to NAND flash memory 2 to NAND flash memory 2.

[0020] The PLP capacitor 5 stores electrical energy used to drive the memory system SYS after a power outage. The electrical energy stored in the PLP capacitor 5 enables the execution of PLP operation. The PLP capacitor 5 is composed of one or more capacitors. The types of capacitors that make up the PLP capacitor 5 are not limited to a specific type. For example, the PLP capacitor 5 may be composed of aluminum electrolytic capacitors or tantalum polymer capacitors.

[0021] PLP-IC4 is an integrated circuit that receives power from the host HS. PLP-IC4 charges the PLP capacitor 5 using the power supplied from the host HS. In addition, PLP-IC4 generates power using the electrical energy stored in the PLP capacitor 5 in response to a power outage. PLP-IC4 supplies power to the power supply IC6, either using the power supplied from the host HS or the power generated using the electrical energy stored in the PLP capacitor 5.

[0022] The power supply IC 6 is an integrated circuit that uses power supplied from the PLP-IC 4 to generate power to drive the controller 1, the NAND flash memory 2, and the DRAM 3. The voltages for the power to drive the controller 1, the power to drive the NAND flash memory 2, and the power to drive the DRAM 3 may or may not be the same.

[0023] Refer to Figures 2 and 3 to explain the details of the PLP operation.

[0024] Figure 2 shows the flow of data and power in the memory system SYS according to the first embodiment while power is supplied from the host HS.

[0025] As shown in Figure 2, while power is supplied from the host HS, the PLP-IC4 supplies power from the host HS to the power supply IC6. Furthermore, the PLP-IC4 uses the power supplied from the host HS to charge the PLP capacitor 5.

[0026] The power supply IC 6 generates power at a predetermined voltage using the power supplied from the PLP-IC 4. The power supply IC 6 then supplies the generated power to the controller 1, the NAND flash memory 2, and the DRAM 3.

[0027] Controller 1 uses the power supplied from power supply IC 6 to perform host transfer operations.

[0028] In host transfer operations, controller 1 can use DRAM 3 as a buffer for write data and read data. For example, in a write operation, controller 1 stores (buffers) the write data received from host HS in DRAM 3 and transfers the write data stored in DRAM 3 to NAND flash memory 2. In a read operation, controller 1 reads the read data from NAND flash memory 2 and stores (buffers) it in DRAM 3, and transfers the read data stored in DRAM 3 to host HS.

[0029] Figure 3 shows the flow of data and power in the memory system SYS according to the first embodiment when a power outage occurs.

[0030] The PLP-IC4 generates power using the electrical energy stored in the PLP capacitor 5 through charging, and supplies the generated power to the power supply IC 6.

[0031] The power supply IC 6 generates power at a predetermined voltage using the power supplied from the PLP-IC 4, just as when power is supplied from the host HS. The power supply IC 6 then supplies the generated power to the controller 1, the NAND flash memory 2, and the DRAM 3.

[0032] Controller 1 stops host transfer operations in response to power outages and then performs PLP operations using power supplied from power supply IC 6.

[0033] In PLP operation, the controller 1 writes data that has been buffered in the DRAM 3 but has not yet been written to the NAND flash memory 2 to the NAND flash memory 2.

[0034] The data written to the NAND flash memory 2 by the PLP operation includes write data that has not yet been written to the NAND flash memory 2. As mentioned above, in the write operation, the DRAM 3 is used as a buffer for the write data. Therefore, the write data buffered in the DRAM 3 may include write data that has not yet been written to the NAND flash memory 2. In the PLP operation, write data that has not yet been written to the NAND flash memory 2 is targeted for writing to the NAND flash memory 2.

[0035] In addition, the memory system SYS may be configured such that management information is cached in DRAM 3 and the management information in DRAM 3 is updated as needed. In such cases, during PLP operation, the management information or the updated portion of the management information may also be included as targets for writing to the NAND flash memory 2 during PLP operation.

[0036] The method for detecting a power outage and the method by which the controller 1 recognizes a power outage are not limited to any particular method. For example, power outage detection is performed by the PLP-IC 4. The PLP-IC 4 monitors the voltage of the power line connecting the host HS and the PLP-IC 4. When the voltage of the power line falls below a threshold, the PLP-IC 4 determines that a power outage has occurred. In response to determining that a power outage has occurred, the PLP-IC 4 notifies the controller 1 that a power outage has occurred and starts generating power using the electrical energy stored in the PLP capacitor 5. Therefore, the PLP-IC 4 and the power supply IC 6 can continue to generate power to drive the memory system SYS for a while even after a power outage has occurred.

[0037] Note that PLP-IC4 and power supply IC6 are examples of power supply circuits. As explained with reference to Figures 2 and 3, while power is supplied from the host HS, PLP-IC4 and power supply IC6 use the power supplied from the host HS to charge the PLP capacitor 5 and generate power to supply to the controller 1, etc. In response to a power outage, that is, when the power supply from the host HS is interrupted, PLP-IC4 and power supply IC6 start generating power to supply to the controller 1, etc., using the electrical energy stored in the PLP capacitor 5.

[0038] The power supplied from the host HS is an example of the first power. The power supplied by the power supply IC 6 to the controller 1, etc., is an example of the second power.

[0039] Next, we will explain how to select the capacitors that make up the PLP capacitor 5.

[0040] In the event of a power outage, the PLP operation is performed using the electrical energy stored in the PLP capacitor 5. Therefore, the PLP capacitor 5 must have a capacity to store at least enough electrical energy to complete the PLP operation. The amount of electrical energy required to complete the PLP operation is referred to as the amount of electrical energy needed for the PLP operation, or more simply, the amount of energy required for the PLP.

[0041] The amount of energy required for the PLP changes with the temperature of the memory system SYS. For example, in controller 1, the higher the temperature of controller 1, the greater the leakage current in controller 1, and this increase in leakage current increases the amount of energy required for each operation performed by controller 1. Therefore, even if there are variations from memory system SYS to memory system SYS, the higher the temperature of the memory system SYS, the greater the amount of energy required for the PLP.

[0042] The capacitance of the PLP capacitor 5 also varies depending on the temperature. For example, in the temperature range guaranteed for the operation of the memory system SYS, the capacitor used as the PLP capacitor 5 is based on the room temperature, and has the temperature-dependent characteristic that the higher the temperature, the greater the capacitance of the PLP capacitor 5.

[0043] Also, the capacitance of the PLP capacitor 5 decreases due to aging deterioration.

[0044] The designer of the memory system SYS determines the rated capacitance and the number of capacitors that make up the PLP capacitor 5. Even after aging deterioration, the rated capacitance and the number of capacitors are determined such that the amount of electrical energy stored in the PLP capacitor 5 is not less than the required PLP energy amount at any temperature within the operation-guaranteed temperature range of the memory system SYS. Hereinafter, the sum of the rated capacitances of all the capacitors that make up the PLP capacitor 5 is referred to as the set capacitance of the PLP capacitor 5.

[0045] As one method for the memory system SYS itself to diagnose how much the capacitance of the PLP capacitor 5 has changed with respect to the set capacitance, PLP capacitor health check can be considered.

[0046] The PLP capacitor health check is a diagnostic operation for PLP capacitors, and the results can be viewed on the host HS as SMART (Self-Monitoring Analysis and Reporting Technology) information. It is recommended to perform the PLP capacitor health check at predetermined time intervals, such as every 15 minutes. The PLP capacitor health check measures the capacitance of the PLP capacitor. If the value measured by the PLP capacitor health check (hereinafter referred to as the capacitance measurement value) is equal to or greater than the capacitance threshold, the PLP capacitor is considered healthy. A healthy PLP capacitor means that it maintains a capacitance that is capable of storing the amount of electrical energy required for PLP operation. In other words, a healthy PLP capacitor means that the capacitance of PLP capacitor 5 is greater than the amount of electrical energy required for PLP operation. If the capacitance measurement value is less than the capacitance threshold, the PLP capacitor is considered unhealthy. A PLP capacitor being unhealthy means that its capacitance is less than the amount of electrical energy required for PLP operation.

[0047] The memory system SYS is configured to perform a PLP capacitor health check. Based on the capacitance measurement values ​​obtained from the PLP capacitor health check and the capacitance threshold, the memory system SYS calculates an index of the health of the PLP capacitor 5 and outputs the calculated index to the host HS. The index of the health of the PLP capacitor is called the PLP capacitor health status. The PLP capacitor health status is a numerical information expressed as a percentage, where 1% or more indicates that the PLP capacitor is healthy, and 0% indicates that the PLP capacitor is not healthy. The memory system SYS responds with the PLP capacitor health status in response to a predetermined command from the host HS.

[0048] The technology to be compared with the first embodiment will be described. The technology to be compared with the first embodiment is denoted as a comparative example. In the comparative example, a value corresponding to the maximum amount of PLP required energy in the operation guarantee temperature range of the memory system is set as the capacity threshold. The value corresponding to the maximum amount is either the maximum amount or a value obtained by adding a predetermined margin to the maximum amount. The set capacity of the PLP capacitor is determined so that the capacity of the PLP capacitor is equal to or greater than the capacity threshold at any temperature within the operation guarantee temperature range of the memory system. The maximum value of the PLP required energy amount of the memory system is determined by referring to the value of the highest temperature within the operation guarantee temperature range. Also, the capacity of the PLP capacitor is determined by referring to the value of the lowest temperature within the operation guarantee temperature range.

[0049] However, as described above, the amount of PLP required energy increases as the temperature of the memory system increases. On the other hand, the capacity of the PLP capacitor decreases as the temperature decreases. Therefore, according to the comparative example, the set capacity of the PLP capacitor is determined based on the comparison between the amount of PLP required energy when the temperature is high and the capacity of the PLP capacitor when the temperature is low.

[0050] Actually, the amount of PLP required energy increases as the temperature increases, but the capacity of the PLP capacitor also increases. The capacity of the PLP capacitor decreases as the temperature decreases, but the amount of PLP required energy also decreases. Therefore, according to the comparative example, the set capacity of the PLP capacitor will be overestimated. And when a capacitor with the set capacity estimated by the comparative example is mounted in the memory system, the cost of the memory system will increase.

[0051] Therefore, according to the first embodiment, instead of making the capacity threshold constant as in the comparative example, the capacity threshold is made temperature-dependent.

[0052] FIG. 4 is a diagram showing an example of the correspondence relationship between the capacity threshold and the temperature according to the first embodiment. In this figure, the horizontal axis represents the temperature. The vertical axis represents the amount of electrical energy or the capacity. The amount of electrical energy shown on the vertical axis is converted into the capacity based on the relational expression between the electrostatic energy and the charge / voltage.

[0053] Tmin is the lower limit of the operating temperature range for the memory system SYS, and Tmax is the upper limit of the operating temperature range for the memory system SYS. The PLP energy requirement is shown by a dashed line.

[0054] In the example shown in Figure 4, the energy required for the PLP is E0 at temperature Tmin and E1 at temperature Tmax, which is greater than E0. In this example, the energy required for the PLP increases linearly with temperature.

[0055] In the temperature range above a certain temperature Tb within the operating temperature range, the capacity threshold is set to E1, which is the same value as the PLP energy requirement at temperature Tmax. In other words, if the temperature of the memory system SYS is higher than temperature Tb, the capacity threshold is E1. In the temperature range below temperature Tb within the operating temperature range, the capacity threshold is set to C1, which is the same value as the PLP energy requirement at temperature Tb. In other words, if the temperature of the memory system SYS is lower than temperature Tb, the capacity threshold is C1. Therefore, at any temperature within the operating temperature range, the capacity threshold is greater than or equal to the PLP energy requirement.

[0056] The designer determines the set capacitance of the PLP capacitor 5 such that its capacitance is equal to or greater than the capacitance threshold at any temperature within the operating temperature range. For example, if the set capacitance of the PLP capacitor 5 is determined so that it has the capacitance shown by the dashed line in Figure 4, it is possible to complete PLP operation at any temperature within the operating temperature range. Furthermore, regardless of the temperature at which the PLP capacitor health check is performed, it is possible to obtain a value of 1% or more as the PLP capacitor health status.

[0057] In this comparative example, the set capacitance of the PLP capacitor is determined such that the capacitance of the PLP capacitor is E1 or greater at any temperature within the operating temperature range. That is, for example, at temperature Tmin, the capacitance of the PLP capacitor is E1 or greater. Therefore, the capacitance of the PLP capacitor is significantly greater than the capacitance shown by the dashed line in Figure 4.

[0058] In contrast, according to the first embodiment, as can be seen from the dashed line in Figure 4, it is permissible for the capacitance of the PLP capacitor 5 to be smaller than E1 at temperature Tmin. In other words, it is possible to set a smaller capacitance for the PLP capacitor 5 compared to the comparative example.

[0059] Furthermore, the correspondence between the capacity threshold and temperature can be modified in various ways, as long as, when the temperature is the first value, the second value is used as the capacity threshold, and when the temperature is the third value (lower than the first value), the fourth value (smaller than the second value) is used as the capacity threshold. In the example shown in Figure 4, a certain temperature higher than temperature Tb corresponds to the first value, and E1 corresponds to the second value. A certain temperature lower than temperature Tb corresponds to the third value, and C1 corresponds to the fourth value.

[0060] Figure 5 shows another example of the relationship between the capacity threshold and temperature according to the first embodiment.

[0061] In the example shown in Figure 4, the capacitance threshold is configured to vary between two values. In the example shown in Figure 5, the capacitance threshold is configured to vary in steps between three or more values. More specifically, the capacitance threshold is finely adjusted according to temperature so that the difference between the capacitance threshold and the required energy amount for the PLP is as small as possible at any temperature within the operating temperature range. Therefore, there is room to further reduce the set capacitance of the PLP capacitor 5 compared to the example shown in Figure 4.

[0062] For example, if the set capacitance of the PLP capacitor 5 is determined so that it has the capacitance shown by the dashed line in Figure 5, the set capacitance of the PLP capacitor 5 can be reduced compared to the example shown in Figure 4.

[0063] The information recording the correspondence between the capacitance threshold and temperature shown in Figure 4 or Figure 5 (referred to as threshold setting information) is stored in a predetermined non-volatile memory area (e.g., NAND flash memory 2) during manufacturing. When performing a PLP capacitor health check, the controller 1 acquires a temperature detection value from the temperature sensor 7. The controller 1 then obtains a value associated with the temperature detection value by referring to the threshold setting information and sets the acquired value as the capacitance threshold.

[0064] The PLP capacitor health check performed by controller 1 is an example of a capacitance test operation.

[0065] Here, we will explain the operation when the capacitor degrades more than the designer of the memory system SYS anticipated, and the capacitance measurement obtained by the PLP capacitor health check falls below the capacitance threshold. As mentioned above, the capacitance of the PLP capacitor 5 decreases due to aging. If the capacitance measurement obtained by the PLP capacitor health check falls below the capacitance threshold (in other words, if the measured capacitance of the PLP capacitor 5 falls below the capacitance threshold), it is presumed that the PLP operation cannot be completed when the power is cut off. In such a case, the controller 1 transitions from normal mode to abnormal mode.

[0066] The normal mode is a mode in which controller 1 uses DRAM 3 as a buffer to perform host transfer operations, and is guaranteed to complete PLP operations even if a power outage occurs. In contrast, the abnormal mode is a mode in which write operations among the host transfer operations are prohibited, or write operations can be performed under predetermined constraints.

[0067] Specifically, an abnormal mode is, for example, read-only mode. In read-only mode, read operations are possible, but write operations are prohibited. In other words, in read-only mode, controller 1 executes read requests from host HS, but does not execute write requests from host HS. In read-only mode, write data is not buffered in DRAM 3. Therefore, it is possible to eliminate or significantly reduce the amount of data that should be written to NAND flash memory 2 by PLP operation.

[0068] Alternatively, an unconventional mode is write-through mode. In write-through mode, read and write requests from the host HS can be executed, but the data to be written is written to the NAND flash memory 2 without being buffered in the DRAM 3. With write-through mode, as with read-only mode, it is possible to eliminate or significantly reduce the amount of data that should be written to the NAND flash memory 2 by PLP operation.

[0069] Alternatively, the non-normal mode is the warning mode. After transitioning from normal mode to warning mode, the memory system SYS notifies the host HS via SMART information that "a hardware error has occurred in the memory system SYS." "A hardware error has occurred in the memory system SYS" means that the memory system SYS is unable to complete PLP operations when the power is lost. In warning mode, the memory system SYS can perform read and write operations as in normal mode, but there is no guarantee that the memory system SYS will complete PLP operations.

[0070] Note that the normal mode is an example of the first operating mode, and the abnormal mode is an example of the second operating mode.

[0071] Figure 6 shows an example of the configuration of the controller 1 according to the first embodiment.

[0072] In the example shown in Figure 6, the controller 1 comprises a CPU (Central Processing Unit) 11, a host interface (I / F) circuit 12, and a memory interface (I / F) circuit 13.

[0073] The host interface circuit 12 is responsible for communication between the controller 1 and the host HS. The memory interface circuit 13 is responsible for communication between the controller 1 and the NAND flash memory 2.

[0074] The CPU 11 is a processor capable of executing computer programs. Based on the firmware program, the CPU 11 implements various functions as a controller for the memory system SYS. Specifically, the CPU 11 controls various operations such as host transfer operations, PLP operations, PLP capacitor health checks, and setting the operating mode of the memory system SYS.

[0075] Furthermore, some or all of the controller functions of the memory system SYS may be comprised of logic circuits. Some or all of the controller functions of the memory system SYS may be comprised of circuits such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).

[0076] Next, the operation of the memory system SYS according to the first embodiment will be described.

[0077] Figure 7 is a flowchart showing an example of the operation of a PLP capacitor health check according to the first embodiment.

[0078] First, the controller 1 instructs the PLP-IC 4 to measure the capacitance of the PLP capacitor 5 (S101).

[0079] The PLP-IC4 measures the capacitance of the PLP capacitor 5 in response to instructions from the controller 1 (S102). The PLP-IC4 transmits the measured capacitance value (i.e., capacitance measurement value) of the PLP capacitor 5 to the controller 1, and the controller 1 acquires the capacitance measurement value.

[0080] The controller 1 acquires the temperature detection value from the temperature sensor 7 (S103).

[0081] Furthermore, the controller 1 may be configured to acquire temperature detection values ​​from the temperature sensor 7 at predetermined short time intervals, such as every second, for use in other operations of the PLP capacitor health check. If the controller 1 is configured in this way, in S103, the controller 1 may acquire the latest temperature detection value from a series of temperature detection values ​​acquired sequentially at predetermined short time intervals.

[0082] Controller 1 sets a value corresponding to the temperature detection value obtained by the process in S103 as the capacity threshold (S104). Controller 1 sets the capacity threshold by referring to the threshold setting information explained using Figure 4 or Figure 5, etc.

[0083] Controller 1 records pairs of capacity measurements and capacity thresholds (S105).

[0084] Furthermore, the recording location of the capacity measurement value pair and capacity threshold value pair is not limited to a specific location. For example, controller 1 records the capacity measurement value pair and capacity threshold value pair in a non-volatile storage area such as NAND flash memory 2.

[0085] Controller 1 determines whether the measured capacity is less than the capacity threshold (S106).

[0086] If the measured capacity is less than the capacity threshold (S106: Yes), controller 1 transitions to an abnormal mode (S107). Following the example described above, controller 1 transitions to read-only mode, write-through mode, or warning mode. If controller 1 is already in an abnormal mode, the process in S107 may be skipped.

[0087] If the measured capacity is not smaller than the capacity threshold (S106: No), or after the processing in S107, the controller 1 determines whether a predetermined amount of time has elapsed since the last execution of the processing in S101 (S108). For example, if the controller 1 is set to perform a PLP capacitor health check at 15-minute intervals, in S108 the controller 1 determines whether 15 minutes have elapsed since the last execution of the processing in S101.

[0088] If the predetermined time has not yet elapsed (S108: No), the controller 1 executes the process in S108 again. If the predetermined time has elapsed (S108: Yes), control transitions to S101.

[0089] Thus, controller 1 performs a PLP capacitor health check at predetermined intervals. If the measured capacitance value is less than the capacitance threshold, it cannot be guaranteed that the capacitance of the PLP capacitor 5 is greater than the amount of electrical energy required for PLP operation. Therefore, controller 1 transitions to an abnormal mode as the measured capacitance value falls below the capacitance threshold.

[0090] In the example shown in Figure 7, once controller 1 transitions to an abnormal mode, controller 1 does not return to normal mode. Alternatively, even after controller 1 has transitioned to an abnormal mode, if the capacity measurement value recovers to above the capacity threshold, controller 1 may return from abnormal mode to normal mode.

[0091] Figure 8 is a flowchart showing an example of the operation of outputting the PLP capacitor health status of the memory system SYS according to the first embodiment.

[0092] When controller 1 receives a SMART command from host HS (S201), it calculates the PLP capacitor health status based on the last recorded pair of capacitance measurement value and capacitance threshold value (S202). Then, controller 1 responds to host HS with the PLP capacitor health status obtained from the calculation (S203). The operation of outputting the PLP capacitor health status then ends.

[0093] As described above, according to the first embodiment, the controller 1 performs a PLP capacitor health check once or more at different timings (see, for example, S101 to S106 in Figure 7). In the PLP capacitor health check, the controller 1 has the PLP-IC 4 measure the capacitance of the PLP capacitor 5 and obtains the capacitance measurement value, and obtains the temperature detection value from the temperature sensor 7 (see, for example, S101 to S103 in Figure 7). Then, if the temperature detection value is a first value, the controller 1 sets the second value as the capacitance threshold, and if the temperature detection value is a third value lower than the first value, the controller 1 sets a fourth value smaller than the second value as the capacitance threshold (see, for example, S104 in Figures 4, 5, and 7). Then, the controller 1 compares the capacitance measurement value with the capacitance threshold (see, for example, S106 in Figure 7). In the PLP capacitor health check, the controller 1 transitions to an abnormal mode as the capacitance measurement value becomes smaller than the capacitance threshold (see, for example, S107 in Figure 7). If a power outage occurs, the controller 1 stops the write operation in response to the power outage. The controller 1 writes any data remaining in the DRAM 3 that has not yet been written to the NAND flash memory 2 to the NAND flash memory 2 (see, for example, Figures 2 and 3).

[0094] Therefore, when determining the set capacitance of the PLP capacitor 5 so that its capacitance is equal to or greater than the capacitance threshold, it is possible to reduce the set capacitance of the PLP capacitor 5 compared to the comparative example. In other words, it becomes possible to suppress the set capacitance of the installed capacitor.

[0095] Furthermore, according to the first embodiment, the non-normal mode is read-only mode, write-through mode, or warning mode.

[0096] In both read-only and write-through operating modes, the write data is not buffered in the DRAM 3, thus eliminating or reducing the data that is written to the NAND flash memory 2 by the PLP operation. This reduces the power required for the PLP operation, making it possible to complete the PLP operation or even omit the PLP operation altogether, even for capacitors whose measured capacity is below the capacity threshold.

[0097] In warning mode, controller 1 does not need to guarantee that the PLP operation will be completed. In warning mode, the memory system SYS can continue writing operations in the same way as in normal mode as long as a power outage does not occur. In addition, it can promptly notify the host that the capacitor is no longer able to complete the PLP operation.

[0098] In the first embodiment, the controller 1 sets the capacity threshold corresponding to the temperature detection value by referring to information recording the correspondence between the capacity threshold and temperature shown in Figure 4 or Figure 5. The correspondence between the capacity threshold and temperature may be defined by a function. That is, the capacity threshold may be expressed as a function of temperature. In this function, the order of temperature may be first or higher.

[0099] In the first embodiment, the controller 1 responds to the host HS with the PLP capacitor health status in response to a SMART command from the host HS. The PLP capacitor health status is an indicator of the health of the PLP capacitor 5, calculated using the capacitance measurement value and the capacitance threshold value.

[0100] (Second Embodiment) In the second embodiment, a low-power mode is used as yet another example of an atypical mode. In the description of the second embodiment, the mode in which the memory system SYS operates at rated power consumption is referred to as the normal mode, and the mode in which the power consumption of the memory system SYS is suppressed to a level lower than the rated power consumption is referred to as the low-power mode.

[0101] The second embodiment differs from the first embodiment only in the non-normal mode and the operation for transitioning to the non-normal mode. All other aspects of the non-normal mode and the operation for transitioning to the non-normal mode are the same as in the first embodiment.

[0102] Figure 9 is a diagram illustrating the transition method of the operating modes of the memory system SYS according to the second embodiment. In this figure, the horizontal axis represents temperature, and the vertical axis represents electrical energy or capacity. The electrical energy shown on the vertical axis has been converted to the dimension of capacity.

[0103] Figure 9 shows lines indicating the PLP energy requirements for each of the following modes: normal mode, first low power consumption mode, and second low power consumption mode. Both the first and second low power consumption modes are modes in which power consumption is suppressed to a level lower than the rated power consumption, but in the second low power consumption mode, power consumption is suppressed to an even lower level compared to the first low power consumption mode.

[0104] The method for suppressing power consumption is as follows: Controller 1 suppresses power consumption by intentionally limiting the number of commands processed per unit time. In other words, by controller 1 controlling the upper limit of the number of commands processed per unit time, transitions between normal mode, first low-power mode, and second low-power mode are achieved. As the number of commands processed per unit time is suppressed, the data transfer rate during write operations decreases, and write operations are suppressed.

[0105] The amount of PLP energy required in the first low-power mode and the amount of PLP energy required in the second low-power mode increase with temperature, similar to the amount of PLP energy required in the normal mode. However, the lower the power consumption of the memory system SYS, the less energy is required for the PLP. Therefore, under common temperature conditions, the amount of PLP energy required in the first low-power mode is less than the amount of PLP energy required in the normal mode, and the amount of PLP energy required in the second low-power mode is less than the amount of PLP energy required in the first low-power mode.

[0106] Controller 1 performs a PLP capacitor health check at predetermined time intervals, as shown in Figure 7. Then, as the measured capacitance value falls below the capacitance threshold, Controller 1 transitions from normal mode to either the first low-power mode or the second low-power mode. Whether the transitioned operating mode is the first low-power mode or the second low-power mode is determined based on the relationship between the pair of capacitance measured values ​​and temperature detected values ​​obtained by the PLP capacitor health check, and the lines for the required PLP energy for the first low-power mode and the second low-power mode, respectively.

[0107] Information indicating the PLP energy requirements for the first low-power mode and the second low-power mode is pre-recorded in a predetermined non-volatile memory area (e.g., NAND flash memory 2). When the measured capacity falls below the capacity threshold, the controller 1 compares the pair of measured capacity and temperature detection values ​​with the PLP energy requirements for the first low-power mode and the second low-power mode. Through this comparison, the controller 1 identifies the mode in which the reduction in power consumption that allows the PLP operation to be completed is smaller. The controller 1 then transitions the operating mode of the memory system SYS to the identified mode.

[0108] For example, in Figure 9, if a PLP capacitor health check yields a pair of capacitance measurement value and temperature detection value shown at point Pm1, the controller 1 transitions from normal mode to abnormal mode because the capacitance measurement value is smaller than the capacitance threshold value corresponding to the temperature detection value. According to the lines for the PLP energy requirements in the first low-power mode and the second low-power mode, the PLP energy requirements in both the first low-power mode and the second low-power mode are less than or equal to the capacitance measurement value at the obtained temperature detection value. Therefore, PLP operation can be completed in either the first low-power mode or the second low-power mode. Accordingly, the controller 1 transitions the operating mode of the memory system SYS to the first low-power mode, which has a smaller reduction in power consumption than the first low-power mode.

[0109] Furthermore, taking into account manufacturing variations in the memory system SYS, the lines for the required PLP energy for the first low-power mode and the second low-power mode may be set so that there is a margin for the required PLP energy at each temperature within the operating temperature range.

[0110] Thus, in the second embodiment, the power consumption of the memory system SYS is suppressed in the non-normal mode. This makes it possible to complete the PLP operation as usual even if the measured capacitance of the capacitor is below the capacitance threshold in the normal mode.

[0111] (Third Embodiment) In the third embodiment, the controller 1 periodically measures the capacitance of the PLP capacitor 5, similar to the first and second embodiments. However, the details of the operation for measuring the capacitance of the PLP capacitor 5 and the trigger for transitioning to the abnormal mode differ from those of the first and second embodiments. Other matters are the same as in the first or second embodiment.

[0112] Figure 10 illustrates a trigger for transitioning to an abnormal mode according to a third embodiment. In this figure, the horizontal axis represents temperature, and the vertical axis represents electrical energy or capacity. The electrical energy shown on the vertical axis is converted to the dimension of capacity.

[0113] When Controller 1 measures the capacitance of the PLP capacitor 5, it estimates the relationship between the capacitance of the PLP capacitor 5 and temperature based on the capacitance measurement. Based on the estimated relationship, Controller 1 identifies the temperature range within the operating temperature range in which the capacitance of the PLP capacitor 5 is less than the required energy amount for the PLP.

[0114] Here, as an example of the correspondence between the capacitance of the PLP capacitor 5 and temperature, a first-order temperature function representing the capacitance of the PLP capacitor 5 is used. Furthermore, the value of the slope of the capacitance of the PLP capacitor 5 with respect to temperature is determined in advance by observation or estimation and recorded as a slope setting value in predetermined information. This information is stored in a predetermined non-volatile memory area (e.g., NAND flash memory 2) during manufacturing or other times. The controller 1 obtains a temperature function representing the capacitance of the PLP capacitor 5 based on the pair of capacitance measurement values ​​obtained by measuring the capacitance of the PLP capacitor 5 and the temperature detection value obtained from the temperature sensor 7 during the measurement of the capacitance of the PLP capacitor 5, as well as the slope setting value.

[0115] For example, if a pair of capacitance measurement values ​​and temperature detection values ​​is obtained at point Pm2, the controller 1 acquires a straight line of the slope of the slope setting value passing through point Pm2 (capacitance estimation line Lm2 in Figure 10) as the correspondence between the capacitance of the PLP capacitor 5 and the temperature.

[0116] In another example, if a pair of capacitance measurement values ​​and temperature detection values ​​is obtained at point Pm3, the controller 1 acquires a straight line of the slope of the slope set value passing through point Pm3 (capacitance estimation line Lm3 in Figure 10) as the correspondence between the capacitance of the PLP capacitor 5 and the temperature.

[0117] Controller 1 identifies the temperature range in which the capacity of the PLP capacitor 5 becomes smaller than the PLP energy requirement by comparing the capacity estimation line with the PLP energy requirement line. The PLP energy requirement line, like the slope setting value, is recorded in predetermined information, and this information is stored in a predetermined non-volatile memory area (e.g., NAND flash memory 2) during manufacturing.

[0118] The PLP energy requirement is expressed as a first-order function of temperature. For example, a first-order function of temperature representing the PLP energy requirement is stored in a predetermined non-volatile memory area as a PLP energy requirement line, that is, information representing the correspondence between the amount of electrical energy required for PLP operation and temperature. Note that the information representing the PLP energy requirement line is not limited to a first-order function of temperature. The information representing the PLP energy requirement line may be a second-order or higher function of temperature. The information representing the PLP energy requirement line may also be in table format.

[0119] The capacitance estimation line Lm2 does not intersect with the PLP required energy amount line within the operating temperature range, and exceeds the PLP required energy amount throughout the entire operating temperature range. In such a case, there is no temperature range within the operating temperature range where the capacitance of the PLP capacitor 5 is less than the PLP required energy amount. Therefore, when the capacitance estimation line Lm2 is obtained, the controller 1 does not transition from normal mode to abnormal mode due to the capacitance of the PLP capacitor 5.

[0120] The capacitance estimation line Lm3 intersects with the PLP required energy amount line at temperature Tcrs within the operating temperature range. Within the temperature range, at temperatures higher than Tcrs, the capacitance of the PLP capacitor 5 becomes smaller than the PLP required energy amount. Therefore, the controller 1 identifies the temperature range higher than Tcrs and below Tmax as the temperature range where the capacitance of the PLP capacitor 5 is smaller than the PLP required energy amount. The controller 1 then transitions to an abnormal mode if the temperature of the memory system SYS falls within the temperature range higher than Tcrs and below Tmax.

[0121] Hereafter, the temperature range in which the capacitance of the PLP capacitor 5 is less than the required energy amount for the PLP will be referred to as the target temperature range.

[0122] As the abnormal mode of the third embodiment, either the abnormal mode of the first embodiment or the abnormal mode of the second embodiment can be adopted.

[0123] Controller 1 measures the temperature of the memory system SYS even when measuring the capacitance of the PLP capacitor 5. After the target temperature range is determined, Controller 1 determines whether the temperature of the memory system SYS falls within the target temperature range each time the temperature of the memory system SYS is measured.

[0124] Figure 11 is a flowchart showing an example of the operation for measuring the capacitance of the PLP capacitor 5 according to the third embodiment. Note that the operations S301 to S306 shown in Figure 11 are an example of the capacitance test operation according to the third embodiment.

[0125] First, in steps S301 to S303, the same processing as in steps S101 to S103 shown in Figure 7 is performed. Through the processing in steps S301 to S303, the controller 1 acquires the measured capacity and temperature detection values. The temperature detection value acquired through the processing in step S303 is an example of the first temperature detection value.

[0126] After S303, the controller 1 acquires a capacitance estimation line based on the capacitance measurement value and the temperature detection value (S304). The controller 1 uses the slope setting value to acquire a straight line passing through the points formed by the pairs of capacitance measurement values ​​and temperature detection values ​​as the capacitance estimation line. The capacitance estimation line acquired in S304 is an example of the first correspondence relationship, which is the correspondence relationship between the capacitance and temperature of the PLP capacitor 5.

[0127] Controller 1 determines whether or not the target temperature range exists by comparing the capacity estimation line with the PLP required energy amount line (S305). The PLP required energy amount line is an example of a second correspondence relationship, which is the correspondence between the value corresponding to the amount of electrical energy required for PLP operation and temperature.

[0128] If a target temperature range exists (S305: Yes), the controller 1 stores the target temperature range (S306).

[0129] If controller 1 already has another target temperature range stored, in S306, the stored target temperature range is discarded and the target temperature range identified in S305 is newly stored.

[0130] If no target temperature range exists (S305: No), or after S306, the controller 1 determines whether a predetermined time has elapsed since the last execution of the process in S301 (S307). For example, if the controller 1 is set to measure the capacitance of the PLP capacitor 5 at 15-minute intervals, in S307 the controller 1 determines whether 15 minutes have elapsed since the last execution of the process in S301.

[0131] If the predetermined time has not yet elapsed (S307: No), the controller 1 executes the process in S307 again. If the predetermined time has elapsed (S307: Yes), control transitions to S301.

[0132] Figure 12 is a flowchart showing an example of the operation of the memory system SYS when temperature is detected, according to the third embodiment.

[0133] The controller 1 acquires a temperature detection value from the temperature sensor 7 (S401). The temperature detection value acquired in S401 is an example of a second temperature detection value.

[0134] Controller 1 determines whether the temperature detected value obtained in S401 falls within the target temperature range (S402). If the target temperature range does not exist, Controller 1 determines that the temperature detected value does not fall within the target temperature range.

[0135] If the detected temperature falls within the target temperature range (S402: Yes), controller 1 transitions to abnormal mode (S403). If controller 1 is already in abnormal mode, controller 1 skips the process in S403.

[0136] If the detected temperature value does not fall within the target temperature range (S402: No), or after S403, the controller 1 repeats the process of S401.

[0137] In the example shown in Figure 12, once controller 1 transitions to an abnormal mode, controller 1 does not return to normal mode. Alternatively, even after controller 1 transitions to an abnormal mode, if the temperature detection value is no longer included in the target temperature range, controller 1 may return to normal mode.

[0138] As described above, according to the third embodiment, in the capacitance test operation, the controller 1 has the PLP-IC 4 measure the capacitance of the PLP capacitor 5 and obtains the capacitance measurement value, and obtains the temperature detection value from the temperature sensor 7 (see, for example, S301 to S303 in Figure 11). Then, the controller 1 estimates the correspondence between the capacitance of the PLP capacitor 5 and the temperature based on the pair of capacitance measurement value and temperature detection value (see, for example, S304 in Figure 11). Then, based on the estimated correspondence, which is the capacitance estimation line, the controller 1 identifies the target temperature range, which is the temperature range in which the capacitance of the PLP capacitor 5 becomes smaller than the value corresponding to the amount of electrical energy required for PLP operation (see, for example, S305 and S306 in Figure 11). After the capacitance test operation, the controller 1 obtains a second temperature detection value from the temperature sensor 7 and transitions from normal mode to abnormal mode depending on whether the second temperature detection value falls within the target temperature range (see, for example, Figure 12).

[0139] When the memory system SYS is configured as described above, the designer can determine the set capacitance of the PLP capacitor 5 installed in the memory system SYS such that the estimated capacitance line Lm of the PLP capacitor 5, which is assumed to have deteriorated, exceeds the PLP energy requirement over the entire operating temperature range. When the set capacitance of the PLP capacitor 5 is determined to satisfy the above condition, it is possible to reduce the set capacitance of the PLP capacitor 5 compared to the comparative example, as in the first and second embodiments.

[0140] In addition, according to the third embodiment, the controller 1 identifies the target temperature range based on the first correspondence, which is the capacity estimation line, and the second correspondence, which is the PLP required energy amount line (see, for example, Figure 10).

[0141] The controller 1 may be configured to acquire the second temperature detection value at a shorter time interval than the measurement of the capacitance of the PLP capacitor 5. For example, the controller 1 may measure the capacitance of the PLP capacitor 5 every 15 minutes and acquire the second temperature detection value every second, in accordance with a predetermined standard or design.

[0142] In a configuration where the acquisition of the second temperature detection value is performed at a shorter time interval than the measurement of the capacitance of the PLP capacitor 5, the controller 1 can determine whether the temperature of the memory system SYS falls within the target temperature range each time the second temperature detection value is acquired. In other words, the controller 1 can determine whether the temperature of the memory system SYS falls within the target temperature range at a shorter time interval than the measurement of the capacitance of the PLP capacitor 5. This makes it possible to quickly detect when it becomes impossible to complete the PLP operation.

[0143] Note that the time interval for measuring the capacitance of the PLP capacitor 5, the time interval for acquiring the second temperature detection value, and the relative magnitudes of these two time intervals are not limited to the examples described above.

[0144] (Fourth Embodiment) In the third embodiment, the controller 1 acquired a capacity estimation line based on one pair of capacity measurement values ​​and temperature detection values. In the fourth embodiment, multiple pairs of capacity measurement values ​​and temperature detection values ​​are used to acquire the capacity estimation line. Other aspects of the operation of acquiring the capacity estimation line in the fourth embodiment are the same as in the third embodiment.

[0145] Figure 13 illustrates an example of a method for obtaining a capacity estimation line according to the fourth embodiment. In this figure, the horizontal axis represents temperature, and the vertical axis represents electrical energy or capacity. The electrical energy shown on the vertical axis has been converted to the dimension of capacity.

[0146] If multiple pairs of capacitance measurements and temperature detection values ​​are obtained through sequentially performed capacitance measurements of the PLP capacitor 5, the controller 1 obtains a capacitance estimation line by fitting these multiple pairs to a linear function.

[0147] In the example shown in Figure 13, a total of nine pairs of data, shown at points Pm10 to Pm18, are obtained by nine measurements of the capacitance of the PLP capacitor 5. The controller 1 obtains the capacitance estimation line Lmf by fitting these nine pairs of data to a linear function.

[0148] Thus, in the fourth embodiment, a capacity estimation line is obtained based on multiple pairs of capacity measurements and temperature detection values. Therefore, the memory system SYS does not require a slope setting value.

[0149] Furthermore, the temperature dependence of the capacitance of the PLP capacitor 5 may vary among multiple memory system SYSs. However, since a capacitance estimation line is obtained based on multiple pairs of capacitance measurement values ​​and temperature detection values, the controller 1 can obtain a highly accurate capacitance estimation line in each memory system SYS, regardless of the variation in the temperature dependence of the capacitance of the PLP capacitor 5. Therefore, the accuracy of detecting when it becomes impossible to complete PLP operation is improved.

[0150] In the fourth embodiment, a capacity estimation line is obtained based on multiple pairs of capacity measurements and temperature detection values. Therefore, the order of temperature in the function representing the capacity estimation line does not necessarily have to be first order. The order of temperature in the function representing the capacity estimation line may be second order or higher.

[0151] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0152] 1 Controller, 2 NAND flash memory, 3 DRAM, 4 PLP-IC, 5 PLP capacitor, 6 Power supply IC, 7 Temperature sensor, 11 CPU, 12 Host interface circuit, 13 Memory interface circuit, C1, E1 values, Lm2, Lm3, Lmf Capacitance estimation lines, Pm1, Pm2, Pm3, Pm10, Pm11, Pm12, Pm13, Pm14, Pm15, Pm16, Pm17, Pm18 points, Tb, Tcrs, Tmax, Tmin Temperature, SYS Memory system, HS Host.

Claims

1. A memory system connectable to a host, comprising: a temperature sensor; a capacitor; a power supply circuit configured to charge the capacitor and generate a second power using the first power supplied from an external source while the first power is supplied from an external source, to start generating the second power using the electrical energy stored in the capacitor when the first power is interrupted, and to measure the capacitance of the capacitor; a volatile first memory; a non-volatile second memory; a write operation driven by the second power, which writes data received from the host to the second memory; in a first operating mode, which uses the first memory as a buffer to perform the write operation; and which performs a capacitance test operation one or more times at different timings. A memory system comprising a controller configured such that the capacity test operation involves having the power supply circuit measure the capacity of the capacitor to obtain a capacity measurement value which is the measured value of the capacitor's capacity, obtaining a temperature detection value from the temperature sensor, setting the second value as the capacity threshold value if the temperature detection value is a first value, setting the fourth value which is smaller than the second value as the capacity threshold value if the temperature detection value is a third value which is lower than the first value, and comparing the capacity measurement value with the capacity threshold value, transitioning from the first operating mode to the second operating mode as the capacity measurement value becomes smaller than the capacity threshold value in the capacity test operation, stopping the write operation in response to a power outage and writing data from the first memory that has not yet been written to the second memory to the second memory.

2. The memory system according to claim 1, wherein the controller, in the second operating mode, prohibits the write operation, or performs the write operation without using the first memory as a buffer, or notifies the host of first information, or reduces the power consumption of the memory system, the first information being information that notifies the host that the completion of the write operation is not guaranteed.

3. The memory system according to claim 1, wherein the controller sets the capacity threshold using a temperature function of first order or higher in the capacity test operation.

4. The memory system according to any one of claims 1 to 3, wherein the controller responds to the host, in response to a request from the host, with an index of the health of the capacitor based on the capacitance measurement value and the capacitance threshold.

5. A memory system connectable to a host, comprising: a temperature sensor; a capacitor; a power supply circuit configured to charge the capacitor and generate a second power using the first power supplied from an external source while the first power is supplied from an external source, to start generating the second power using the electrical energy stored in the capacitor in response to a power outage of the first power, and to measure the capacitance of the capacitor; a volatile first memory; a non-volatile second memory; a device driven by the second power, which performs a write operation to write data received from the host to the second memory; in a first operating mode, which uses the first memory as a buffer to perform the write operation; which stops the write operation in response to a power outage and performs a PLP (Power Loss Protection) operation, the PLP operation being an operation to write data from the first memory that has not yet been written to the second memory to the second memory; and a capacity test operation. A memory system comprising a controller configured such that the capacity test operation involves having the power supply circuit measure the capacity of the capacitor to obtain a capacity measurement value which is the measured value of the capacitor's capacity, obtaining a first temperature detection value from the temperature sensor, estimating a first correspondence relationship which is the correspondence relationship between the capacitor's capacity and temperature based on the pair of the capacity measurement value and the first temperature detection value, and identifying a temperature range in which the capacitor's capacity becomes smaller than a value corresponding to the amount of electrical energy required for the PLP operation, and after the capacity test operation, obtaining a second temperature detection value from the temperature sensor, and transitioning from the first operating mode to the second operating mode depending on whether the second temperature detection value falls within the temperature range.

6. The memory system according to claim 5, wherein the controller, in the second operating mode, prohibits the write operation, or performs the write operation without using the first memory as a buffer, or notifies the host of first information, or reduces the power consumption of the memory system, the first information being information that notifies the host that the completion of the write operation is not guaranteed.

7. The memory system according to claim 5, wherein the first correspondence is a primary temperature function representing the capacitance of the capacitor, and the controller obtains the function in the capacitance test operation based on a pair of the capacitance measurement value and the first temperature detection value and a set slope value.

8. The memory system according to claim 5, wherein the first correspondence is a first-order or higher temperature function representing the capacitance of the capacitor, and the controller performs the capacitance test operation two or more times at different timings, and obtains the function by fitting a plurality of pairs of capacitance measurement values ​​obtained by the two or more capacitance test operations and the first temperature detection value.

9. The memory system according to claim 5, wherein the controller determines the temperature range based on the first correspondence and the second correspondence, which is a correspondence between a value corresponding to the amount of electrical energy required for the PLP operation and temperature.

10. The memory system according to any one of claims 5 to 9, wherein the controller performs the capacity test operation at a first time interval and acquires the second temperature detection value at a second time interval shorter than the first time interval.

11. A method comprising: performing a write operation to write data received from a host to a first memory; in a first operating mode, performing the write operation using a volatile second memory as a buffer; performing a capacity test operation once or more at different timings; the capacity test operation being an operation to obtain a capacity measurement value which is a measurement of the capacitance of a capacitor, obtain a temperature detection value from a temperature sensor, set the second value as the capacity threshold if the temperature detection value is a first value, set the fourth value which is smaller than the second value as the capacity threshold if the temperature detection value is a third value which is lower than the first value, and compare the capacity measurement value and the capacity threshold; transitioning from the first operating mode to the second operating mode as the capacity measurement value becomes smaller than the capacity threshold in the capacity test operation; and stopping the write operation in response to a power outage and writing data from the second memory that has not yet been written to the first memory to the second memory using the electrical energy stored in the capacitor.

12. A method comprising: performing a write operation to write data received from a host to a first memory; in a first operating mode, performing the write operation using a volatile second memory as a buffer; stopping the write operation in response to a power outage and performing a PLP operation using the electrical energy stored in the capacitor, wherein the PLP operation is an operation to write data from the second memory that has not yet been written to the first memory to the first memory; performing a capacity test operation; the capacity test operation is an operation to obtain a capacity measurement value which is a measurement of the capacitance of the capacitor, obtain a first temperature detection value from a temperature sensor, estimate a first correspondence relationship which is a correspondence relationship between the capacitance of the capacitor and the temperature based on the pair of the capacity measurement value and the first temperature detection value, and identify a temperature range in which the capacitance of the capacitor becomes smaller than a value corresponding to the amount of electrical energy required for the PLP operation based on the first correspondence relationship; and after the capacity test operation, obtaining a second temperature detection value from the temperature sensor, and transitioning from the first operating mode to the second operating mode in response to the second temperature detection value being included in the temperature range.

13. The method according to claim 11 or 12, wherein the second operating mode includes prohibiting the write operation, performing the write operation without using the second memory as a buffer, notifying the host of first information, or suppressing power consumption, wherein the first information is information notifying the host that the completion of the write operation is not guaranteed.

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