Multilayer ceramic electronic component

Abstract

The present invention provides a highly reliable multilayer ceramic electronic component that makes it possible to suppress the occurrence of cracks in a laminate of the multilayer ceramic electronic component.　A multilayer ceramic capacitor 1 comprises: a laminate 10 including an inner layer part 11 in which a dielectric layer 20 and an internal electrode layer 30 are alternately laminated and main-surface-side outer layer parts 12 which are disposed so as to sandwich the inner layer part 11 from both sides in the lamination direction T, and in which dielectric layers 20 are laminated; a first external electrode 40A disposed on one end of the laminate 10 in the length direction L; and a second external electrode 40B disposed on the other end of the laminate 10 in the length direction, wherein the main-surface-side outer layer part 12 is provided with a fine particle layer ML which is disposed on the surface layer and a base layer BL which is disposed further to the inner layer part 11 side than the fine particle layer ML, and the particle size of ceramic particles MG constituting the fine particle layer ML is smaller than the particle size of ceramic particles BG constituting the base layer BL.

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] Multilayer ceramic capacitors have been known conventionally as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor comprises a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and external electrodes connected to the internal electrode layers and provided on both end faces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, wherein the terminal electrodes as external electrodes are composed of a metal component and an inorganic binder, and a plurality of voids are formed inside.

[0003] Japanese Patent Application Publication No. 5-3132

[0004] The multilayer ceramic capacitor described in Patent Document 1 has voids in its terminal electrodes. Therefore, external stress is relieved, and the occurrence of cracks inside the capacitor is suppressed. This enhances the reliability of the multilayer ceramic capacitor. However, in recent years, even higher reliability has been required, necessitating further measures.

[0005] The present invention aims to provide a highly reliable multilayer ceramic electronic component that can suppress crack formation in the laminate of the multilayer ceramic electronic component.

[0006] The multilayer ceramic electronic component according to the present invention comprises a plurality of stacked ceramic layers and a plurality of internal conductor layers, and is a laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, the laminate comprising an effective layer portion in which the ceramic layers and the internal conductor layers are alternately stacked, and an outer layer portion disposed to sandwich the effective layer portion from the first main surface side and the second main surface side, and a first external electrode disposed on the first end surface and a second external electrode disposed on the second end surface, wherein the outer layer portion comprises a micronized layer disposed on the surface and a base layer disposed on the effective layer side of the micronized layer, and the particle diameter of the ceramic particles constituting the micronized layer is smaller than the particle diameter of the ceramic particles constituting the base layer.

[0007] According to the present invention, it is possible to provide a highly reliable multilayer ceramic electronic component that can suppress crack formation in the laminate of the multilayer ceramic electronic component.

[0008] This is an external perspective view of the multilayer ceramic capacitor of this embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. This is an enlarged view of section V of the multilayer ceramic capacitor shown in Figure 2. This is an enlarged view of section VI of the multilayer ceramic capacitor shown in Figure 5. This is a schematic diagram showing an example of the configuration of a double-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a triple-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a quadruple-gang multilayer ceramic capacitor.

[0009] <Embodiment> Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the first embodiment of this disclosure will be described with reference to Figures 1 to 4. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IV-IV.

[0010] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0011] Figures 1 to 4 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross section shown in Figure 2 is also called the LT cross section. The cross section shown in Figure 3 is also called the WT cross section. The cross section shown in Figure 4 is also called the LW cross section.

[0012] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the lamination direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the lamination direction T and the width direction W.

[0013] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 as an effective layer and a main surface-side outer layer 12 as an outer layer. The main surface-side outer layer 12 has a first main surface-side outer layer 12A and a second main surface-side outer layer 12B, which are arranged to sandwich the inner layer 11 in the lamination direction T. The first main surface-side outer layer 12A and the second main surface-side outer layer 12B include a plurality of dielectric layers 20 as a plurality of ceramic layers.

[0016] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0017] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as those listed above. Furthermore, the dielectric material may be obtained by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first pull-out portion 31B and the second pull-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0027] The first main surface-side outer layer 12A is located on the first main surface TS1 side of the laminate 10. The first main surface-side outer layer 12A is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface-side outer layer 12A may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0028] The second main surface-side outer layer 12B is located on the second main surface TS2 side of the laminate 10. The second main surface-side outer layer 12B is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface-side outer layer 12B may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figure 4 shows the width W and length L ranges of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 3 and 4 show the width direction W range of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2 and 4 show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called an L gap or end gap.

[0032] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0033] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0036] The first external electrode 40A includes a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A includes a first Ni plating layer 71A as an under-plating layer and a first Sn plating layer 72A as an over-plating layer.

[0037] The second external electrode 40B includes a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B has a second Ni plating layer 71B as a lower layer plating layer and a second Sn plating layer 72B as an upper layer plating layer.

[0038] Here, the basic configurations of the respective layers constituting the first external electrode 40A and the second external electrode 40B are the same. Also, the first external electrode 40A and the second external electrode 40B are substantially plane-symmetric with respect to the LW cross-section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish and describe the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0039] Also, when there is no need to particularly distinguish and describe the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50.

[0040] Also, when there is no need to particularly distinguish and describe the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60.

[0041] Also, when there is no need to particularly distinguish and describe the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70.

[0042] Also, when there is no need to particularly distinguish and explain between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71. Also, when there is no need to particularly distinguish and explain between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72.

[0043] Also, when there is no need to particularly distinguish and explain between the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B, the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B may be collectively referred to as the main surface side outer layer portion 12.

[0044] Also, when there is no need to particularly distinguish and explain between the first end face LS1 and the second end face LS2, the first end face LS1 and the second end face LS2 may be collectively referred to as the end face LS. Also, when there is no need to particularly distinguish and explain between the first main surface TS1 and the second main surface TS2, the first main surface TS1 and the second main surface TS2 may be collectively referred to as the main surface TS.

[0045] The base electrode layer 50 has a first base electrode layer 50A and a second base electrode layer 50B.

[0046] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. Also, the first base electrode layer 50A may be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0047] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. Also, the second base electrode layer 50B may be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0048] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are baking layers. The baking layer preferably contains either a metal component and a glass component or a ceramic component, or both. Thereby, the adhesion between the laminate 10 and the base electrode layer can be improved. The metal component contains, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component contains, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. When there is a glass component, it can assist the sintering of the metal component in the base electrode layer and promote the sintering. The ceramic component may be the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component contains, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ and the like, and contains at least one selected therefrom.

[0049] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or by firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0050] The longitudinal thickness of the first base electrode layer 50A located at the first end face LS1 is preferably, for example, 2 μm to 220 μm at the center of the first base electrode layer 50A in the lamination direction T and width direction W.

[0051] The longitudinal thickness of the second base electrode layer 50B located at the second end face LS2 is preferably, for example, 2 μm to 220 μm at the center of the second base electrode layer 50B in the lamination direction T and width direction W.

[0052] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the lamination direction provided in this part is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0053] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the first base electrode layer 50A in the width direction provided in this portion is, for example, 4 μm or more and 40 μm or less at the center of the first base electrode layer 50A in the length direction L and the lamination direction T.

[0054] When a second base electrode layer 50B is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided in this portion in the lamination direction is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0055] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B in the width direction provided in this portion is preferably, for example, 4 μm or more and 40 μm or less at the center of the second base electrode layer 50B in the length direction L and the lamination direction T.

[0056] The external electrode 40 has a conductive resin layer 60 containing resin and metal components, which is placed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0057] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B.

[0058] The longitudinal thickness of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, 10 μm to 200 μm at the center of the first conductive resin layer 60A in the lamination direction T and width direction W.

[0059] The longitudinal thickness of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, 10 μm to 200 μm at the center of the second conductive resin layer 60B in the lamination direction T and width direction W.

[0060] When the first conductive resin layer 60A is also provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the first conductive resin layer 60A in the lamination direction T provided in these portions is preferably, for example, 10 μm or more and 200 μm or less at the center of the length direction L and width direction W of the first conductive resin layer 60A provided in these portions.

[0061] When the first conductive resin layer 60A is also provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, it is preferable that the thickness of the first conductive resin layer 60A in the width direction W provided on this portion is, for example, 10 μm or more and 200 μm or less at the center of the first conductive resin layer 60A in the length direction L and the lamination direction T provided on this portion.

[0062] When a second conductive resin layer 60B is provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the second conductive resin layer 60B provided in this portion in the lamination direction T is preferably, for example, 10 μm to 200 μm at the center of the length direction L and width direction W of the second conductive resin layer 60B provided in this portion.

[0063] When a second conductive resin layer 60B is provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the second conductive resin layer 60B in the width direction W provided on this portion is preferably, for example, 10 μm or more and 200 μm or less at the center of the second conductive resin layer 60B in the length direction L and the lamination direction T.

[0064] The conductive resin layer 60 is placed on the underlying electrode layer 50. The plating layer 70 is then placed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0065] The conductive resin layer 60 has a resin portion and a conductive filler dispersed within the resin portion.

[0066] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin portion of the conductive resin layer 60 contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0067] Because the conductive resin layer 60 includes such resin components, it is more flexible than, for example, the base electrode layer 50 which consists of a plated film or a fired product of metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0068] The conductive filler is dispersed within the resin portion in a substantially uniform distribution. The conductive filler is primarily responsible for the conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0069] The metal constituting the conductive filler may be pure silver (Ag), an alloy containing Ag, or a metal powder with an Ag coating on its surface. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, as a noble metal, Ag is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders containing these metals.

[0070] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be metal powder coated with Sn, Ni, or Cu on its surface. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0071] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical metal powder and flattened metal powder.

[0072] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0073] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0074] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0075] The first plating layer 70A is arranged to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0076] The second plating layer 70B is arranged to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as a part of the first side surface WS1 and a part of the second side surface WS2.

[0077] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, the first Sn plating layer 72A is placed on the first Ni plating layer 71A, and preferably the second Sn plating layer 72B is placed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the underlying electrode layer 50 and the conductive resin layer 60 from being corroded by the solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0078] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A are preferably 1 μm or more and 15 μm or less.

[0079] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B are preferably 1 μm or more and 15 μm or less.

[0080] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0081] Here, through repeated studies, experiments, and simulations, the inventors of the present invention have found that, in order to suppress the occurrence of cracks in the laminate, it is desirable to reduce the crack initiation point during deflection by micronizing the grain on the surface of the base material (laminated body) of the multilayer ceramic capacitor as a multilayer ceramic electronic component.

[0082] The embodiment will be described in detail below with reference to Figures 5 and 6. Figure 5 is an enlarged view of section V of the multilayer ceramic capacitor 1 shown in Figure 2. Figure 6 is an enlarged view of section VI of the multilayer ceramic capacitor 1 shown in Figure 5.

[0083] As shown in Figures 5 and 6, the outer layer 12 has a micronized layer ML arranged on the surface and a base layer BL arranged on the inner layer 11 side of the micronized layer ML. The micronized layer ML is a layer composed of ceramic particles MG that are more micronized than the ceramic particles BG that make up the base layer BL. The ceramic particles MG that make up the micronized layer ML are preferably pulverized particles. Pulverized particles are particles that have been micronized by applying mechanical external force. The pulverized particles are preferably crystalline particles. Crystalline particles are particles that have crystalline properties.

[0084] The thickness t of the atomized layer is preferably 300 nm or less. More preferably, the thickness t of the atomized layer is 10 nm or more and 300 nm or less.

[0085] Preferably, the particle size D of the ceramic particles BG constituting the base layer BL is 200 nm or more, and the particle size d of the ceramic particles constituting the particle layer ML is 50 nm or less. More preferably, the particle size D of the ceramic particles BG constituting the base layer BL is 200 nm or more and 500 nm or less, and the particle size d of the ceramic particles constituting the particle layer ML is 10 nm or more and 50 nm or less.

[0086] It is preferable that a dislocation crystal layer is placed between the finely milled layer ML and the base layer BL. Here, the dislocation crystal layer refers to a particle layer in which the crystals of the particles constituting the particle layer have dislocations (hereinafter referred to as dislocation defects), which are lattice defects.

[0087] The degree of unevenness of the surface S2 of the atomized layer ML that is away from the inner layer 11 is smaller than the degree of unevenness of the surface S1 of the atomized layer ML that is closer to the inner layer 11.

[0088] <Measurement and Verification Methods for Various Structures> Next, we will explain how to verify various dimensions such as the length, thickness, and degree of unevenness of each part of a multilayer ceramic capacitor, as well as the state of the atomized layer. The degree of unevenness may be defined, for example, by the arithmetic mean roughness (Ra). The LT cross-sections shown in Figures 5 and 6 can be observed, for example, as follows: Polish the multilayer ceramic capacitor 1 to the center position in the width direction. Then, observe the cross-section exposed by polishing with a transmission electron microscope (TEM). Furthermore, various dimensions such as the length, thickness, and degree of unevenness of each part of the multilayer ceramic capacitor, as well as the state of the atomized layer, can be measured and observed from the observed cross-section.

[0089] For example, by observing the portion of the LT cross-section exposed by polishing, including the micronized layer, with a transmission electron microscope (TEM), various dimensions such as the average particle diameter, the thickness of the micronized layer, and the degree of surface roughness of the micronized layer can be measured. Image analysis software (for example, WinROOF manufactured by Mitani Corporation) can be used to measure these various dimensions.

[0090] For example, the thickness of the atomized layer at the longitudinal center of the first external electrode positioned on the first main surface and the second main surface, and the thickness of the atomized layer at the longitudinal center of the second external electrode positioned on the first main surface and the second main surface are measured, and the average value of these measurements is taken as the thickness of the atomized layer in this disclosure.

[0091] For example, particle size measurement in the atomized layer is performed by image processing of the electron analysis image of the particles obtained by a transmission electron microscope (TEM) to identify the contour of each individual particle and then converting it to an equivalent diameter. The average particle size in the atomized layer is calculated using the average value of the measured individual particles.

[0092] Furthermore, the arithmetic mean roughness Ra, which represents the degree of surface irregularity of the atomized layer, can also be calculated by extracting the contour lines of the atomized layer's surface from the electron analysis image of the particles obtained by a transmission electron microscope (TEM) using image analysis software.

[0093] Furthermore, to confirm whether a material is crystalline, for example, one can check whether a crystal-specific pattern can be obtained using electron diffraction with a transmission electron microscope (TEM). Also, to confirm the presence or absence of dislocation defects, for example, one can check for dislocation defects by observing the electron analysis image using a transmission electron microscope (TEM).

[0094] <Manufacturing Method> Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0095] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0096] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0097] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12A on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 12B on the second main surface TS2 side. This completes the production of the laminated sheet.

[0098] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0099] The laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0100] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0101] The surface of the fired laminate 10 is polished by barrel polishing. In this barrel polishing, the laminate 10 having the surface of the present disclosure is obtained by adjusting the material, shape and size of the media, polishing time, etc. Specifically, the laminate 10 having the atomized layer of the present disclosure can be obtained by reducing the mass of the media and setting a longer polishing time. The thickness of the atomized layer can be controlled by adjusting the mass of the media and the rotation conditions of the barrel. For example, the heavier the mass of the media, the thicker the atomized layer can be. Conversely, the lighter the mass of the media, the thinner the atomized layer can be.

[0102] A conductive paste, which will become the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. After that, a baking process is performed to form the base electrode layer 50. The temperature of this baking process is preferably 700°C to 950°C.

[0103] Next, a conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the underlying electrode layer 50, or it may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the underlying electrode layer 50.

[0104] First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which serves as the base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, a silver (Ag) metal powder.

[0105] Subsequently, a conductive resin paste is applied to the base electrode layer 50 using a dipping method, and heat treatment is performed at a temperature of 200°C to 550°C. This causes the resin to heat-cur, forming a conductive resin layer 60. The atmosphere during this heat treatment is N ２ It is preferable that the atmosphere is such that the oxygen concentration is kept below 100 ppm in order to prevent the scattering of resin and to prevent oxidation of various metal components.

[0106] Subsequently, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electroplating method. For example, barrel plating is preferred as the plating method.

[0107] A multilayer ceramic capacitor 1 is manufactured using the above manufacturing method.

[0108] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0109] (1) The multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a plurality of stacked dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and is a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, wherein the dielectric layers 20 and the internal electrode layers 30 are stacked alternately in an inner layer portion 11 The laminate 10 includes an effective layer portion 11 and a main surface side outer layer portion 12 (outer layer portion 12) arranged to sandwich the inner layer portion 11 from the first main surface TS1 side and the second main surface TS2 side, and a first external electrode 40A arranged on the first end surface LS1 and a second external electrode 40B arranged on the second end surface LS2, wherein the main surface side outer layer portion 12 comprises a micronized layer ML arranged on the surface and a base layer BL arranged on the inner layer portion 11 side of the micronized layer ML, and the particle diameter d of the ceramic particles MG constituting the micronized layer ML is smaller than the particle diameter D of the ceramic particles BG constituting the base layer BL.

[0110] This results in finer grain boundaries, making it less likely for the reaction layer during plating or external electrode firing to erode the grain boundaries, thus reducing the likelihood of crack initiation. Furthermore, the complexity of the grain boundary pathways makes crack propagation more difficult. This allows for the provision of highly reliable multilayer ceramic electronic components that can suppress crack formation in the laminated structure of multilayer ceramic electronic components.

[0111] (2) In the multilayer ceramic capacitor 1 of this embodiment, the ceramic particles MG constituting the atomized layer ML are crushed particles.

[0112] This makes the grain boundary paths more complex, which helps to further suppress crack formation in the laminated structure of multilayer ceramic electronic components.

[0113] (3) In the multilayer ceramic capacitor 1 of this embodiment, the crushed particles are crystalline particles.

[0114] This makes it possible to suppress crack formation in the laminated structure of multilayer ceramic electronic components.

[0115] (4) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the atomized layer ML is 300 nm or less.

[0116] This suppresses the loss of the atomized layer during processing, while also further suppressing crack formation in the laminated structure of multilayer ceramic electronic components.

[0117] (5) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the atomized layer ML is 10 nm or more and 300 nm or less.

[0118] This suppresses the loss of the atomized layer during processing while further suppressing crack formation in the laminate of multilayer ceramic electronic components. However, if the thickness t of the atomized layer ML is less than 10 nm, the stress dispersion effect is small, and the crack suppression effect is not sufficiently obtained. Also, if the thickness t of the atomized layer ML exceeds 300 nm, loss of the atomized layer occurs, making it impossible to stably reproduce a consistent processing state and thus failing to ensure processing stability.

[0119] (6) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the atomized layer ML is 10% or less of the thickness T of the main surface side outer layer portion 12.

[0120] This suppresses the loss of the atomized layer during processing, while also further suppressing crack formation in the laminated structure of multilayer ceramic electronic components.

[0121] (7) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the atomized layer ML is 1% or less of the thickness T of the main surface side outer layer portion 12.

[0122] This suppresses the loss of the atomized layer during processing, while also further suppressing crack formation in the laminated structure of multilayer ceramic electronic components.

[0123] (8) In the multilayer ceramic capacitor 1 of this embodiment, the particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more, and the particle diameter d of the ceramic particles MG constituting the micronized layer ML is 50 nm or less.

[0124] This makes it possible to further suppress crack formation in the laminated structure of multilayer ceramic electronic components.

[0125] (9) In the multilayer ceramic capacitor 1 of this embodiment, the particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more and 500 nm or less, and the particle diameter d of the ceramic particles MG constituting the micronized layer ML is 10 nm or more and 50 nm or less.

[0126] This further suppresses crack formation in the laminate of multilayer ceramic electronic components. However, if the particle size d of the ceramic particles MG constituting the micronized layer ML is less than 10 nm, it is difficult to form the micronized layer necessary to obtain the crack suppression effect, and the crack suppression effect is not sufficiently obtained. Also, if the particle size d of the ceramic particles MG constituting the micronized layer ML exceeds 50 nm, the complexity of the grain boundary pathways is insufficient, and the crack suppression effect is not sufficiently obtained.

[0127] (10) In the multilayer ceramic capacitor 1 of this embodiment, a dislocation crystal layer having dislocations in the crystals of the particles constituting the particle layer is arranged between the atomization layer ML and the base layer BL.

[0128] This makes it possible to further suppress crack formation in the laminated structure of multilayer ceramic electronic components.

[0129] (11) In the multilayer ceramic capacitor 1 of this embodiment, the degree of unevenness of the surface S2 of the atomized layer ML that is away from the inner layer 11 is smaller than the degree of unevenness of the surface S1 of the atomized layer ML that is closer to the inner layer 11.

[0130] This makes it more difficult for cracks to originate, and the complexity of the grain boundary pathways makes it harder for cracks to propagate, thus further suppressing crack formation in the laminated structure of multilayer ceramic electronic components.

[0131] <Examples> Examples of the multilayer ceramic capacitor 1 of this embodiment will be described with reference to Table 1. Table 1 is a table showing examples of the multilayer ceramic capacitor of this embodiment. The samples, evaluation items, and evaluation conditions of the examples are as follows. Samples were manufactured in lots, with the manufacturing conditions adjusted so that the thickness of the atomized layer differed according to the manufacturing method described above, as samples for Examples 1 to 10 and comparative examples. The samples within each lot were manufactured under the same manufacturing conditions. For each example, n=10 samples for measuring the thickness of the atomized layer and confirming processing stability, and n=30 samples for deflection testing were taken from the same lot and prepared. For measuring the thickness of the atomized layer, the average value of the measurement results was used.

[0132] <Samples> For the samples, the surface of the laminate after firing using the above manufacturing method was polished by barrel polishing, adjusting the barrel rotation conditions and media mass so that the thickness of the atomized layer was the value shown in Table 1. Samples of Examples 1 to 10 and Comparative Examples were prepared to have the atomized layer shown in Table 1. The Comparative Examples are samples without an atomized layer. The specifications of the multilayer ceramic capacitor are as follows: ・Dimensions of the multilayer ceramic capacitor: 2.0 mm (length direction L) × 1.2 mm (width direction W) × 1.2 mm (lamination direction T) ・Ceramic material: BaTiO ３• Capacitance: 1.0 μF • Rated voltage: 50 V • Outer layer structure Outer layer thickness: 85 μm Average particle size of base layer: 200 nm Average particle size of atomized layer: 30 nm • External electrode structure (1) Underlayment electrode layer: Electrode containing conductive metal (Cu) and glass component Thickness of the underlayment electrode layer at the center in the height direction of the underlayment electrode layer located at the first and second end faces: 15 μm Thickness of the underlayment electrode layer at the center in the length direction of the underlayment electrode layer located on the first and second main surfaces, first side surface and second side surface: 4 μm (2) Conductive resin layer Conductive resin layer: Conductive filler: Ag Resin: Epoxy-based Thermosetting temperature: 200 °C Thickness of the first conductive resin layer at the center in the height direction of the first end face and second end face: 20 μm (1) Ni plating layer Thickness of the Ni plating layer at the center of the length direction of the Ni plating layer located on the first main surface and the second main surface, the first side surface and the second side surface: 20 μm (3) Ni plating layer Thickness of the Ni plating layer at the center of the height direction of the Ni plating layer located on the first end surface and the second end surface: 2 μm Thickness of the Ni plating layer at the center of the length direction of the Ni plating layer located on the first main surface and the second main surface, the first side surface and the second side surface: 2.0 μm (4) Sn plating layer Thickness of the Sn plating layer at the center of the height direction of the Sn plating layer located on the first end surface and the second end surface: 1.5 μm Thickness of the Sn plating layer at the center of the length direction of the Sn plating layer located on the first main surface and the second main surface, the first side surface and the second side surface: 1.0 μm

[0133] Deflection tests were conducted on the prepared Examples 1 to 10 and Comparative Example. The deflection tests were conducted to confirm the crack suppression effect, and the number of deflection cracks was confirmed to evaluate the deflection effect. In addition, the processing stability of Examples 1 to 10 and Comparative Example were confirmed and the thickness of the granulated layer was measured. The details of the deflection tests, processing stability confirmation, and measurement of the granulated layer thickness are described below.

[0134] <Deflection Test> Multilayer ceramic capacitors, which are samples from Examples 1 to Experimental Example 10 and Comparative Example, were mounted on a mounting board using solder paste. The orientation of the multilayer ceramic capacitors was such that the first main surface faced the mounting board. The thickness of the mounting board was 0.8 mm. Then, a pressing jig was pressed against the side of the mounting board opposite to the mounting surface to bend the mounting board. The pressing jig was a 5 mm diameter push rod. The amount of deflection of the mounting board was 2.0 mm. The mounting board was held in the bent state for 5 seconds.

[0135] Subsequently, the multilayer ceramic capacitor was removed from the mounting substrate and checked for crack formation. Specifically, the laminate was polished from the mounting surface side (first main surface) to expose the LW cross-section passing through the center of the laminate in the stacking direction T. The polished surface was observed under a microscope to check for the presence of cracks in the laminate. The microscope magnification was set to 40x.

[0136] <Confirmation of processing stability and measurement of the thickness of the atomized layer> Processing stability is determined by checking whether at least a portion of the atomized layer detaches from the outer layer during the manufacturing of the multilayer ceramic capacitor. Therefore, in this embodiment, if even one atomized layer detachment occurs among the 10 samples checked for confirmation of processing stability, it is determined that there is no processing stability. Furthermore, the thickness of the atomized layer was measured according to the measurement method described above. Table 1 shows the measurement results of the atomized layer thickness, the number of deflection cracks, the deflection judgment effect, the results of the confirmation of processing stability, and the evaluation results of the overall evaluation.

[0137] Furthermore, the criteria for judging processing stability result A is that there is no loss of the micronized layer from the laminate, and this is judged as good. The criteria for judging processing stability result B is that there is a loss of one or more micronized layers from the laminate, and this is judged as unacceptable.

[0138] Furthermore, the criteria for evaluation result A of deflection cracks is as follows: the number of cracks is 0, and it is judged as good. The criteria for evaluation result B of deflection cracks is as follows: the number of cracks is 1 or more but less than 20, and it is judged as acceptable. The criteria for evaluation result C of deflection cracks is as follows: the number of cracks is 20 or more, and it is judged as unacceptable.

[0139] Furthermore, the criteria for an overall evaluation of A is when the processing stability evaluation result is A and the deflection crack evaluation result is A, and the evaluation is judged as good. The criteria for an overall evaluation of B is when the deflection crack evaluation result is anything other than C, and at least one of the processing stability evaluation result and the deflection crack evaluation result is B, and the evaluation is judged as good. The criteria for an overall evaluation of C is when the deflection crack evaluation result is C, and the evaluation is judged as bad. <Processing Stability> B: Bad A: Good <Deformation Crack Evaluation> C: Bad B: Good A: Good <Overall Evaluation Criteria> C: Bad B: Good A: Good

[0140]

[0141] Compared to a comparative example in which the thickness of the atomized layer ML was 0 nm, it was confirmed that the number of deflection cracks was reduced in Examples 1 to 10, which were equipped with the atomized layer ML. From these results, it was confirmed that the number of deflection cracks can be suppressed by forming an atomized layer ML, which is composed of ceramic particles MG with a particle diameter d smaller than the particle diameter D of the ceramic particles BG that constitute the base layer BL, on the main surface outer layer portion 12 of the multilayer ceramic capacitor 1.

[0142] Furthermore, it was found that processing stability can be ensured when the thickness t of the micronized layer ML is 300 nm or less. It was also confirmed that the number of deflection cracks can be suppressed when the thickness t of the micronized layer ML is 10 nm or more. Moreover, it was confirmed that processing stability can be ensured while suppressing the number of deflection cracks to zero when the thickness t of the micronized layer ML is between 10 nm and 300 nm.

[0143] Note that the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 7, 8, and 9.

[0144] The multilayer ceramic capacitor 1 shown in Figure 7 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 8 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 9 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0145] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0146] In the embodiments described above, a multilayer ceramic capacitor was given as an example in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, thermistors using semiconductor ceramic as the ceramic layer, and inductors using magnetic ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite and other ceramics.

[0147] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the individual desirable configurations described in the above embodiments also constitutes the present invention.

[0148] 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 11 Inner layer (effective layer) 12 Outer layer 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 40A First external electrode 40B Second external electrode BL Base layer BG Ceramic particles ML Micronized layer MG Ceramic particles T Height direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end surface LS2 Second end surface

Claims

1. A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, comprising: an effective layer portion formed by alternately stacking the ceramic layers and the internal conductor layers; an outer layer portion disposed to sandwich the effective layer portion from the first main surface side and the second main surface side; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the outer layer portion comprises a micronized layer disposed on the surface layer and a base layer disposed on the effective layer side of the micronized layer, and the particle diameter of the ceramic particles constituting the micronized layer is smaller than the particle diameter of the ceramic particles constituting the base layer.

2. The multilayer ceramic electronic component according to claim 1, wherein the ceramic particles constituting the atomized layer are crushed particles.

3. The multilayer ceramic electronic component according to claim 2, wherein the pulverized particles are crystalline particles.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the thickness of the atomized layer is 300 nm or less.

5. The multilayer ceramic electronic component according to claim 4, wherein the thickness of the atomized layer is 10 nm or more and 300 nm or less.

6. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the thickness of the atomized layer is 10% or less of the thickness of the outer layer.

7. The multilayer ceramic electronic component according to claim 6, wherein the thickness of the atomized layer is 1% or less of the thickness of the outer layer.

8. The multilayer ceramic electronic component according to any one of claims 1 to 7, wherein the particle size of the ceramic particles constituting the base layer is 200 nm or more, and the particle size of the ceramic particles constituting the micronized layer is 50 nm or less.

9. The multilayer ceramic electronic component according to claim 8, wherein the particle size of the ceramic particles constituting the base layer is 200 nm or more and 500 nm or less, and the particle size of the ceramic particles constituting the micronized layer is 10 nm or more and 50 nm or less.

10. A multilayer ceramic electronic component according to any one of claims 1 to 9, wherein a dislocation crystal layer having dislocations in the crystals of the particles constituting the particle layer is disposed between the atomized layer and the base layer.

11. The multilayer ceramic electronic component according to any one of claims 1 to 10, wherein the degree of unevenness of the surface of the atomized layer that is away from the effective layer is smaller than the degree of unevenness of the surface of the atomized layer that is closer to the effective layer.

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