Phase adjustment device and phase adjustment method

Abstract

This phase adjustment device (30) comprises: input units (IN1, IN2, IN3) that receive a first clock signal and a second clock signal; a first phase variable unit (31) that changes the phase of the second clock signal from a second phase to a first phase; a communication unit (34) that transmits the second clock signal changed to the first phase to a transmission device (20); and a second phase variable unit (32) that returns the phase of the second clock signal from the first phase to the second phase at a predetermined phase adjustment speed (v1) while the transmission device (20) operates at the second clock signal changed to the first phase. The phase adjustment speed (v1) is set on the basis of at least one of the tracking limit of an oscillator mounted on the phase adjustment device (30), the phase jump tolerance of the transmission device (20), and the operation limit of an elastic buffer mounted on the transmission device (20).

Description

Phase Adjustment Device and Phase Adjustment Method

[0001] The present disclosure relates to a phase adjustment device and a phase adjustment method.

[0002] Services such as fixed telephones and digital dedicated lines are provided by a network using the time division multiplexing (TDM; Time Division Multiplexing) method. Therefore, it is required to match the frequencies and phases of each device installed in the network with high precision. To match the frequencies, a clock path using a master clock, which is a reference frequency source, as the highest level, a clock supply device (CSM: Clock Supply Module), and a transmission device capable of clock transmission is hierarchically constructed to achieve frequency synchronization across the entire network.

[0003] Also, when the clock supply device (hereinafter abbreviated as "CSM") deteriorates, the old CSM (hereinafter referred to as "old CSM") is replaced with a new CSM (hereinafter referred to as "new CSM"). Non-Patent Document 1 describes that a phase jump of up to 200 [nsec] occurs due to the switching of the redundant part of the clock system device. Non-Patent Document 2 describes a clock supply device that enables high-precision frequency synchronization and time synchronization on a packet transport network.

[0004] NTT East Japan: Information on the output of network synchronization clocks, Internet [searched on January 27, 2025], "https: / / www.ntt-east.co.jp / info-st / info_dsl / clock.html" R&D-NTT Technical Journal, Practical application of a new clock supply device that supports telephone communication and dedicated line communication for corporations, Internet [searched on January 27, 2025], "https: / / journal.ntt.co.jp / backnumber2 / 1707 / files / JN20170744.pdf"

[0005] When constructing a new CSM, the phase difference between the clock of the new CSM and the clock of the old CSM may increase due to the passage of time, lightning strikes, malfunctions, etc. A phase adjustment device is used to adjust the phase difference. When adjusting the phase difference using a phase adjustment device, for example, it takes about 1 second to adjust a phase difference of 1 [ns]. That is, the phase adjustment speed is about 1 [ns / second]. When the phase difference is small, it is possible to adjust the phase difference in a short time. However, if a phase difference of, for example, 1069 [μ / s] occurs, adjusting the phase at the above phase adjustment speed would take about 300 hours (12 days), which is a problem as it prolongs the time required for phase adjustment. Non-patent documents 1 and 2 mentioned above do not mention anything about shortening the phase adjustment time.

[0006] This disclosure has been made in view of the above circumstances, and its purpose is to provide a phase adjustment device and a phase adjustment method that can quickly adjust the phase of the clock output from a new clock supply device to the phase of the clock output from the clock supply device before replacement.

[0007] A phase adjustment device according to one aspect of the present disclosure is a phase adjustment device that changes the clock supplied to a transmission device from a first clock of a first phase transmitted from a first clock supply device to a second clock of a second phase transmitted from a second clock supply device, comprising: an input unit that receives the first clock and the second clock; a first phase variable unit that changes the phase of the second clock from the second phase to the first phase; a communication unit that transmits the second clock after it has been changed to the first phase to the transmission device; and a second phase variable unit that, while the transmission device is operating with the second clock after it has been changed to the first phase, changes the phase of the second clock back from the first phase to the second phase at a predetermined phase adjustment speed, wherein the phase adjustment speed is set based on at least one of the tracking limit of an oscillator mounted on the phase adjustment device, the phase jump tolerance of the transmission device, and the operating limit of an elastic buffer mounted on the transmission device.

[0008] A phase adjustment method according to one aspect of the present disclosure is a phase adjustment method for changing the clock supplied to a transmission device from a first clock of a first phase transmitted from a first clock supply device to a second clock of a second phase transmitted from a second clock supply device, wherein an input unit receives the first clock and the second clock, a first phase variable unit changes the phase of the second clock from the second phase to the first phase, a communication unit transmits the second clock after the change to the first phase to the transmission device, and while the transmission device is operating with the second clock after the change to the first phase, the second phase variable unit changes the phase of the second clock back from the first phase to the second phase at a phase adjustment speed set based on at least one of the tracking limit of an oscillator mounted on the phase adjustment device, the phase jump tolerance of the transmission device, and the operating limit of an elastic buffer mounted on the transmission device.

[0009] According to this disclosure, it becomes possible to quickly adjust the phase of the clock output from the new clock supply device to the phase of the clock output from the clock supply device before replacement.

[0010] Figure 1 is an explanatory diagram showing a clock path network in which the clocks of multiple clock supply devices and transmission devices are synchronized by a master clock. Figure 2 is an explanatory diagram schematically showing the process of changing the clock supply source of a transmission device from an old CSM to a new CSM. Figure 3 is a block diagram showing the configuration of a phase adjustment device and its peripheral equipment according to an embodiment. Figure 4 is an explanatory diagram showing the transmission of the clock from the old CSM to the transmission device. Figure 5 is an explanatory diagram showing the transmission of the clock from the new CSM to the E-system input terminal of the transmission device via the phase adjustment device. Figure 6 is an explanatory diagram showing the change from the second clock to the first clock of the clock transmitted to the E-system input terminal of the transmission device. Figure 7 is an explanatory diagram showing the switching of the E-system input terminal of the transmission device from SBY to ACT. Figure 8 is an explanatory diagram showing the gradual change of the phase of the clock transmitted to the E-system input terminal of the transmission device from the first phase φ1 to the second phase φ2. Figure 9 is an explanatory diagram showing the connection of the N-system input terminal of the transmission device to the N-system output terminal of the new CSM. Figure 10 is an explanatory diagram showing the switching of the N-system input terminal of the transmission device from SBY to ACT. Figure 11 is an explanatory diagram showing the switching of the CSM, which is the clock supply source of the transmission device, to a new CSM. Figure 12 is a flowchart showing the processing procedure of the phase adjustment device according to the embodiment. Figure 13 is a graph showing the waveform s1 of the first clock output from the old CSM and the waveform s2 of the second clock output from the new CSM. Figure 14 is a timing chart showing the time required for phase adjustment when the phase adjustment speed v1 is 1 [ns / sec] and 20 [ns / sec]. Figure 15 is a block diagram showing the hardware configuration of this embodiment.

[0011] The embodiments will be described below with reference to the drawings. Figure 1 is an explanatory diagram showing a clock path network that synchronizes the clocks of multiple clock supply devices and transmission devices connected in a hierarchical manner by a master clock. As shown in Figure 1, the frequency of the clock supply device 52 (CSM 52) is synchronized by a reference clock transmitted from the master clock output unit 51A of the operational system or the master clock output unit 51B of the standby system, which is installed upstream of the CSM 52. Furthermore, the frequency of the CSM 53 installed downstream of the CSM 52 is synchronized by the clock transmitted from the CSM 52, and the frequency of the clock transmission device 54 is synchronized by the clock transmitted from the CSM 53.

[0012] The CSM 10, installed downstream of the transmission device 54, is synchronized by the clock transmitted from the transmission device 54, and the transmission device 20, installed downstream of the CSM 10, has its clock synchronized by the clock transmitted from the CSM 10. In this way, the clocks of each transmission device connected to the clock path network are synchronized to a reference clock.

[0013] Figure 2 is a schematic diagram illustrating the process of replacing an aging old CSM (first clock supply device; hereinafter referred to as "old CSM 11") with a new CSM (second clock supply device; hereinafter referred to as "new CSM 12"). The clock transmitted from the master clock output unit 51A (or 51B) is supplied to the old CSM 11 installed in the main station B1, and then sequentially supplied to the old CSM 11 installed in the first building B2, the second building B3, and the third building B4. The transmission devices 20 installed in the main station B1 and in each building B2 to B4 are operated by the clock transmitted from each old CSM 11.

[0014] When replacing the old CSM11 installed in the main station B1 and each building B2 to B4 with the new CSM12, it is necessary to match the phase of the clock output by the new CSM12 with the phase of the clock output by the old CSM11. In this embodiment, a phase adjustment device 30 (see Figure 3, described later) is installed between the new CSM12 and the old CSM11 to adjust the clock supplied to the transmission device 20 so that it gradually changes from the clock of the old CSM11 (first clock) to the clock of the new CSM12 (second clock). Specifically, it gradually changes from the first phase φ1 of the first clock to the second phase φ2 of the second clock, which has the same frequency as the first clock.

[0015] Figure 3 is a block diagram showing the configuration of a phase adjustment device 30 and its peripheral equipment according to an embodiment. As shown in Figure 3, the phase adjustment device 30 includes three input units IN1, IN2, and IN3, an output unit OUT, a first phase variable unit 31, a second phase variable unit 32, an operation unit 33, a communication unit 34, and an oscillator 35. The phase adjustment device 30 is driven by a control clock output from the oscillator 35 and changes the clock supplied to the transmission device 20 from the first clock of the first phase transmitted from the old CSM 11 (first clock supply device) to the second clock of the second phase transmitted from the new CSM 12 (second clock supply device).

[0016] Input unit IN1 is connected to the E-system output terminal 112 of the old CSM11 via IF unit 41. Input unit IN2 is connected to the N-system output terminal 121 of the new CSM12 via IF unit 42. Input unit IN3 is connected to the E-system output terminal 122 of the new CSM12 via IF unit 43. Output unit OUT is connected to the E-system input terminal 22 of the transmission device 20. In other words, input units IN1 to IN3 receive the first clock and the second clock.

[0017] The operation unit 33 is equipped with controls such as a keyboard and a touch panel (not shown) and accepts various operations from the operator. When the operator inputs a CSM switching command, the operation unit 33 outputs a phase change command to the first phase variable unit 31 and the second phase variable unit 32. A "phase change command" refers to a command to change the phase of the clock transmitted from the old CSM 11 (referred to as the first phase φ1) to the phase of the clock transmitted from the new CSM 12 (referred to as the second phase φ2), and the opposite command to change from the second phase φ2 to the first phase φ1.

[0018] When the operator inputs a phase adjustment speed v1, the operation unit 33 outputs information of this phase adjustment speed v1 to the first phase variable unit 31 and the second phase variable unit 32. The phase adjustment speed v1 refers to the amount of change in phase difference per second. For example, if the phase difference is changed by 1 [ns] per second, the phase adjustment speed v1 is 1 [ns / second]. In this embodiment, the phase adjustment speed v1 is set according to the following conditions: (1) the tracking limit of the oscillator 35 (2) the phase jump tolerance of the transmission device 20 (3) the specifications of the elastic buffer 24 of the transmission device 20

[0019] The tracking limit of the oscillator 35 shown in (1) above is the speed at which the oscillator 35 can track changes in phase difference, and the maximum speed is about 20 [ns / second]. This speed can be considered a fixed value. The phase jump tolerance of the transmission device 20 shown in (2) above indicates the limit of the amount of change that the transmission device 20 can smoothly operate in response to changes in the clock phase, and the maximum speed is in the range of 10 to 1000 [ns / second]. In most cases it is about 200 [ns / second]. The specification of the elastic buffer 24 of the transmission device 20 shown in (3) (details will be described later) is the maximum speed of phase change based on the specification of the elastic buffer 24 installed in the transmission device 20 that stores data when the phase difference changes, and is generally 0 to 125000 [ns / second], which is capable of temporarily storing SDH standard transmission devices.

[0020] The operator inputs the slowest speed among the maximum speeds defined by the above conditions (1) to (3) as the phase adjustment speed v1 into the control unit 33. For example, if the slowest speed defined by condition (1) is 20 [ns / sec], the operator inputs 20 [ns / sec] as the phase adjustment speed v1 into the control unit 33. In addition to input by the operator, the minimum speed based on the above conditions (1) to (3) may be calculated and set as the phase adjustment speed v1.

[0021] In other words, the operator sets the phase adjustment speed v1 based on at least one of the following: the tracking limit of the oscillator 35 mounted on the phase adjustment device 30, the phase jump tolerance of the transmission device 20, and the operating limit of the elastic buffer 24 mounted on the transmission device 20. Furthermore, the phase adjustment speed v1 should be set to the slowest speed among the maximum speeds allowed by the tracking limit of the oscillator 35 mounted on the phase adjustment device 30, the jump tolerance limit of the transmission device 20, and the operating limit of the elastic buffer 24 mounted on the transmission device 20.

[0022] The first phase variable unit 31 acquires the clock transmitted from the old CSM 11 and received at the input unit IN1 (this will be called the first clock). The first phase variable unit 31 acquires the clock transmitted from the E-system output terminal 122 of the new CSM 12 and received at the input unit IN3 (this will be called the second clock).

[0023] When the operator inputs the above-described phase change command, the first phase variable unit 31 performs a process to change the phase of the second clock transmitted from the new CSM 12 (referred to as the second phase φ2) to the phase of the first clock transmitted from the old CSM 11 (referred to as the first phase φ1). The frequencies of the first clock and the second clock are assumed to be the same. That is, the first phase variable unit 31 changes the phase of the second clock from the second phase to the first phase.

[0024] The second phase variable unit 32, after the phase of the second clock has been changed from the second phase φ2 to the first phase φ1 by the first phase variable unit 31, receives a switching completion signal (details to be described later) transmitted from the transmission device 20, and performs the process of returning the first phase φ1 of the second clock transmitted from the new CSM 12 back to the second phase φ2 at the phase adjustment speed v1 described above. The second phase variable unit 32 returns the phase of the second clock from the first phase φ1 to the second phase φ2 at a predetermined phase adjustment speed v1 while the transmission device 20 is operating with the second clock after it has been changed to the first phase φ1.

[0025] Specifically, when a phase change command is input to the operation unit 33, the first phase variable unit 31 instantly changes the phase of the second clock from the second phase φ2 to the first phase φ1, and when a switching completion signal is transmitted from the transmission device 20, the second phase variable unit 32 gradually returns the phase of the second clock from the first phase φ1 to the second phase φ2 at a phase adjustment speed v1.

[0026] The communication unit 34 communicates data with the communication unit 23 mounted on the transmission device 20. The communication unit 34 sends a command to the transmission device 20 to switch between ACT (operating state) and SBY (standby state).

[0027] The transmission device 20 is equipped with an N-system (normal; operational) input terminal 21 and an E-system (emergency; standby) input terminal 22. That is, the transmission device 20 has a redundant configuration by being equipped with two input terminals 21 and 22, one for the N-system and one for the E-system. The transmission device 20 operates based on a clock received at either of the two input terminals 21 or 22. The transmission device 20 is equipped with a communication unit 23 and an elastic buffer 24 (labeled "EB" in the figure). The communication unit 23 communicates data with the phase adjustment device 30. The elastic buffer 24 is a buffer for aligning the phase of the clock and can be configured, for example, with a small-capacity FIFO (first-in first-out) register. The transmission device 20 is switched by a switching command transmitted from the phase adjustment device 30 so that one of the N-system input terminal 21 and the E-system input terminal 22 is set to ACT and the other to SBY.

[0028] Next, referring to the flowcharts shown in Figures 4 to 11 and Figure 12, we will explain the process by which the phase adjustment device 30 switches the clock supply source of the transmission device 20 from the old CSM 11 to the new CSM 12.

[0029] Figure 4 is a schematic diagram illustrating the connection state and clock transmission path when the old CSM 11 is supplying a clock to the transmission device 20. In Figure 4, black circles indicate the first clock (first phase φ1 clock) transmitted from the old CSM 11, and white circles indicate the second clock (second phase φ2 clock) transmitted from the new CSM 12. Solid arrows indicate the clock flow of the N system (operational system), and dashed arrows indicate the clock flow of the E system (standby system). The same applies to Figures 5 to 11.

[0030] As shown in Figure 4, the N-system output terminal 111 and E-system output terminal 112 of the old CSM 11 are connected to the N-system input terminal 21 and E-system input terminal 22 of the transmission device 20, respectively. Therefore, the first clock transmitted from the N-system output terminal 111 of the old CSM 11 is supplied to the N-system input terminal 21 of the transmission device 20. The first clock transmitted from the E-system output terminal 112 of the old CSM 11 is supplied to the E-system input terminal 22 of the transmission device 20.

[0031] The transmission device 20 has its N-system input terminal 21 set to ACT (operating state) and its E-system input terminal 22 set to SBY (standby state). Therefore, the transmission device 20 operates based on the first clock transmitted from the N-system output terminal 111 of the old CSM 11. Furthermore, if the first clock received at the N-system input terminal 21 is interrupted for any reason, the transmission device 20 can continue to operate by switching the E-system input terminal 22 from SBY to ACT.

[0032] If the CSM supplying the clock to the transmission device 20 needs to be changed from the old CSM 11 to the new CSM 12 due to aging or other reasons, the operator inputs a CSM switching command using the operation unit 33.

[0033] When a switching command is input, in step S11 shown in Figure 12, the phase adjustment device 30 receives the first clock transmitted from the E-system output terminal 112 of the old CSM 11 at input IN1 (see Figure 3). In step S12, the phase adjustment device 30 receives the second clock transmitted from the E-system output terminal 122 of the new CSM 12 at input IN3.

[0034] Furthermore, in step S13, the phase adjustment device 30 transmits the second clock received at the input unit IN3 to the E-system input terminal 22 of the transmission device 20 from the output unit OUT. As a result, as shown in Figure 5, the E-system input terminal 22 of the transmission device 20 is supplied with the second clock (the clock of the second phase φ2) transmitted from the new CSM 12. At this time, the transmission device 20 maintains operation based on the first clock because the N-system input terminal 21 is set to ACT and the E-system input terminal 22 is set to SBY.

[0035] When a CSM switching command is input to the operation unit 33, the above-mentioned phase change command is input to the first phase variable unit 31 and the second phase variable unit 32.

[0036] In step S14, the first phase variable unit 31 instantaneously changes the phase of the second clock (second phase φ2) transmitted to the E-system input terminal 22 of the transmission device 20 to the first phase φ1. Specifically, as shown in Figures 3 and 6, the first phase variable unit 31 of the phase adjustment device 30 acquires the first clock transmitted from the E-system output terminal 112 of the old CSM 11 and calculates the phase of this first clock (first phase φ1). The first phase variable unit 31 acquires the second clock transmitted from the E-system output terminal 122 of the new CSM 12 and calculates the phase of this second clock (second phase φ2). The first phase variable unit 31 changes the phase of the second clock from the second phase φ2 to the first phase φ1. Therefore, the E-system input terminal 22 of the transmission device 20 receives the clock with the first phase φ1, i.e., the first clock.

[0037] Figure 13 is an explanatory diagram showing the waveforms of the first and second clocks. Curve s1 in Figure 13 shows the waveform of the first clock, and curve s2 shows the waveform of the second clock. Both curves s1 and s2 have the same frequency, and the phase difference is Φ. By changing the phase of the second clock from the second phase φ2 to the first phase φ1, the waveform of the second clock is changed from curve s2 to curve s1, i.e., the waveform of the first clock (arrow L1). This change process is performed instantaneously. Therefore, as shown in Figure 6, the clock with the first phase φ1, i.e., the first clock, is input to the E system input terminal 22 of the transmission device 20.

[0038] In step S15, the phase adjustment device 30 changes the E-system input terminal 22 of the transmission device 20 from SBY to ACT. The communication unit 34 of the phase adjustment device 30, as shown in Figure 3, transmits an ACT-SBY switching signal to the communication unit 23 of the transmission device 20. Upon receiving the switching signal, the transmission device 20 executes the process of switching the N-system input terminal 21 to SBY and the E-system input terminal 22 to ACT, as shown in Figure 7. At this time, since the E-system input terminal 22 is receiving the first clock, it does not affect the operation of the transmission device 20. Once the transmission device 20 has switched the E-system input terminal 22 to ACT, it transmits a switching completion signal to the phase adjustment device 30.

[0039] In step S16, the second phase variable unit 32 receives a switching completion signal and gradually changes the phase of the clock transmitted to the E-system input terminal 22 of the transmission device 20 to the second phase φ2. When the operator inputs the phase adjustment speed v1 using the operation unit 33, the second phase variable unit 32 performs a process to gradually change the phase of the clock transmitted to the E-system input terminal 22 (designated as ACT) of the transmission device 20 from the first phase φ1 to the second phase φ2, as shown in Figure 8. At this time, the phase change speed is set to the phase adjustment speed v1 described above. Therefore, the clock supplied to the E-system input terminal 22 of the transmission device 20 is gradually returned from curve s1 to curve s2 (arrow L2), as shown in Figure 13. That is, the clock received at the E-system input terminal 22 gradually changes from the first clock to the second clock. At this time, the phase adjustment speed v1 is set to, for example, 20 [ns / second].

[0040] Since the phase of the clock supplied to the transmission device 20 gradually changes at the phase adjustment speed v1 determined to satisfy the above-described conditions (1) to (3), it is possible to avoid affecting the operation of the transmission device 20. Note that the solid circles indicated by hatching in FIG. 8 indicate the clocks for phase return.

[0041] In step S17, the phase adjustment device 30 executes a process of connecting the N-system input terminal 21 of the transmission device 20 to the N-system output terminal 121 of the new CSM12 as shown in FIG. 9. As a result, the second clock transmitted from the N-system output terminal 121 of the new CSM12 is supplied to the N-system input terminal 21 of the transmission device 20. At this time, since the N-system input terminal 21 of the transmission device 20 is set to SB Y, it does not affect the operation of the transmission device 20.

[0042] In step S18, the phase adjustment device 30 determines whether or not the phase of the clock supplied to the E-system input terminal 22 of the transmission device 20 has reached the second phase φ2. If it has reached (S18; YES), the process proceeds to step S19.

[0043] In step S19, the phase adjustment device 30 changes the N-system input terminal 21 of the transmission device 20 from SB Y to ACT. That is, the phase adjustment device 30 transmits a switching signal of SB Y-ACT to the transmission device 20. Specifically, the above switching signal is transmitted from the communication unit 34 shown in FIG. 3 to the communication unit 23 of the transmission device 20. The transmission device 20 executes a process of switching the N-system input terminal 21 to ACT and the E-system input terminal 22 to SB Y as shown in FIG. 10 by receiving the switching signal.

[0044] In step S20, the phase adjustment device 30 executes a process of connecting the E-system input terminal 22 of the transmission device 20 to the E-system output terminal 122 of the new CSM12. As a result, as shown in FIG. 11, the N-system output terminal 121 and the E-system output terminal 122 of the new CSM12 are connected to the N-system input terminal 21 and the E-system input terminal 22 of the transmission device 20, respectively. That is, the transmission device 20 operates by the second clock transmitted from the new CSM12. Thus, the clock supply source of the transmission device 20 can be switched from the aged old CSM11 to the new CSM12.

[0045] In the phase adjustment device 30 according to this embodiment, when changing the phase of the clock supplied to the transmission device 20 from the first phase φ1 to the second phase φ2, the amount of phase change per unit time is set to be larger than in the conventional method. For example, the phase adjustment speed v1 is set to 20 [ns / second], which is 20 times the conventional phase adjustment speed v1 = 1 [ns / second]. As a result, it becomes possible to shorten the time required for CSM replacement compared to the conventional method.

[0046] Figure 14 is a timing chart showing the time required for phase adjustment when the phase difference Φ between the first phase φ1 and the second phase φ2 is 30 [μs], and the phase adjustment speed v1 is 1 [ns / second] and 20 [ns / second]. As shown in Figure 14, when v1 = 1 [ns / second], 30 [μs] = 30,000 [ns], so 30,000 seconds = 8 hours and 20 minutes. Furthermore, since the time required for start and end is about 15 minutes each, the phase adjustment is completed in a total time of 8 hours and 50 minutes.

[0047] In contrast, when v1 = 20 [ns / second], (30000 / 20) = 1500 seconds = 25 minutes. Furthermore, since the time required for start and end is approximately 15 minutes each, the phase adjustment is completed in a total of 50 minutes. In other words, it is understood that by adopting the phase adjustment device 30 of this embodiment, the time required for phase adjustment can be shortened by time T1 (approximately 8 hours).

[0048] As described above, the phase adjustment device 30 according to the present embodiment is a phase adjustment device that changes the clock supplied to the transmission device 20 from the first clock of the first phase φ1 transmitted from the first clock supply device (old CSM11) to the second clock of the second phase φ2 transmitted from the second clock supply device (new CSM12). The phase adjustment device 30 includes input units IN1, IN2, and IN3 that receive the first clock and the second clock, a first phase variable unit 31 that changes the phase of the second clock from the second phase to the first phase, a communication unit 34 that transmits the second clock after being changed to the first phase to the transmission device 20, and a second phase variable unit 32 that returns the phase of the second clock to the second phase from the first phase at a predetermined phase adjustment speed v1 while the transmission device 20 is operating with the second clock after being changed to the first phase. The phase adjustment speed v1 is set based on at least one of the tracking limit of the oscillator 35 mounted on the phase adjustment device 30, the phase jump tolerance of the transmission device 20, and the operating limit of the elastic buffer 24 mounted on the transmission device 20.

[0049] In the present embodiment, the phase (second phase φ2) of the second clock output from the new CSM12 (second clock supply device) can be adjusted to the phase (first phase φ1) of the first clock output from the old CSM11 (first clock supply device) in a short time. Therefore, the time required for the CSM replacement work can be shortened.

[0050] In the present embodiment, based on the tracking limit of the oscillator 35 mounted on the phase adjustment device 30, the phase jump tolerance of the transmission device 20, and the specifications of the elastic buffer 24 of the transmission device २०, the slowest speed that allows each of the above conditions is set as the phase adjustment speed v1. Therefore, the operation of the phase adjustment device 30 and the transmission device 20 is not affected by the phase change of the clock. For this reason, the CSM switching operation can be smoothly performed.

[0051] In this embodiment, the first phase variable unit 31 transmits the second clock, after it has been changed to the first phase φ1, to the E-system input terminal 22 which is in SBY (standby state). The second phase variable unit 32 then gradually returns the phase of the second clock from the first phase back to the second phase after the E-system input terminal 22 is switched from SBY to ACT (operation state). That is, the transmission device 20 is equipped with two input terminals 21 and 22, one of which is in an operational state and the other in a standby state. The communication unit 34 transmits the second clock, after it has been changed to the first phase by the first phase variable unit 31, to one input terminal which is in a standby state. The second phase variable unit 32 then returns the phase of the second clock from the first phase back to the second phase after the one input terminal is switched from a standby state to an operational state. Therefore, abrupt changes in phase can be suppressed, and malfunctions of the transmission device 20 and the phase adjustment device 30 can be prevented.

[0052] As shown in Figure 15, the phase adjustment device 30 of this embodiment described above can use a general-purpose computer system that includes, for example, a CPU (Central Processing Unit, processor) 901, memory 902, storage 903 (HDD: Hard Disk Drive, SSD: Solid State Drive), communication device 904, input device 905, and output device 906. The memory 902 and storage 903 are storage devices. In this computer system, the CPU 901 executes a predetermined program loaded onto the memory 902, thereby realizing each function of the phase adjustment device 30.

[0053] The phase adjustment device 30 may be implemented on one computer or on multiple computers. Furthermore, the phase adjustment device 30 may be a virtual machine implemented on a computer.

[0054] The program for the phase adjustment device 30 can be stored on a computer-readable recording medium such as an HDD, SSD, USB (Universal Serial Bus) memory, CD (Compact Disc), or DVD (Digital Versatile Disc), or it can be distributed via a network. A computer-readable recording medium is, for example, a non-transitory recording medium.

[0055] This disclosure is not limited to the embodiments described above, and numerous modifications are possible within the scope of its essence.

[0056] 11 Clock supply device (first clock supply device; old CSM) 12 Clock supply device (second clock supply device; new CSM) 20 Transmission device 21 N-series input terminal 22 E-series input terminal 23, 34 Communication unit 24 Elastic buffer 30 Phase adjustment device 31 First phase variable unit 32 Second phase variable unit 33 Operation unit 34 Communication unit 35 Oscillator 111 N-series output terminal 112 E-series output terminal 121 N-series output terminal 122 E-series output terminal v1 Phase adjustment speed φ1 First phase φ2 Second phase

Claims

1. A phase adjustment device for changing the clock supplied to a transmission device from a first clock of a first phase transmitted from a first clock supply device to a second clock of a second phase transmitted from a second clock supply device, comprising: an input unit for receiving the first clock and the second clock; a first phase variable unit for changing the phase of the second clock from the second phase to the first phase; a communication unit for transmitting the second clock after it has been changed to the first phase to the transmission device; and a second phase variable unit for changing the phase of the second clock back from the first phase to the second phase at a predetermined phase adjustment speed while the transmission device is operating with the second clock after it has been changed to the first phase, wherein the phase adjustment speed is set based on at least one of the following: the tracking limit of an oscillator mounted on the phase adjustment device, the phase jump tolerance of the transmission device, and the operating limit of an elastic buffer mounted on the transmission device.

2. The phase adjustment device according to claim 1, wherein the phase adjustment speed is set to the slowest speed among the maximum speeds allowed by the tracking limit of the oscillator mounted on the phase adjustment device, the phase jump tolerance of the transmission device, and the operating limit of the elastic buffer mounted on the transmission device.

3. The phase adjustment device according to claim 1 or 2, wherein the transmission device is equipped with two input terminals, one of which is in an operational state and the other in a standby state, the communication unit transmits the second clock, which has been changed to a first phase by the first phase variable unit, to the input terminal which is in a standby state, and the second phase variable unit returns the phase of the second clock from the first phase to the second phase after the input terminal which is switched from the standby state to an operational state.

4. A phase adjustment method for changing the clock supplied to a transmission device from a first clock of first phase transmitted from a first clock supply device to a second clock of second phase transmitted from a second clock supply device, wherein an input unit receives the first clock and the second clock; a first phase variable unit changes the phase of the second clock from the second phase to the first phase; a communication unit transmits the second clock after the change to the first phase to the transmission device; and while the transmission device is operating with the second clock after the change to the first phase, the second phase variable unit changes the phase of the second clock back from the first phase to the second phase at a phase adjustment speed set based on at least one of the tracking limit of an oscillator mounted on a phase adjustment device, the phase jump tolerance of the transmission device, and the operating limit of an elastic buffer mounted on the transmission device.

Images