Pattern forming method

Abstract

[Problem] To form a pattern without a discontinuous portion even when overlay accuracy is not ensured during stitching exposure. [Solution] In a pattern forming method according to an embodiment, after a resist is formed on an underlying layer provided on a semiconductor wafer, the resist is exposed by stitching exposure, and the exposed resist is developed to form a first resist pattern. The first resist pattern has a first pattern corresponding to a first photomask, and a second pattern corresponding to a second photomask and connected to the first pattern. The first resist pattern is etched by directional etching in which active species are supplied from an oblique direction to the surface of the semiconductor wafer so that a discontinuous portion at a connection portion between the first pattern and the second pattern is removed, thereby forming a second resist pattern. The underlying layer is etched using the second resist pattern as a mask.

Description

Pattern formation method

[0001] This embodiment relates to a pattern forming method.

[0002] In High-NA lithography, which is being considered for future implementation, stitching lithography (also called stippling lithography), which involves connecting two or more exposure regions during exposure, is being explored. For example, in EUV lithography, the use of anamorphic optics reduces the exposure area on the semiconductor wafer, making stitching lithography essential for manufacturing large-area chips.

[0003] However, ensuring the accuracy of the overlap in areas that are double-exposed is difficult. If this accuracy is insufficient, areas other than those intended may be exposed, resulting in a pattern that is not formed as designed. Specifically, discontinuities may occur at the pattern connection points where the line width changes significantly. As a result, for example, the electrical characteristics of the wiring may deteriorate.

[0004] By precisely correcting the mask pattern around the connection points of the exposure area using Optical Proximity Correction (OPC), it is possible to ensure uniformity of line width and continuity of shape in the formed pattern. Here, OPC is a technique that corrects the pattern transferred onto the semiconductor wafer to the desired shape by intentionally deforming the pattern on the photomask (mask pattern) in advance.

[0005] However, this requires complex OPC processing on the mask pattern, increasing the design burden of the photomask. Furthermore, if the OPC correction is insufficient, there is a risk that line width uniformity may not be ensured at the connection points of the exposed areas.

[0006] The problem that this invention aims to solve is to provide a pattern forming method that can form a pattern without discontinuities, even when overlapping accuracy cannot be ensured in stitching exposure.

[0007] The pattern formation method according to this embodiment involves forming a resist on a substrate layer provided on a semiconductor wafer, exposing the resist by stitching exposure, and developing the exposed resist to form a first resist pattern. The first resist pattern has a first pattern corresponding to a first photomask and a second pattern corresponding to a second photomask and connected to the first pattern. The first resist pattern is etched by directional etching, which involves supplying active species to the surface of the semiconductor wafer from an oblique direction, so as to remove discontinuities at the connection portion between the first and second patterns, thereby forming a second resist pattern. The substrate layer is etched using the second resist pattern as a mask.

[0008] This is a flowchart illustrating an example of a pattern forming method according to the first embodiment. This is a cross-sectional view illustrating an example of a pattern forming method according to the first embodiment. This is a plan view illustrating an example of a pattern forming method according to the first embodiment, following Figure 2. This is a cross-sectional view along line I-I in Figure 3. This is a plan view illustrating an example of a pattern forming method according to the first embodiment, following Figure 4. This is a side view illustrating an example of directional etching in the pattern forming method according to the first embodiment. This is a side view illustrating an example of directional etching in the pattern forming method according to the first embodiment. This is a plan view illustrating an example of a pattern forming method according to the first embodiment, following Figure 7. This is a cross-sectional view along line II-II in Figure 8. This is a cross-sectional view illustrating an example of a pattern forming method according to the first embodiment, following Figure 9. This is a plan view illustrating an example of a pattern forming method according to a modification 1 of the first embodiment. This is a partially enlarged view of Figure 12. This is a plan view illustrating an example of a pattern forming method according to a modification 1 of the first embodiment, following Figure 13. This is a plan view illustrating an example of a pattern forming method according to a modification 1 of the first embodiment, following Figure 14. This is a plan view illustrating an example of a pattern forming method according to a modification 2 of the first embodiment. This is a partially enlarged view of Figure 16. Figure 17 is a perspective view illustrating an example of a pattern forming method according to a modification 2 of the first embodiment. Figure 18 is a plan view illustrating an example of a pattern forming method according to a modification 2 of the first embodiment. Figure 18 is a plan view illustrating an example of a pattern forming method according to a modification 3 of the first embodiment. Figure 22 is a flowchart illustrating an example of a pattern forming method according to the second embodiment. Figure 25 is a cross-sectional view illustrating an example of a pattern forming method according to the third embodiment.Figure 26 is a cross-sectional view illustrating an example of a pattern forming method according to the third embodiment. Figure 27 is a cross-sectional view illustrating an example of a pattern forming method according to the third embodiment. Figure 28 is a cross-sectional view illustrating an example of a pattern forming method according to the third embodiment. Figure 29 is a cross-sectional view illustrating an example of a pattern forming method according to the third embodiment.

[0009] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic and mainly show characteristic parts of each embodiment, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. The same elements are denoted by the same reference numerals in the specification and drawings.

[0010] (First Embodiment) The pattern formation method according to the first embodiment will be described in accordance with the flowchart shown in Figure 1.

[0011] Step S11: As shown in Figure 2, a resist R is formed on the underlayer 10 provided on the semiconductor wafer W. The semiconductor wafer W is, for example, a silicon wafer, but it may also be a wafer of another semiconductor material (silicon carbide, compound semiconductor, etc.).

[0012] The base layer 10 is a layer processed by the pattern forming method according to this embodiment. The type of base layer 10 is not particularly limited and may be a semiconductor layer (for example, an n-type or p-type silicon layer), a conductive layer (for example, a polysilicon layer, a metal layer), or an insulating layer (for example, SiO ２ film, Si ３ N ４ It may be a film (or an SiOC film).

[0013] The resist R is formed by applying a resist to the surface of a semiconductor wafer W fixed on a stage of a coater apparatus (not shown), rotating the semiconductor wafer W at high speed to create a uniform resist film, and then undergoing a heat treatment process called pre-baking.

[0014] Step S12: A resist pattern is formed by stitching exposure and development. Specifically, the resist R formed in step S11 is exposed by stitching exposure using a first photomask and a second photomask (not shown), and the exposed resist R is developed. In stitching exposure, for example, the first photomask and the second photomask are partially overlapped to form an overlapping region, and then the exposure regions of the first photomask and the second photomask are exposed sequentially. Alternatively, only the exposure region of the first photomask is exposed, and then only the exposure region of the second photomask is exposed.

[0015] Figure 3 is a plan view of the resist pattern P1 formed in step S12. The resist pattern P1 has a pattern 11 corresponding to the first photomask and a pattern 12 corresponding to the second photomask and connected to pattern 11.

[0016] In this embodiment, pattern 11 extends in the first direction (longitudinal direction; vertical direction in Figure 3), and has a line width CD. １ This is a line pattern having the following characteristics: Pattern 12 extends in the first direction and has a line width CD １ Line width CD equal to ２ This is a line pattern that has the following characteristics.

[0017] In the example shown in Figure 3, a lateral (widthwise) positional misalignment X occurs between pattern 11 and pattern 12 due to the overlapping misalignment of the first and second photomasks. The resist pattern P1 has a discontinuity (step) in the stitching region SA corresponding to the overlapping region of the first and second photomasks. Figure 4 is a cross-sectional view along the line I-I in Figure 3.

[0018] Step S13: The resist pattern P1 formed in step S12 is measured by an inspection device to determine whether there is a discontinuity greater than a specified value in the connection portion (stitching region SA) between pattern 11 and pattern 12. For example, if a step difference greater than a specified value is detected, it is determined that a discontinuity exists. If a discontinuity exists in the resist pattern P1 (S13: Yes), the process proceeds to step S14. On the other hand, if there is no discontinuity in the resist pattern P1 (S13: No), the process proceeds to step S15.

[0019] The inspection device used in step S13 is, for example, a dimensional measuring device such as a superimposed inspection device, a CD-SEM (Critical Dimension-Scanning Electron Microscope), or an AFM (Atomic Force Microscope).

[0020] Step S14: Discontinuities in the resist pattern P1 are removed by directional etching. As shown in Figure 5, active species G1 and G2 are supplied along the direction in which patterns 11 and 12 extend. The type of active species is not particularly limited and may be ions (such as ions derived from chlorine, bromine, or fluorine gases) or radicals (such as radicals generated from fluorine, chlorine, or bromine gases). The type of etching gas used to generate ions or radicals depends on the material of patterns 11 and 12. For example, if patterns 11 and 12 are made of silicon, a fluorine gas is used, and if patterns 11 and 12 are made of aluminum and polycrystalline silicon, a chlorine gas is used.

[0021] The etching method used in step S14 is not particularly limited as long as it is dry etching, and methods such as reactive ion etching (RIE), reactive active species etching (RIBE), inductively coupled plasma-reactive ion etching (ICP-RIE), ion beam etching (IBE), and chemical dry etching (CDE) can be used. When using methods such as IBE or RIBE, an ion beam is irradiated onto the resist pattern P1 along the longitudinal direction of patterns 11 and 12.

[0022] In the directional etching step, active species G1 and G2 are supplied to the surface of the semiconductor wafer W from an oblique direction. As a result, the active species strike the steps in the discontinuities, and the steps in the resist pattern P1 are removed. For example, directional etching is performed by tilting the semiconductor wafer W with respect to the horizontal plane. As shown in Figure 6, by tilting the semiconductor wafer W so that the pattern 11 side is raised, active species G1 is introduced from pattern 11 to pattern 12. Next, as shown in Figure 7, by tilting the semiconductor wafer W so that the pattern 12 side is raised, active species G2 is introduced from pattern 12 to pattern 11.

[0023] Thus, in step S14, first, the active species G1 is introduced to remove the protruding portion on the right side of pattern 12. Next, the active species G2 is introduced to remove the protruding portion on the left side of pattern 11. Directional etching may also be performed by changing the direction of introduction of the active species without changing the tilt of the semiconductor wafer W.

[0024] Figure 8 shows the resist pattern P2 (patterns 11 and 12) after two etching processes have removed the discontinuities. Figure 9 is a cross-sectional view along the line II-II in Figure 8. Line width CD of patterns 11 and 12 after the discontinuities have been removed. ３ The line width is CD １ CD２ is smaller than.

[0025] Thus, by step S14, a resist pattern P2 with the discontinuous portion removed is formed.

[0026] Step S15: As shown in FIG. 10, the underlying layer 10 is etched using the resist pattern P2 with the discontinuous portion removed as a mask. The etching in this step may be dry etching or wet etching. After this step, the resist pattern P2 is removed. Thereby, a pattern (stitching pattern) without a discontinuous portion is formed. Note that the pattern formed by etching the underlying layer 10 is, for example, a wiring, but is not particularly limited.

[0027] As described above, according to the pattern forming method according to the first embodiment, a resist R is formed on the underlying layer 10, and directional etching is performed on the resist pattern P1 having a discontinuous portion formed by stitching exposure and development for the resist R, thereby forming a resist pattern P2 with the discontinuous portion removed, and etching the underlying layer 10 using the formed resist pattern P2 as a mask. Thereby, even when the overlay accuracy is not ensured in the stitching exposure (for example, when an overlay shift occurs between the first photomask and the second photomask in the stitching exposure, and a positional shift occurs between the pattern 11 and the pattern 12), a pattern without a discontinuous portion can be formed.

[0028] Further, according to the present embodiment, even when the line width of the resist pattern P1 is partially formed large due to insufficient optical proximity effect correction (OPC), a pattern without a discontinuous portion can be formed.

[0029] Furthermore, according to the present embodiment, a pattern without a discontinuous portion can be formed without performing optical proximity effect correction.

[0030] In the above description, in the stitching exposure, the pattern 11 and the pattern 12 are connected with a shift in the width direction due to the horizontal misalignment between the first photomask and the second photomask. However, the present embodiment is not limited to this, and it is also applicable when the pattern 11 and the pattern 12 are connected with a shift in the longitudinal direction due to the vertical misalignment between the first photomask and the second photomask in the stitching exposure. That is, as shown in FIG. 11, even when the line width of the line pattern is partially enlarged around the stitching region SA due to the vertical misalignment between the first photomask and the second photomask, by performing directional etching with the active species G1 and G2, a pattern without a discontinuous portion similar to the pattern shown in FIG. 8 can be formed.

[0031] <Modification Example 1> Referring to FIGS. 12 to 15, a modification example 1 according to the first embodiment will be described.

[0032] In this modification example, the line width of the pattern of the first photomask is thicker than the line width of the pattern of the second photomask. Therefore, as shown in FIG. 12, the resist pattern P1 formed by the stitching exposure and development in step S12 has a line width CD of the pattern 11 １ is larger than the line width CD of the pattern 12 ２ That is, the pattern 11 is a line pattern extending in the first direction and having a line width CD １ The pattern 12 is a line pattern extending in the first direction and having a line width CD １ smaller than CD ２ That is, the pattern 12 is a line pattern extending in the first direction and having a line width CD smaller than the line width CD of the pattern 11.

[0033] As shown in the enlarged view of FIG. 13, the pattern 12 is shifted by X in the width direction with respect to the pattern 11. That is, the difference between the center line CL1 of the pattern 11 and the center line CL2 of the pattern 12 is X.

[0034] In the directional etching of step S14, as shown in FIG. 14, active species G is supplied from pattern 12 toward pattern 11 along the first direction. As a result, as shown in FIG. 15, a resist pattern P2 with the discontinuous portion removed is formed. Note that the supply of active species in the direction from pattern 11 to pattern 12 is not performed. That is, in the directional etching of this modification, the etching process is performed only once.

[0035] According to this modification, since the etching process in step S14 (directional etching) is only once, the efficiency of the pattern formation process can be improved.

[0036] Furthermore, compared with the above-described embodiment, the line width of the resist pattern P2 can be maintained. That is, a pattern with a desired line width can be formed. Specifically, if the amount of misalignment X satisfies the relationship of Equation 1, a pattern having the line width of the design dimension can be formed. X ≤ (CD １ − CD ２ ) / 2 ... (1)

[0037] <Modification 2> A modification 2 according to the first embodiment will be described with reference to FIGS. 16 to 19.

[0038] In this modification, the line width of the pattern of the first photomask is the same as the line width of the pattern of the second photomask, but the line width at the end of the pattern of the first photomask is wider than the line width of the pattern of the second photomask. Therefore, as shown in FIG. 16, in the resist pattern P1 formed by the stitching exposure and development in step S12, the line width of the end portion 11e of the pattern 11 is larger than the line width CD ２ of the pattern 12. That is, the pattern 11 is a line pattern extending in the first direction and having a line width CD １ . The pattern 12 is a line pattern extending in the first direction and having a line width CD １ equal to the line width CD ２ . However, the pattern 11 has an end portion 11e that is connected to the pattern 12 and has a line width larger than the line width CD １ .

[0039] As shown in the enlarged view of Figure 17, pattern 12 is offset by X in the width direction relative to pattern 11. The angle θ in Figure 17 is given by equation 2: θ = Arctan(X / L) ... (2) Here, L is the length of the end portion 11e and X is the amount of displacement.

[0040] Thus, the angle θ is an angle based on the amount of displacement X between pattern 11 and pattern 12 in a second direction (i.e., the width direction of patterns 11 and 12) that is perpendicular to the first direction in the plane of the semiconductor wafer W, and the length L of the edge 11e of pattern 11.

[0041] In this modified example, in the directional etching of step S14, the active species G is supplied along the direction of angle θ, as shown in Figure 18. That is, the active species is supplied along the direction rotated by angle θ from the longitudinal direction (first direction) of patterns 11 and 12. Directional etching in this modified example is performed, for example, by rotating a semiconductor wafer W tilted with respect to the horizontal plane by angle θ around the normal to its surface.

[0042] In this modified example, the number of etching steps in directional etching is the same as in the above embodiment, which is two. That is, the active species is supplied from pattern 11 to pattern 12, and then from pattern 12 to pattern 11. This forms a resist pattern P2 with discontinuities removed, as shown in Figure 19.

[0043] According to this modified example, the line width of the resist pattern P2 can be maintained. That is, a pattern with a desired line width can be formed.

[0044] Note that θ is not limited to the value given by Equation 2, but may also satisfy the range of Equation 3. 0 < θ < Arctan(X / L) ... (3)

[0045] <Modification 3> Modification 3 according to the first embodiment will be described with reference to Figure 20. In this modification, steps S11 to S13 are as described above.

[0046] In the directional etching of step S14, the number of etching cycles is the same as in the above embodiment, which is two. That is, active species are supplied from pattern 11 to pattern 12, and then from pattern 12 to pattern 11.

[0047] In this modified example, only the discontinuous portions are partially etched by directional etching. For example, as described in the second embodiment, the resist pattern P1 other than the discontinuous portions is coated with a protective film before supplying the active species, thereby etching only the discontinuous portions. As a result, as shown in Figure 20, only the discontinuous portions are removed, and a resist pattern P2 is formed in which patterns 11 and 12 are smoothly connected.

[0048] According to this modified version, the line width of the resist pattern P2 can be better maintained in areas other than the discontinuous parts. As a result, when the underlying layer 10 is a conductive layer that forms wiring, the increase in wiring resistance can be suppressed.

[0049] (Second Embodiment) Next, a pattern formation method according to the second embodiment will be described in accordance with the flowchart shown in Figure 21. One of the differences between the second embodiment and the first embodiment is that in the second embodiment, a protective film is formed to cover the resist pattern P1 other than the discontinuous parts before directional etching is performed.

[0050] The second embodiment will now be described, focusing on the differences from the first embodiment.

[0051] Step S21: A resist R is formed on the underlayer 10 provided on the semiconductor wafer W. This step is the same as step S11 described in the first embodiment, so a detailed explanation is omitted.

[0052] Step S22: A resist pattern is formed by stitching exposure and development. This step is the same as step S12 described in the first embodiment, so a detailed explanation is omitted.

[0053] Step S23: The resist pattern P1 formed in step S22 is measured by an inspection device to determine whether or not there are discontinuities exceeding a specified amount in the connection portion (stitching region SA) between pattern 11 and pattern 12. This step is the same as step S13 described in the first embodiment, so a detailed explanation is omitted.

[0054] If there is a discontinuity in the resist pattern P1 (S23: Yes), proceed to step S24. On the other hand, if there is no discontinuity in the resist pattern P1 (S23: No), proceed to step S26.

[0055] Step S24: A protective film is formed that exposes the discontinuities of the resist pattern P1. Specifically, as shown in Figure 22, a protective film 20 is formed that covers the resist pattern P1, excluding the discontinuities. The protective film 20 is made of a different resist material than the resist pattern P1. The protective film 20 may be made of an organic polymer used in the Organic Planarization Layer (OPL), or an organic material used in SOG (spin-on-glass).

[0056] Note that the resist pattern P1 in Figure 22 is the same as the one described with reference to Figure 11, and is a resist pattern in which the line width of the line pattern is partially enlarged, mainly in the stitching region SA, due to the vertical overlapping misalignment of the first photomask and the second photomask. Needless to say, the resist pattern in this embodiment is not limited to this.

[0057] In the example shown in Figure 22, the protective film 20 has an exposed portion with a width D1. The width D1 may be determined considering the amount of the protective film 20 that is removed by directional etching performed after step S24.

[0058] Step S25: Discontinuities in the resist pattern P1 are removed by directional etching. As shown in Figure 22, active species G1 and G2 are supplied along the direction in which patterns 11 and 12 extend. This step is the same as step S14 described in the first embodiment. Figure 23 shows the resist pattern P2 (patterns 11 and 12) from which the discontinuities have been removed by directional etching in step S25.

[0059] Furthermore, in the second embodiment, the methods described in the first embodiment and its modifications can also be used for directional etching.

[0060] As shown in Figure 23, the width D2 of the protective film 20 after directional etching is greater than the width D1 before directional etching. Although the protective film 20 is removed by directional etching and the exposed area of ​​patterns 11 and 12 is enlarged, by appropriately determining the width D1 in advance, it is possible to avoid the removal of unintended areas by directional etching.

[0061] Step S26: The underlayer 10 is etched using the resist pattern P2 from which the discontinuities have been removed as a mask. This step is the same as step S15 described in the first embodiment, so a detailed explanation is omitted.

[0062] As described above, according to the pattern formation method of the second embodiment, the resist pattern P1 having discontinuous portions formed by stitching exposure and development is covered with a protective film 20 on the portions other than the discontinuous portions, and then directional etching is performed to form a resist pattern P2 from which the discontinuous portions have been removed, and the formed resist pattern P2 is used as a mask to etch the underlying layer 10. As a result, similar to the first embodiment, even if the overlapping accuracy cannot be ensured in stitching exposure, a pattern without discontinuous portions (stitching pattern) can be formed.

[0063] Furthermore, the protective film 20 prevents the resist pattern P1 from being etched unintentionally due to directional etching.

[0064] (Third Embodiment) Next, the pattern formation method according to the third embodiment will be described in accordance with the flowchart shown in Figure 24. One of the differences between the third embodiment and the first embodiment is that a hard mask is formed on the base layer 10.

[0065] The third embodiment will now be described, focusing on the differences from the first embodiment.

[0066] Step S31: As shown in Figure 25, a hard mask HM is formed on the underlayer 10 provided on the semiconductor wafer W, and a resist R is formed on the hard mask HM. The hard mask HM is, for example, SiO ２ film, Si ３ N ４ It is a film or an SiOC film.

[0067] Step S32: A resist pattern is formed by stitching exposure and development. Specifically, the resist R formed in step S31 is exposed by stitching exposure using a first photomask and a second photomask (not shown), and the exposed resist R is developed. This forms the resist pattern P1 described with reference to Figure 3 in the first embodiment. Figure 26 is a cross-sectional view along the line corresponding to line I-I in Figure 3.

[0068] Step S33: The resist pattern P1 formed in step S32 is measured by an inspection device to determine whether there is a discontinuity greater than a specified value in the connection portion (stitching region SA) between pattern 11 and pattern 12. For example, if a step greater than a predetermined value is detected, it is determined that a discontinuity exists. If a discontinuity exists in the resist pattern P1 (S33: Yes), the process proceeds to step S34. On the other hand, if there is no discontinuity in the resist pattern P1 (S33: No), the process proceeds to step S37.

[0069] Step S34: As shown in Figure 27, the hard mask HM is etched using the resist pattern P1 as a mask. This forms the hard mask pattern HMP1 as shown in Figure 28. The hard mask pattern HMP1 has a pattern 13 corresponding to pattern 11 and a pattern 14 corresponding to pattern 12 and connected to pattern 13. That is, pattern 13 is a line pattern that extends in the same first direction as pattern 11 and has a first line width. Pattern 14 is a line pattern that extends in the first direction and has a second line width equal to the first line width.

[0070] The etching method used in step S34 is not particularly limited as long as it is dry etching, and methods such as reactive ion etching (RIE), reactive active species etching (RIBE), inductively coupled plasma-reactive ion etching (ICP-RIE), ion beam etching (IBE), and chemical dry etching (CDE) can be used. When using methods such as IBE or RIBE, the ion beam is irradiated onto the hard mask pattern HMP1 along the longitudinal direction of patterns 13 and 14.

[0071] Step S35: The hard mask pattern HMP1 formed in step S34 is measured by the inspection device to determine whether there is a discontinuity greater than a specified value at the connection between pattern 13 and pattern 14. For example, if a step greater than a predetermined value is detected, it is determined that a discontinuity exists. If a discontinuity exists in the hard mask pattern HMP1 (S35: Yes), the process proceeds to step S36. On the other hand, if there is no discontinuity in the hard mask pattern HMP1 (S35: No), the process proceeds to step S37. Note that the same inspection device used in step S33 can be used.

[0072] Step S36: Discontinuities in the hard mask pattern HMP1 are removed by directional etching. Specifically, as shown in Figure 29, the hard mask pattern HMP1 is etched so as to remove the discontinuities at the connection between pattern 13 and pattern 14, thereby forming the hard mask pattern HMP2. For example, as described with reference to Figure 5 in the first embodiment, discontinuities are removed by sequentially supplying active species G1 and active species G2 along the direction in which patterns 13 and 14 of the hard mask pattern HMP1 extend.

[0073] Furthermore, for the directional etching in step S36, the method described in each of the modifications of the first embodiment may be adopted. For example, when adopting the method described in Modification 1 of the first embodiment, a hard mask pattern HMP1 having the same shape as in Figure 12 in plan view may be formed, and in the directional etching of step S36, a hard mask pattern HMP2 may be formed by supplying active species along the first direction (longitudinal direction) from the narrow pattern 14 to the wide pattern 13.

[0074] Alternatively, when adopting the method described in Modification 2 of the First Embodiment, a hard mask pattern HMP1 having the same shape as in Figure 16 in plan view is formed, and in the directional etching of step S36, an active species is supplied along a direction rotated from the longitudinal direction of patterns 13 and 14 by an angle (corresponding to θ in Figure 17) based on the amount of positional displacement between patterns 13 and 14 in the width direction of the semiconductor wafer W (corresponding to X in Figure 17) and the length of the end of pattern 13 (corresponding to L in Figure 17), thereby forming a hard mask pattern HMP2. In this case, the angle only needs to satisfy the aforementioned equation (2) or equation (3).

[0075] Step S37: As shown in Figure 30, the underlying layer 10 is etched using the hard mask pattern HMP2, from which the discontinuities have been removed, as a mask. The etching in this step may be dry etching or wet etching. After this step, the hard mask pattern HMP2 is removed. This forms a pattern without discontinuities. The pattern formed by etching the underlying layer 10 is, for example, wiring, but is not particularly limited.

[0076] As described above, according to the pattern formation method of the third embodiment, a hard mask HM is formed on the base layer 10, a resist R is formed on the hard mask HM, the hard mask HM is etched using the resist pattern P1 having discontinuities formed by stitching exposure and development of the resist R as a mask to form a hard mask pattern HMP1, and a hard mask pattern HMP2 from which discontinuities have been removed is formed by directional etching of this hard mask pattern HMP1. Then, the base layer 10 is etched using the formed hard mask pattern HMP2 as a mask. As a result, similar to the first embodiment, even if the overlapping accuracy cannot be ensured in stitching exposure, a pattern without discontinuities (stitching pattern) can be formed.

[0077] Furthermore, in the third embodiment, the hard mask pattern HMP2 is used as a mask to etch the underlying layer 10 and form a pattern. This provides higher etching resistance than the resist pattern P2, and allows for the formation of structures with high aspect ratios, fine patterns, and the like.

[0078] In the above flow, step S33 determines whether or not there is a discontinuity in the resist pattern P1, and step S35 determines whether or not there is a discontinuity in the hard mask pattern HMP1. However, the process is not limited to this, and only the determination in step S35 may be performed.

[0079] Alternatively, between step S33 and step S34, discontinuities in the resist pattern P1 may be removed by directional etching. In this case, steps S35 and S36 may be omitted.

[0080] The first to third embodiments of the present invention have been described above. The embodiments may be combined as appropriate. For example, the formation of the protective film 20 described in the second embodiment may be performed between steps S35 and S36 of the third embodiment. That is, a protective film covering the hard mask pattern HMP1, excluding discontinuous portions, may be formed before directional etching.

[0081] Furthermore, the pattern formation method described above can be applied when manufacturing any semiconductor device, such as logic semiconductors, memory semiconductors, and power semiconductors.

[0082] Based on the above description, those skilled in the art may conceive of additional effects and various modifications of the present invention, but the embodiments of the present invention are not limited to the individual embodiments described above. Components from different embodiments may be combined as appropriate. Various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present invention derived from the claims and their equivalents.

[0083] 10 Underlayer 11, 12, 13, 14 Pattern 20 Protective film CL1, CL2 Centerline D1, D2 Width G, G1, G2 Active species HM Hard mask L (edge) Length P1, P2 Resist pattern R Resist SA Stitching area W Semiconductor wafer X Positional displacement

Claims

1. A pattern formation method comprising: forming a resist on a substrate layer provided on a semiconductor wafer; exposing the resist by stitching exposure; developing the exposed resist to form a first resist pattern having a first pattern corresponding to a first photomask and a second pattern corresponding to a second photomask and connected to the first pattern; etching the first resist pattern by directional etching, supplying active species to the surface of the semiconductor wafer from an oblique direction, so as to remove discontinuities at the connection portion between the first and second patterns, to form a second resist pattern; and etching the substrate layer using the second resist pattern as a mask.

2. The pattern forming method according to claim 1, wherein, before performing the directional etching, a protective film is formed to cover the first resist pattern, excluding the discontinuous portion.

3. The pattern forming method according to claim 1, wherein the first pattern is a line pattern extending in a first direction and having a first line width, and the second pattern is a line pattern extending in the first direction and having a second line width equal to the first line width, and the second resist pattern is formed by performing a first directional etching process in which an active species is supplied from the first pattern toward the second pattern along the first direction, and then performing a second directional etching process in which an active species is supplied from the second pattern toward the first pattern along the first direction.

4. The pattern forming method according to claim 1, wherein the first pattern is a line pattern extending in a first direction and having a first line width, and the second pattern is a line pattern extending in the first direction and having a second line width smaller than the first line width, and the second resist pattern is formed by supplying an active species from the second pattern toward the first pattern along the first direction in the directional etching.

5. The pattern forming method according to claim 1, wherein the first pattern is a line pattern extending in a first direction and having a first line width, the second pattern is a line pattern extending in the first direction and having a second line width equal to the first line width, the first pattern has an end connected to the second pattern and having a third line width greater than the first line width, and in the directional etching, an active species is supplied along a direction rotated from the first direction by an angle based on the amount of displacement between the first pattern and the second pattern in a second direction perpendicular to the first direction in the plane of the semiconductor wafer and the length of the end of the first pattern.

6. The pattern forming method according to claim 5, wherein the angle is within the range of the following formula: 0 < θ ≤ Arctan(X / L), where θ is the angle, L is the length of the end, and X is the amount of displacement.

7. The pattern forming method according to claim 1, wherein only the discontinuous portion is partially etched by the directional etching.

8. A pattern forming method comprising: forming a hard mask on a substrate layer provided on a semiconductor wafer; forming a resist on the hard mask; exposing the resist by stitching exposure; developing the exposed resist to form a resist pattern having a first pattern corresponding to a first photomask and a second pattern corresponding to a second photomask and connected to the first pattern; etching the hard mask using the resist pattern as a mask to form a first hard mask pattern having a third pattern corresponding to the first pattern and a fourth pattern corresponding to the second pattern and connected to the third pattern; etching the first hard mask pattern by directional etching, supplying active species to the surface of the semiconductor wafer from an oblique direction, so as to remove discontinuities at the connection portion between the third pattern and the fourth pattern, to form a second hard mask pattern; and etching the substrate layer using the second hard mask pattern as a mask.

9. The pattern forming method according to claim 8, wherein, before performing the directional etching, a protective film is formed to cover the first hard mask pattern, excluding the discontinuous portion.

10. The pattern forming method according to claim 8, wherein the first pattern is a line pattern extending in a first direction and having a first line width, and the second pattern is a line pattern extending in the first direction and having a second line width equal to the first line width, and the second hard mask pattern is formed by performing a first directional etching process in which an active species is supplied from the third pattern toward the fourth pattern along the first direction, and then performing a second directional etching process in which an active species is supplied from the fourth pattern toward the third pattern along the first direction.

11. The pattern forming method according to claim 8, wherein the first pattern is a line pattern extending in a first direction and having a first line width, and the second pattern is a line pattern extending in the first direction and having a second line width smaller than the first line width, and the second hard mask pattern is formed by supplying an active species along the first direction from the fourth pattern toward the third pattern in the directional etching.

12. The pattern forming method according to claim 8, wherein the first pattern is a line pattern extending in a first direction and having a first line width, the second pattern is a line pattern extending in the first direction and having a second line width equal to the first line width, the first pattern has an end connected to the second pattern and having a third line width greater than the first line width, and in the directional etching, an active species is supplied along a direction rotated from the first direction by an angle based on the amount of displacement between the third pattern and the fourth pattern in a second direction perpendicular to the first direction in the plane of the semiconductor wafer and the length of the end of the third pattern.

13. The pattern forming method according to claim 12, wherein the angle is within the range of the following formula: 0 < θ ≤ Arctan(X / L), where θ is the angle, L is the length of the end, and X is the amount of displacement.

14. The pattern forming method according to claim 8, wherein only the discontinuous portion is partially etched by the directional etching.

15. The pattern forming method according to any one of claims 1 to 14, wherein directional etching is performed when the step difference of the discontinuous portion is greater than or equal to a specified value.

Images