Power conversion device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-10-15
- Publication Date
- 2026-08-13
Smart Images
Figure JP2025036270_13082026_PF_FP_ABST
Abstract
Description
Power conversion device
[0001] The present invention relates to a power conversion device.
[0002] As a kind of semiconductor switching element used in a power conversion device, a semiconductor switching element having two gates that can be driven independently of each other is known.
[0003] For example, FIGS. 1 and 2 of Patent Document 1 describe that when turning off an IGBT (Insulated Gate Bipolar Transistor) having two gates that can be driven independently of each other, by inputting an off driving signal to the second gate electrode before the first gate electrode, the turn-off loss can be reduced.
[0004] International Publication No. 2014 / 038064
[0005] However, since an IGBT structurally has a pnpn parasitic thyristor, in the RBSOA (Reverse Bias Safe Operating Area) where a high voltage is applied, the parasitic thyristor may latch up and the IGBT may be destroyed.
[0006] The problem to be solved by the present invention is to provide a power conversion device that can suppress the operation of a parasitic thyristor in an IGBT having two gates that can be driven independently of each other and improve the RBSOA tolerance.
[0007] To solve the above-mentioned problems, the present invention provides a power conversion device comprising: a semiconductor switching element having a first gate electrode and a second gate electrode that can be driven independently of each other; and a drive circuit for driving the semiconductor switching element, wherein the semiconductor switching element is an IGBT and comprises: a first conductivity type drift layer; a second conductivity type body layer disposed on the surface side of the drift layer; a first trench disposed on one side of the body layer and having a first gate insulating film and the first gate electrode inside; a second trench disposed on the other side of the body layer and having a second gate insulating film and the second gate electrode inside; and a first conductive element disposed on the surface side of the body layer. The semiconductor switching element comprises an electrically conductive emitter layer, an emitter electrode disposed on the surface side of the body layer and electrically connected to the emitter layer, a second conductivity type contact layer ohmic connecting the body layer and the emitter electrode, a second conductivity type collector layer disposed on the back side of the drift layer, and a collector electrode electrically connected to the collector layer, wherein when the semiconductor switching element is turned off, an off signal is applied to the second gate electrode before the first gate electrode, and when the distance between the contact layer and the first trench is defined as the first distance and the distance between the contact layer and the second trench is defined as the second distance, the second distance is shorter than the first distance.
[0008] According to the present invention, it is possible to realize a power conversion device that can suppress the operation of parasitic thyristors in an IGBT having two gates that can be driven independently of each other, thereby improving the RBSOA withstand capability.
[0009] A circuit diagram showing an example of the power conversion device of Example 1. A timing chart showing an example of the driving method for the semiconductor switching element of Example 1. A cross-sectional view showing an example of the semiconductor switching element of Example 1. A cross-sectional view showing an example of the semiconductor switching element of Example 2. A cross-sectional view showing an example of the semiconductor switching element of Example 3. A cross-sectional view showing an example of the semiconductor switching element of Example 4.
[0010] The embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant explanations are omitted.
[0011] Figure 1 is a circuit diagram showing an example of the power conversion device of Embodiment 1.
[0012] In this embodiment, a three-phase inverter is used as an example of a power conversion device, but the invention is not limited to this.
[0013] The power converter 200 of this embodiment includes a semiconductor switching element 100 having a first gate electrode and a second gate electrode that can be driven independently of each other, and a drive circuit 120 that drives the semiconductor switching element 100.
[0014] More specifically, the power conversion device 200 of this embodiment includes a semiconductor switching element 100, a diode 110, a drive circuit 120, an input terminal 130, and an output terminal 140.
[0015] In this embodiment, an IGBT having two gates that can be driven independently of each other is used as the semiconductor switching element 100.
[0016] DC power supplies are connected to the two input terminals 130, and DC power is input to them.
[0017] Between the two input terminals 130, the semiconductor switching element 100 constituting the upper arm and the semiconductor switching element 100 constituting the lower arm are connected in series to form a one-phase leg. The power converter 200 in this embodiment has three-phase legs. An AC output is output to the output terminal 140 from the connection node between the emitter of the semiconductor switching element 100 constituting the upper arm and the collector of the semiconductor switching element 100 constituting the lower arm.
[0018] Each semiconductor switching element 100 has a diode 110 connected to it in antiparallel.
[0019] The drive circuit 120 drives each of the semiconductor switching elements 100.
[0020] Figure 2 is a timing chart showing an example of a driving method for the semiconductor switching element in Example 1. In Figure 2, the horizontal axis represents time, and the vertical axis represents voltage.
[0021] The drive circuit 120 applies a first gate drive signal G1 to the first gate electrode of the semiconductor switching element 100 and a second gate drive signal G2 to the second gate electrode of the semiconductor switching element 100.
[0022] Figure 2 shows an example of a driving method when turning off the semiconductor switching element 100, where +Vg is the ON signal and -Vg is the OFF signal. As shown in Figure 2, when turning off the semiconductor switching element 100, the OFF signal is applied to the second gate electrode by a period Δt before the first gate electrode. This reduces the turn-off loss. The reason for this will be explained later.
[0023] Although not shown in the diagram, when turning on the semiconductor switching element 100, it is desirable to apply an ON signal to the first gate electrode before the second gate electrode, or to apply an ON signal to the second gate electrode before the first gate electrode. This makes it possible to control the time rate of change of the output voltage, dv / dt, when the semiconductor switching element 100 is turned on.
[0024] Figure 3 is a cross-sectional view showing an example of a semiconductor switching element of Example 1.
[0025] In this embodiment, a side-gate structured n-type double-gate IGBT is described as an example. In this embodiment, the first conductivity type of the semiconductor layer is n-type and the second conductivity type is p-type. The impurity concentration of the semiconductor layer increases in the order n- < n < n+ and p- < p < p+. The concentrations of n+ and p+ are high enough to enable ohmic connection. Note that the impurity concentration of the semiconductor layer in this embodiment is just an example, and it can be changed as appropriate within a range that allows the intended operation in this embodiment to be achieved.
[0026] The semiconductor switching element 100 in this embodiment is an IGBT and includes a drift layer 1, a body layer 2, a trench 3, a gate insulating film 4, a gate electrode 5, an emitter layer 6, a contact layer 7, a collector layer 8, an emitter electrode 11, and a collector electrode 12. Furthermore, the semiconductor switching element 100 in this embodiment also includes an interlayer insulating film 10, a field plate 13, and a trench insulating film 14. Preferably, the semiconductor switching element 100 in this embodiment also includes a buffer layer 9.
[0027] The drift layer 1 is a first-conductivity semiconductor layer, and its impurity concentration is, for example, n-.
[0028] Body layer 2 is a second-conductivity semiconductor layer, and its impurity concentration is, for example, p. Body layer 2 is located on the surface side of drift layer 1.
[0029] Trench 3 has a first trench 3A and a second trench 3B. Gate insulating film 4 has a first gate insulating film 4A and a second gate insulating film 4B. Gate electrode 5 has a first gate electrode 5A and a second gate electrode 5B. Gate electrode 5 is made of, for example, polysilicon.
[0030] The first trench 3A is located on one side of the body layer 2 and contains a first gate insulating film 4A and a first gate electrode 5A. The second trench 3B is located on the other side of the body layer 2 and contains a second gate insulating film 4B and a second gate electrode 5B.
[0031] The first gate drive signal G1, as described in Figure 2, is applied to the first gate electrode 5A. Similarly, the second gate drive signal G2, as described in Figure 2, is applied to the second gate electrode 5B.
[0032] The emitter layer 6 is a first-conductivity semiconductor layer, and its impurity concentration is, for example, n+. The emitter layer 6 is located on the surface side of the body layer 2. In this embodiment, the emitter layer 6 is located both near the first trench 3A and near the second trench 3B.
[0033] The emitter electrode 11 is a surface electrode formed of, for example, a conductive metal. The emitter electrode 11 is positioned on the surface side of the body layer 2 and is electrically connected to the emitter layer 6.
[0034] The contact layer 7 is a second-conductivity semiconductor layer, and its impurity concentration is, for example, p+. The contact layer 7 ohmic connects the body layer 2 and the emitter electrode 11. The impurity concentration of the contact layer 7 is higher than that of the body layer 2.
[0035] The interlayer insulating film 10 insulates the gate electrode 5 from the emitter electrode 11. The emitter electrode 11 is electrically connected to the emitter layer 6 and the contact layer 7 through contact holes provided in the interlayer insulating film 10.
[0036] The collector layer 8 is a second-conductivity semiconductor layer, and its impurity concentration is, for example, p. The collector layer 8 is located on the back side of the drift layer 1.
[0037] The collector electrode 12 is a back electrode formed of, for example, a conductive metal. The collector electrode 12 is electrically connected to the collector layer 8.
[0038] The buffer layer 9 is a first-conductivity semiconductor layer with an impurity concentration of, for example, n. The buffer layer 9 is located between the drift layer 1 and the collector layer 8. The impurity concentration of the buffer layer 9 is higher than that of the drift layer 1.
[0039] Furthermore, the semiconductor switching element 100 in this embodiment is a side-gate IGBT, and the trench 3 is formed wider than that of a typical trench-gate IGBT described later. The gate insulating film 4 and gate electrode 5 are arranged on one side wall and the other side wall inside the trench 3, respectively. Between the gate electrode 5 on one side wall and the gate electrode 5 on the other side wall, there is an in-trench insulating film 14 that insulates them from each other. The in-trench insulating film 14 is also part of the interlayer insulating film 10. It is desirable that the gate electrode 5 has a so-called sidewall shape, which widens from the top surface to the bottom surface. In a side-gate IGBT, the feedback capacitance can be reduced compared to a typical trench-gate IGBT, and the turn-off loss can be reduced while maintaining the same on-voltage as a typical trench-gate IGBT.
[0040] Furthermore, it is desirable that the semiconductor switching element 100 in this embodiment has a field plate 13 provided inside the trench 3. The field plate 13 is electrically connected to the emitter electrode 11 and is insulated from the drift layer 1 by an insulating film that is about the same thickness as the gate insulating film 4. In addition, the field plate 13 is also insulated from the two gate electrodes 5 arranged inside the same trench 3 by an in-trench insulating film 14.
[0041] Next, the operation of the semiconductor switching element 100 in this embodiment will be described.
[0042] First, we will explain why the drive method described in Figure 2 can reduce turn-off losses in a double-gate IGBT.
[0043] The semiconductor switching element 100 in this embodiment is a double-gate IGBT, and as explained in Figure 2, when the semiconductor switching element 100 is turned off, the off signal is applied to the second gate electrode 5B before the first gate electrode 5A.
[0044] When an off signal is applied to the second gate electrode 5B, the channel on the second gate electrode 5B side, which has been generated in the body layer 2 by the second gate electrode 5B, disappears. As a result, electrons are no longer injected from the emitter layer 6 into the drift layer 1 on the second gate electrode 5B side. Accordingly, the amount of holes 15 injected from the collector layer 8 into the drift layer 1 decreases.
[0045] When an off signal is applied to the first gate electrode 5A in this state, the channel on the first gate electrode 5A side, which has been generated in the body layer 2 by the first gate electrode 5A, also disappears. As a result, electrons are no longer injected from the emitter layer 6 into the drift layer 1 on the first gate electrode 5A side either. Consequently, the semiconductor switching element 100 turns off.
[0046] Here, when an off signal is applied to the first gate electrode 5A, the amount of holes 15 accumulated in the drift layer 1 decreases, so the discharge time of the holes 15 is shortened accordingly. As a result, the turn-off time of the semiconductor switching element 100 is shortened, and the turn-off loss can be reduced.
[0047] Next, the problem of latch-up of the parasitic thyristor in the IGBT will be described.
[0048] The IGBT has a pnpn parasitic thyristor composed of a p-type collector layer 8, an n-type drift layer 1, a p-type body layer 2, and an n+-type emitter layer 6 inside the element.
[0049] When a large current flows through the IGBT, current also flows through the body layer 2 directly beneath the emitter layer 6. As a result, a voltage drop occurs due to the resistance of the body layer 2. This creates a potential difference between the emitter layer 6 and the body layer 2, causing electrons to be injected from the emitter layer 6 into the body layer 2. Consequently, the parasitic NPN transistor formed by the emitter layer 6, body layer 2, and drift layer 1 is turned on. The current in this parasitic NPN transistor becomes the base current of the parasitic PNP transistor formed by the body layer 2, drift layer 1, and collector layer 8, turning on the parasitic PNP transistor. This further increases the potential difference between the emitter layer 6 and the body layer 2, resulting in positive feedback. As a result, the parasitic PNPN thyristor latches up.
[0050] Here, by connecting the emitter electrode 11 and the body layer 2 with low resistance via a p+ type contact layer 7, for example, in an RBSOA where a high voltage is applied, the holes 15 generated by the dynamic avalanche flow into the contact layer 7 and are discharged to the emitter electrode 11. Because the contact resistance can be reduced by the contact layer 7, a potential difference between the emitter layer 6 and the body layer 2 is less likely to occur, the base current of the parasitic NPN transistor is suppressed, and it becomes possible to prevent the turning on of the parasitic NPN transistor, the turning on of the parasitic PNP transistor, and the latch-up of the parasitic thyristor.
[0051] However, even with a contact layer 7, if the distance over which the current flows from the emitter layer 6 to the body layer 2 increases, the potential difference between the emitter layer 6 and the body layer 2 increases accordingly. This allows electrons to be injected from the emitter layer 6 into the body layer 2, making it easier for the parasitic NPN transistor to turn on. As a result, latch-up of the parasitic thyristor becomes more likely.
[0052] Therefore, in this embodiment, the semiconductor switching element 100 is configured such that when the semiconductor switching element 100 is turned off, an off signal is applied to the second gate electrode 5B before the first gate electrode 5A, and the distance between the contact layer 7 and the first trench 3A is defined as the first distance d1, and the distance between the contact layer 7 and the second trench 3B is defined as the second distance d2, wherein the second distance d2 is shorter than the first distance d1.
[0053] Furthermore, in order to achieve a configuration in which the second distance d2 is shorter than the first distance d1, it is desirable to use an asymmetrical arrangement, as shown in Figure 3, where the distance from the emitter electrode 11 to the second trench 3B is set to be shorter than the distance from the emitter electrode 11 to the first trench 3A. This makes it possible to achieve a configuration in which the second distance d2 is shorter than the first distance d1, even if the distance by which the contact layer 7 protrudes from the contact portion with the emitter electrode 11 toward the first trench 3A is the same as the distance by which the contact layer 7 protrudes from the contact portion with the emitter electrode 11 toward the second trench 3B. However, this is not limited to this, and the distance by which the contact layer 7 protrudes from the contact portion with the emitter electrode 11 toward the first trench 3A is different from the distance by which the contact layer 7 protrudes from the contact portion with the emitter electrode 11 toward the second trench 3B.
[0054] When an off signal is applied to the second gate electrode 5B, as shown in Figure 3, holes 15 accumulate around the second gate electrode 5B near the interface between the body layer 2 and the second gate insulating film 4B, and near the interface between the drift layer 1 and the second gate insulating film 4B. These holes 15 can easily escape to the contact layer 7 because the second distance d2 is short. As a result, the amount of holes 15 accumulated in the drift layer 1 before an off signal is applied to the first gate electrode 5A can be further reduced compared to the case where the second distance d2 is equal to or greater than the first distance d1. Consequently, the hole 15 elimination time is further shortened compared to the case where the second distance d2 is equal to or greater than the first distance d1, the turn-off time of the semiconductor switching element 100 is further shortened, and the turn-off loss can be further reduced.
[0055] Furthermore, because the second distance d2 is shorter than the first distance d1, the distance over which the current flows to the body layer 2 directly below the emitter layer 6 can also be shortened, thereby reducing the voltage drop that occurs in the body layer 2. This suppresses the operation of parasitic NPN transistors. As a result, the operation of parasitic thyristors can be suppressed, and the RBSOA withstand capability can be improved.
[0056] In this embodiment, it is desirable that the semiconductor switching element 100 has a configuration in which a plurality of semiconductor switching elements, including at least a first semiconductor switching element 100A, a second semiconductor switching element 100B, and a third semiconductor switching element 100C, are connected in parallel with each other. By configuring the semiconductor switching element 100 with a plurality of semiconductor switching elements connected in parallel with each other, it becomes possible to pass a large current.
[0057] The first semiconductor switching element 100A, the second semiconductor switching element 100B, and the third semiconductor switching element 100C are arranged in this order in a direction that intersects the extending direction of the trench 3 and in a direction that intersects the line connecting the front and back surfaces. A first trench 3A is located between the first semiconductor switching element 100A and the second semiconductor switching element 100B. A second trench 3B is located between the second semiconductor switching element 100B and the third semiconductor switching element 100C.
[0058] The first trench 3A contains the first gate electrode 5A of the first semiconductor switching element 100A, the first gate electrode 5A of the second semiconductor switching element 100B, and the first trench-internal insulating film 14A disposed between them.
[0059] Similarly, the second trench 3B contains the second gate electrode 5B of the second semiconductor switching element 100B, the second gate electrode 5B of the third semiconductor switching element 100C, and the second trench insulating film 14B disposed between them.
[0060] When even more semiconductor switching elements are arranged, the same structure is repeated. In this case, the first semiconductor switching element 100A and the third semiconductor switching element 100C have the same structure. Therefore, the second semiconductor switching element 100B is placed next to the third semiconductor switching element 100C, which is also the first semiconductor switching element 100A, and the third semiconductor switching element 100C is placed next to that. Furthermore, focusing on the trench 3, the configuration consists of the first trench 3A and the second trench 3B arranged alternately.
[0061] By using this arrangement, the same gate drive signal can be applied to the two gate electrodes 5 located inside the same trench 3, thus simplifying the wiring layout for supplying the gate drive signal.
[0062] However, the arrangement is not limited to this configuration, and a configuration in which the first gate electrode 5A and the second gate electrode 5B are located inside the same trench 3 is also possible.
[0063] As described above, according to this embodiment, it is possible to realize a power converter 200 that can suppress the operation of parasitic thyristors in an IGBT having two gates that can be driven independently of each other, and improve the RBSOA withstand capability.
[0064] Figure 4 is a cross-sectional view showing an example of a semiconductor switching element of Example 2.
[0065] Example 2 is a modification of Example 1. In Example 2, the configuration of the emitter layer 6 is different from that of Example 1.
[0066] In this embodiment, the semiconductor switching element 100 has an emitter layer 6 located near the first trench 3A, but not near the second trench 3B.
[0067] In other words, the outermost surface of the semiconductor layer located on the first trench 3A side is of the first conductivity type, and the outermost surface of the semiconductor layer located on the second trench 3B side is of the second conductivity type.
[0068] According to this embodiment, when an off signal is applied to the second gate electrode 5B and the hole 15 is discharged, the emitter layer 6 is not located near the second trench 3B, so there are no parasitic thyristors and no latch-up of parasitic thyristors occurs. Therefore, the operation of parasitic thyristors can be suppressed, and the RBSOA tolerance can be improved compared to Embodiment 1.
[0069] Figure 5 is a cross-sectional view showing an example of a semiconductor switching element of Example 3.
[0070] Example 3 is a modification of Example 2. Example 3 differs from Example 2 in that the second distance d2 is 0.
[0071] In this embodiment, the semiconductor switching element 100 has a contact layer 7 and a second trench 3B in contact.
[0072] According to this embodiment, when an off signal is applied to the second gate electrode 5B and the hole 15 is discharged, the second distance d2 is 0, making it easier to discharge the hole 15 compared to the case where the second distance d2 is longer than 0.
[0073] As a modification of this embodiment, the emitter layer 6 may also be applied to a configuration in which the emitter layer 6 is located near the second trench 3B, as in Embodiment 1. In this case as well, since the second distance d2 is 0, it is easier to discharge the holes 15 compared to the case where the second distance d2 is longer than 0. Also, since the resistance of the contact layer 7 is smaller than the resistance of the body layer 2, the voltage drop due to the current flowing directly beneath the emitter layer 6 near the second trench 3B is reduced. Therefore, the operation of parasitic thyristors can be suppressed, and the RBSOA withstand capability can be improved compared to Embodiment 1.
[0074] Figure 6 is a cross-sectional view showing an example of a semiconductor switching element according to Example 4.
[0075] Example 4 is a modification of Example 1. Example 4 differs from Example 1 in that the semiconductor switching element 100 is a general trench gate IGBT.
[0076] The semiconductor switching element 100 in this embodiment has the same basic structure as in Embodiment 1, but differs from Embodiment 1 in that the trench 3 is not a wide trench, and one gate electrode 5 is located inside the trench 3.
[0077] Inside the first trench 3A, there is a first gate electrode 5A that serves as both the first gate electrode 5A of the first semiconductor switching element 100A and the first gate electrode 5A of the second semiconductor switching element 100B.
[0078] Similarly, the second trench 3B contains a second gate electrode 5B that serves as both the second gate electrode 5B of the second semiconductor switching element 100B and the second gate electrode 5B of the third semiconductor switching element 100C.
[0079] According to this embodiment, the same effects as in Embodiment 1 can be obtained, except for the effects specific to side-gate IGBTs.
[0080] Although embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical idea of the present invention. Furthermore, some or all of the configurations described in each embodiment may be combined and applied.
[0081] For example, the configuration of Example 4 may be applied to Example 2 or Example 3.
[0082] 1: Drift layer, 2: Body layer, 3: Trench, 3A: First trench, 3B: Second trench, 4: Gate insulating film, 4A: First gate insulating film, 4B: Second gate insulating film, 5: Gate electrode, 5A: First gate electrode, 5B: Second gate electrode, 6: Emitter layer, 7: Contact layer, 8: Collector layer, 9: Buffer layer, 10: Interlayer insulating film, 11: Emitter electrode, 12: Collector electrode, 13: Field plate, 14: Insulating film in trench, 14A: Second 1: Insulating film in trench 1, 14B: Insulating film in trench 2, 15: Hole, 100: Semiconductor switching element, 100A: First semiconductor switching element, 100B: Second semiconductor switching element, 100C: Third semiconductor switching element, 110: Diode, 120: Drive circuit, 130: Input terminal, 140: Output terminal, 200: Power converter, d1: First distance, d2: Second distance, G1: First gate drive signal, G2: Second gate drive signal.
Claims
1. A power conversion device comprising: a semiconductor switching element having a first gate electrode and a second gate electrode that can be driven independently of each other; and a drive circuit for driving the semiconductor switching element, wherein the semiconductor switching element is an IGBT and comprises: a drift layer of a first conductivity type; a body layer of a second conductivity type disposed on the surface side of the drift layer; a first trench disposed on one side of the body layer and having a first gate insulating film and the first gate electrode inside; a second trench disposed on the other side of the body layer and having a second gate insulating film and the second gate electrode inside; an emitter layer of a first conductivity type disposed on the surface side of the body layer and electrically connected to the emitter layer; a contact layer of a second conductivity type ohmic connecting the body layer and the emitter electrode; a collector layer of a second conductivity type disposed on the back side of the drift layer; and a collector electrode electrically connected to the collector layer. A power conversion device characterized in that, when the semiconductor switching element is turned off, an off signal is applied to the second gate electrode before the first gate electrode, and when the distance between the contact layer and the first trench is defined as the first distance and the distance between the contact layer and the second trench is defined as the second distance, the second distance is shorter than the first distance.
2. The power conversion device according to claim 1, characterized in that the emitter layer is located both near the first trench and near the second trench.
3. The power conversion device according to claim 1, characterized in that the emitter layer is located near the first trench but not near the second trench.
4. The power conversion device according to claim 1, characterized in that the contact layer and the second trench are in contact.
5. The power conversion device according to claim 1, comprising a plurality of semiconductor switching elements connected in parallel to each other, including at least a first semiconductor switching element, a second semiconductor switching element, and a third semiconductor switching element, wherein the first semiconductor switching element, the second semiconductor switching element, and the third semiconductor switching element are arranged in this order, the first trench is disposed between the first semiconductor switching element and the second semiconductor switching element, and the second trench is disposed between the second semiconductor switching element and the third semiconductor switching element.
6. The power conversion device according to claim 5, wherein the first trench contains the first gate electrode of the first semiconductor switching element, the first gate electrode of the second semiconductor switching element, and a first trench-internal insulating film disposed between them, and the second trench contains the second gate electrode of the second semiconductor switching element, the second gate electrode of the third semiconductor switching element, and a second trench-internal insulating film disposed between them.
7. The power conversion device according to claim 5, wherein the first trench has a first gate electrode that serves as both the first gate electrode of the first semiconductor switching element and the first gate electrode of the second semiconductor switching element, and the second trench has a second gate electrode that serves as both the second gate electrode of the second semiconductor switching element and the second gate electrode of the third semiconductor switching element.