Semiconductor element

Abstract

The present invention provides a semiconductor element having a barrier region and a pillar region, wherein gate interference is suppressed. Provided is a semiconductor element, wherein: a boundary region is a region which is part of a diode region and which is positioned within a region of the same width as the thickness from an IGBT region to a drift region; and a main region is a region which is part of the diode region and which is positioned on the opposite side from the IGBT region with the boundary region sandwiched therebetween. Within a specific unit semiconductor region, which is at least one unit semiconductor region within the boundary region, the voltage drop that occurs in a current pass-through region when current flows to from the drift region to a collector electrode via the current pass-through region is less than that in the main region.

Description

semiconductor element

[0001] (Cross-reference of related applications) This application is a related application to Japanese Patent Application No. 2025-016693, filed on 4 February 2025, and claims priority based on this Japanese Patent Application. All contents of this Japanese Patent Application are incorporated herein by reference as constituting this specification.

[0002] The technologies disclosed herein relate to semiconductor devices.

[0003] Japanese Patent Publication No. 2015-165541 discloses a semiconductor device incorporating an IGBT (insulated gate bipolar transistor) and a diode. This type of semiconductor device is sometimes called an RC-IGBT (Reverse Conducting-IGBT). This semiconductor device has a semiconductor substrate, an emitter electrode provided on the upper part of the semiconductor substrate, and a collector electrode provided on the lower part of the semiconductor substrate. The semiconductor substrate has an IGBT region and a diode region. An IGBT is provided in the IGBT region, and a pn diode (hereinafter simply referred to as a diode) is provided in the diode region. The p-type body region of the IGBT is provided spanning from the IGBT region to the diode region. The body region within the diode region functions as the anode of the diode. The anode of the diode is connected to the emitter electrode, and the cathode of the diode is connected to the collector electrode. This semiconductor device can operate as both an IGBT and a diode.

[0004] When an RC-IGBT turns on as a diode, a higher potential is applied to the emitter electrode than to the collector electrode. Also, when an RC-IGBT is operating as a diode, if a potential above the gate threshold is applied to the gate electrode, a channel is formed within the IGBT region, connecting the emitter electrode to the drift region, and the potential in the drift region within the IGBT region rises. When the potential in the drift region within the IGBT region rises, the potential in the drift region within the diode region near the IGBT region also rises. Therefore, it becomes difficult for the diode to turn on within the diode region near the IGBT region. This difficulty in turning on the diode due to the potential of the gate electrode is called gate interference. When gate interference occurs, the operation of the diode becomes unstable. For example, when gate interference occurs, diode snapback occurs within the diode region near the IGBT region. Snapback is a phenomenon in which a pn diode does not turn on even when the potential of the emitter electrode (potential relative to the collector electrode) is raised to a potential higher than the forward voltage of the diode, but turns on when the potential of the emitter electrode is raised even further, causing a sharp drop in the potential of the emitter electrode.

[0005] In RC-IGBTs, a structure is sometimes adopted in which an n-type barrier region is provided inside the body region, separating the body region into upper and lower sections by the barrier region. Additionally, an n-type pillar region may be provided connecting the barrier region and the emitter electrode. The barrier region makes Schottky contact with the emitter electrode. Providing the barrier region and pillar region suppresses hole injection from the body region into the drift region, improving the diode's switching characteristics. This specification proposes a technique for suppressing gate interference in semiconductor devices having a barrier region and a pillar region.

[0006] The semiconductor device disclosed herein comprises a semiconductor substrate, an emitter electrode in contact with the upper surface of the semiconductor substrate, and a collector electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode and a current-passing region in contact with the collector electrode. The current-passing region is composed of an n-type cathode region, or an alternating arrangement region in which an n-type cathode region narrower than the collector region and a p-type current-shielding region narrower than the collector region are alternately arranged. When the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region, and the area overlapping with the current-passing region is the diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. The trench within the IGBT region has a gate trench in which a gate insulating film and a gate electrode are disposed inside. The trench within the diode region has a dummy trench in which a dummy electrode insulated from the gate electrode is disposed inside. Each semiconductor region sandwiched between the centerlines of the plurality of trenches is a unit semiconductor region. A plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region. Each of the unit semiconductor regions within the IGBT region and the diode region has a p-type contact region in contact with the emitter electrode, a p-type top body region in contact with the contact region and the trench and having a lower p-type impurity concentration than the contact region, an n-type barrier region in contact with the top body region from below and in contact with the trench, a p-type bottom body region in contact with the barrier region from below and in contact with the trench, and an n-type pillar region connecting the emitter electrode and the barrier region and making Schottky contact with the emitter electrode.At least one of the unit semiconductor regions within the IGBT region has an n-type emitter region that is in contact with the emitter electrode, in contact with the trench above the top body region, and separated from the barrier region by the top body region. The semiconductor substrate is distributed across the IGBT region and the diode region, and each unit semiconductor region has an n-type drift region that is in contact with the bottom body region from below. Of the diode region, the region adjacent to the IGBT region is the boundary region. Of the diode region, the region located on the opposite side of the IGBT region across the boundary region is the main region. Within a specific unit semiconductor region which is at least one of the unit semiconductor regions within the boundary region, the voltage drop that occurs in the current-passing region when current flows from the drift region to the collector electrode via the current-passing region is smaller than in the main region.

[0007] In this semiconductor device, a diode is formed within a diode region by a contact region, a top body region, a barrier region, a bottom body region, a drift region, and a cathode region. The contact region, top body region, and bottom body region function as the anode region of the diode. When the potential of the emitter electrode increases, current flows from the contact region to the cathode region through the top body region, barrier region, bottom body region, and drift region. Within a specific unit semiconductor region, the voltage drop that occurs in the current-passing region when current flows from the drift region to the collector electrode via the current-passing region is smaller than within the main region. Therefore, the diode is more easily turned on within the boundary region having a specific unit semiconductor region than within the main region. For this reason, even if a channel is formed in the IGBT region and the potential of the drift region within the boundary region increases, the diode within the boundary region can be turned on appropriately, and gate interference can be suppressed.

[0008] A top view of the semiconductor element 10 of Example 1. A cross-sectional view along line II-II in Figure 1. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 1. Cross-sectional views of semiconductor elements of Examples 2 to 6. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 2. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 3. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 4. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 5. A cross-sectional comparison diagram of a specific unit semiconductor region 66b and a unit semiconductor region 66a of Example 6. A cross-sectional view of the semiconductor element of Example 7. A cross-sectional view of a modified semiconductor element of Example 7. A cross-sectional view of the semiconductor element of Example 8. A cross-sectional view of the semiconductor element of Example 9. A cross-sectional comparison diagram showing an example of a combination of multiple examples. A cross-sectional comparison diagram showing an example of a combination of multiple examples. Cross-sectional view of a semiconductor device of a modified example of Example 1.

[0009] As shown in Figure 1, the semiconductor element 10 of Embodiment 1 has a semiconductor substrate 12 made of silicon. As shown in Figure 1, when viewed from above, the semiconductor substrate 12 is divided into an element portion 13 and an outer peripheral portion 17. The element portion 13 is divided into a plurality of IGBT regions 15 and a plurality of diode regions 16. IGBTs are provided in the IGBT regions 15, and diodes are provided in the diode regions 16. Each of the IGBT regions 15 and diode regions 16 has a rectangular shape that is long in the x direction. The IGBT regions 15 and diode regions 16 are arranged alternately in the y direction which is perpendicular to the x direction. That is, the y direction is the direction from the IGBT region 15 to the diode region 16. The boundary 14 between the IGBT region 15 and the diode region 16 extends along the x direction. Although not shown, a pressure-resistant structure such as a guard ring is provided on the outer peripheral portion 17. A signal electrode pad 18 is also provided on the outer peripheral portion 17. One of the signal electrode pads 18 is a gate pad that controls the gate voltage of the IGBT.

[0010] Figure 2 shows a cross-section of the semiconductor element 10 cut along the y-direction in the area spanning the IGBT region 15 and the diode region 16. As shown in Figure 2, an emitter electrode 70 is provided on the upper surface 12a of the semiconductor substrate 12. The emitter electrode 70 is provided over the entire element portion 13. The emitter electrode 70 is in contact with the upper surface 12a in the IGBT region 15 and the diode region 16. A collector electrode 72 is provided on the lower surface 12b of the semiconductor substrate 12. The collector electrode 72 is provided over the entire lower surface 12b. The collector electrode 72 is in contact with the lower surface 12b in the IGBT region 15 and the diode region 16.

[0011] The semiconductor substrate 12 has a p-type collector region 20 and an n-type cathode region 22. The collector region 20 and the cathode region 22 are located in a region that includes the lower surface 12b. The collector region 20 and the cathode region 22 are in ohmic contact with the collector electrode 72. The collector region 20 is located within the IGBT region 15, and the cathode region 22 is located within the diode region 16. In other words, when the semiconductor substrate 12 is viewed along the thickness direction (i.e., the z direction), the region overlapping with the collector region 20 is the IGBT region 15, and the region overlapping with the cathode region 22 is the diode region 16. In addition, gate trenches 60a and dummy trenches 60b are provided on the upper surface 12a of the semiconductor substrate 12. Multiple gate trenches 60a are provided within the IGBT region 15, and multiple dummy trenches 60b are provided within the diode region 16. Therefore, when the semiconductor substrate 12 is viewed along the thickness direction, the area where multiple gate trenches 60a are provided can be considered as the IGBT region 15, and the area where multiple dummy trenches 60b are provided can be considered as the diode region 16. In the following, trenches 60a and 60b may be collectively referred to as trench 60. Note that dummy trenches 60b may be provided within the IGBT region 15.

[0012] On the upper surface 12a of the semiconductor substrate 12, each trench 60 extends linearly along the x-direction. Multiple trenches 60 are arranged at intervals in the y-direction on the upper surface 12a of the semiconductor substrate 12. Multiple trenches 60 are provided in both the IGBT region 15 and the diode region 16. As described above, each trench 60 provided in the IGBT region 15 is a gate trench 60a, and each trench 60 provided in the diode region 16 is a dummy trench 60b.

[0013] A gate insulating film 62a and a gate electrode 64a are arranged within each gate trench 60a. Each gate insulating film 62a covers the inner surface of the corresponding gate trench 60a. Each gate electrode 64a is positioned within the corresponding gate trench 60a and surrounded by the gate insulating film 62a. Each gate electrode 64a is insulated from the semiconductor substrate 12 by the gate insulating film 62a. An interlayer insulating film 68 is provided above each gate electrode 64a. Each gate electrode 64a is insulated from the emitter electrode 70 by the interlayer insulating film 68. Each gate electrode 64a is connected to a gate pad by wiring (not shown). The gate pad is connected to an external drive circuit (not shown). The potential of each gate electrode 64a is controlled by the external drive circuit.

[0014] An insulating film 62b and a dummy electrode 64b are arranged within each dummy trench 60b. Each insulating film 62b covers the inner surface of the corresponding dummy trench 60b. Each dummy electrode 64b is positioned within the corresponding dummy trench 60b, surrounded by the insulating film 62b. Each dummy electrode 64b is insulated from the gate electrode 64a. No interlayer insulating film 68 is provided above each dummy electrode 64b. Therefore, each dummy electrode 64b is connected to the emitter electrode 70 at its upper end.

[0015] In Figure 2, the center line C1 represents the center of each trench 60 in the y-direction. Hereafter, each region within the semiconductor area of ​​the semiconductor substrate 12 that is sandwiched between two center lines C1 will be referred to as a unit semiconductor region 66. Multiple unit semiconductor regions 66 are provided within both the IGBT region 15 and the diode region 16.

[0016] Each unit semiconductor region 66 within the IGBT region 15 has an emitter region 34. Each emitter region 34 is an n-type region having a high n-type impurity concentration. Each emitter region 34 is positioned including the upper surface 12a and is in ohmic contact with the emitter electrode 70. Each emitter region 34 is in contact with the side surface of the gate trench 60a. Each emitter region 34 is in contact with the gate insulating film 62a covering the side surface of the gate trench 60a. In this embodiment, an n-type region corresponding to the emitter region 34 is not provided within the diode region 16, but an n-type region corresponding to the emitter region 34 may be provided within the diode region 16.

[0017] Each unit semiconductor region 66 within the IGBT region 15 and the diode region 16 has a contact region 33, a top body region 32, a barrier region 30, a bottom body region 28, and a pillar region 26.

[0018] Each contact region 33 is a p-type region having a high p-type impurity concentration. Each contact region 33 is positioned to include the upper surface 12a and is in ohmic contact with the emitter electrode 70. Within the IGBT region 15, each contact region 33 is positioned away from the trench 60. However, each contact region 33 within the IGBT region 15 may be in contact with the trench 60. Within the diode region 16, each contact region 33 is in contact with the trench 60. However, each contact region 33 within the diode region 16 may be positioned away from the trench 60.

[0019] Each top body region 32 is a p-type region having a lower p-type impurity concentration than the contact region 33. Each top body region 32 is in contact with the contact region 33 and also with the side surface of the trench 60. Within the IGBT region 15, each top body region 32 is located below the emitter region 34 and the contact region 33. Within the IGBT region 15, each top body region 32 is below the emitter region 34 and in contact with the side surface of the gate trench 60a. Within the IGBT region 15, each top body region 32 is in contact with the gate insulating film 62a covering the side surface of the gate trench 60a. Within the diode region 16, each top body region 32 is located below and to the side of the contact region 33. Within the diode region 16, each top body region 32 is in contact with the side surface of the dummy trench 60b. Each top body region 32 within the diode region 16 is in contact with the insulating film 62b that covers the side surface of the dummy trench 60b.

[0020] Each barrier region 30 is an n-type region having a lower n-type impurity concentration than the emitter region 34. Each barrier region 30 is located below the top body region 32. Each barrier region 30 is in contact with the top body region 32 from below. Each barrier region 30 is in contact with the side surface of the trench 60 below the top body region 32. Each barrier region 30 within the IGBT region 15 is in contact with the gate insulating film 62a covering the side surface of the gate trench 60a. Each barrier region 30 within the diode region 16 is in contact with the insulating film 62b covering the side surface of the dummy trench 60b. Each barrier region 30 within the IGBT region 15 is separated from the emitter region 34 by the top body region 32.

[0021] Each bottom body region 28 is a p-type region having a lower p-type impurity concentration than the contact region 33. Each bottom body region 28 is located below the barrier region 30. Each bottom body region 28 is in contact with the barrier region 30 from below. Each bottom body region 28 is in contact with the side surface of the trench 60 below the barrier region 30. Each bottom body region 28 in the IGBT region 15 is in contact with the gate insulating film 62a covering the side surface of the gate trench 60a. Each bottom body region 28 in the diode region 16 is in contact with the insulating film 62b covering the side surface of the dummy trench 60b. Each bottom body region 28 is separated from the top body region 32 by the barrier region 30.

[0022] Each pillar region 26 is an n-type region having a lower n-type impurity concentration than the emitter region 34. Each pillar region 26 extends along the z-direction from the barrier region 30 to the emitter electrode 70. The pillar region 26 is in contact with the barrier region 30 at its lower end and with the emitter electrode 70 at its upper end. In other words, each pillar region 26 connects the barrier region 30 and the emitter electrode 70. Each pillar region 26 is in Schottky contact with the emitter electrode 70.

[0023] The semiconductor substrate 12 has a drift region 25 and a buffer region 24. The drift region 25 and the buffer region 24 are located between the upper structure of the semiconductor substrate 12 (i.e., the emitter region 34, contact region 33, top body region 32, barrier region 30, bottom body region 28, pillar region 26, etc.) and the lower structure (i.e., the collector region 20 and cathode region 22).

[0024] The drift region 25 is 1.0 × 10 １５ (atms / cm ３) is an n-type region having the following n-type impurity concentration. The n-type impurity concentration in the drift region 25 is lower than that in the barrier region 30 and the pillar region 26. The drift region 25 is distributed across the IGBT region 15 and the diode region 16. The drift region 25 is in contact with the bottom body region 28 from below in each unit semiconductor region 66. The drift region 25 is in contact with the side and bottom surfaces of the trench 60 below each bottom body region 28. Within the IGBT region 15, the drift region 25 is in contact with the gate insulating film 62a in the gate trench 60a. Within the diode region 16, the drift region 25 is in contact with the insulating film 62b in the dummy trench 60b. The drift region 25 is separated from the barrier region 30 by the bottom body region 28.

[0025] Buffer area 24 is 1.0 × 10 １５ (atms / cm ３ The n-type region has an n-type impurity concentration that is higher than that of the IGBT region 15 and lower than that of the cathode region 22. The buffer region 24 is distributed across the IGBT region 15 and the diode region 16. The buffer region 24 is in contact with the drift region 25 from below. The buffer region 24 is in contact with the collector region 20 and the cathode region 22 from above.

[0026] As shown in Figure 2, the drift region 25 has a thickness T. In other words, the thickness T is the distance in the z direction between the bottom body region 28 and the buffer region 24. Also, the width W shown in Figure 2 is equal to the thickness T. In this specification, the region located within a width W on the diode region 16 side from the boundary 14 between the IGBT region 15 and the diode region 16 is called the boundary region 16b. The boundary region 16b is a part of the diode region 16. That is, the boundary region 16b is the part of the diode region 16 adjacent to the IGBT region 15. The boundary region 16b has a plurality of unit semiconductor regions 66. Also, in this specification, the region of the diode region 16 located on the opposite side of the IGBT region 15, with the boundary region 16b in between, is called the main region 16a. In other words, the main region 16a is the region of the diode region 16 that is located at a width W or more away from the boundary 14. The main region 16a has a plurality of unit semiconductor regions 66.

[0027] Within the boundary region 16b, a specific unit semiconductor region 66b is provided, having a structure different from the unit semiconductor region 66 in the main region 16a. Hereinafter, unit semiconductor regions 66 other than the specific unit semiconductor region 66b within the diode region 16 may be referred to as unit semiconductor regions 66a. In Example 1, all unit semiconductor regions 66 within the boundary region 16b are specific unit semiconductor regions 66b. However, as shown in Figure 16, both specific unit semiconductor regions 66b and unit semiconductor regions 66a (i.e., unit semiconductor regions having the same structure as the main region 16a) may exist within the boundary region 16b. In Example 1, the contact structure of the pillar region 26 with respect to the emitter electrode 70 differs between the specific unit semiconductor region 66b and the other unit semiconductor regions 66a.

[0028] Figure 3 shows a cross-section of a unit semiconductor region 66a and a cross-section of a specific unit semiconductor region 66b. In Figure 3, the density of the hatching in the pillar region 26 indicates the distribution of the n-type impurity concentration in the pillar region 26. As shown in Figure 3, in each pillar region 26, the n-type impurity concentration is distributed such that it decreases with increasing depth. That is, in each pillar region 26, the n-type impurity concentration decreases from the top to the bottom. In the specific unit semiconductor region 66b, a recess 80 is provided on the upper surface 12a of the semiconductor substrate 12 within the range of the pillar region 26, and the emitter electrode 70 is in contact with the pillar region 26 within the recess 80. On the other hand, in the unit semiconductor region 66a, the recess 80 is not provided on the upper surface 12a of the semiconductor substrate 12. That is, in the unit semiconductor region 66a, the upper surface 12a is flat within the range of the pillar region 26, the top body region 32, and the contact region 33. In the unit semiconductor region 66a, the emitter electrode 70 is in contact with the pillar region 26 on the flat upper surface 12a. Therefore, in the specific unit semiconductor region 66b, the contact position of the emitter electrode 70 with respect to the pillar region 26 is located lower than in the unit semiconductor region 66a. Consequently, in the specific unit semiconductor region 66b, the n-type impurity concentration of the pillar region 26 at the contact position between the pillar region 26 and the emitter electrode 70 is lower than in the unit semiconductor region 66a. Therefore, in the specific unit semiconductor region 66b, the Schottky barrier at the interface between the pillar region 26 and the emitter electrode 70 is higher than in the unit semiconductor region 66a.

[0029] Next, the operation of the semiconductor element 10 in Example 1 will be described. The potential of the gate electrode 64a is controlled by an external drive circuit. The potential of the dummy electrode 64b is fixed to the same potential as the emitter electrode 70.

[0030] When the semiconductor element 10 operates as an IGBT, a higher potential is applied to the collector electrode 72 than to the emitter electrode 70. When a gate-on potential higher than the gate threshold is applied to the gate electrode 64a, channels are formed in the top body region 32 and the bottom body region 28 near the gate insulating film 62a. The channel formed in the top body region 32 connects the emitter region 34 to the barrier region 30, and the channel formed in the bottom body region 28 connects the barrier region 30 to the drift region 25. As a result, electrons flow from the emitter electrode 70 to the drift region 25. At the same time, holes flow from the collector electrode 72 to the drift region 25 via the collector region 20 and the buffer region 24, and the resistance of the drift region 25 decreases. Electrons flow from the drift region 25 to the collector electrode 72 via the buffer region 24 and the collector region 20. This flow of electrons turns on the IGBT. When the potential of the gate electrode 64a is lowered to a gate-off potential lower than the gate threshold, the channel disappears and the current flowing through the IGBT stops.

[0031] When the semiconductor element 10 operates as a diode, a higher potential is applied to the emitter electrode 70 than to the collector electrode 72. This applies a forward voltage to the pn junction between the top body region 32 and the barrier region 30, and to the pn junction between the bottom body region 28 and the drift region 25, turning these pn junctions on. As a result, within the diode region 16, holes flow from the emitter electrode 70 to the drift region 25 via the contact region 33, top body region 32, barrier region 30, and bottom body region 28. Simultaneously, electrons flow from the collector electrode 72 to the drift region 25 via the cathode region 22 and buffer region 24. Electrons then flow from the drift region 25 back to the emitter electrode 70 via the bottom body region 28, barrier region 30, top body region 32, and contact region 33. This flow of electrons turns on the diode. When the diode is ON, the barrier region 30 and pillar region 26 suppress the flow of holes from the emitter electrode 70 to the drift region 25, so few holes flow into the drift region 25. Subsequently, when the potential of the emitter electrode 70 becomes lower than the potential of the collector electrode 72, the diode turns OFF and the current flowing through the diode stops. At this time, holes in the drift region 25 are discharged to the emitter electrode 70, causing a reverse current (so-called recovery current) to flow instantaneously through the diode. As described above, since few holes flow into the drift region 25 when the diode is ON, few holes are discharged to the emitter electrode 70 when the diode turns OFF, and the recovery current is suppressed. In this way, the barrier region 30 and pillar region 26 suppress the recovery current.

[0032] When the semiconductor element 10 operates as a diode (i.e., when a higher potential is applied to the emitter electrode 70 than to the collector electrode 72), a gate-on potential may be applied to the gate electrode 64a. In this case, a channel is formed within the IGBT region 15, and each emitter region 34 is connected to the drift region 25 via the channel. As a result, the potential of the drift region 25 becomes high within the IGBT region 15. In this case, the potential of the drift region 25 also becomes high in the diode region 16 near the IGBT region 15 (i.e., the boundary region 16b).

[0033] Generally, when the potential of the drift region within the boundary region increases due to the application of the gate-on potential, it becomes difficult to apply voltage to the pn junction of the diode within the boundary region, making it difficult for the diode to turn on. This phenomenon (i.e., the phenomenon in which the diode within the boundary region becomes difficult to turn on due to the application of the gate-on potential) is called gate interference. When gate interference occurs, the forward voltage of the diode becomes higher than the design value, causing increased losses and other problems. In addition, when gate interference occurs, the operation of the diode becomes unstable. For example, when the diode within the boundary region becomes difficult to turn on due to gate interference, snapback may occur when the potential of the emitter electrode rises. Snapback is a phenomenon in which the diode does not turn on even when the potential of the emitter electrode rises to the design forward voltage (i.e., the voltage at which the diode turns on), but when the potential of the emitter electrode is further increased, the diode turns on and at the same time the potential of the emitter electrode drops sharply. In contrast, in the semiconductor element 10 of Example 1, gate interference is suppressed as described below.

[0034] As described above, in the semiconductor element 10 of Embodiment 1, a specific unit semiconductor region 66b is provided within the boundary region 16b. Within the specific unit semiconductor region 66b, the Schottky barrier at the interface between the pillar region 26 and the emitter electrode 70 is higher than within the main region 16a. Therefore, the potential clamp of the barrier region 30 is weaker within the boundary region 16b than within the main region 16a. Consequently, when the potential of the emitter electrode 70 rises, the pn junction at the interface between the top body region 32 and the barrier region 30 is more easily turned on within the boundary region 16b than within the main region 16a. For this reason, even if the potential of the drift region 25 within the boundary region 16b increases due to the application of a gate-on potential, the diode within the boundary region 16b can be turned on almost simultaneously with the diode within the main region 16a. That is, when the potential of the emitter electrode 70 rises, the diode within the boundary region 16b can be turned on at an appropriate potential. In this way, gate interference can be suppressed according to the semiconductor element 10 of Embodiment 1.

[0035] In Example 1, in the specific unit semiconductor region 66b, the emitter electrode 70 was in contact with the pillar region 26 within the recess 80, resulting in a low n-type impurity concentration at the interface between the emitter electrode 70 and the pillar region 26. However, if the n-type impurity concentration at the interface between the emitter electrode 70 and the pillar region 26 is lower in the specific unit semiconductor region 66b than in the unit semiconductor region 66a, the recess 80 may be omitted. For example, a difference in the n-type impurity concentration at the interface may be created by changing the implantation concentration of n-type impurities on the upper surface 12a.

[0036] Next, the semiconductor devices of Examples 2 to 6 will be described. First, the common structure of the semiconductor devices of Examples 2 to 6 will be explained using Figure 4. As shown in Figure 4, unlike Example 1, Examples 2 to 6 do not have a recess 80 on the upper surface 12a within the specific unit semiconductor region 66b. Also, in Examples 2 to 6, the distribution of n-type impurity concentration within the pillar region 26 is not limited to the distribution shown in Figure 3 (i.e., a distribution where the concentration decreases from the top to the bottom). Furthermore, as will be described later, in Examples 2 to 6, the impurity concentration in a specific region differs between the unit semiconductor region 66a and the specific unit semiconductor region 66b. Therefore, when current flows from the contact region 33 to the drift region 25, the voltage drop that occurs between them is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. Except for these points, the structure of the semiconductor devices of Examples 2 to 6 is the same as the structure of the semiconductor device 10 of Example 1. The semiconductor devices of Examples 2 to 6 can also operate as IGBTs and diodes, similar to the semiconductor device of Example 1.

[0037] As shown in Figure 5, in the semiconductor device of Example 2, the p-type impurity concentration pc-b in the contact region 33 within the specific unit semiconductor region 66b is higher than the p-type impurity concentration pc-a in the contact region 33 within the unit semiconductor region 66a. Therefore, when the diode is turned on and current flows from the contact region 33 to the drift region 25, the voltage drop that occurs between the contact region 33 and the drift region 25 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. Consequently, the diode is more easily turned on in the boundary region 16b than in the main region 16a.

[0038] When the semiconductor device of Example 2 operates as a diode (that is, when a potential higher than that of the collector electrode 72 is applied to the emitter electrode 70), when a gate-on potential is applied to the gate electrode 64a, the potential of the drift region 25 in the boundary region 16b becomes high. However, as described above, in the semiconductor device of Example 2, in the boundary region 16b, the diode is more likely to turn on than in the main region 16a. Therefore, even if the potential of the drift region 25 in the boundary region 16b becomes high due to the application of the gate-on potential, the diode in the boundary region 16b can turn on substantially simultaneously with the diode in the main region 16a. That is, even if the potential of the drift region 25 in the boundary region 16b becomes high due to the application of the gate-on potential during the diode operation, the diode in the boundary region 16b can turn on appropriately. Thus, according to the semiconductor device of Example 2, gate interference can be suppressed.

[0039] As shown in FIG. 6, in the semiconductor device of Example 3, the n-type impurity concentration np-b of the pillar region 26 in the specific unit semiconductor region 66b is lower than the n-type impurity concentration np-a of the pillar region 26 in the unit semiconductor region 66a. For this reason, the resistance of the pillar region 26 in the specific unit semiconductor region 66b is higher than the resistance of the pillar region 26 in the unit semiconductor region 66a. Therefore, in the specific unit semiconductor region 66b, the potential clamping of the barrier region 30 is weaker than in the unit semiconductor region 66a. For this reason, in the specific unit semiconductor region 66b, the pn junction at the interface between the top body region 32 and the barrier region 30 is more likely to turn on than in the unit semiconductor region 66a. Therefore, when the diode turns on and current flows from the contact region 33 to the drift region 25, the voltage drop generated between the contact region 33 and the drift region 25 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. For this reason, in the boundary region 16b, the diode is more likely to turn on than in the main region 16a. Therefore, even if the potential of the drift region 25 in the boundary region 16b becomes high due to the application of the gate-on potential during the diode operation, the diode in the boundary region 16b can turn on appropriately. Thus, according to the semiconductor device of Example 3, gate interference can be suppressed.

[0040] As shown in Figure 7, in the semiconductor device of Example 4, the p-type impurity concentration pt-b in the top body region 32 within the specific unit semiconductor region 66b is higher than the p-type impurity concentration pt-a in the top body region 32 within the unit semiconductor region 66a. Therefore, when the diode is turned on and current flows from the contact region 33 to the drift region 25, the voltage drop between the contact region 33 and the drift region 25 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. For this reason, the diode is more easily turned on in the boundary region 16b than in the main region 16a. Consequently, even if the potential of the drift region 25 in the boundary region 16b increases due to the application of a gate-on potential during diode operation, the diode in the boundary region 16b can be turned on almost simultaneously with the diode in the main region 16a. In this way, gate interference can be suppressed according to the semiconductor device of Example 4.

[0041] As shown in Figure 8, in the semiconductor device of Example 5, the n-type impurity concentration nb-b in the barrier region 30 within a specific unit semiconductor region 66b is lower than the n-type impurity concentration nb-a in the barrier region 30 within a unit semiconductor region 66a. Therefore, when the diode is turned on and current flows from the contact region 33 to the drift region 25, the voltage drop between the contact region 33 and the drift region 25 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. For this reason, the diode is more easily turned on in the boundary region 16b than in the main region 16a. Consequently, even if the potential of the drift region 25 within the boundary region 16b increases due to the application of a gate-on potential during diode operation, the diode within the boundary region 16b can be turned on appropriately. In this way, gate interference can be suppressed according to the semiconductor device of Example 5.

[0042] As shown in FIG. 9, in the semiconductor device of Example 6, the p-type impurity concentration pb-b of the bottom body region 28 in the specific unit semiconductor region 66b is higher than the p-type impurity concentration pb-a of the bottom body region 28 in the unit semiconductor region 66a. Therefore, when the diode is turned on and current flows from the contact region 33 to the drift region 25, the voltage drop generated between the contact region 33 and the drift region 25 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. For this reason, in the boundary region 16b, the diode is more likely to be turned on than in the main region 16a. Therefore, even if the potential of the drift region 25 in the boundary region 16b increases due to the application of the gate-on potential during the diode operation, the diode in the boundary region 16b can be appropriately turned on. Thus, according to the semiconductor device of Example 6, gate interference can be suppressed.

[0043] As shown in Figure 10, in Example 7, the drift region 25 within the IGBT region 15 has a thickness Tc. In Example 7, the diode region 16 region within a width W equal to the thickness Tc from the boundary 14 is the boundary region 16b. Unlike Example 1, in Example 7, there is no recess 80 (see Figures 2 and 3) on the upper surface 12a within the specific unit semiconductor region 66b. Also, in Example 7, the distribution of n-type impurity concentration within the pillar region 26 is not limited to the distribution shown in Figure 3 (i.e., a distribution where the concentration decreases from top to bottom). Furthermore, in Example 7, the upper surface 12a within the specific unit semiconductor region 66b is recessed relative to the upper surface 12a within the IGBT region 15 and the main region 16a, thereby forming a stepped recess on the upper surface 12a. For this reason, the thickness of the semiconductor substrate 12 is thinner within the specific unit semiconductor region 66b than within the IGBT region 15 and the main region 16a. In other words, the upper surface 12a within the specific unit semiconductor region 66b is located lower than the upper surface 12a within the IGBT region 15 and the main region 16a. Therefore, within the specific unit semiconductor region 66b, the upper structure of the semiconductor element is shifted downward compared to within the IGBT region 15 and the main region 16a. Consequently, within the specific unit semiconductor region 66b, the bottom body region 28 is shifted downward compared to within the IGBT region 15 and the main region 16a. As a result, the thickness Tb of the drift region 25 within the specific unit semiconductor region 66b is thinner than the thickness Tc of the drift region 25 within the IGBT region 15 and the thickness Tc of the drift region 25 within the main region 16a. Note that thickness Ta and thickness Tc are equal. Except for these points, the structure of the semiconductor element in Example 7 is the same as the structure of the semiconductor element 10 in Example 1. The semiconductor element in Example 7 can also operate as an IGBT and a diode, similar to the semiconductor element in Example 1.

[0044] As described above, in Example 7, the thickness Tb of the drift region 25 within the specific unit semiconductor region 66b is thinner than the thickness Ta of the drift region 25 within the main region 16a (i.e., within the unit semiconductor region 66a). Therefore, the resistance of the drift region 25 within the specific unit semiconductor region 66b is lower than the resistance of the drift region 25 within the main region 16a. As a result, the diode turns on more easily within the boundary region 16b than within the main region 16a. Consequently, even if the potential of the drift region 25 within the boundary region 16b increases due to the application of a gate-on potential during diode operation, the diode within the boundary region 16b can turn on appropriately. In this way, gate interference can be suppressed according to the semiconductor element of Example 7.

[0045] Furthermore, as shown in Figure 11, the buffer region 24 protrudes upward within the specific unit semiconductor region 66b, so the thickness Tb of the drift region 25 within the specific unit semiconductor region 66b may be thinner than the thickness Ta of the drift region 25 within the main region 16a. Gate interference can also be suppressed with this configuration.

[0046] As shown in Figure 12, in Example 8, unlike Example 1, a recess 80 (see Figures 2 and 3) is not provided on the upper surface 12a within the specific unit semiconductor region 66b. Also, in Example 8, the distribution of n-type impurity concentration within the pillar region 26 is not limited to the distribution shown in Figure 3 (i.e., a distribution where the concentration decreases from top to bottom). Furthermore, in Example 8, the n-type impurity concentration nc-b in the cathode region 22 within the specific unit semiconductor region 66b is higher than the n-type impurity concentration nc-a in the cathode region 22 within the unit semiconductor region 66a. Except for these points, the structure of the semiconductor element in Example 8 is the same as the structure of the semiconductor element 10 in Example 1. The semiconductor element in Example 8 can also operate as an IGBT and a diode, similar to the semiconductor element in Example 1.

[0047] As described above, in Example 8, the n-type impurity concentration nc-b in the cathode region 22 within the specific unit semiconductor region 66b is higher than the n-type impurity concentration nc-a in the cathode region 22 within the unit semiconductor region 66a. Therefore, the resistance of the cathode region 22 within the specific unit semiconductor region 66b is lower than the resistance of the cathode region 22 within the main region 16a. Consequently, when the diode is turned on and current flows from the drift region 25 through the cathode region 22 to the collector electrode 72, the voltage drop that occurs in the cathode region 22 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. Therefore, the diode is more easily turned on in the boundary region 16b than in the main region 16a. Consequently, even if the potential of the drift region 25 within the boundary region 16b increases due to the application of a gate-on potential during diode operation, the diode within the boundary region 16b can be turned on appropriately. In this way, gate interference can be suppressed according to the semiconductor element of Example 8.

[0048] As shown in Figure 13, in Example 9, unlike Example 1, a recess 80 (see Figures 2 and 3) is not provided on the upper surface 12a within the specific unit semiconductor region 66b. Also, in Example 9, the distribution of n-type impurity concentration within the pillar region 26 is not limited to the distribution shown in Figure 3 (i.e., a distribution where the concentration decreases from top to bottom). Furthermore, in Example 9, a current-passing region 90 is provided instead of the cathode region 22 of Example 1. The current-passing region 90 is an alternating arrangement region in which n-type cathode regions 90a and p-type shielding regions 90b are arranged alternately. The cathode regions 90a and shielding regions 90b are arranged alternately in the y direction. In the y direction, the width of each cathode region 90a and the width of each current-shielding region 90b are narrower than the width of the collector region 20. The cathode region 90a has a higher n-type impurity concentration than the buffer region 24 and is in ohmic contact with the collector electrode 72. As shown in Figure 13, in the current-passing region 90, the area ratio of the cathode region 90a decreases and the area ratio of the shielding region 90b increases as the distance from the boundary 14 increases. Therefore, within a specific unit semiconductor region 66b, the area ratio of the cathode region 90a in the current-passing region 90 is higher than within the main region 16a. Except for these points, the structure of the semiconductor element in Example 9 is the same as the structure of the semiconductor element 10 in Example 1. The semiconductor element in Example 9 can also operate as an IGBT and a diode, similar to the semiconductor element in Example 1.

[0049] In Example 9, when the diode is turned on and current flows from the drift region 25 through the current-passing region 90 to the collector electrode 72, the current flows through the cathode region 90a, avoiding the shielding region 90b. As described above, within the specific unit semiconductor region 66b, the area ratio of the cathode region 90a in the current-passing region 90 is higher than within the main region 16a. Therefore, within the specific unit semiconductor region 66b, the current path in the current-passing region 90 is wider and the resistance of the current-passing region 90 is lower than within the main region 16a. For this reason, when the diode is turned on and current flows from the drift region 25 through the current-passing region 90 to the collector electrode 72, the voltage drop that occurs in the current-passing region 90 is smaller in the specific unit semiconductor region 66b than in the unit semiconductor region 66a. For this reason, the diode is more easily turned on within the boundary region 16b than within the main region 16a. Therefore, even if the potential of the drift region 25 within the boundary region 16b increases due to the application of a gate-on potential during diode operation, the diode within the boundary region 16b can be properly turned on. In this way, gate interference can be suppressed according to the semiconductor element of Embodiment 8.

[0050] As described above, gate interference can be suppressed according to Examples 1 to 9. Examples 1 to 9 can also be combined. For example, as shown in Figure 14, Examples 1, 2, and 4 to 8 may be combined. Alternatively, as shown in Figure 15, Examples 2 to 7 and 9 may be combined. The configurations in Figures 14 and 15 allow for more effective suppression of gate interference.

[0051] In Examples 1 to 9, all unit semiconductor regions 66 within the boundary region 16b were specific unit semiconductor regions 66b (i.e., unit semiconductor regions having a different structure from the unit semiconductor regions 66 within the main region 16a). However, gate interference can be suppressed even if only a portion of the unit semiconductor regions 66 within the boundary region 16b are specific unit semiconductor regions 66b. In this case, as illustrated in Figure 16, gate interference can be effectively suppressed by adopting a structure in which at least the unit semiconductor regions 66 adjacent to the IGBT region 15 within the boundary region 16b are specific unit semiconductor regions 66b. Although Figure 16 shows this structure applied to Example 1, this structure may also be applied to Examples 2 to 9.

[0052] Furthermore, in Examples 1 to 9, emitter regions 34 were provided in all unit semiconductor regions 66 within the IGBT region 15, but there may be unit semiconductor regions 66 within the IGBT region 15 that do not have emitter regions 34.

[0053] The configurations of the semiconductor devices disclosed herein are listed below. Configurations A1 to A7 relate to the Schottky barrier, configurations B1 to B10 relate to the voltage drop between the contact region and the drift region, configurations C1 to C6 relate to the thickness of the drift region, and configurations D1 to D7 relate to the voltage drop in the current-passing region. It is also possible to combine configurations A, B, C, and D. (Configuration A1) A semiconductor element comprising: a semiconductor substrate (12); an emitter electrode (70) in contact with the upper surface of the semiconductor substrate; a collector electrode (72) in contact with the lower surface of the semiconductor substrate; the semiconductor substrate comprising: a p-type collector region (20) in contact with the collector electrode; an n-type cathode region (22) in contact with the collector electrode; when the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is an IGBT region (15), and the area overlapping with the cathode region is a diode region (16); when the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction. The trench in the IGBT region has a gate trench (60a) in which a gate insulating film (62a) and a gate electrode (64a) are disposed inside, the trench in the diode region has a dummy trench (60b) in which a dummy electrode (64b) insulated from the gate electrode is disposed inside, each semiconductor region sandwiched by the centerlines of the plurality of trenches is a unit semiconductor region (66), a plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region, each unit semiconductor region in the IGBT region and the diode region has a p-type contact region (33) in contact with the emitter electrode, and a p-type top body region (32) in contact with the contact region and the trench, having a lower p-type impurity concentration than the contact region,The IGBT region has an n-type barrier region (30) that is in contact with the top body region from below and in contact with the trench, a p-type bottom body region (28) that is in contact with the barrier region from below and in contact with the trench, and an n-type pillar region (26) that connects the emitter electrode and the barrier region and is in Schottky contact with the emitter electrode, and at least one of the unit semiconductor regions within the IGBT region has an n-type emitter region (34) that is in contact with the emitter electrode, in contact with the trench above the top body region and separated from the barrier region by the top body region, the semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region (25) in contact with the bottom body region from below within each unit semiconductor region, and the region of the diode region adjacent to the IGBT region is a boundary region (16b), A semiconductor device wherein the diode region is defined as the main region (16a) located on the opposite side of the boundary region from the IGBT region, and within a specific unit semiconductor region (66b) which is at least one of the unit semiconductor regions within the boundary region, the Schottky barrier at the interface between the pillar region and the emitter electrode is higher than within the main region. (Configuration A2) The drift region is 1.0 × 10 １５ (atms / cm ３(Configuration A1) A semiconductor element according to Configuration A1, wherein the region is a region having the following n-type impurity concentration. (Configuration A3) A semiconductor element according to Configuration A1 or A2, wherein the boundary region is a region within the diode region that is located within the same width range as the thickness (T) of the drift region from the IGBT region in the second direction. (Configuration A4) A semiconductor element according to any one of Configurations A1 to A3, wherein within the specific unit semiconductor region, the n-type impurity concentration of the pillar region at the contact position with the emitter electrode is lower than within the main region. (Configuration A5) A semiconductor element according to Configuration A4, wherein in the boundary region and the main region, the n-type impurity concentration in each pillar region is distributed such that it decreases from top to bottom, and in the specific unit semiconductor region, a recess (80) is provided on the upper surface of the semiconductor substrate within the range of the pillar region, and the emitter electrode is in contact with the pillar region within the recess. (Configuration A6) A semiconductor device according to any one of Configurations A1 to A5, wherein the unit semiconductor region adjacent to the IGBT region is the specified unit semiconductor region. (Configuration A7) A semiconductor device according to any one of Configurations A1 to A6, wherein each of the unit semiconductor regions within the boundary region is the specified unit semiconductor region. (Configuration B1) A semiconductor element comprising: a semiconductor substrate (12); an emitter electrode (70) in contact with the upper surface of the semiconductor substrate; a collector electrode (72) in contact with the lower surface of the semiconductor substrate; the semiconductor substrate comprising: a p-type collector region (20) in contact with the collector electrode; an n-type cathode region (22) in contact with the collector electrode; when the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is an IGBT region (15), and the area overlapping with the cathode region is a diode region (16); when the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction.The trench in the IGBT region has a gate trench (60a) in which a gate insulating film (62a) and a gate electrode (64a) are disposed inside, the trench in the diode region has a dummy trench (60b) in which a dummy electrode (64b) insulated from the gate electrode is disposed inside, each semiconductor region sandwiched by the centerlines of the plurality of trenches is a unit semiconductor region (66), a plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region, each unit semiconductor region in the IGBT region and the diode region has a p-type contact region (33) in contact with the emitter electrode, a p-type top body region (32) in contact with the contact region and the trench and having a lower p-type impurity concentration than the contact region, an n-type barrier region (30) in contact with the top body region from below and in contact with the trench, and a p-type bottom body region (28) in contact with the barrier region from below and in contact with the trench The IGBT region has an n-type pillar region (26) that connects the emitter electrode and the barrier region and is in Schottky contact with the emitter electrode, and at least one of the unit semiconductor regions within the IGBT region has an n-type emitter region (34) that is in contact with the emitter electrode, in contact with the trench above the top body region and separated from the barrier region by the top body region, the semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region (25) in contact with the bottom body region from below within each unit semiconductor region, the region of the diode region adjacent to the IGBT region is a boundary region (16b), and the region of the diode region located on the opposite side of the IGBT region across the boundary region is a main region (16a). A semiconductor device in which, within a specific unit semiconductor region (66b) which is at least one of the unit semiconductor regions within the boundary region, the voltage drop that occurs between the contact region and the drift region when current flows from them is smaller than in the main region. (Configuration B2) The drift region is 1.0 × 10 １５(atms / cm ３(Configuration B1) A semiconductor element according to Configuration B1, wherein the region has the following n-type impurity concentration. (Configuration B3) A semiconductor element according to Configuration B1 or B2, wherein the boundary region is a region within the diode region that is located within the same width range as the thickness (T) of the drift region from the IGBT region in the second direction. (Configuration B4) A semiconductor element according to any one of Configurations B1 to B3, wherein the p-type impurity concentration of the contact region is higher than that of the main region within the specific unit semiconductor region. (Configuration B5) A semiconductor element according to Configurations B1 to B4, wherein the n-type impurity concentration of the pillar region is lower than that of the main region within the specific unit semiconductor region. (Configuration B6) A semiconductor element according to Configurations B1 to B5, wherein the p-type impurity concentration of the top body region is higher than that of the main region within the specific unit semiconductor region. (Configuration B7) A semiconductor element according to Configurations B1 to B6, wherein the n-type impurity concentration of the barrier region is lower than that of the main region within the specific unit semiconductor region. (Configuration B8) A semiconductor device according to Configurations B1 to B7, wherein the p-type impurity concentration in the bottom body region is higher within the specified unit semiconductor region than within the main region. (Configuration B9) A semiconductor device according to any one of Configurations B1 to B8, wherein the unit semiconductor region adjacent to the IGBT region is the specified unit semiconductor region. (Configuration B10) A semiconductor device according to any one of Configurations B1 to B8, wherein each of the unit semiconductor regions within the boundary region is the specified unit semiconductor region. (Configuration C1) A semiconductor element comprising: a semiconductor substrate (12); an emitter electrode (70) in contact with the upper surface of the semiconductor substrate; and a collector electrode (72) in contact with the lower surface of the semiconductor substrate, wherein the semiconductor substrate comprises: a p-type collector region (20) in contact with the collector electrode; and an n-type cathode region (22) in contact with the collector electrode, wherein when the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is an IGBT region (15), and the area overlapping with the cathode region is a diode region (16),When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches (60) are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction, the trenches in the IGBT region have gate trenches (60a) in which a gate insulating film (62a) and a gate electrode (64a) are disposed inside, the trenches in the diode region have dummy trenches (60b) in which a dummy electrode (64b) insulated from the gate electrode is disposed inside, each semiconductor region sandwiched by the centerlines of the plurality of trenches is a unit semiconductor region (66), a plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region, and each of the unit semiconductor regions in the IGBT region and the diode region has a p-type contact region (33) in contact with the emitter electrode, The IGBT region has a p-type top body region (32) that is in contact with the contact region and the trench and has a lower p-type impurity concentration than the contact region, an n-type barrier region (30) that is in contact with the top body region from below and is in contact with the trench, a p-type bottom body region (28) that is in contact with the barrier region from below and is in contact with the trench, and an n-type pillar region (26) that connects the emitter electrode and the barrier region and is in Schottky contact with the emitter electrode, and at least one of the unit semiconductor regions within the IGBT region has an n-type emitter region (34) that is in contact with the emitter electrode, is in contact with the trench above the top body region and is separated from the barrier region by the top body region, and the semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region (25) in contact with the bottom body region from below within each unit semiconductor region. Of the diode region, the region adjacent to the IGBT region is the boundary region (16b).Among the diode regions, the region located on the opposite side of the IGBT region across the boundary region is the main region (16a). In a specific unit semiconductor region (66b) which is at least one of the unit semiconductor regions within the boundary region, the thickness of the drift region is thinner than that within the main region. A semiconductor device. (Configuration C2) The drift region is 1.0×10 １５ (atms / cm ３(Configuration C1) A semiconductor element according to Configuration C1, wherein the region has the following n-type impurity concentration. (Configuration C3) A semiconductor element according to Configuration C1 or C2, wherein when the thickness (Tc) of the drift region within the IGBT region is set to a specific thickness, the region within the diode region that is located within the same width range as the IGBT region in the second direction is the boundary region. (Configuration C4) A semiconductor element according to any one of Configurations C1 to C3, wherein the thickness of the semiconductor substrate in the specific unit semiconductor region is thinner than that of the main region because a recess is provided on the upper surface of the semiconductor substrate in the specific unit semiconductor region, and the lower end of the bottom body region is located lower than that of the main region in the specific unit semiconductor region. (Configuration C5) A semiconductor element according to any one of Configurations C1 to C4, wherein the unit semiconductor region adjacent to the IGBT region is the specific unit semiconductor region. (Configuration C6) A semiconductor element according to any one of Configurations C1 to C4, wherein each of the unit semiconductor regions within the boundary region is the specific unit semiconductor region. (Configuration D1) A semiconductor element comprising: a semiconductor substrate (12); an emitter electrode (70) in contact with the upper surface of the semiconductor substrate; and a collector electrode (72) in contact with the lower surface of the semiconductor substrate, wherein the semiconductor substrate comprises: a p-type collector region (20) in contact with the collector electrode; and a current-passing region (90) in contact with the collector electrode, the current-passing region being composed of an n-type cathode region, or an alternating arrangement region in which an n-type cathode region narrower than the collector region and a p-type current-shielding region narrower than the collector region are alternately arranged, wherein when the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region (15), and the area overlapping with the current-passing region is the diode region (16), When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches (60) extending along the first direction are provided on the upper surface, and the plurality of trenches are arranged at intervals in the second direction.The trench in the IGBT region has a gate trench (60a) in which a gate insulating film (62a) and a gate electrode (64a) are disposed inside, the trench in the diode region has a dummy trench (60b) in which a dummy electrode (64b) insulated from the gate electrode is disposed inside, each semiconductor region sandwiched by the centerlines of the plurality of trenches is a unit semiconductor region (66), a plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region, each unit semiconductor region in the IGBT region and the diode region has a p-type contact region (33) in contact with the emitter electrode, a p-type top body region (32) in contact with the contact region and the trench and having a lower p-type impurity concentration than the contact region, an n-type barrier region (30) in contact with the top body region from below and in contact with the trench, and a p-type bottom body region (28) in contact with the barrier region from below and in contact with the trench The IGBT region has an n-type pillar region (26) that connects the emitter electrode and the barrier region and is in Schottky contact with the emitter electrode, and at least one of the unit semiconductor regions within the IGBT region has an n-type emitter region (34) that is in contact with the emitter electrode, in contact with the trench above the top body region and separated from the barrier region by the top body region, the semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region (25) in contact with the bottom body region from below within each unit semiconductor region, the region of the diode region adjacent to the IGBT region is a boundary region (16b), and the region of the diode region located on the opposite side of the IGBT region across the boundary region is a main region (16a). A semiconductor device in which, within a specific unit semiconductor region (66b) which is at least one of the unit semiconductor regions within the boundary region, the voltage drop that occurs in the current-passing region when current flows from the drift region to the collector electrode via the current-passing region is smaller than in the main region. (Configuration D2) The drift region is 1.0 × 10１５ (atms / cm ３ (Configuration D1) A semiconductor element according to Configuration D1, wherein the region is having the following n-type impurity concentration. (Configuration D3) A semiconductor element according to Configuration D1 or D2, wherein the region of the diode region located within the same width range as the thickness (T) of the drift region from the IGBT region in the second direction is the boundary region. (Configuration D4) A semiconductor element according to Configurations D1 to D3, wherein the current-passing region is composed of the cathode region (22), and within the specific unit semiconductor region, the n-type impurity concentration of the cathode region is higher than that of the main region. (Configuration D5) A semiconductor element according to Configurations D1 to D3, wherein the current-passing region is composed of the alternating arrangement regions, and within the specific unit semiconductor region, the area ratio of the cathode region in the current-passing region is higher than that of the main region. (Configuration D6) A semiconductor element according to any one of Configurations D1 to D5, wherein the unit semiconductor region adjacent to the IGBT region is the specific unit semiconductor region. (Configuration D7) A semiconductor element according to any one of Configurations D1 to D5, wherein each of the unit semiconductor regions within the boundary region is the specified unit semiconductor region.

[0054] In configuration A1, the barrier region is connected to the emitter electrode by the pillar region, so the potential of the pillar region is clamped to the potential of the emitter electrode via the barrier region. However, within a specific unit semiconductor region, the Schottky barrier at the interface between the pillar region and the emitter electrode is higher than within the main region, so the potential clamping of the barrier region is weaker within the specific unit semiconductor region than within the main region. Therefore, when the potential of the emitter electrode rises, the pn junction at the interface between the top body region and the barrier region is more easily turned on within the specific unit semiconductor region than within the main region. For this reason, the diode is more easily turned on within the boundary region having the specific unit semiconductor region than within the main region. For this reason, even if a channel is formed in the IGBT region and the potential of the drift region within the boundary region rises, the diode within the boundary region can be turned on appropriately, and gate interference can be suppressed.

[0055] According to configuration A4, the Schottky barrier at the interface between the pillar region and the emitter electrode can be made higher within a specific unit semiconductor region than within the main region.

[0056] According to configuration A5, the n-type impurity concentration in the pillar region at the contact position with the emitter electrode can be lower within a specific unit semiconductor region than within the main region.

[0057] In configuration B1, the voltage drop between the contact region and the drift region when current flows from the contact region to the drift region is smaller within a specific unit semiconductor region than within the main region. Therefore, the diode turns on more easily within the boundary region containing the specific unit semiconductor region than within the main region. As a result, even if a channel is formed in the IGBT region and the potential of the drift region within the boundary region rises, the diode within the boundary region can turn on appropriately, and gate interference can be suppressed.

[0058] According to configurations B4 to B8, the voltage drop occurring between the contact region and the drift region within a specific unit semiconductor region can be reduced compared to the voltage drop within the main region.

[0059] In configuration C1, the thickness of the drift region is thinner within a specific unit semiconductor region than within the main region, so the resistance of the drift region is lower within the specific unit semiconductor region than within the main region. Therefore, the diode turns on more easily within the boundary region containing the specific unit semiconductor region than within the main region. As a result, even if a channel is formed in the IGBT region and the potential of the drift region within the boundary region rises, the diode within the boundary region can turn on appropriately, and gate interference can be suppressed.

[0060] According to configuration C4, the thickness of the drift region can be made thinner within a specific unit semiconductor region than within the main region.

[0061] In configuration D1, within a specific unit semiconductor region, the voltage drop in the current-passing region is smaller than within the main region when current flows from the drift region to the collector electrode via the current-passing region. Therefore, within the boundary region containing the specific unit semiconductor region, the diode turns on more easily than within the main region. As a result, even if a channel is formed in the IGBT region and the potential of the drift region within the boundary region rises, the diode within the boundary region can turn on appropriately, suppressing gate interference.

[0062] According to configurations D4 and D5, the voltage drop occurring in the current-passing region within a specific unit semiconductor region can be reduced compared to the voltage drop occurring in the main region.

[0063] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A semiconductor element comprising: a semiconductor substrate; an emitter electrode in contact with the upper surface of the semiconductor substrate; and a collector electrode in contact with the lower surface of the semiconductor substrate, wherein the semiconductor substrate comprises: a p-type collector region in contact with the collector electrode; and a current-passing region in contact with the collector electrode, which is composed of an n-type cathode region, or an alternating arrangement region in which an n-type cathode region narrower than the collector region and a p-type current-shielding region narrower than the collector region are alternately arranged, wherein when the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region, and the area overlapping with the current-passing region is the diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction, the trenches in the IGBT region have gate trenches in which a gate insulating film and a gate electrode are disposed inside, the trenches in the diode region have dummy trenches in which a dummy electrode insulated from the gate electrode is disposed inside, each semiconductor region sandwiched by the centerlines of the plurality of trenches is a unit semiconductor region, a plurality of the unit semiconductor regions are provided in each of the IGBT region and the diode region, each of the unit semiconductor regions in the IGBT region and the diode region has a p-type contact region in contact with the emitter electrode, and a p-type top body region in contact with the contact region and the trench, having a lower p-type impurity concentration than the contact region, It has an n-type barrier region that is in contact with the top body region from below and in contact with the trench, a p-type bottom body region that is in contact with the barrier region from below and in contact with the trench, and an n-type pillar region that connects the emitter electrode and the barrier region and is in Schottky contact with the emitter electrode,A semiconductor device wherein at least one of the unit semiconductor regions within the IGBT region has an n-type emitter region that is in contact with the emitter electrode, in contact with the trench above the top body region, and separated from the barrier region by the top body region, the semiconductor substrate is distributed across the IGBT region and the diode region, and each unit semiconductor region has an n-type drift region that is in contact with the bottom body region from below, the region of the diode region adjacent to the IGBT region is a boundary region, the region of the diode region located on the opposite side of the IGBT region across the boundary region is a main region, and in a specific unit semiconductor region which is at least one of the unit semiconductor regions within the boundary region, the voltage drop that occurs in the current-passing region when current flows from the drift region to the collector electrode via the current-passing region is smaller than in the main region.

2. The drift region is 1.0 × 10 １５ (atms / cm ３ The semiconductor device according to claim 1, wherein the region has the following n-type impurity concentrations.

3. The semiconductor element according to claim 1, wherein the boundary region is a region within the diode region that is located in the second direction within a width range equal to the thickness of the drift region from the IGBT region.

4. The semiconductor element according to claim 1, wherein the current-passing region is composed of the cathode region, and within the specific unit semiconductor region, the n-type impurity concentration in the cathode region is higher than within the main region.

5. The semiconductor element according to claim 1, wherein the current-passing region is composed of the alternating arrangement regions, and within the specific unit semiconductor region, the area ratio of the cathode region in the current-passing region is higher than that within the main region.

6. The semiconductor device according to any one of claims 1 to 5, wherein the unit semiconductor region adjacent to the IGBT region is the specific unit semiconductor region.

7. The semiconductor element according to any one of claims 1 to 5, wherein each of the unit semiconductor regions within the boundary region is the specified unit semiconductor region.

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