Manufacturing method for substrate for forming semiconductor device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-08-13
Smart Images
Figure JP2025041237_13082026_PF_FP_ABST
Abstract
Description
Manufacturing method for semiconductor substrates
[0001] One embodiment of the present invention relates to a method for manufacturing a semiconductor device substrate for forming a semiconductor device.
[0002] In the manufacturing of semiconductor devices containing single-crystal silicon (e.g., transistors), not only single-crystal silicon substrates but also SOI (Silicon on Insulator) substrates are used. Semiconductor devices manufactured using SOI substrates have improved insulation performance, making them suitable for high-integration semiconductor devices. Specifically, in transistors using SOI substrates, the single-crystal silicon film on the SOI substrate can function as a channel.
[0003] In recent years, the use of semiconductor devices containing nitride semiconductors such as gallium nitride (e.g., light-emitting diodes (LEDs)) has been increasing. Generally, nitride semiconductors are formed using sapphire or silicon carbide substrates, which are smaller and more expensive than single-crystal silicon substrates. To provide inexpensive semiconductor devices, it is effective to mass-produce them using large-area substrates. Therefore, development is underway to manufacture semiconductor devices containing gallium nitride using SOI substrates (see, for example, Patent Document 1). According to Patent Document 1, the single-crystal silicon film on the SOI substrate is used as a buffer layer for growing gallium nitride.
[0004] Thus, single-crystal silicon films on SOI substrates are beginning to be used in many semiconductor devices, as they can function not only as channels but also as buffer layers.
[0005] Special Publication No. 2011-501431
[0006] As disclosed in Patent Document 1, in SOI substrates where multiple single-crystal silicon films are formed, seams are formed between adjacent single-crystal silicon films. If the width of the seam is small, it is possible to form epitaxially grown gallium nitride on the seam by lateral epitaxial growth. However, the edges of single-crystal silicon films contain many crystal defects. Therefore, even if the distance between adjacent single-crystal silicon films is reduced, it is difficult to form high-quality gallium nitride on the seam due to the presence of edges of single-crystal silicon films containing many crystal defects. Furthermore, it is difficult to form high-quality gallium nitride films not only on the seams but also on edges of single-crystal silicon films containing many crystal defects. Such problems are not limited to semiconductor devices containing gallium nitride. In semiconductor devices containing single-crystal silicon, it is also preferable to reduce crystal defects at the edges of single-crystal silicon films from the viewpoint of high integration.
[0007] One of the objectives of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device substrate that can be scaled up to a large area and has an improved region in which a semiconductor device is formed, in view of the above problems.
[0008] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate, cutting the first single crystal substrate so that it has a first shape, forming a first resist on the first surface of the first single crystal substrate so that the first peripheral region of the first surface of the first single crystal substrate is exposed, etching the first single crystal substrate using the first resist as a mask so that the first embrittlement layer in the first peripheral region is removed, peeling off the first single crystal film including the first surface from the first embrittlement layer, and bonding the first single crystal film onto a glass substrate.
[0009] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate, cutting the first single crystal substrate so that it has a first shape, forming a first resist on the first surface of the first single crystal substrate so that the first peripheral region of the first surface of the first single crystal substrate is exposed, etching the first single crystal substrate using the first resist as a mask so that the first embrittlement layer in the first peripheral region is removed, bonding the first single crystal substrate to a glass substrate, peeling off the first single crystal film including the first surface from the first embrittlement layer, and bonding the first single crystal film to the glass substrate.
[0010] This is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic plan view showing the configuration of a semiconductor device substrate according to one embodiment of the present invention. This is a schematic plan view showing the configuration of a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view showing the configuration of a semiconductor device manufactured using a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention.
[0011] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with respect to previously shown figures are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.
[0012] In this specification, terms such as "up" and "down" describe the relative positional relationship between the structure of interest and other structures. However, for the sake of explanation, the up-down relationship may be reversed in some cases compared to the diagram. "Plan view" refers to viewing the surface of the single-crystal substrate or glass substrate, as described later, from a direction perpendicular to it.
[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A through C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.
[0014] In this specification, the words "first," "second," or "third" attached to each component are merely convenient indicators used to distinguish each component, and unless otherwise specified, they have no further meaning.
[0015] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.
[0016] In this specification, "semiconductor device forming substrate" refers to a semiconductor device or a large-area substrate (e.g., a glass substrate) on which multiple single-crystal films are formed, which is used in the manufacture of a semiconductor device. A "semiconductor device forming substrate" can also be a support substrate for forming a semiconductor device. In the manufacturing method of a semiconductor device, in order to improve the manufacturing efficiency of the semiconductor device, there is a method in which multiple semiconductor devices are manufactured using a large-area substrate, and then the large-area substrate is divided to obtain individual semiconductor devices. Alternatively, multiple semiconductor devices may be formed on the large-area substrate using, for example, photolithography. In this case, it is desirable that the regions on which multiple semiconductor devices are formed are arranged at regular intervals on the large-area substrate. That is, it is desirable that the multiple semiconductor devices on the large-area substrate be arranged at a predetermined pitch. The single-crystal films on the large-area substrate may function as part of the semiconductor device, or they may be used in the process of manufacturing the semiconductor device.
[0017] In this specification, "nitride semiconductor" refers to a compound containing one or more Group 13 elements and nitrogen, and having semiconductor properties. Examples of nitride semiconductors include, but are not limited to, gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).
[0018] In this specification, "semiconductor device" means, for example, a transistor or a light-emitting diode, but is not limited to these.
[0019] <First Embodiment> [1. Method for Manufacturing a Semiconductor Device Forming Substrate] Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. Figures 2 to 7 are schematic cross-sectional or plan views illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. As shown in Figure 1, the method for manufacturing a semiconductor device forming substrate includes steps S100 to S150. Hereinafter, the steps of the flowchart in Figure 1 will be described in order, with appropriate reference to Figures 2 to 7.
[0020] In step S100, ions are implanted from the surface 101 side of the single crystal substrate 100 (see Figure 2). The ions are implanted into the single crystal substrate 100 using ion implantation or ion doping. The implanted ions are hydrogen ions (H ＋ , H ２ ＋ , or H ３ ＋ ) is preferable, but not limited to this. An embrittlement layer 110 is formed in the single crystal substrate 100 by ion implantation. The embrittlement layer 110 has its bonds broken by the implanted ions, making it brittle and easily peeled off compared to other regions. The position of the embrittlement layer 110 in the thickness direction of the single crystal substrate 100 (distance from the surface 101) can be adjusted by the ion implantation conditions (e.g., acceleration voltage or dose amount). For example, the position of the embrittlement layer 110 is 25 nm to 150 nm from the surface 101, preferably 50 nm to 100 nm.
[0021] The single crystal substrate 100 is, for example, a single crystal silicon substrate, but is not limited thereto. The single crystal substrate 100 may be a substrate containing a nitride semiconductor such as gallium nitride, or it may be an aluminum oxide substrate or a zinc oxide substrate. Furthermore, it is preferable that the surface 101 of the single crystal substrate 100 has high smoothness.
[0022] In step S110, the single crystal substrate 100 is cut into a predetermined shape (see Figure 3). The single crystal substrate 100 is cut, for example, to have a rectangular shape. For example, if the single crystal substrate 100 is a 300 mmφ substrate, it can be cut into a rectangular shape with a maximum area of 210 mm□. However, the predetermined shape of the single crystal substrate 100 is not limited to a rectangular shape. Depending on the shape of the large-area substrate to be bonded, the predetermined shape of the single crystal substrate 100 may be a polygon or a curved shape. Laser processing or scribing may be used to cut the single crystal substrate 100.
[0023] In step S120, a resist 300 having a predetermined shape is formed on the surface 101 of the single crystal substrate 100 using photolithography (see Figure 4). The resist 300 is formed such that the peripheral region of the surface 101 of the single crystal substrate 100 is exposed. The width of the peripheral region is 50 μm or more and 500 μm or less from the end face of the single crystal substrate 100, preferably 100 μm or more and 400 μm or less.
[0024] In step S130, the single crystal substrate 100 is etched using the resist 300 as a mask (see Figure 5). This removes the peripheral region of the single crystal substrate 100. Preferably, the etching also removes the brittle layer 110 in the peripheral region. After the single crystal substrate 100 has been etched, the resist 300 is removed.
[0025] The peripheral region of the single crystal substrate 100 contains many crystal defects due to microcracks generated by cutting in step S110. It is difficult to form a high-quality nitride semiconductor on a region containing many crystal defects. However, by etching the peripheral region of the single crystal substrate 100 in step S130, the peripheral region containing many crystal defects can be removed from the single crystal substrate 100.
[0026] In step S140, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 6). The single crystal film 120 is a part of the single crystal substrate 100 that has been separated from the embrittlement layer 110. The method for peeling off the single crystal film 120 is not particularly limited. In the embrittlement layer 110, many minute pores or grooves (hereinafter referred to as "microvoids" for convenience of explanation) are generated due to the breaking of bonds. When the single crystal substrate 100 is heated, the volume of microvoids in the embrittlement layer 110 expands, and separation occurs along the embrittlement layer 110. Therefore, by pulling the surface 101 while heating the single crystal substrate 100, the single crystal film 120 can be peeled off from the single crystal substrate 100. The heating temperature of the single crystal substrate 100 is, for example, 300°C to 700°C, preferably 400°C to 600°C.
[0027] In step S150, the large-area substrate 200 and the single-crystal film 120 are bonded and joined together (see FIG. 7). Specifically, the single-crystal film 120 is placed on the large-area substrate 200 such that the peeling surface 102 on the side opposite to the surface 101 faces the surface of the large-area substrate 200. Thereby, the large-area substrate 200 and the single-crystal film 120 are joined to some extent. However, in order to improve the joining strength, it is preferable to perform heat treatment after the large-area substrate 200 and the single-crystal film 120 are bonded together. Further, so-called anodic bonding may be performed in which a voltage is applied while performing heat treatment.
[0028] The large-area substrate 200 is, for example, a glass substrate. The glass substrate is generally amorphous having no crystal structure, but a crystal structure may exist in a minute region. The upper limit of the thermal expansion coefficient of the glass substrate is less than 4.2×10 －６ / K, preferably less than 4.0×10 －６ / K. The lower limit of the thermal expansion coefficient of the glass substrate exceeds 3.0×10 －６ / K, preferably exceeds 3.5×10 －６ / K. Although details will be described later, a semiconductor device manufactured using a semiconductor device formation substrate is manufactured at a temperature of less than 650°C. Therefore, the glass substrate preferably has heat resistance at a temperature of at least 650°C. The lower limit of the glass transition point of the glass substrate is 650°C or higher, preferably 720°C or higher. The upper limit of the glass transition point of the glass substrate is 900°C or lower, preferably 810°C or lower. For the same reason, the lower limit of the softening point of the glass substrate is 900°C or higher, preferably 950°C or higher. The upper limit of the softening point of the glass substrate is 1150°C or lower, preferably 1050°C or lower.
[0029] Note that the large-area substrate 200 is not limited to a glass substrate. The large-area substrate 200 may be a quartz substrate. The large-area substrate 200 may be a substrate larger than the single-crystal substrate 100.
[0030] As described above, when steps S100 to S150 are executed, one single crystal film 120 is bonded onto the large-area substrate 200. In this embodiment, by repeatedly executing steps S100 to S150, a semiconductor device forming substrate having a plurality of single crystal films 120 bonded onto the large-area substrate 200 can be manufactured.
[0031] In steps S140 and S150, the single crystal film 120 can also be peeled off and bonded using a transfer substrate. Specifically, the single crystal substrate 100 and the transfer substrate are bonded together, the single crystal film 120 is peeled off from the single crystal substrate 100, and then, by bonding the large-area substrate 200 and the transfer substrate together, the single crystal film 120 can be bonded onto the large-area substrate 200. Since the peeled-off single crystal film 120 is temporarily bonded to the transfer substrate, when the transfer substrate is bonded to the large-area substrate 200, the single crystal film 120 separates from the transfer substrate and is bonded to the large-area substrate 200.
[0032] [2. Configuration of the semiconductor device forming substrate 10] FIG. 8 is a schematic plan view showing the configuration of a semiconductor device forming substrate 10 according to an embodiment of the present invention.
[0033] FIG. 8 shows a semiconductor device forming substrate 10 on which nine single crystal films 120 having the same size are arranged on the large-area substrate 200. A seam is formed between two adjacent single crystal films 120. As a result of removing the peripheral region containing many crystal defects from the single crystal substrate 100 by step S130 described above, the single crystal film 120 has a low crystal defect density equivalent to that of the central portion up to its end portion and has high crystallinity over the entire surface. Therefore, in the semiconductor device forming substrate 10, a high-quality nitride semiconductor can be formed on the end portion of the single crystal film 120, or the end portion of the single crystal film 120 can be used as a channel. In other words, the semiconductor device forming substrate 10 can reduce the seam between adjacent 120s and include more regions for forming semiconductor devices.
[0034] The single crystal films 120 arranged on the large-area substrate 200 are not limited to the same size. FIG. 9 is a schematic plan view showing the configuration of a semiconductor device forming substrate 10A according to an embodiment of the present invention.
[0035] Figure 9 shows a semiconductor device forming substrate 10A on a large-area substrate 200A, on which single crystal films 120A-1, 120A-2, and 120A-3 of different sizes (hereinafter, when not specifically distinguished, these may be described as single crystal film 120A) are arranged. In this embodiment, single crystal films 120A-1, 120A-2, and 120A-3 of different sizes can be arranged according to the shape of the large-area substrate 200A. In the semiconductor device forming substrate 10A, the seams between adjacent 120A can be made smaller, and the area for forming the semiconductor device can be made larger.
[0036] Note that the semiconductor device substrate 10 shown in Figure 8 or the semiconductor device substrate 10A shown in Figure 9 are examples of semiconductor device substrates. In other words, the semiconductor device substrate manufactured by the semiconductor device substrate manufacturing method described in this embodiment is not limited to the semiconductor device substrate 10 or the semiconductor device substrate 10A.
[0037] [3. Configuration of Semiconductor Device 20] Figure 10 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 manufactured using a semiconductor device forming substrate 10 according to one embodiment of the present invention. The semiconductor device 20 is a so-called blue light-emitting diode. The semiconductor device 20 is an example of a semiconductor device manufactured using the single crystal film 120 of the semiconductor device forming substrate 10.
[0038] As shown in Figure 10, the semiconductor device 20 includes a large-area substrate 200, a single-crystal film 120, an undoped semiconductor layer 210, an n-type semiconductor layer 220, an emissive layer 230, a p-type semiconductor layer 240, a p-type electrode 250, and an n-type electrode 260. The undoped semiconductor layer 210 is provided on the single-crystal film 120. The n-type semiconductor layer 220 is provided on the undoped semiconductor layer 210. The emissive layer 230 is provided on the n-type semiconductor layer 220. The p-type semiconductor layer 240 is provided on the emissive layer 230. The p-type electrode 250 is provided on the p-type semiconductor layer 240 and is electrically connected to the p-type semiconductor layer 240. The n-type electrode 260 is provided on the n-type semiconductor layer 220 exposed from the emissive layer 230 and the p-type semiconductor layer 240 (in other words, within the recess of the n-type semiconductor layer 220) and is electrically connected to the n-type semiconductor layer 220.
[0039] Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 contains a nitride semiconductor. Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 can be deposited using sputtering.
[0040] Here, we will describe nitride semiconductors deposited using sputtering. The single crystal film 120 functions as a buffer layer for the nitride semiconductor being deposited, improving the crystallinity of the nitride semiconductor. Nitride semiconductors with a hexagonal close-packed structure grow in the c-axis direction to minimize surface energy, but deposition on the single crystal film 120 promotes crystal growth of the nitride semiconductor in the c-axis direction. Therefore, the nitride semiconductor deposited on the single crystal film 120 has a highly crystalline c-axis orientation. The materials of the single crystal substrate 100 described above, silicon, aluminum oxide, and zinc oxide, can function as buffer layers for nitride semiconductors.
[0041] The undoped semiconductor layer 210 has insulating properties and can electrically insulate the single crystal film 120. Furthermore, the undoped semiconductor layer 210 can also function as a buffer layer to adjust the lattice matching of the nitride semiconductor. In this embodiment, it is also possible to apply a configuration without the undoped semiconductor layer 210. For example, if the material of the single crystal film 120 is gallium nitride, the undoped semiconductor layer 210 may not be necessary.
[0042] The n-type semiconductor layer 220 has electron conductivity and can transport electrons supplied from the n-type electrode 260 to the light-emitting layer 230. The n-type semiconductor layer 220 includes a nitride semiconductor doped with impurities such as silicon (Si) or germanium (Ge) (hereinafter referred to as "n-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the n-type semiconductor layer 220 of the blue light-emitting diode.
[0043] The light-emitting layer 230 can emit light when electrons transported from the n-type semiconductor layer 220 and holes transported from the p-type semiconductor layer 240 are recombined. The blue light-emitting diode includes a light-emitting layer 230 (blue light-emitting layer) that emits blue light. The light-emitting layer 230 of the blue light-emitting diode has a multiple quantum well (MQW) structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately stacked.
[0044] The p-type semiconductor layer 240 has hole conductivity and can transport positive charge supplied from the p-type electrode 250 to the light-emitting layer 230. The p-type semiconductor layer 240 includes a nitride semiconductor doped with impurities such as magnesium (Mg) (hereinafter referred to as "p-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the p-type semiconductor layer 240 of a blue light-emitting diode.
[0045] The p-type electrode 250 is electrically connected to the electrode of the pixel circuit (not shown) and can supply holes to the p-type semiconductor layer 240. As the p-type electrode 250, a metal such as palladium (Pd) or gold (Au) can be used.
[0046] The n-type electrode 260 is electrically connected to the electrode of the pixel circuit (not shown) and can supply electrons to the n-type semiconductor layer 220. For example, a metal such as indium (In) can be used as the n-type electrode 260.
[0047] The structure of the light-emitting diode as a component of the semiconductor device 20 has been described above with reference to Figure 10, but the structure of the light-emitting diode shown in Figure 10 is just one example, and the structure of the light-emitting diode is not limited to this. The light-emitting diode shown in Figure 10 has a so-called horizontal electrode structure in which the p-type electrode 250 and the n-type electrode 260 do not overlap in the thickness direction. However, the semiconductor device 20 may also have a so-called vertical electrode structure in which the p-type electrode and the n-type electrode overlap with a light-emitting layer in between in the thickness direction.
[0048] The semiconductor device 20 utilizes the single-crystal film 120 of the semiconductor device substrate 10. More specifically, the nitride semiconductor of the semiconductor device 20 is deposited on the single-crystal film 120 using sputtering. Therefore, since the semiconductor device 20 can be manufactured using a large-area substrate 200, manufacturing costs can be reduced.
[0049] The nitride semiconductor layer included in the semiconductor device 20 can be formed on a large-area substrate 200 using sputtering. Therefore, the semiconductor device substrate 10 may include not only the single crystal film 120, but also the nitride semiconductor layer formed on the single crystal film 120.
[0050] The above describes a semiconductor device 20 in which the single crystal film 120 is used as a buffer layer for a nitride semiconductor layer. However, semiconductor devices manufactured using the semiconductor device forming substrate 10 are not limited to this. The semiconductor device may also be a transistor that uses the single crystal film 120 of the semiconductor device forming substrate 10 as a channel. For example, if the single crystal film 120 is a single crystal silicon film, a transistor that uses the single crystal silicon film as a channel can be manufactured using the semiconductor device forming substrate 10.
[0051] According to this embodiment, a semiconductor device forming substrate 10 is manufactured in which a plurality of single crystal films 120 are arranged on a large-area substrate 200. Although a seam is formed between two adjacent single crystal films 120, since the edges of the single crystal films 120 have high crystallinity, semiconductor devices can be manufactured using not only the central part of the single crystal films 120 but also the edges. For example, a high-quality nitride semiconductor can be formed on the edges of the single crystal films 120, or the single crystal films 120 can be used as channels. Therefore, in this embodiment, it is possible to manufacture a semiconductor device forming substrate 10 that reduces the seam between adjacent 120s and includes a large area in which semiconductor devices can be formed.
[0052] <Modification> Referring to Figure 11, a method for manufacturing a semiconductor device substrate, which is a modification of the first embodiment, will be described. In the following, when the configuration of this modification is the same as that of the first embodiment, the description of the configuration of this modification may be omitted.
[0053] Figure 11 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Specifically, Figure 11 is a schematic cross-sectional view illustrating step S150 of the flowchart in Figure 1.
[0054] As shown in Figure 11, an interface control layer 205 is provided on the surface of the large-area substrate 200. The single crystal film 120 is bonded to the interface control layer 205 on the large-area substrate 200.
[0055] The interface control layer 205 improves the bonding strength when bonding the large-area substrate 200 and the single-crystal film 120. For example, the interface control layer 205 can prevent the diffusion of impurities contained in the large-area substrate 200 and improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. In addition, the interface control layer 205 has more hydrophilicity than the surface of the large-area substrate 200 and can improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. For example, silicon oxide (SiO₂) can be used as the interface control layer. ｘ ), silicon oxide nitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon nitride (SiNｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxide nitride (AlO ｘ N ｙ ), aluminum nitride (AlN ｘ O ｙ ), or aluminum nitride (AlN ｘ ) and the like are used. Here, silicon oxide nitride (SiO ｘ N ｙ ) and aluminum oxide nitride (AlO ｘ N ｙ Silicon nitride (SiN) is a silicon compound and an aluminum compound that contains nitrogen (N) in a smaller proportion (x > y) than oxygen (O). ｘ O ｙ ) and aluminum nitride (AlN ｘ O ｙ These are silicon compounds and aluminum compounds that contain oxygen (O) in a smaller proportion (x > y) than nitrogen (N).
[0056] When the large-area substrate 200 is a glass substrate, it is preferable to use silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride as the interface control layer 205. These materials can particularly improve the bonding strength when bonding with a single-crystal silicon substrate.
[0057] According to this modified example, the interface control layer 205 can improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. Furthermore, in this modified example as well, it is possible to reduce the size of the seams between adjacent 120s and to manufacture a semiconductor device forming substrate 10 that includes a large area on which a semiconductor device can be formed.
[0058] <Second Embodiment> A method for manufacturing a semiconductor device substrate, different from the first embodiment, will be described with reference to Figures 12 to 14. In the following, when the configuration of this embodiment is the same as that of the first embodiment, the description of the configuration of this embodiment may be omitted.
[0059] Figure 12 is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Figures 13 and 14 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. As shown in Figure 12, the method for manufacturing a semiconductor device substrate includes steps S200 to S250. Hereinafter, the steps of the flowchart in Figure 12 will be described in order, with appropriate reference to Figures 13 and 14.
[0060] Steps S200 to S230 are the same as steps S100 to S130, so the explanation for steps S200 to S230 will be omitted.
[0061] In step S240, the large-area substrate 200 and the single-crystal substrate 100 are bonded together (see Figure 13). Specifically, the single-crystal substrate 100 is placed on the large-area substrate 200 such that its surface 101 faces the surface of the large-area substrate 200. This bonds the large-area substrate 200 and the single-crystal substrate 100 to a certain extent. In other words, the large-area substrate 200 and the single-crystal substrate 100 are temporarily bonded together.
[0062] In step S250, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 14). When the single crystal substrate 100 is heated, the large-area substrate 200 and the single crystal substrate 100 (more specifically, the surface 101 of the single crystal substrate 100) are firmly bonded together. Also, heating the single crystal substrate 100 causes the volume of microvoids in the embrittlement layer 110 to expand, resulting in separation along the embrittlement layer 110. As described above, the surface 101 of the single crystal substrate 100 remains intact because it is bonded to the large-area substrate 200. That is, the single crystal film 120, including the surface 101 of the single crystal substrate 100, is formed on the large-area substrate 200. As a result, a semiconductor device substrate is manufactured in which the single crystal film 120 is bonded to the large-area substrate 200. In this embodiment, the peeled surface 102 of the single crystal film 120 is exposed, so each layer of the semiconductor device is formed on the peeled surface 102.
[0063] In this embodiment as well, it is possible to manufacture a semiconductor device forming substrate 10 that reduces the size of the seams between adjacent 120 and includes a large area where a semiconductor device can be formed.
[0064] The embodiments and modifications described above as embodiments of the present invention can be combined as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on the embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.
[0065] Any effects or benefits other than those brought about by the embodiments and modifications described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.
[0066] 10, 10A: Semiconductor substrate 20: Semiconductor 100: Single crystal substrate 101: Surface 102: Exfoliation surface 110: Embrittlement layer 120, 120A, 120A-1, 120A-2, 120A-3: Single crystal film 200, 200A: Large area substrate 205: Interface control layer 210: Undoped semiconductor layer 220: n-type semiconductor layer 230: Light-emitting layer 240: p-type semiconductor layer 250: p-type electrode 260: n-type electrode 300: Resist
Claims
1. A method for manufacturing a semiconductor device substrate, comprising: implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate; cutting the first single crystal substrate so that it has a first shape; forming a first resist on the first surface of the first single crystal substrate so that the first peripheral region of the first surface of the first single crystal substrate is exposed; etching the first single crystal substrate using the first resist as a mask so that the first embrittlement layer in the first peripheral region is removed; peeling off the first single crystal film including the first surface from the first embrittlement layer; and bonding the first single crystal film to a glass substrate.
2. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising depositing a nitride semiconductor film on the first single crystal film using sputtering.
3. The method for manufacturing a semiconductor device substrate according to claim 1, wherein the first single crystal film contains silicon.
4. The method for manufacturing a semiconductor device substrate according to claim 1, wherein the peeled surface of the first single crystal film is bonded onto the glass substrate.
5. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising forming an interface control layer on the glass substrate before bonding the first single crystal film.
6. The method for manufacturing a semiconductor device substrate according to claim 5, wherein the interface control layer contains silicon oxide.
7. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising: implanting hydrogen ions from the second surface side of the second single crystal substrate to form a second embrittlement layer in the second single crystal substrate; cutting the second single crystal substrate so that it has a second shape; forming a second resist on the second surface of the second single crystal substrate so that the second peripheral region of the second surface of the second single crystal substrate is exposed; etching the second single crystal substrate using the second resist as a mask so that the second embrittlement layer in the second peripheral region is removed; peeling off the second single crystal film including the second surface from the second embrittlement layer; and bonding the second single crystal film adjacent to the first single crystal film on the glass substrate.
8. The method for manufacturing a semiconductor device substrate according to claim 7, wherein the second shape is different from the first shape.
9. A method for manufacturing a semiconductor device substrate, comprising: implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate; cutting the first single crystal substrate so that it has a first shape; forming a first resist on the first surface of the first single crystal substrate so that the first peripheral region of the first surface of the first single crystal substrate is exposed; etching the first single crystal substrate using the first resist as a mask so that the first embrittlement layer in the first peripheral region is removed; bonding the first single crystal substrate to a glass substrate; peeling off the first single crystal film including the first surface from the first embrittlement layer; and bonding the first single crystal film to the glass substrate.
10. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising depositing a nitride semiconductor film on the first single crystal film using sputtering.
11. The method for manufacturing a semiconductor device substrate according to claim 9, wherein the first single crystal film contains silicon.
12. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising forming an interface control layer on the glass substrate before bonding the first single crystal film.
13. The method for manufacturing a semiconductor device substrate according to claim 12, wherein the interface control layer contains silicon oxide.
14. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising: implanting hydrogen ions from the second surface side of the second single crystal substrate to form a second embrittlement layer in the second single crystal substrate; cutting the second single crystal substrate so that it has a second shape; forming a second resist on the second surface of the second single crystal substrate so that the second peripheral region of the second surface of the second single crystal substrate is exposed; etching the second single crystal substrate using the second resist as a mask so that the second embrittlement layer in the second peripheral region is removed; bonding the second single crystal substrate adjacent to the first single crystal film on a glass substrate; peeling the second single crystal film including the second surface from the second embrittlement layer; and bonding the second single crystal film onto the glass substrate.
15. The method for manufacturing a semiconductor device substrate according to claim 14, wherein the second shape is different from the first shape.