Semiconductor device formation substrate and production method therefor, and semiconductor device

Abstract

This semiconductor device formation substrate is for forming a plurality of semiconductor devices at a first pitch P1 in a first direction and at a second pitch P2 in a second direction orthogonal to the first direction. The semiconductor device formation substrate includes: a glass substrate; a first single crystal film on the glass substrate; and a second single crystal film disposed adjacent to the first single crystal film in the first direction on the glass substrate. The distance dF12 between the first single crystal film and the second single crystal film satisfies formula (1). Here, ds1 and ds2 are a first set value and a second set value, respectively, which are previously set, and L1 is the length of each of the plurality of semiconductor devices in the first direction.

Description

Semiconductor substrate and method for manufacturing the same, and semiconductor device

[0001] One embodiment of the present invention relates to a semiconductor device forming substrate for forming multiple semiconductor devices. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device forming substrate for forming multiple semiconductor devices.

[0002] In the manufacturing of semiconductor devices containing single-crystal silicon (e.g., transistors), not only single-crystal silicon substrates but also SOI (Silicon on Insulator) substrates are used. Semiconductor devices manufactured using SOI substrates have improved insulation performance, making them suitable for high-integration semiconductor devices. Specifically, in transistors using SOI substrates, the single-crystal silicon film on the SOI substrate can function as a channel.

[0003] In recent years, the use of semiconductor devices containing nitride semiconductors such as gallium nitride (e.g., light-emitting diodes (LEDs)) has been increasing. Generally, nitride semiconductors are formed using sapphire or silicon carbide substrates, which are smaller and more expensive than single-crystal silicon substrates. To provide inexpensive semiconductor devices, it is effective to mass-produce them using large-area substrates. Therefore, development is underway to manufacture semiconductor devices containing gallium nitride using SOI substrates (see, for example, Patent Document 1). According to Patent Document 1, the single-crystal silicon film on the SOI substrate is used as a buffer layer for growing gallium nitride.

[0004] Thus, single-crystal silicon films on SOI substrates are beginning to be used in many semiconductor devices, as they can function not only as channels but also as buffer layers.

[0005] Special Publication No. 2011-501431

[0006] As disclosed in Patent Document 1, in SOI substrates where multiple single-crystal silicon films are formed, seams are formed between adjacent single-crystal silicon films. If the width of the seam is small, it is possible to form epitaxially grown gallium nitride on the seam by lateral epitaxial growth. However, since the edges of single-crystal silicon films contain many crystal defects, the gallium nitride formed on the seam may differ in quality from the gallium nitride formed on the single-crystal silicon film. In this case, variations occur in the crystal quality of the gallium nitride formed on the SOI substrate, resulting in a decrease in the yield of semiconductor devices. Such problems are not limited to semiconductor devices containing gallium nitride. In semiconductor devices containing single-crystal silicon, variations occur between the central and edge parts of the single-crystal silicon film that functions as a channel, resulting in a decrease in the yield of semiconductor devices.

[0007] One embodiment of the present invention aims to provide a semiconductor device formation substrate that can be scaled up to a large area and is compatible with the formation patterns of multiple semiconductor devices, in view of the above problems. Another embodiment of the present invention aims to provide a method for manufacturing a semiconductor device formation substrate that can be scaled up to a large area and is compatible with the formation patterns of multiple semiconductor devices.

[0008] A semiconductor device forming substrate according to one embodiment of the present invention comprises a plurality of semiconductor devices arranged in a first direction at a first pitch P １ It has a second pitch P in a direction perpendicular to the first direction. ２ A semiconductor device forming substrate for forming a semiconductor device, comprising a glass substrate and a plurality of single crystal films on the glass substrate, wherein the plurality of single crystal films are bonded to the glass substrate such that the plurality of semiconductor devices are located inside the plurality of single crystal films at a predetermined distance from each edge of the plurality of single crystal films.

[0009] A semiconductor device formation substrate according to one embodiment of the present invention has a plurality of semiconductor device formation patterns including a plurality of semiconductor devices including a group of semiconductor devices, arranged in a first direction at a first pitch P １ It has a second pitch P in a direction perpendicular to the first direction. ２A semiconductor device forming substrate for forming with, comprising a glass substrate and a plurality of single crystal films on the glass substrate, wherein the plurality of single crystal films are bonded on the glass substrate such that a plurality of semiconductor devices are located inside at a predetermined distance from each end of the plurality of single crystal films.

[0010] A semiconductor device forming substrate according to an embodiment of the present invention has a plurality of semiconductor devices with a first pitch P in a first direction １ and a second pitch P in a second direction orthogonal to the first direction, and is a semiconductor device forming substrate for forming with, comprising a glass substrate, a first single crystal film on the glass substrate, and a second single crystal film disposed adjacent to the first single crystal film in the first direction on the glass substrate, wherein the distance d between the first single crystal film and the second single crystal film ２ satisfies the formula (1). Here, d Ｆ１２ and d ｓ１ are respectively a preset first set value and a second set value, and L ｓ２ is the length of each of the plurality of semiconductor devices in the first direction. １

[0011]

[0012] A semiconductor device forming substrate according to an embodiment of the present invention has a plurality of semiconductor device forming patterns including a group of semiconductor devices with a first pitch P in a first direction １ and a second pitch P in a second direction orthogonal to the first direction, and is a semiconductor device forming substrate for forming with, comprising a glass substrate, a first single crystal film on the glass substrate for forming a first semiconductor device forming pattern of the plurality of semiconductor device forming patterns, and a second single crystal film disposed adjacent to the first single crystal film in the first direction on the glass substrate for forming a second semiconductor device forming pattern of the plurality of semiconductor device forming patterns, wherein the distance d between the first single crystal film and the second single crystal film ２ satisfies the above formula (1). Here, d Ｆ１２ and d ｓ１ are respectively a preset first set value and a second set value, and L ｓ２ is the length of each of the plurality of semiconductor devices in the first direction. １is the length of each of the multiple semiconductor device formation patterns in the first direction.

[0013] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves arranging a plurality of semiconductor devices in a first direction and at a first pitch P in the first direction. １ It has a second pitch P in a second direction perpendicular to the first direction. ２ A method for manufacturing a semiconductor device substrate having a first single crystal film peeled from a first single crystal substrate and bonded to a glass substrate, and a second single crystal film peeled from a second single crystal substrate and bonded to a glass substrate adjacent to the first single crystal film in a first direction, wherein the distance d between the first single crystal film and the second single crystal film is Ｆ１２ The elements are joined together such that they satisfy equation (1) above. Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively, and L １ is the length of each of the multiple semiconductor devices in the first direction.

[0014] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves forming a plurality of semiconductor device formation patterns, including a group of semiconductor devices, in a first direction at a first pitch P １ It has a second pitch P in a second direction perpendicular to the first direction. ２ A method for manufacturing a semiconductor device substrate having a first single crystal film peeled from a first single crystal substrate and bonded to a glass substrate, and a second single crystal film peeled from a second single crystal substrate and bonded to a glass substrate adjacent to the first single crystal film in a first direction, wherein the distance d between the first single crystal film and the second single crystal film is Ｆ１２ The elements are joined together such that they satisfy equation (1) above. Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively, and L １ is the length of each of the multiple semiconductor device formation patterns in the first direction.

[0015] A semiconductor device according to one embodiment of the present invention is manufactured using the method for manufacturing a semiconductor device substrate described above.

[0016] This is a schematic plan view showing the configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view showing the configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view showing the configuration of a semiconductor device manufactured using a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view showing the configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view showing the configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a flowchart illustrating the method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating the method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating the method for manufacturing a single crystal film on a semiconductor device forming substrate according to one embodiment of the present invention.This is a schematic cross-sectional view showing the configuration of a large-area substrate for a semiconductor device according to one embodiment of the present invention.

[0017] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with respect to previously shown figures are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0018] In this specification, terms such as "up" and "down" describe the relative positional relationship between the structure of interest and other structures. However, for the sake of explanation, the up-down relationship may be reversed in some cases compared to the diagram. "Plan view" refers to viewing the surface of the single-crystal substrate or glass substrate, as described later, from a direction perpendicular to it.

[0019] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A through C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0020] In this specification, the words "first," "second," or "third" attached to each component are merely convenient indicators used to distinguish each component, and unless otherwise specified, they have no further meaning.

[0021] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0022] In this specification, "semiconductor device forming substrate" refers to a semiconductor device or a large-area substrate (e.g., a glass substrate) on which multiple single-crystal films are formed, which is used in the manufacture of a semiconductor device. A "semiconductor device forming substrate" can also be a support substrate for forming a semiconductor device. In the manufacturing method of a semiconductor device, in order to improve the efficiency of semiconductor device manufacturing, there is a method in which multiple semiconductor devices are manufactured using a large-area substrate, and then the large-area substrate is divided to obtain individual semiconductor devices. Alternatively, multiple semiconductor devices may be formed on a large-area substrate using, for example, photolithography. In this case, it is desirable that the regions on which multiple semiconductor devices are formed are arranged at regular intervals on the large-area substrate. That is, it is desirable that the multiple semiconductor devices on the large-area substrate be arranged at a predetermined pitch. The single-crystal films on the large-area substrate may function as part of the semiconductor device, or they may be used in the process of manufacturing the semiconductor device.

[0023] In this specification, "nitride semiconductor" refers to a compound containing one or more Group 13 elements and nitrogen, and having semiconductor properties. Examples of nitride semiconductors include, but are not limited to, gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).

[0024] In this specification, "semiconductor device" means, for example, a transistor or a light-emitting diode, but is not limited to these.

[0025] [1. Configuration of the semiconductor device substrate 10] Figures 1 and 2 are schematic plan views showing the configuration of the semiconductor device substrate 10 according to one embodiment of the present invention. Specifically, Figure 2 is an enlarged plan view of region A shown in Figure 1.

[0026] The semiconductor device forming substrate 10 includes a large-area substrate 200 and a plurality of single-crystal films 120. Figure 1 shows a semiconductor device forming substrate 10 in which nine single-crystal films 120 are arranged on the large-area substrate 200. The nine single-crystal films 120 have the same shape and size and are arranged in a matrix in a first direction D1 and a second direction perpendicular to the first direction D1. For example, the planar shape of the single-crystal film 120 is a square with four sides of equal length, but is not limited to this. The planar shape of the single-crystal film 120 may also be a rectangle with two opposing sides of equal length. The semiconductor device forming substrate 10 is a substrate for forming a plurality of semiconductor devices 20. The plurality of semiconductor devices 20 are manufactured using the semiconductor device forming substrate 10, but in the following explanation, for convenience of explanation, the semiconductor device forming substrate 10 may include the semiconductor devices 20.

[0027] The large-area substrate 200 is, for example, a glass substrate. The glass substrate is generally amorphous and does not have a crystalline structure, but a crystalline structure may exist in trace areas. The upper limit of the thermal expansion coefficient of the glass substrate is 4.2 × 10⁻⁶. －６ Less than / K, preferably 4.0 × 10 －６ It is less than / K. The lower limit of the thermal expansion coefficient of the glass substrate is 3.0 × 10⁻⁶. －６ / K exceeds, preferably 3.5 × 10 －６ The temperature exceeds / K. As will be described in detail later, the semiconductor device 20 manufactured using the semiconductor device forming substrate 10 is manufactured at a temperature of less than 650°C. Therefore, it is preferable that the glass substrate has heat resistance at a temperature of at least 650°C. The lower limit of the glass transition temperature of the glass substrate is 650°C or higher, preferably 720°C or higher. The upper limit of the glass transition temperature of the glass substrate is 900°C or lower, preferably 810°C or lower. For the same reason, the lower limit of the softening temperature of the glass substrate is 900°C or higher, preferably 950°C or higher. The upper limit of the softening temperature of the glass substrate is 1150°C or lower, preferably 1050°C or lower.

[0028] Note that the large-area substrate 200 is not limited to a glass substrate. The large-area substrate 200 may be a quartz substrate. The large-area substrate 200 may be any substrate larger than the single-crystal film 120.

[0029] The manufacturing method for the single crystal film 120 will be described later, but the single crystal film 120 is manufactured from a single crystal substrate. Therefore, the material of the single crystal film 120 is the same as the material of the single crystal substrate. The single crystal substrate is, for example, a single crystal silicon substrate, but is not limited to this. The single crystal substrate may be a substrate containing a nitride semiconductor such as gallium nitride, or it may be an aluminum oxide substrate or a zinc oxide substrate. Furthermore, it is preferable that the surface of the single crystal substrate has high smoothness.

[0030] A seam is formed between two adjacent single-crystal films 120. As will be described in detail later, it is difficult to deposit a highly crystalline nitride semiconductor by sputtering in the region of the seam where no single-crystal film 120 exists. For this reason, it is preferable to make the width of the seam as small as possible. On the other hand, as described above, multiple semiconductor devices 20 are arranged at regular intervals on a large-area substrate 200, but depending on the arrangement of the single-crystal films 120, it is possible to make the presence of the seam not a problem. That is, in the semiconductor device formation substrate 10, multiple single-crystal films 120 are arranged according to the formation pattern of the multiple semiconductor devices 20 so that no semiconductor devices 20 are formed on top of the seam. The size and pitch of the semiconductor devices 20 are taken into consideration when arranging the multiple single-crystal films 120.

[0031] In this embodiment, as shown in Figure 1, a plurality of semiconductor devices 20 having a predetermined shape are arranged at equal pitches in each of the first direction D1 and the second direction D2. As shown in Figure 2, the semiconductor devices 20 have a first length L in the first direction D1. １ It has a second length L in the second direction D2. ２ The semiconductor device 20 shown in Figure 1 has a rectangular planar shape, but is not limited to this. The planar shape of the semiconductor device 20 may be circular, elliptical, or polygonal. If the planar shape of the semiconductor device 20 is not rectangular, it is possible to convert the planar shape of the semiconductor device 20 to rectangular by setting the maximum length in the first direction D1 as the first length L1 and the maximum length in the second direction D2 as the second length L2. Furthermore, multiple semiconductor devices 20 have a first pitch P in the first direction D1. １It has a second pitch P in the second direction D2. ２ Therefore, the distance between two adjacent semiconductor devices 20 in the first direction D1 is P １ -L １ Therefore, the distance between two adjacent semiconductor devices 20 in the second direction D2 is P ２ -L ２ That is the case.

[0032] Figure 2 shows four single-crystal films 120 (referred to as the first single-crystal film 120-1, the second single-crystal film 120-2, the third single-crystal film 120-3, and the fourth single-crystal film 120-4 in Figure 2). The second single-crystal film 120-2 is adjacent to the first single-crystal film 120-1 in the first direction D1. The third single-crystal film 120-3 is adjacent to the first single-crystal film 120-1 in the second direction D2. The fourth single-crystal film 120-4 is adjacent to the second single-crystal film 120-2 in the second direction D2, and also adjacent to the third single-crystal film 120-3 in the first direction D1. The distance between the first single-crystal film 120-1 and the second single-crystal film 120-2 is d Ｆ１２ The distance between the first single crystal film 120-1 and the third single crystal film 120-3 is d Ｆ１３ The distance between the second single crystal film 120-2 and the fourth single crystal film 120-4 is d Ｆ２４ The distance between the third single crystal film 120-3 and the fourth single crystal film 120-4 is d Ｆ３４ It is. Distance d Ｆ１２ d Ｆ１３ d Ｆ２４ , and d Ｆ３４ This corresponds to the width of the seam between two adjacent single-crystal films 120.

[0033] In the semiconductor device substrate 10, the distance d Ｆ１２ d Ｆ１３ d Ｆ２４ , and d Ｆ３４ However, the arrangement of the multiple single crystal films 120 is controlled so as to satisfy equations (1), (2), (3), and (4), respectively.

[0034]

[0035] Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively. Generally, the peripheral region of the single crystal film 120 has lower crystallinity than the central region. Therefore, it is important that the semiconductor device 20 is not formed not only at the seams but also in the peripheral region of the single crystal film 120 where the crystallinity is reduced.

[0036] First setting value d ｓ１ This corresponds to the minimum distance between two adjacent single crystal films 120. Ideally, the edges of the single crystal films 120 (corresponding to the rectangular sides of the single crystal films 120) should be straight, but in reality, fine irregularities or curved shapes are formed during the manufacturing process. Therefore, the first set value d ｓ１ This is determined considering the manufacturing process margin of the single crystal film 120. For example, the first set value d ｓ１ The lower limit is greater than 0 μm, and the first set value d ｓ１ The upper limit is 10 μm or less, preferably 7 μm or less, and more preferably 5 μm or less.

[0037] Second setting value d ｓ２ This corresponds to the distance from the edge of the single crystal film 120, that is, the distance of the peripheral region where the semiconductor device 20 is not formed. The distance over which the crystallinity of the single crystal film 120 decreases in the peripheral region differs depending on the manufacturing process of the single crystal film 120. As will be described in detail later, when the peripheral region of the single crystal substrate is etched to manufacture the single crystal film 120, the distance over which the crystallinity of the peripheral region of the single crystal film 120 decreases can be reduced. On the other hand, when the peripheral region of the single crystal substrate is not etched, the distance over which the crystallinity of the peripheral region of the single crystal film 120 decreases increases. Therefore, when the peripheral region of the single crystal substrate is etched during the manufacturing of the single crystal film 120, the second set value d ｓ２ The thickness is 0 μm or more and 50 μm or less, preferably 0 μm or more and 25 μm or less, and more preferably 0 μm or more and 10 μm or less. Also, when the peripheral region of the single crystal substrate is not etched during the manufacturing of the single crystal film 120, the second set value d ｓ２The particle size is 50 μm or more and 500 μm or less, preferably 50 μm or more and 400 μm or less, and more preferably 50 μm or more and 300 μm or less.

[0038] Second setting value d ｓ２ Furthermore, the bonding accuracy in the bonding process of the single crystal film 120 may be taken into consideration when determining the second set value d. ｓ２ This can include the manufacturing process margin in the bonding process. For example, if the bonding accuracy is ±10 μm, the manufacturing process margin is 20 μm, and the second set value d described above. ｓ２ This value may be added to it.

[0039] [2. Method for Manufacturing the Semiconductor Device Forming Substrate 10] Figure 3 is a flowchart illustrating the method for manufacturing the semiconductor device forming substrate 10 according to one embodiment of the present invention. Figures 4 to 10 are schematic plan views illustrating the method for manufacturing the semiconductor device forming substrate 10 according to one embodiment of the present invention. As shown in Figure 3, the method for manufacturing the semiconductor device forming substrate 10 includes steps S10 to S60. Hereinafter, the steps of the flowchart in Figure 3 will be explained in order, with appropriate reference to Figures 4 to 10.

[0040] In step S10, the first single crystal film 120-1 is bonded to the large-area substrate 200 in a predetermined area of ​​the large-area substrate 200 (see Figure 4). For example, the first single crystal film 120-1 is bonded to the large-area substrate 200 in the central area of ​​the large-area substrate 200, and then the first single crystal film 120-1 is pressed against the large-area substrate 200 while heating the first single crystal film 120-1 or the large-area substrate 200. This bonds the first single crystal film 120-1 to the large-area substrate 200. In addition, so-called anodic bonding, in which a voltage is applied while heating, may be performed when bonding the first single crystal film 120-1 to the large-area substrate 200.

[0041] In step S20, the second single crystal film 120-2 is bonded to the large-area substrate 200 so that it is adjacent to the first single crystal film 120-1 in the first direction D1 (see Figure 5). In step S20, the distance d between the first single crystal film 120-1 and the second single crystal film 120-2 Ｆ１２Alignment is performed so that equation (1) is satisfied. Specifically, the perpendicular bisector of one side of the first single crystal film 120-1 is made to coincide with the perpendicular bisector of one side of the second single crystal film 120-2, and the second single crystal film 120-2 is moved in the direction of the direction vector of the perpendicular bisector so that equation (1) is satisfied. This alignment brings the second single crystal film 120-2 to a distance d from the first single crystal film 120-1. Ｆ１２ It has the ability to be bonded adjacently to the large-area substrate 200. Then, in the same manner as in step S10, the second single crystal film 120-2 is bonded to the large-area substrate 200.

[0042] The alignment described above can be performed using alignment means including a camera and a moving mechanism. By detecting one side of the first single crystal film 120-1 and one side of the second single crystal film 120-2 with the camera (for example, one side of the single crystal film 120 is detected as a straight line using the square root of the sum of squares), the perpendicular bisectors of each can be calculated based on these. Furthermore, the calculated perpendicular bisectors and distance d Ｆ１２ Based on this, the second single crystal film 120-2 can be moved by the movement mechanism.

[0043] In step S30, the third single crystal film 120-3 is bonded to the large-area substrate 200 so that it is adjacent to the first single crystal film 120-1 in the second direction D2 (see Figure 6). In step S30, the distance d between the first single crystal film 120-1 and the third single crystal film 120-3 Ｆ１３ Alignment is performed so that equation (2) is satisfied. The alignment in step S30 is the same as the step in step S20, so the explanation is omitted here.

[0044] In step S40, similar to step S20, the fourth single crystal film 120-4 is bonded to the large-area substrate 200 so that it is adjacent to the first single crystal film 120-1 in the first direction D1. Also, similar to step S30, the fifth single crystal film 120-5 is bonded to the large-area substrate 200 so that it is adjacent to the first single crystal film 120-1 in the second direction D2 (see Figure 7). As a result, all edges of the first single crystal film 120-1 are adjacent to one edge of the other single crystal films 120.

[0045] In step S50, the sixth single crystal film 120-6 is bonded to the large-area substrate 200 such that it is adjacent to the second single crystal film 120-2 in the second direction D2 and adjacent to the third single crystal film 120-3 in the first direction (see Figure 8). The sixth single crystal film 120-6 is positioned so that it is adjacent not only to the second single crystal film 120-2 but also to the third single crystal film 120-3. In this case, unless the angle between one side of the second single crystal film 120-2 and one side of the third single crystal film 120-3 adjacent to the sixth single crystal film 120-6 is 90°, it is not possible to make the perpendicular bisectors of the two sides of the sixth single crystal film 120-6 coincide with one side of the second single crystal film 120-2 and one side of the third single crystal film 120-3. Therefore, when aligning another single crystal film 120 so that it is adjacent to two single crystal films 120 bonded on a large-area substrate 200, a straight line connecting the midpoints of the sides of the two single crystal films 120 is used. Specifically, the straight line connecting the midpoint of one side of the second single crystal film 120-2 and the midpoint of one side of the third single crystal film 120-3 is made to coincide with the straight line connecting the midpoints of the two intersecting sides of the sixth single crystal film 120-6. In addition, while maintaining the direction vector of the straight line, equations (3) and (4) are satisfied (d in equation (3)). Ｆ２４ and d in equation (4) Ｆ３４ These are, respectively, d Ｆ２６ and d Ｆ３６ The sixth single crystal film 120-6 is moved in this manner. This alignment moves the sixth single crystal film 120-6 to a distance d from the second single crystal film 120-2. Ｆ２６ They are adjacent and have a distance d from the third single crystal film 120-3. Ｆ３６ It has the ability to be bonded adjacently to the large-area substrate 200. Then, in the same manner as in step S10, the sixth single crystal film 120-6 is bonded to the large-area substrate 200.

[0046] Furthermore, in step S50, a method other than the alignment described above can be applied. First, the sixth single crystal film 120-6 is rotated so that one of its four vertices, which is close to 90°, approaches the edges of the second single crystal film 120-2 and the third single crystal film 120-3. Next, the sixth single crystal film 120-6 is moved in the first direction D1 to satisfy equation (3) (see Figure 9), and then the sixth single crystal film 120-6 is moved in the second direction D2 to satisfy equation (4) (see Figure 10). This alignment also brings the sixth single crystal film 120-6 to a distance d from the second single crystal film 120-2. Ｆ２６ They are adjacent and have a distance d from the third single crystal film 120-3. Ｆ３６ It has the ability to be attached adjacent to a large-area substrate 200.

[0047] In any of the alignment methods described above, the two opposing sides of the two adjacent single crystal films 120 may not be parallel, and the distance between the two sides may increase or decrease. In this case, the distance d Ｆ２６ or distance d Ｆ３６ Although it does not become a constant value, the distance d Ｆ２６ The maximum value and distance d Ｆ３６ The position of the sixth single crystal film 120-6 can also be finely adjusted by rotating and moving it so that the maximum values ​​of both are minimized.

[0048] Subsequently, the same steps as in step S50 are repeated, and another single crystal film 120 is sequentially bonded to the large-area substrate 200 so as to be adjacent to the two single crystal films 120 bonded to the large-area substrate 200. This manufactures the semiconductor device substrate 10 shown in Figure 1.

[0049] Although the semiconductor device substrate 10 shown in Figure 1 contains nine single-crystal films 120, the number of single-crystal films 120 included in the semiconductor device substrate 10 is not limited to this. By applying an alignment method corresponding to the number of adjacent single-crystal films 120, even fewer than nine or more single-crystal films 120 can be bonded to the large-area substrate 200.

[0050] [3. Method for Manufacturing the Single Crystal Film 120] Figure 11 is a flowchart illustrating the method for manufacturing the single crystal film 120 of the semiconductor device substrate 10 according to one embodiment of the present invention. Figures 12 to 16 are schematic cross-sectional or plan views illustrating the method for manufacturing the single crystal film 120 of the semiconductor device substrate 10 according to one embodiment of the present invention. As shown in Figure 11, the method for manufacturing the single crystal film 120 includes steps S100 to S150. Hereinafter, the steps of the flowchart in Figure 11 will be explained in order, with appropriate reference to Figures 12 to 16.

[0051] In step S100, ions are implanted from the surface 101 side of the single crystal substrate 100 (see Figure 12). The ions are implanted into the single crystal substrate 100 using ion implantation or ion doping. The implanted ions are hydrogen ions (H ＋ , H ２ ＋ , or H ３ ＋ ) is preferable, but not limited to this. An embrittlement layer 110 is formed in the single crystal substrate 100 by ion implantation. The embrittlement layer 110 has its bonds broken by the implanted ions, making it brittle and easily peeled off compared to other regions. The position of the embrittlement layer 110 in the thickness direction of the single crystal substrate 100 (distance from the surface 101) can be adjusted by the ion implantation conditions (e.g., acceleration voltage or dose amount). For example, the position of the embrittlement layer 110 is 25 nm to 150 nm from the surface 101, preferably 50 nm to 100 nm.

[0052] In step S110, the single crystal substrate 100 is cut into a predetermined shape (see Figure 13). The single crystal substrate 100 is cut, for example, to have a rectangular shape. For example, if the single crystal substrate 100 is a 300 mmφ substrate, it can be cut into a square shape with a maximum area of ​​210 mm□. However, the predetermined shape of the single crystal substrate 100 is not limited to a square. The predetermined shape of the single crystal substrate 100 may be rectangular, depending on the shape of the large-area substrate to which it is bonded. Laser processing or scribing may be used to cut the single crystal substrate 100.

[0053] In step S120, a resist 300 having a predetermined shape is formed on the surface 101 of the single crystal substrate 100 using photolithography (see Figure 14). The resist 300 is formed such that the peripheral region of the surface 101 of the single crystal substrate 100 is exposed. The width of the peripheral region is 50 μm or more and 500 μm or less from the end face of the single crystal substrate 100, preferably 100 μm or more and 400 μm or less.

[0054] In step S130, the single crystal substrate 100 is etched using the resist 300 as a mask (see Figure 15). This removes the peripheral region of the single crystal substrate 100. Preferably, the etching also removes the embrittlement layer 110 in the peripheral region. After the single crystal substrate 100 has been etched, the resist 300 is removed.

[0055] The peripheral region of the single crystal substrate 100 contains many crystal defects due to microcracks generated by cutting in step S110. It is difficult to form a high-quality nitride semiconductor on a region containing many crystal defects. However, by etching the peripheral region of the single crystal substrate 100 in step S130, the peripheral region containing many crystal defects can be removed from the single crystal substrate 100.

[0056] In step S140, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 16). The single crystal film 120 is a part of the single crystal substrate 100 that has been separated from the embrittlement layer 110. The method for peeling off the single crystal film 120 is not particularly limited. In the embrittlement layer 110, many minute pores or grooves (hereinafter referred to as "microvoids" for convenience of explanation) are generated due to the breaking of bonds. When the single crystal substrate 100 is heated, the volume of microvoids in the embrittlement layer 110 expands, and separation occurs along the embrittlement layer 110. Therefore, by pulling the surface 101 while heating the single crystal substrate 100, the single crystal film 120 can be peeled off from the single crystal substrate 100. The heating temperature of the single crystal substrate 100 is, for example, 300°C to 700°C, preferably 400°C to 600°C.

[0057] In addition, when bonding the single crystal film 120 to the large-area substrate 200, either the surface 101 or the peel surface 102 of the single crystal film 120 may be facing the surface of the large-area substrate 200.

[0058] Furthermore, in step S140, the single crystal film 120 can also be peeled off using a transfer substrate. Specifically, the single crystal substrate 100 and the transfer substrate are bonded together, and the single crystal film 120 is peeled off from the single crystal substrate 100. At this time, the peeled single crystal film 120 is temporarily bonded to the transfer substrate. Therefore, by subsequently bonding the large-area substrate 200 and the transfer substrate together, the single crystal film 120 can be bonded to the large-area substrate 200.

[0059] As explained above, the above manufacturing method produces a single crystal film 120 in which the peripheral region of the single crystal substrate 100 is etched. However, in this embodiment, the second set value d ｓ２ By setting an appropriate value, it is possible to manufacture a semiconductor device substrate 10 by applying a single crystal film 120 that is manufactured without etching the peripheral region of the single crystal substrate 100. In this case, steps S120 to S140 do not need to be performed in the manufacturing of the single crystal film 120.

[0060] [4. Configuration of Semiconductor Device 20] Figure 17 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 manufactured using a semiconductor device forming substrate 10 according to one embodiment of the present invention. The semiconductor device 20 is a so-called blue light-emitting diode. The semiconductor device 20 is an example of a semiconductor device manufactured using the single crystal film 120 of the semiconductor device forming substrate 10.

[0061] As shown in Figure 17, the semiconductor device 20 includes a large-area substrate 200, a single-crystal film 120, an undoped semiconductor layer 210, an n-type semiconductor layer 220, an emissive layer 230, a p-type semiconductor layer 240, a p-type electrode 250, and an n-type electrode 260. The undoped semiconductor layer 210 is provided on the single-crystal film 120. The n-type semiconductor layer 220 is provided on the undoped semiconductor layer 210. The emissive layer 230 is provided on the n-type semiconductor layer 220. The p-type semiconductor layer 240 is provided on the emissive layer 230. The p-type electrode 250 is provided on the p-type semiconductor layer 240 and is electrically connected to the p-type semiconductor layer 240. The n-type electrode 260 is provided on the n-type semiconductor layer 220 exposed from the emissive layer 230 and the p-type semiconductor layer 240 (in other words, within the recess of the n-type semiconductor layer 220) and is electrically connected to the n-type semiconductor layer 220.

[0062] Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 contains a nitride semiconductor. Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 can be deposited using sputtering.

[0063] Here, we will describe nitride semiconductors deposited using sputtering. The single crystal film 120 functions as a buffer layer for the nitride semiconductor being deposited, improving the crystallinity of the nitride semiconductor. Nitride semiconductors with a hexagonal close-packed structure grow in the c-axis direction to minimize surface energy, but deposition on the single crystal film 120 promotes crystal growth of the nitride semiconductor in the c-axis direction. Therefore, the nitride semiconductor deposited on the single crystal film 120 has a highly crystalline c-axis orientation. The materials of the single crystal substrate 100 described above, silicon, aluminum oxide, and zinc oxide, can function as buffer layers for nitride semiconductors.

[0064] The undoped semiconductor layer 210 has insulating properties and can electrically insulate the single crystal film 120. Furthermore, the undoped semiconductor layer 210 can also function as a buffer layer to adjust the lattice matching of the nitride semiconductor. In this embodiment, it is also possible to apply a configuration without the undoped semiconductor layer 210. For example, if the material of the single crystal film 120 is gallium nitride, the undoped semiconductor layer 210 may not be necessary.

[0065] The n-type semiconductor layer 220 has electron conductivity and can transport electrons supplied from the n-type electrode 260 to the light-emitting layer 230. The n-type semiconductor layer 220 includes a nitride semiconductor doped with impurities such as silicon (Si) or germanium (Ge) (hereinafter referred to as "n-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the n-type semiconductor layer 220 of the blue light-emitting diode.

[0066] The light-emitting layer 230 can emit light when electrons transported from the n-type semiconductor layer 220 and holes transported from the p-type semiconductor layer 240 are recombined. The blue light-emitting diode includes a light-emitting layer 230 (blue light-emitting layer) that emits blue light. The light-emitting layer 230 of the blue light-emitting diode has a multiple quantum well (MQW) structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately stacked.

[0067] The p-type semiconductor layer 240 has hole conductivity and can transport positive charge supplied from the p-type electrode 250 to the light-emitting layer 230. The p-type semiconductor layer 240 includes a nitride semiconductor doped with impurities such as magnesium (Mg) (hereinafter referred to as "p-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the p-type semiconductor layer 240 of a blue light-emitting diode.

[0068] The p-type electrode 250 is electrically connected to the electrode of the pixel circuit (not shown) and can supply holes to the p-type semiconductor layer 240. As the p-type electrode 250, a metal such as palladium (Pd) or gold (Au) can be used.

[0069] The n-type electrode 260 is electrically connected to the electrode of the pixel circuit (not shown) and can supply electrons to the n-type semiconductor layer 220. For example, a metal such as indium (In) can be used as the n-type electrode 260.

[0070] The structure of the blue light-emitting diode as the configuration of the semiconductor device 20 has been described above with reference to Figure 17, but the structure of the light-emitting diode in Figure 17 is not limited to this. The semiconductor device 20 shown in Figure 17 has a so-called horizontal electrode structure in which the p-type electrode 250 and the n-type electrode 260 do not overlap in the thickness direction. However, the semiconductor device 20 may also have a so-called vertical electrode structure in which the p-type electrode and the n-type electrode overlap with a light-emitting layer in between in the thickness direction.

[0071] The semiconductor device 20 is formed on the semiconductor device substrate 10 using sputtering. In other words, the nitride semiconductor of the semiconductor device 20 is deposited using sputtering. Therefore, since the semiconductor device 20 can be manufactured using a large-area substrate 200, manufacturing costs can be reduced.

[0072] The above describes a semiconductor device 20 in which the single crystal film 120 is used as a buffer layer for a nitride semiconductor layer. However, the semiconductor device 20 manufactured using the semiconductor device substrate 10 is not limited to this. The semiconductor device 20 may also be a transistor that uses the single crystal film 120 of the semiconductor device substrate 10 as a channel. For example, if the single crystal film 120 is a single crystal silicon film, a transistor that uses the single crystal silicon film as a channel can be manufactured using the semiconductor device substrate 10.

[0073] According to this embodiment, the width of the seams between multiple single-crystal films 120 (corresponding to the distance between two adjacent single-crystal films 120) is adjusted according to the formation pattern of multiple semiconductor devices 20, and a semiconductor device forming substrate 10 is provided in which multiple single-crystal films 120 are bonded to a large-area substrate 200. By manufacturing semiconductor devices 20 using the semiconductor device forming substrate 10, the semiconductor devices 20 are not formed on the seams or in the peripheral regions of single-crystal films 120 where the crystallinity has decreased, so the semiconductor devices 20 are formed efficiently and the yield can be improved.

[0074] This embodiment can be modified in various ways. Several modifications of this embodiment are described below. However, the modifications of this embodiment are not limited to those described below.

[0075] <First Modification> The first modification will be described with reference to Figures 18 and 19. In the following, if the configuration of the first modification is the same as the configuration described above, the description of that configuration may be omitted.

[0076] Figures 18 and 19 are schematic plan views showing the configuration of a semiconductor device forming substrate 10 according to one embodiment of the present invention. Specifically, Figure 19 is an enlarged plan view of region B shown in Figure 18.

[0077] The configuration of the semiconductor device formation substrate 10 shown in Figure 18 is the same as that of the semiconductor device formation substrate 10 shown in Figure 1. However, in this modified example, the multiple semiconductor devices 20 formed on the semiconductor device formation substrate 10 are not arranged at equal pitches. Even in such a case, if the multiple semiconductor device formation patterns 20P, which include a group of semiconductor devices 20, are arranged at equal pitches, it is possible to manufacture a semiconductor device formation substrate 10 in which multiple single crystal films 120 are bonded to a large-area substrate 200 according to the semiconductor device formation patterns 20P.

[0078] As shown in Figure 18, the plurality of semiconductor device formation patterns 20P are arranged at equal pitches in the first direction D1 and the second direction D2. The semiconductor device formation patterns 20P have a first length L in the first direction D1. １ It has a length L in the second direction D2. ２It has. Also, the plurality of semiconductor device formation patterns 20P have a first pitch P in the first direction D1 １ and have a second pitch P in the second direction D2 ２ Thus, the distance between two adjacent semiconductor device formation patterns 20P in the first direction D1 is P １ - L １ and the distance between two adjacent semiconductor device formation patterns 20P in the second direction D2 is P ２ - L ２ In this modified example, according to the above-described definition, the semiconductor device formation substrate 10 can be manufactured by applying formulas (1) to (4).

[0079] According to this modified example, the width of the joints of the plurality of single crystal films 120 (corresponding to the distance between two adjacent single crystal films 120) can be adjusted according to the plurality of semiconductor device formation patterns 20P, and a semiconductor device formation substrate 10 in which the plurality of single crystal films 120 are joined to the large-area substrate 200 can be provided. By manufacturing the semiconductor device 20 using the semiconductor device formation substrate 10, the semiconductor device 20 is not formed on the joints or in the peripheral region of the single crystal film 120 where the crystallinity has decreased, so that the semiconductor device 20 can be efficiently formed and the yield can be improved.

[0080] <Second Modified Example> Referring to FIGS. 20 to 22, the second modified example will be described. Hereinafter, when the configuration of the second modified example is the same as the above-described configuration, the description of the configuration may be omitted.

[0081] Figure 20 is a flowchart illustrating a method for manufacturing a single crystal film 120 on a semiconductor device substrate 10 according to one embodiment of the present invention. Figures 21 and 22 are schematic cross-sectional views illustrating a method for manufacturing a single crystal film 120 on a semiconductor device substrate 10 according to one embodiment of the present invention. As shown in Figure 20, the method for manufacturing the single crystal film 120 includes steps S100 to S130 of the flowchart shown in Figure 11. Thereafter, one of the steps S10 to S60 of the flowchart shown in Figure 3 is executed. That is, in this modified example, the single crystal substrate 100 and the large-area substrate 200 are bonded together, and then the single crystal film 120 is peeled off from the single crystal substrate 100 and bonded to the large-area substrate 200. Hereinafter, the bonding of the single crystal film 120 using the single crystal substrate 100 to the large-area substrate 200 will be described with appropriate reference to Figures 20 and 21.

[0082] First, the large-area substrate 200 and the single-crystal substrate 100 are bonded together (see Figure 21). Specifically, the single-crystal substrate 100 is placed on the large-area substrate 200 so that its surface 101 faces the surface of the large-area substrate 200. This partially bonds the surface 101 of the single-crystal substrate 100 to the large-area substrate 200. In other words, the large-area substrate 200 and the single-crystal substrate 100 are temporarily bonded together.

[0083] Next, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 22). When the single crystal substrate 100 is heated, the large-area substrate 200 and the single crystal substrate 100 (more specifically, the surface 101 of the single crystal substrate 100) are firmly bonded together. Also, heating the single crystal substrate 100 causes the volume of microvoids in the embrittlement layer 110 to expand, resulting in separation along the embrittlement layer 110. As described above, since the single crystal substrate 100 is temporarily bonded to the large-area substrate 200, the single crystal film 120, including the surface 101, remains intact. In other words, the single crystal film 120 is bonded onto the large-area substrate 200.

[0084] Even with the single crystal film 120 produced by this modified method, the semiconductor device substrate 10 can be manufactured by applying formulas (1) to (4).

[0085] According to this modification example, the width of the seam of the plurality of single crystal films 120 (corresponding to the distance between two adjacent single crystal films 120) is adjusted according to the formation pattern of the plurality of semiconductor devices 20, and a semiconductor device formation substrate 10 in which the plurality of single crystal films 120 are joined to the large area substrate 200 can be provided. By manufacturing the semiconductor device 20 using the semiconductor device formation substrate 10, the semiconductor device 20 is not formed on the seam or in the peripheral region of the single crystal film 120 where the crystallinity has decreased, so that the semiconductor device 20 can be efficiently formed and the yield can be improved.

[0086] <Third modification example> Referring to FIG. 23, the third modification example will be described. In the following, when the configuration of the third modification example is the same as the above-described configuration, the description of the configuration may be omitted.

[0087] FIG. 23 is a schematic cross-sectional view showing the configuration of the large area substrate 200 of the semiconductor device formation substrate 10 according to an embodiment of the present invention.

[0088] As shown in FIG. 23, an interface control layer 205 is provided on the surface of the large area substrate 200. The single crystal film 120 is bonded and joined to the interface control layer 205 on the large area substrate 200.

[0089] The interface control layer 205 improves the bonding strength in the bonding of the large area substrate 200 and the single crystal film 120. For example, the interface control layer 205 can prevent the diffusion of impurities contained in the large area substrate 200 and improve the bonding strength between the large area substrate 200 and the single crystal film 120. In addition, the interface control layer 205 has higher hydrophilicity than the surface of the large area substrate 200, and can improve the bonding strength between the large area substrate 200 and the single crystal film 120. For example, as the interface control layer, silicon oxide (SiO ｘ ), silicon oxynitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon nitride oxide (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlO ｘ N ｙ ), aluminum nitride oxide (AlN ｘO ｙ ), or aluminum nitride (AlN ｘ ) and the like are used. Here, silicon oxide nitride (SiO ｘ N ｙ ) and aluminum oxide nitride (AlO ｘ N ｙ Silicon nitride (SiN) is a silicon compound and an aluminum compound that contains nitrogen (N) in a smaller proportion (x > y) than oxygen (O). ｘ O ｙ ) and aluminum nitride (AlN ｘ O ｙ These are silicon compounds and aluminum compounds that contain oxygen (O) in a smaller proportion (x > y) than nitrogen (N).

[0090] When the large-area substrate 200 is a glass substrate, it is preferable to use silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride as the interface control layer 205. These materials can particularly improve the bonding strength when bonding with a single-crystal silicon substrate.

[0091] According to this modified example, the interface control layer 205 can improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. In this modified example as well, the width of the seams between the multiple single-crystal films 120 (corresponding to the distance between two adjacent single-crystal films 120) can be adjusted according to the formation pattern of the multiple semiconductor devices 20, thereby providing a semiconductor device forming substrate 10 in which multiple single-crystal films 120 are bonded to the large-area substrate 200. By manufacturing the semiconductor devices 20 using the semiconductor device forming substrate 10, the semiconductor devices 20 are not formed on the seams or in the peripheral regions of the single-crystal films 120 where the crystallinity has decreased, so the semiconductor devices 20 are formed efficiently and the yield can be improved.

[0092] The embodiments and modifications described above as embodiments of the present invention can be combined as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on the embodiments and modifications, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0093] Any effects or benefits other than those brought about by the embodiments and modifications described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0094] 10: Semiconductor device substrate 20: Semiconductor device 20P: Semiconductor device formation pattern 100: Single crystal substrate 101: Surface 102: Delamination surface 110: Embrittlement layer 120, 120-2, 120-3, 120-4, 120-5, 120-6: Single crystal film 200: Large area substrate 205: Interface control layer 210: Undoped semiconductor layer 220: n-type semiconductor layer 230: Light-emitting layer 240: p-type semiconductor layer 250: p-type electrode 260: n-type electrode 300: Resist

Claims

1. Multiple semiconductor devices are arranged in a first direction at a first pitch P １ It has a second pitch P in a direction perpendicular to the first direction. ２ A semiconductor device forming substrate for forming a semiconductor device, comprising: a glass substrate; and a plurality of single crystal films on the glass substrate, wherein the plurality of single crystal films are bonded to the glass substrate such that the plurality of semiconductor devices are located inside the plurality of single crystal films at a predetermined distance from each end of the plurality of single crystal films.

2. Multiple semiconductor device formation patterns, including a group of semiconductor devices, are formed in a first direction with a first pitch P. １ It has a second pitch P in a direction perpendicular to the first direction. ２ A semiconductor device forming substrate for forming a semiconductor device, comprising: a glass substrate; and a plurality of single crystal films on the glass substrate, wherein the plurality of single crystal films are bonded to the glass substrate such that the plurality of semiconductor devices are located inside the plurality of single crystal films at a predetermined distance from each end of the plurality of single crystal films.

3. Each of the plurality of single crystal films is bonded to the glass substrate using a single crystal substrate whose peripheral region has been etched, and the predetermined distance is 5 μm or more and 10 μm or less, according to claim 1 or claim 2.

4. The semiconductor device substrate according to claim 1 or claim 2, wherein the plurality of single crystal films include silicon.

5. A semiconductor device forming substrate for forming a plurality of semiconductor devices having a first pitch P in a first direction and a second pitch P in a second direction orthogonal to the first direction, the semiconductor device forming substrate comprising: a glass substrate; a first single crystal film on the glass substrate; and a second single crystal film disposed adjacent to the first single crystal film in the first direction on the glass substrate, the distance d between the first single crystal film and the second single crystal film satisfying the formula (1). １ (Here, d ２ and d Ｆ１２ are respectively a preset first set value and a second set value, and L is the length of each of the plurality of semiconductor devices in the first direction.) ｓ１ and d ｓ２ are respectively a preset first set value and a second set value, and L １ is the length of each of the plurality of semiconductor devices in the first direction.) 6. Furthermore, the glass substrate includes a third single crystal film disposed adjacent to the first single crystal film in the second direction, wherein the distance d between the first single crystal film and the third single crystal film is... Ｆ１３ A semiconductor device forming substrate according to claim 5, wherein the formula satisfies equation (2). (Here, L ２ (where is the length of each of the plurality of semiconductor devices in the second direction.) 7. Furthermore, the glass substrate includes a fourth single crystal film, which is positioned adjacent to the second single crystal film in the second direction and adjacent to the third single crystal film in the first direction, wherein the distance d between the second single crystal film and the fourth single crystal film is Ｆ２４ The equation (3) is satisfied, and the distance d between the third single crystal film and the fourth single crystal film is... Ｆ３４ A semiconductor device forming substrate according to claim 6, wherein the formula (4) is satisfied.

8. Multiple semiconductor device formation patterns, including a group of semiconductor devices, are formed in a first direction with a first pitch P １ It has a second pitch P in a second direction perpendicular to the first direction. ２ A semiconductor device forming substrate for forming a plurality of semiconductor device forming patterns, comprising: a glass substrate; a first single crystal film on the glass substrate for forming a first semiconductor device forming pattern of the plurality of semiconductor device forming patterns; and a second single crystal film on the glass substrate, arranged adjacent to the first single crystal film in the first direction, for forming a second semiconductor device forming pattern of the plurality of semiconductor device forming patterns, wherein the distance d between the first single crystal film and the second single crystal film is Ｆ１２ A semiconductor device substrate that satisfies equation (1). (Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively, and L １ (where is the length of each of the plurality of semiconductor device formation patterns in the first direction.) 9. Furthermore, the glass substrate includes a third single crystal film arranged adjacent to the first single crystal film in the second direction for forming a third semiconductor device formation pattern of the plurality of semiconductor device formation patterns, wherein the distance d between the first single crystal film and the third single crystal film is Ｆ１３ A semiconductor device forming substrate according to claim 8, wherein the formula satisfies equation (2). (Here, L ２ (where is the length of each of the plurality of semiconductor device formation patterns in the second direction.) 10. Furthermore, for forming a fourth semiconductor formation pattern of the plurality of semiconductor device formation patterns, a fourth single crystal film is provided on the glass substrate, which is arranged adjacent to the second single crystal film in the second direction and separated from the third single crystal film in the first direction, wherein the distance d between the second single crystal film and the fourth single crystal film is provided. Ｆ２４ The equation (3) is satisfied, and the distance d between the third single crystal film and the fourth single crystal film is... Ｆ３４ A semiconductor device forming substrate according to claim 9, wherein the expression satisfies formula (4).

11. Each of the first single crystal film and the second single crystal film is bonded to the glass substrate using a single crystal substrate whose peripheral region has been etched, and the second set value d ｓ２ The semiconductor device forming substrate according to claim 5 or claim 8, wherein the thickness is 5 μm or more and 10 μm or less.

12. The semiconductor device substrate according to claim 5 or claim 8, wherein each of the first single crystal film and the second single crystal film comprises silicon.

13. Multiple semiconductor devices arranged in a first direction at a first pitch P １ It has a second pitch P in a second direction perpendicular to the first direction. ２ A method for manufacturing a semiconductor device substrate having, comprising: bonding a first single crystal film peeled from a first single crystal substrate onto a glass substrate; and bonding a second single crystal film peeled from a second single crystal substrate onto the glass substrate adjacent to the first single crystal film in the first direction, wherein the distance d between the first single crystal film and the second single crystal film is Ｆ１２ A method for manufacturing a semiconductor device substrate, wherein the substrates are joined such that they satisfy equation (1). (Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively, and L １ (where is the length of each of the plurality of semiconductor devices in the first direction.) 14. Furthermore, the method includes bonding a third single crystal film, peeled from a third single crystal substrate, onto the glass substrate adjacent to the first single crystal film in the second direction, wherein the distance d between the first single crystal film and the third single crystal film is such that the third single crystal film is bonded to the glass substrate, wherein the distance d between the first single crystal film and the third single crystal film is such that the third single crystal film is bonded to the glass substrate, wherein the distance d between the first single crystal film and the third single crystal film is such that the third single crystal film is bonded to the glass substrate, adjacent to the first single crystal film in the second direction distance d Ｆ１３ A method for manufacturing a semiconductor device substrate according to claim 13, wherein the substrates are joined such that they satisfy formula (2). (Here, L ２ (where is the length of each of the plurality of semiconductor devices in the second direction.) 15. Furthermore, the method includes bonding a fourth single crystal film, which has been peeled from a fourth single crystal substrate, onto the glass substrate, adjacent to the second single crystal film in the second direction and adjacent to the third single crystal film in the first direction, wherein the distance d between the second single crystal film and the fourth single crystal film is such that the fourth single crystal film is bonded to the glass substrate adjacent to the second single crystal film in the second direction and adjacent to the third single crystal film in the first direction, Ｆ２４ The equation (3) is satisfied, and the distance d between the third single crystal film and the fourth single crystal film is... Ｆ３４ A method for manufacturing a semiconductor device substrate according to claim 14, wherein the substrates are joined such that they satisfy formula (4).

16. Furthermore, the process includes etching the peripheral regions of the first single crystal substrate and the second single crystal substrate, wherein the second set value d ｓ２ The method for manufacturing a semiconductor device substrate according to claim 13, wherein the thickness is 5 μm or more and 10 μm or less.

17. The method for manufacturing a semiconductor device substrate according to claim 13, further comprising depositing a nitride semiconductor film on the first single crystal film and the second single crystal film using sputtering.

18. Multiple semiconductor device formation patterns including a group of semiconductor devices are formed in a first direction with a first pitch P １ It has a second pitch P in a second direction perpendicular to the first direction. ２ A method for manufacturing a semiconductor device substrate having, comprising: bonding a first single crystal film peeled from a first single crystal substrate onto a glass substrate; and bonding a second single crystal film peeled from a second single crystal substrate onto the glass substrate adjacent to the first single crystal film in the first direction, wherein the distance d between the first single crystal film and the second single crystal film is Ｆ１２ A method for manufacturing a semiconductor device substrate, wherein the substrates are joined such that they satisfy equation (1). (Here, d ｓ１ and d ｓ２ These are the first and second preset values, respectively, and L １ (where is the length of each of the plurality of semiconductor device formation patterns in the first direction.) 19. Furthermore, the method includes bonding a third single crystal film, peeled from a third single crystal substrate, onto the glass substrate adjacent to the first single crystal film in the second direction, wherein the distance d between the first single crystal film and the third single crystal film is such that the third single crystal film is bonded to the glass substrate, wherein the distance d between the first single crystal film and the third single crystal film is such that the distance d Ｆ１３ A method for manufacturing a semiconductor device substrate according to claim 18, wherein the elements are joined such that they satisfy formula (2). (Here, L ２ (where is the length of each of the plurality of semiconductor device formation patterns in the second direction.) 20. Further, a fourth single-crystal film that is adjacent to the second single-crystal film in the second direction and adjacent to a third single-crystal film in the first direction and is peeled off from a fourth single-crystal substrate is bonded onto the glass substrate, and a distance d between the second single-crystal film and the fourth single-crystal film Ｆ２４ satisfies Expression (3), and a distance d between the third single-crystal film and the fourth single-crystal film Ｆ３４ is bonded so as to satisfy Expression (4). The method of manufacturing a semiconductor device forming substrate according to claim 19 21. Furthermore, the process includes etching the peripheral regions of the first single crystal substrate and the second single crystal substrate, wherein the second set value d ｓ２ The method for manufacturing a semiconductor device substrate according to claim 18, wherein the thickness is 5 μm or more and 10 μm or less.

22. The method for manufacturing a semiconductor device substrate according to claim 18, further comprising depositing a nitride semiconductor film on the first single crystal film and the second single crystal film using sputtering.

23. A semiconductor device manufactured using the method for manufacturing a semiconductor device substrate according to any one of claims 13 to 22.

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