Production method for semiconductor device formation substrate

Abstract

According to the present invention, a production method for a semiconductor device formation substrate involves implanting hydrogen ions from a first surface side of a first single-crystal substrate and forming a first embrittlement layer at the first single-crystal substrate, etching the first single-crystal substrate such that the first surface has a first shape pattern, peeling a first single-crystal film that includes the first surface from the first embrittlement layer, affixing the first single-crystal film at a first position on a glass substrate, and bonding at least a portion of the first single-crystal film.

Description

Manufacturing method for semiconductor substrates

[0001] One embodiment of the present invention relates to a method for manufacturing a semiconductor device substrate for forming a semiconductor device.

[0002] In the manufacturing of semiconductor devices containing single-crystal silicon (e.g., transistors), not only single-crystal silicon substrates but also SOI (Silicon on Insulator) substrates are used. Semiconductor devices manufactured using SOI substrates have improved insulation performance, making them suitable for high-integration semiconductor devices. Specifically, in transistors using SOI substrates, the single-crystal silicon film on the SOI substrate can function as a channel.

[0003] In recent years, the use of semiconductor devices containing nitride semiconductors such as gallium nitride (e.g., light-emitting diodes (LEDs)) has been increasing. Generally, nitride semiconductors are formed using sapphire or silicon carbide substrates, which are smaller and more expensive than single-crystal silicon substrates. To provide inexpensive semiconductor devices, it is effective to mass-produce them using large-area substrates. Therefore, development is underway to manufacture semiconductor devices containing gallium nitride using SOI substrates (see, for example, Patent Document 1). According to Patent Document 1, the single-crystal silicon film on the SOI substrate is used as a buffer layer for growing gallium nitride.

[0004] Thus, single-crystal silicon films on SOI substrates are beginning to be used in many semiconductor devices, as they can function not only as channels but also as buffer layers.

[0005] Special Publication No. 2011-501431

[0006] In the SOI substrate disclosed in Patent Document 1, multiple single-crystal silicon substrates cut to a predetermined size are bonded together, and a single-crystal silicon film is formed even in areas where gallium nitride is not required. Furthermore, seams are formed between adjacent single-crystal silicon films, and the edges of the single-crystal silicon films contain many crystal defects caused by the cutting of the single-crystal silicon substrates. Therefore, even if the distance between adjacent single-crystal silicon films is reduced, it is difficult to form high-quality gallium nitride on or near the seams due to the presence of edges of single-crystal silicon films containing many crystal defects. Such problems are not limited to semiconductor devices containing gallium nitride. In semiconductor devices containing single-crystal silicon, it is also preferable to reduce crystal defects at the edges of the single-crystal silicon film from the viewpoint of high integration.

[0007] One embodiment of the present invention aims to provide a method for manufacturing a semiconductor device substrate having a single crystal film for efficiently forming a semiconductor device, in view of the above-mentioned problems.

[0008] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate, etching the first single crystal substrate so that the first surface has a first shape pattern, peeling off the first single crystal film including the first surface from the first embrittlement layer, bonding the first single crystal film to a first position on a glass substrate, and joining at least a portion of the first single crystal film.

[0009] A method for manufacturing a semiconductor device substrate according to one embodiment of the present invention involves implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate, etching the first single crystal substrate so that the first surface has a first shape pattern, bonding the first single crystal substrate to a first position on a glass substrate, peeling off a first single crystal film including at least a portion of the first surface from the first embrittlement layer, and bonding the first single crystal film onto the glass substrate.

[0010] This is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic plan view illustrating a configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a configuration of a semiconductor device forming substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. This is a schematic cross-sectional viewThis is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention.

[0011] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art could easily conceive by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are naturally included within the scope of the present invention. In order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and drawings, components similar to those described above with respect to previously shown figures are denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0012] In this specification, terms such as "up" and "down" describe the relative positional relationship between the structure of interest and other structures. However, for the sake of explanation, the up-down relationship may be reversed in some cases compared to the diagram. "Plan view" refers to viewing the surface of the single-crystal substrate or glass substrate, as described later, from a direction perpendicular to it.

[0013] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A through C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] In this specification, the words "first," "second," or "third" attached to each component are merely convenient indicators used to distinguish each component, and unless otherwise specified, they have no further meaning.

[0015] In this specification, the terms "membrane" and "layer" may be interchangeable as appropriate.

[0016] In this specification, "semiconductor device forming substrate" refers to a semiconductor device or a large-area substrate (e.g., a glass substrate) on which multiple single-crystal films are formed, which is used in the manufacture of a semiconductor device. A "semiconductor device forming substrate" can also be a support substrate for forming a semiconductor device. In the manufacturing method of a semiconductor device, in order to improve the manufacturing efficiency of the semiconductor device, there is a method in which multiple semiconductor devices are manufactured using a large-area substrate, and then the large-area substrate is divided to obtain individual semiconductor devices. Alternatively, multiple semiconductor devices may be formed on the large-area substrate using, for example, photolithography. In this case, it is desirable that the regions on which multiple semiconductor devices are formed are arranged at regular intervals on the large-area substrate. That is, it is desirable that the multiple semiconductor devices on the large-area substrate be arranged at a predetermined pitch. The single-crystal films on the large-area substrate may function as part of the semiconductor device, or they may be used in the process of manufacturing the semiconductor device.

[0017] In this specification, "nitride semiconductor" refers to a compound containing one or more Group 13 elements and nitrogen, and having semiconductor properties. Examples of nitride semiconductors include, but are not limited to, gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).

[0018] In this specification, "semiconductor device" means, for example, a transistor or a light-emitting diode, but is not limited to these.

[0019] <First Embodiment> [1. Method for Manufacturing a Semiconductor Device Forming Substrate] Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. Figures 2 to 9 are schematic cross-sectional or plan views illustrating a method for manufacturing a semiconductor device forming substrate according to one embodiment of the present invention. As shown in Figure 1, the method for manufacturing a semiconductor device forming substrate includes steps S110 to S150. Hereinafter, the steps of the flowchart in Figure 1 will be described in order, with appropriate reference to Figures 2 to 9.

[0020] In step S110, ions are implanted from the surface 101 side of the single crystal substrate 100 (see Figure 2). The ions are implanted into the single crystal substrate 100 using ion implantation or ion doping. The implanted ions are hydrogen ions (H ＋ , H ２ ＋ , or H ３ ＋ ) is preferable, but not limited to this. An embrittlement layer 110 is formed in the single crystal substrate 100 by ion implantation. The embrittlement layer 110 has its bonds broken by the implanted ions, making it brittle and easily peeled off compared to other regions. The position of the embrittlement layer 110 in the thickness direction of the single crystal substrate 100 (distance from the surface 101) can be adjusted by the ion implantation conditions (e.g., acceleration voltage or dose amount). For example, the position of the embrittlement layer 110 is 25 nm to 150 nm from the surface 101, preferably 50 nm to 100 nm.

[0021] The single crystal substrate 100 is, for example, a single crystal silicon substrate, but is not limited thereto. The single crystal substrate 100 may be a substrate containing a nitride semiconductor such as gallium nitride, or it may be an aluminum oxide substrate or a zinc oxide substrate. Furthermore, it is preferable that the surface 101 of the single crystal substrate 100 has high smoothness.

[0022] In step S120, a resist 300 having a predetermined shape pattern is formed on the surface 101 of the single crystal substrate 100 using photolithography (see Figure 3). Figure 3 shows a resist 300 in which multiple structures are separated with gaps between them, but the resist 300 has a shape pattern in which multiple linear patterns are connected at both ends, as shown in Figure 4. In other words, the resist 300 is a single film with multiple openings. The planar shape of the multiple openings is linear, but is not limited to this. The planar shape of the multiple openings may be circular, elliptical, polygonal, or a shape in which these are combined. As described above, the resist 300 only needs to be a single film, and may have a shape pattern with notches or irregularities on its outer periphery. For example, as shown in Figure 5, the resist 300 may have a shape pattern in which two adjacent island-like patterns of multiple island-like patterns are connected. Also, when the single crystal substrate 100 is circular, the outer shape of the shape pattern of the resist 300 may be rectangular (see Figure 4). The shape pattern of the resist 300 is determined according to the arrangement pattern of the semiconductor device formed using the semiconductor device substrate.

[0023] Figure 4 shows a resist 300 having a rectangular shape with multiple openings inside, but the resist 300 may also have a rectangular shape without multiple openings inside (see Figure 6).

[0024] In this embodiment, the single crystal substrate 100 is not cut. Therefore, no crystal defects caused by cutting are generated in the single crystal substrate 100.

[0025] In step S130, the single crystal substrate 100 is etched using the resist 300 as a mask (see Figure 7). As a result, a portion of the surface 101 exposed from the resist 300 is removed, and grooves are formed on the single crystal substrate 100 corresponding to the openings in the shape pattern of the resist 300, and steps are formed corresponding to the outer shape of the shape pattern of the resist 300. That is, a shape pattern similar to that of the resist 300 is formed on the surface 101 of the single crystal substrate 100. In etching the single crystal substrate 100, it is preferable that the embrittlement layer 110 is removed in the grooves and steps. After the single crystal substrate 100 is etched, the resist 300 is removed.

[0026] In step S140, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 8). The single crystal film 120 is a part of the single crystal substrate 100 that has been separated from the embrittlement layer 110. The method for peeling off the single crystal film 120 is not particularly limited. In the embrittlement layer 110, many minute pores or grooves (hereinafter referred to as "microvoids" for convenience of explanation) are generated due to the breaking of bonds. When the single crystal substrate 100 is heated, the volume of microvoids in the embrittlement layer 110 expands, and separation occurs along the embrittlement layer 110. Therefore, by pulling the surface 101 while heating the single crystal substrate 100, the single crystal film 120 can be peeled off from the single crystal substrate 100. The heating temperature of the single crystal substrate 100 is, for example, 300°C to 700°C, preferably 400°C to 600°C.

[0027] As described above, since the single crystal substrate 100 is not cut, the single crystal film 120 does not contain crystal defects caused by cutting. Furthermore, since the outer shape of the single crystal film 120 is formed by etching, the edges of the single crystal film 120 also do not contain crystal defects and have high crystallinity. In addition, the single crystal film 120 has a shape pattern that includes openings. In order to improve the utilization efficiency of the single crystal film 120, it is preferable that the width of the openings included in the shape pattern is small. Specifically, it is preferable that the width of the openings is smaller than the width of two adjacent linear patterns (see Figure 4) or island-shaped patterns (see Figure 5).

[0028] In step S150, the large-area substrate 200 and the single-crystal film 120 are bonded together (see FIG. 9). Specifically, the single-crystal film 120 is placed on the large-area substrate 200 such that the release surface 102 on the side opposite to the surface 101 faces the surface of the large-area substrate 200. Thereby, the large-area substrate 200 and the single-crystal film 120 are bonded to some extent. However, in order to improve the bonding strength, it is preferable to perform a heat treatment after the large-area substrate 200 and the single-crystal film 120 are bonded together. Further, so-called anodic bonding may be performed in which a voltage is applied while performing the heat treatment.

[0029] The large-area substrate 200 is, for example, a glass substrate. The glass substrate is generally amorphous having no crystal structure, but a crystal structure may exist in a minute region. The upper limit of the thermal expansion coefficient of the glass substrate is less than 4.2×10 －６ / K, preferably less than 4.0×10 －６ / K. The lower limit of the thermal expansion coefficient of the glass substrate exceeds 3.0×10 －６ / K, preferably exceeds 3.5×10 －６ / K. Although details will be described later, a semiconductor device manufactured using a semiconductor device forming substrate is manufactured at a temperature less than 650°C. Therefore, the glass substrate preferably has heat resistance at least at a temperature of 650°C. The lower limit of the glass transition point of the glass substrate is 650°C or higher, preferably 720°C or higher. Also, the upper limit of the glass transition point of the glass substrate is 900°C or lower, preferably 810°C or lower. For the same reason, the lower limit of the softening point of the glass substrate is 900°C or higher, preferably 950°C or higher. Also, the upper limit of the softening point of the glass substrate is 1150°C or lower, preferably 1050°C or lower.

[0030] Note that the large-area substrate 200 is not limited to a glass substrate. The large-area substrate 200 may be a quartz substrate. The large-area substrate 200 may be any substrate larger than the single-crystal substrate 100.

[0031] As described above, when steps S100 to S150 are executed, one single crystal film 120 having a shape pattern in which a plurality of linear patterns or a plurality of island patterns are connected on the large area substrate 200 or one single crystal film 120 having a shape pattern in which a plurality of openings are not provided inside is joined. In the present embodiment, by repeatedly executing steps S100 to S150, a semiconductor device forming substrate on which a plurality of single crystal films 120 are joined can be manufactured on the large area substrate 200.

[0032] In addition, when the single crystal film 120 has a shape pattern in which a plurality of linear patterns or a plurality of island patterns are connected, the connection region connecting the plurality of linear patterns or the plurality of island patterns may be removed. For example, the connection region can be removed using photolithography or a laser.

[0033] Also, in steps S140 and S150, the single crystal film 120 can be peeled off and joined using a transfer substrate. Specifically, the single crystal substrate 100 and the transfer substrate are bonded together, the single crystal film 120 is peeled off from the single crystal substrate 100, and then the single crystal film 120 can be joined to the large area substrate 200 by bonding the large area substrate 200 and the transfer substrate together. In this case, since the single crystal film 120 having the pattern shape peeled off from the single crystal substrate 100 is temporarily joined to the transfer substrate, it is also possible that the single crystal film 120 to be peeled off has a shape pattern in which a plurality of linear patterns or a plurality of island patterns are separated from each other. Since the step of removing the connection region is not required, the manufacturing tact of the semiconductor device forming substrate can be shortened, and the semiconductor device forming substrate can be manufactured at a low cost.

[0034] [2. Configuration of semiconductor device forming substrate 10] FIG. 10 is a schematic plan view showing the configuration of a semiconductor device forming substrate 10 according to an embodiment of the present invention.

[0035] Figure 10 shows a semiconductor device forming substrate 10 on a large-area substrate 200, on which nine single-crystal films 120 of the same size are arranged. A seam is formed between two adjacent single-crystal films 120. Since the edges of the single-crystal films 120 have high crystallinity, in the semiconductor device forming substrate 10, a high-quality nitride semiconductor can be formed on the edges of the single-crystal films 120, or the edges of the single-crystal films 120 can be used as channels. In other words, the semiconductor device forming substrate 10 can reduce the seam between adjacent 120s and include a large area for forming the semiconductor device.

[0036] Furthermore, the single crystal film 120 of the semiconductor device substrate 10 shown in Figure 10 has a shape pattern that includes openings. In this case, the width of the seam can be adjusted to match the width of the opening. That is, the width of the seam can be made approximately the same as the width of the opening. As a result, a semiconductor device can be formed on the semiconductor device substrate 10 using the single crystal film 120 without relying on the seams.

[0037] The single crystal films 120 placed on the large-area substrate 200 may have different shape patterns. Here, different shape patterns include not only those with different outer shapes or aperture shapes, but also those with different outer shapes or aperture sizes. For example, multiple single crystal films 120 with different outer shapes and sizes may be placed on the large-area substrate 200. Figure 11 is a schematic plan view showing the configuration of a semiconductor device forming substrate 10A according to one embodiment of the present invention.

[0038] Figure 11 shows a semiconductor device forming substrate 10A on a large-area substrate 200A, on which single crystal films 120A-1, 120A-2, and 120A-3 (hereinafter, when not specifically distinguished, they may be described as single crystal film 120A) with different shape patterns are arranged. In this embodiment, single crystal films 120A-1, 120A-2, and 120A-3 with different external dimensions can be arranged according to the shape of the large-area substrate 200A. By making the seams between adjacent 120A films small, the semiconductor device forming substrate 10A can include a large area for forming the semiconductor device.

[0039] Note that the semiconductor device substrate 10 shown in Figure 10 or the semiconductor device substrate 10A shown in Figure 11 are just examples of semiconductor device substrates. In other words, the semiconductor device substrate manufactured by the semiconductor device substrate manufacturing method described in this embodiment is not limited to the semiconductor device substrate 10 or the semiconductor device substrate 10A.

[0040] [3. Configuration of Semiconductor Device 20] Figure 11 is a schematic cross-sectional view showing the configuration of a semiconductor device 20 manufactured using a semiconductor device forming substrate 10 according to one embodiment of the present invention. The semiconductor device 20 is a so-called blue light-emitting diode. The semiconductor device 20 is an example of a semiconductor device manufactured using a single crystal film 120 of the semiconductor device forming substrate 10.

[0041] As shown in Figure 11, the semiconductor device 20 includes a large-area substrate 200, a single-crystal film 120, an undoped semiconductor layer 210, an n-type semiconductor layer 220, an emissive layer 230, a p-type semiconductor layer 240, a p-type electrode 250, and an n-type electrode 260. The undoped semiconductor layer 210 is provided on the single-crystal film 120. The n-type semiconductor layer 220 is provided on the undoped semiconductor layer 210. The emissive layer 230 is provided on the n-type semiconductor layer 220. The p-type semiconductor layer 240 is provided on the emissive layer 230. The p-type electrode 250 is provided on the p-type semiconductor layer 240 and is electrically connected to the p-type semiconductor layer 240. The n-type electrode 260 is provided on the n-type semiconductor layer 220 exposed from the emissive layer 230 and the p-type semiconductor layer 240 (in other words, within the recess of the n-type semiconductor layer 220) and is electrically connected to the n-type semiconductor layer 220.

[0042] Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 contains a nitride semiconductor. Each of the undoped semiconductor layer 210, the n-type semiconductor layer 220, the light-emitting layer 230, and the p-type semiconductor layer 240 can be deposited using sputtering.

[0043] Here, we will describe nitride semiconductors deposited using sputtering. The single crystal film 120 functions as a buffer layer for the nitride semiconductor being deposited, improving the crystallinity of the nitride semiconductor. Nitride semiconductors with a hexagonal close-packed structure grow in the c-axis direction to minimize surface energy, but deposition on the single crystal film 120 promotes crystal growth of the nitride semiconductor in the c-axis direction. Therefore, the nitride semiconductor deposited on the single crystal film 120 has a highly crystalline c-axis orientation. The materials of the single crystal substrate 100 described above, silicon, aluminum oxide, and zinc oxide, can function as buffer layers for nitride semiconductors.

[0044] The undoped semiconductor layer 210 has insulating properties and can electrically insulate the single crystal film 120. Furthermore, the undoped semiconductor layer 210 can also function as a buffer layer to adjust the lattice matching of the nitride semiconductor. In this embodiment, it is also possible to apply a configuration without the undoped semiconductor layer 210. For example, if the material of the single crystal film 120 is gallium nitride, the undoped semiconductor layer 210 may not be necessary.

[0045] The n-type semiconductor layer 220 has electron conductivity and can transport electrons supplied from the n-type electrode 260 to the light-emitting layer 230. The n-type semiconductor layer 220 includes a nitride semiconductor doped with impurities such as silicon (Si) or germanium (Ge) (hereinafter referred to as "n-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the n-type semiconductor layer 220 of the blue light-emitting diode.

[0046] The light-emitting layer 230 can emit light when electrons transported from the n-type semiconductor layer 220 and holes transported from the p-type semiconductor layer 240 are recombined. The blue light-emitting diode includes a light-emitting layer 230 (blue light-emitting layer) that emits blue light. The light-emitting layer 230 of the blue light-emitting diode has a multiple quantum well (MQW) structure in which gallium nitride (GaN) and indium gallium nitride (InGaN) are alternately stacked.

[0047] The p-type semiconductor layer 240 has hole conductivity and can transport positive charge supplied from the p-type electrode 250 to the light-emitting layer 230. The p-type semiconductor layer 240 includes a nitride semiconductor doped with impurities such as magnesium (Mg) (hereinafter referred to as "p-type impurities"). Nitride semiconductors such as gallium nitride (GaN) or aluminum gallium nitride (AlGaN) can be used as the p-type semiconductor layer 240 of a blue light-emitting diode.

[0048] The p-type electrode 250 is electrically connected to the electrode of the pixel circuit (not shown) and can supply holes to the p-type semiconductor layer 240. As the p-type electrode 250, a metal such as palladium (Pd) or gold (Au) can be used.

[0049] The n-type electrode 260 is electrically connected to the electrode of the pixel circuit (not shown) and can supply electrons to the n-type semiconductor layer 220. For example, a metal such as indium (In) can be used as the n-type electrode 260.

[0050] The structure of the light-emitting diode as a component of the semiconductor device 20 has been described above with reference to Figure 12. However, the structure of the light-emitting diode shown in Figure 12 is just one example, and the structure of the light-emitting diode is not limited to this. The light-emitting diode shown in Figure 12 has a so-called horizontal electrode structure in which the p-type electrode 250 and the n-type electrode 260 do not overlap in the thickness direction. However, the semiconductor device 20 may also have a so-called vertical electrode structure in which the p-type electrode and the n-type electrode overlap with a light-emitting layer in between in the thickness direction.

[0051] The semiconductor device 20 utilizes the single-crystal film 120 of the semiconductor device substrate 10. More specifically, the nitride semiconductor of the semiconductor device 20 is deposited on the single-crystal film 120 using sputtering. Therefore, since the semiconductor device 20 can be manufactured using a large-area substrate 200, manufacturing costs can be reduced.

[0052] The nitride semiconductor layer included in the semiconductor device 20 can be formed on a large-area substrate 200 using sputtering. Therefore, the semiconductor device substrate 10 may include not only the single crystal film 120, but also the nitride semiconductor layer formed on the single crystal film 120.

[0053] The above describes a semiconductor device 20 in which the single crystal film 120 is used as a buffer layer for a nitride semiconductor layer. However, semiconductor devices manufactured using the semiconductor device forming substrate 10 are not limited to this. The semiconductor device may also be a transistor that uses the single crystal film 120 of the semiconductor device forming substrate 10 as a channel. For example, if the single crystal film 120 is a single crystal silicon film, a transistor that uses the single crystal silicon film as a channel can be manufactured using the semiconductor device forming substrate 10.

[0054] In this embodiment, the edges of the single crystal substrate 100 are etched so that the single crystal film 120 has a predetermined shape pattern, but the substrate is not cut. Therefore, the edges of the single crystal film 120 have high crystallinity not only in the center but also in the edges, and the edges of the single crystal film 120 can also be used to form a semiconductor device. In other words, in the semiconductor device forming substrate 10 manufactured according to this embodiment, the single crystal film 120 can be used efficiently to form a semiconductor device. Furthermore, since the single crystal film 120 has a shape pattern corresponding to the arrangement pattern of the semiconductor device to be formed, a semiconductor device can be formed only in the necessary area. Therefore, in the semiconductor device forming substrate 10 manufactured according to this embodiment, a semiconductor device can be formed efficiently.

[0055] <Modification 1 of the First Embodiment> Referring to Figures 13 to 16, a method for manufacturing a semiconductor device substrate, which is a modification of the first embodiment, will be described. Hereinafter, when the configuration of this modification is the same as that of the first embodiment, the description of the configuration of this modification may be omitted.

[0056] Figure 13 is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Figures 14 to 16 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. As shown in Figure 13, the method for manufacturing a semiconductor device substrate includes steps S151 and S152 instead of step S150 shown in the flowchart of Figure 1. Steps S151 and S152 will be described in order below, with appropriate reference to Figures 14 to 16.

[0057] In step S151, the large-area substrate 200 and the single-crystal film 120 are bonded together at a first position L1 (or first region) (see Figure 14). In this modified example, the surface of the large-area substrate 200 has a shape pattern. The shape pattern on the surface of the large-area substrate 200 is provided in correspondence with the arrangement pattern of the semiconductor device to be formed. Details are omitted, but the shape pattern on the surface of the large-area substrate 200 can be formed using photolithography.

[0058] To further describe the shape pattern of the surface of the large-area substrate 200, recesses and protrusions are alternately formed on the surface of the large-area substrate 200. The pitch of the protrusions on the large-area substrate 200 is greater than the pitch of the film portion (for example, a linear pattern or an island pattern) of the single-crystal film 120. For example, the pitch of the protrusions on the large-area substrate 200 is twice the pitch of the film portion of the single-crystal film 120. In this case, when the single-crystal film 120 is bonded to the large-area substrate 200, a portion of the single-crystal film 120 (hereinafter, for convenience of explanation, referred to as "first single-crystal film 120_1") comes into contact with the protrusions, while the remaining portion of the single-crystal film 120 is positioned on the recesses without coming into contact. At this time, the single-crystal film 120 may be pressed. When the single crystal film 120 is pressed, the contact between the protrusions of the large-area substrate 200 and the first single crystal film 120_1 becomes strong, and the protrusions of the large-area substrate 200 and the first single crystal film 120_1 are joined together. Furthermore, the single crystal film 120 may be subjected to single crystal film heat treatment. In addition, anodic bonding may be performed.

[0059] Subsequently, the single crystal film 120 is separated from the large-area substrate 200 (Figure 15). As a result, the first single crystal film 120_1 is bonded to the first position L1 on the surface of the large-area substrate 200. On the other hand, a portion of the remaining single crystal film 120 (hereinafter referred to as the "second single crystal film 120-2" for the sake of explanation) is not bonded.

[0060] Furthermore, it is preferable that the pitch of the protrusions on the large-area substrate 200 be a natural number multiple of the pitch of the film portion of the single-crystal film 120.

[0061] In step S152, the large-area substrate 200 and the single-crystal substrate 100 are bonded together at the second position L2 (second region) (see Figure 16). The second position L2 is adjacent to, but not limited to, the first position L1. As a result, the second single-crystal film 120-2 comes into contact with the protrusions of the large-area substrate 200 and is bonded. In step S152, the single-crystal film 120 may also be pressed, or heat treatment may be performed on the single-crystal film 120. Anode bonding may also be performed.

[0062] In the above description, two bonding and joining steps were performed using one single crystal film 120, but multiple bonding and joining steps may also be performed.

[0063] Furthermore, while the above description explained a configuration in which bonding and joining are performed twice at different locations within the same large-area substrate 200, this modified example also allows for a configuration in which bonding and joining are performed multiple times on multiple different large-area substrates 200.

[0064] In this modified example, a shape pattern including protrusions is formed on the surface of the large-area substrate 200. The single crystal film 120 is bonded to the protrusions of the large-area substrate 200. Therefore, by repeating bonding and joining using one single crystal film 120 as one cycle, the single crystal film 120 can be provided in a region larger than the single crystal film 120 so as to correspond to the arrangement pattern of the semiconductor device. Consequently, since semiconductor devices can be formed only in the necessary regions, semiconductor devices can be efficiently formed on the semiconductor device substrate manufactured by this modified example.

[0065] <Modification 2> Referring to Figure 17, a further modification of the first embodiment, a method for manufacturing a semiconductor device substrate, will be described. In the following, when the configuration of this modification is the same as that of the first embodiment, the description of the configuration of this modification may be omitted.

[0066] Figure 17 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Specifically, Figure 17 is a schematic cross-sectional view illustrating step S150 of the flowchart in Figure 1.

[0067] As shown in Figure 17, an interface control layer 205 is provided on the surface of the large-area substrate 200. The single crystal film 120 is bonded to the interface control layer 205 on the large-area substrate 200.

[0068] The interface control layer 205 improves the bonding strength when bonding the large-area substrate 200 and the single-crystal film 120. For example, the interface control layer 205 can prevent the diffusion of impurities contained in the large-area substrate 200 and improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. In addition, the interface control layer 205 has more hydrophilicity than the surface of the large-area substrate 200 and can improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. For example, silicon oxide (SiO₂) can be used as the interface control layer. ｘ ), silicon oxide nitride (SiO ｘ N ｙ ), silicon nitride (SiN ｘ ), silicon nitride (SiN ｘ O ｙ ), aluminum oxide (AlO ｘ ), aluminum oxide nitride (AlO ｘ N ｙ ), aluminum nitride (AlN ｘ O ｙ ), or aluminum nitride (AlN ｘ ) and the like are used. Here, silicon oxide nitride (SiO ｘ N ｙ ) and aluminum oxide nitride (AlO ｘ N ｙSilicon nitride (SiN) is a silicon compound and an aluminum compound that contains nitrogen (N) in a smaller proportion (x > y) than oxygen (O). ｘ O ｙ ) and aluminum nitride (AlN ｘ O ｙ These are silicon compounds and aluminum compounds that contain oxygen (O) in a smaller proportion (x > y) than nitrogen (N).

[0069] When the large-area substrate 200 is a glass substrate, it is preferable to use silicon oxide, silicon oxynitride, aluminum oxide, or aluminum oxynitride as the interface control layer 205. These materials can particularly improve the bonding strength when bonding with a single-crystal silicon substrate.

[0070] In Modification 1, a shape pattern was formed on the surface of the large-area substrate 200, but in this modification, a shape pattern can be formed on the interface control layer 205 using photolithography.

[0071] According to this modified example, the interface control layer 205 can improve the bonding strength between the large-area substrate 200 and the single-crystal film 120. Furthermore, semiconductor devices can be efficiently formed on the semiconductor device substrate manufactured by this modified example.

[0072] <Second Embodiment> A method for manufacturing a semiconductor device substrate, different from the first embodiment, will be described with reference to Figures 18 to 20. In the following, when the configuration of this embodiment is the same as that of the first embodiment, the description of the configuration of this embodiment may be omitted.

[0073] Figure 18 is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Figures 19 and 20 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. As shown in Figure 18, the method for manufacturing a semiconductor device substrate includes steps S210 to S250. Hereinafter, the steps of the flowchart in Figure 18 will be described in order, with appropriate reference to Figures 19 and 20.

[0074] Steps S210 to S230 are the same as steps S110 to S130, so the explanation of steps S210 to S230 will be omitted.

[0075] In step S240, the large-area substrate 200 and the single-crystal substrate 100 are bonded together (see Figure 19). Specifically, the single-crystal substrate 100 is placed on the large-area substrate 200 such that its surface 101 faces the surface of the large-area substrate 200. This bonds the large-area substrate 200 and the single-crystal substrate 100 to a certain extent. In other words, the large-area substrate 200 and the single-crystal substrate 100 are temporarily bonded together.

[0076] In step S250, the single crystal film 120, including the surface 101, is peeled off the single crystal substrate 100 (see Figure 20). When the single crystal substrate 100 is heated, the large-area substrate 200 and the single crystal substrate 100 (more specifically, the surface 101 of the single crystal substrate 100) are firmly bonded together. Also, heating the single crystal substrate 100 causes the volume of microvoids in the embrittlement layer 110 to expand, resulting in separation along the embrittlement layer 110. As described above, the surface 101 of the single crystal substrate 100 remains intact because it is bonded to the large-area substrate 200. That is, the single crystal film 120, including the surface 101 of the single crystal substrate 100, is formed on the large-area substrate 200. As a result, a semiconductor device substrate is manufactured in which the single crystal film 120 is bonded to the large-area substrate 200. In this embodiment, the peeled surface 102 of the single crystal film 120 is exposed, so each layer of the semiconductor device is formed on the peeled surface 102.

[0077] According to this embodiment, since a single crystal film 120 having a shape pattern corresponding to the arrangement pattern of the semiconductor device to be formed is provided, a semiconductor device can be formed only in the necessary area. Therefore, a semiconductor device can be efficiently formed on a semiconductor device substrate manufactured according to this embodiment.

[0078] <Modification of the Second Embodiment> Referring to Figures 21 to 25, a method for manufacturing a semiconductor device substrate, which is a modification of the second embodiment, will be described. Hereinafter, when the configuration of this modification is the same as that of the second embodiment, the description of the configuration of this modification may be omitted.

[0079] Figure 21 is a flowchart illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. Figures 22 to 25 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device substrate according to one embodiment of the present invention. As shown in Figure 21, the method for manufacturing a semiconductor device substrate includes steps S241, S251, S242, and S252 instead of steps S240 and S250 shown in the flowchart of Figure 18. Hereinafter, steps S241, S251, S242, and S252 will be described in order with appropriate reference to Figures 22 to 25.

[0080] In step S241, the large-area substrate 200, which has protrusions and recesses on its surface, is bonded to the single-crystal substrate 100 at a first position L1 (see Figure 22). As a result, a portion of the surface 101 of the single-crystal substrate 100 comes into contact with the protrusions, while the remaining portion of the surface 101 of the single-crystal substrate 100 is positioned on top of the recesses without coming into contact with them.

[0081] In step S251, the single crystal film 120, including a portion of the surface 101, is peeled off from the single crystal substrate 100 (see Figure 23). As a result, a first single crystal film 120_1, including a portion of the surface 101 of the single crystal substrate 100, is formed on the large-area substrate 200. That is, the first single crystal film 120_1 is bonded to a first position L1 on the single crystal substrate 100.

[0082] In step S242, the large-area substrate 200 and the single-crystal film 120 are bonded together at the second position L2 of the large-area substrate 200 (see Figure 24). As a result, the remaining portion of the single-crystal film 120 comes into contact with the protrusion.

[0083] In step S252, the single crystal film 120, including the remaining portion of the surface 101, is peeled off from the single crystal substrate 100 (see Figure 25). As a result, a second single crystal film 120-2, including the remaining portion of the surface 101 of the single crystal substrate 100, is formed on the large-area substrate 200. That is, the second single crystal film 120-2 is bonded to the second position L2 of the single crystal substrate 100.

[0084] According to this modified example, a shape pattern including protrusions is formed on the surface of the large-area substrate 200. Furthermore, the single-crystal film 120 is bonded to the protrusions of the large-area substrate 200. Therefore, by repeating bonding, peeling, and bonding using one single-crystal substrate 100 as one cycle, the single-crystal film 120 can be provided in a region larger than the single-crystal film 120 so as to correspond to the arrangement pattern of the semiconductor device. Consequently, since semiconductor devices can be formed only in the necessary regions, semiconductor devices can be efficiently formed on the semiconductor device substrate manufactured by this modified example.

[0085] The embodiments and modifications described above as embodiments of the present invention can be combined as appropriate, insofar as they do not contradict each other. Furthermore, any additions, deletions, or design changes to components, or additions, omissions, or changes to processes based on the embodiments, made by those skilled in the art, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0086] Any effects or benefits other than those brought about by the embodiments and modifications described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0087] 10, 10A: Semiconductor device substrate 20: Semiconductor device 100: Single crystal substrate 101: Surface 102: Delamination surface 110: Embrittlement layer 120, 120A, 120A-1, 120A-2, 120A-3: Single crystal film 120_1: First single crystal film 120_2: Second single crystal film 200, 200A: Large area substrate 205: Interface control layer 210: Undoped semiconductor layer 220: n-type semiconductor layer 230: Light-emitting layer 240: p-type semiconductor layer 250: p-type electrode 260: n-type electrode 300: Resist

Claims

1. A method for manufacturing a semiconductor device substrate, comprising: implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate; etching the first single crystal substrate so that the first surface has a first shape pattern; peeling off a first single crystal film including the first surface from the first embrittlement layer; bonding the first single crystal film to a first position on a glass substrate and joining at least a portion of the first single crystal film.

2. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising depositing a gallium nitride film on the first single crystal film using sputtering.

3. The method for manufacturing a semiconductor device substrate according to claim 1, wherein the first single crystal film contains silicon.

4. The method for manufacturing a semiconductor device substrate according to claim 1, wherein the peeled surface of the first single crystal film is bonded onto the glass substrate.

5. The method for manufacturing a semiconductor device substrate according to claim 1, wherein a predetermined shape pattern is formed on the surface of the glass substrate to which the first single crystal film is bonded.

6. The method for manufacturing a semiconductor device substrate according to claim 1, wherein the first single crystal substrate is etched so that the outer shape of the first shape pattern becomes rectangular.

7. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising bonding the first single crystal film to a second position on the glass substrate and joining the remaining portion of the first single crystal film.

8. The method for manufacturing a semiconductor device substrate according to claim 1, further comprising: implanting hydrogen ions from the second surface side of the second single crystal substrate to form a second embrittlement layer in the second single crystal substrate; etching the second single crystal substrate so that the second surface has a second shape pattern; peeling off the second single crystal film including the second surface from the second embrittlement layer; bonding the second single crystal film adjacent to at least a portion of the first single crystal film on the glass substrate, thereby joining at least a portion of the second single crystal film.

9. A method for manufacturing a semiconductor device substrate, comprising: implanting hydrogen ions from the first surface side of a first single crystal substrate to form a first embrittlement layer in the first single crystal substrate; etching the first single crystal substrate so that the first surface has a first shape pattern; bonding the first single crystal substrate to a first position on a glass substrate; peeling off a first single crystal film including at least a portion of the first surface from the first embrittlement layer; and bonding the first single crystal film onto the glass substrate.

10. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising depositing a gallium nitride film on the first single crystal film using sputtering.

11. The method for manufacturing a semiconductor device substrate according to claim 9, wherein the first single crystal film contains silicon.

12. The method for manufacturing a semiconductor device substrate according to claim 9, wherein a predetermined shape pattern is formed on the surface of the glass substrate to which the first single crystal film is bonded.

13. The method for manufacturing a semiconductor device substrate according to claim 9, wherein the first single crystal substrate is etched so that the outer shape of the first shape pattern becomes rectangular.

14. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising bonding the first single crystal substrate to a second position on the glass substrate, peeling off the second single crystal film including the remaining portion of the first surface from the first embrittlement layer, and bonding the second single crystal film onto the glass substrate.

15. The method for manufacturing a semiconductor device substrate according to claim 9, further comprising: implanting hydrogen ions from the second surface side of the second single crystal substrate to form a second embrittlement layer in the second single crystal substrate; etching the second single crystal substrate so that the second surface has a second shape pattern; bonding the second single crystal substrate adjacent to the first single crystal film on the glass substrate; peeling off a third single crystal film including at least a portion of the second surface from the second embrittlement layer; and bonding the third single crystal film onto the glass substrate.

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