Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a semiconductor layer; and an external electrode layer laminated on the semiconductor layer with an insulating layer interposed therebetween, the external electrode layer having a plurality of external electrodes for performing electrical connection with an external device, and an organic insulating film that covers the lateral periphery of the external electrodes. An inorganic material is exposed on at least a portion of a side surface of the external electrode layer.

Description

Semiconductor device, method of manufacturing semiconductor device

[0001] The present technology relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device having a WL-CSP structure and a method of manufacturing the same.

[0002] A semiconductor device having a WL-CSP (Wafer Level Chip Scale Package) structure is known. WL-CSP means a semiconductor package manufactured by subjecting a semiconductor wafer on which circuits have been formed to packaging processes and finally separating the wafer into individual packages.

[0003] Regarding a semiconductor device having a WL-CSP structure, singulation is performed by fixing a semiconductor wafer on a pedestal with a dicing tape and then cutting a dicing area in the wafer with a dicing blade.

[0004] Note that the following Patent Document 1 can be cited as a related prior art. Patent Document 1 discloses a technique related to a semiconductor device in which a plurality of semiconductor chip regions are formed on a semiconductor wafer and the wafer is diced along a scribe line region between the semiconductor chip regions, and a chipping prevention portion is provided at a portion on the semiconductor chip region side of each scribe line region.

[0005] Japanese Patent Application Laid-Open No. 9-306872

[0006] However, when dicing is performed by fixing the wafer with a dicing tape as described above, there is a risk that dicing tape debris will dust and adhere to the cut surface (a surface along the thickness direction: side surface) of the singulated semiconductor device.

[0007] The present technology has been made in view of the above circumstances, and an object thereof is to suppress a decrease in the yield of a semiconductor device due to dust adhesion by preventing dicing tape debris from adhering to the semiconductor device as dust.

[0008] The semiconductor device according to this technology comprises a semiconductor layer and an external electrode layer, which is a layer laminated to the semiconductor layer via an insulating layer and has a plurality of external electrodes for making an electrical connection with an external device, and an organic insulating film covering the sides of the external electrodes, wherein an inorganic material is exposed on at least a portion of the side surface of the external electrode layer. As described above, if an inorganic material is exposed on at least a portion of the side surface of the external electrode layer, then during the dicing process in manufacturing, the inorganic material will be present on at least a portion of the cut surface of the external electrode layer. Since dicing tape debris is less likely to adhere to inorganic materials compared to organic insulating films, the presence of inorganic material on at least a portion of the cut surface makes it possible to suppress the adhesion of dicing tape debris to the cut surface more effectively than when the entire cut surface is made of an organic insulating film.

[0009] A method for manufacturing a semiconductor device according to this technology comprises a semiconductor layer and an external electrode layer, which is a layer laminated to the semiconductor layer via an insulating layer and has a plurality of external electrodes for making an electrical connection with an external device and an organic insulating film covering the sides of the external electrodes, and comprises at least an inorganic material forming step of forming an inorganic material on a semiconductor wafer before the semiconductor device is separated into individual pieces, such that the inorganic material is exposed on at least a part of the side surface of the external electrode layer in the semiconductor device after separation, and a dicing step of dicing the semiconductor wafer on which the inorganic material has been formed. By such a manufacturing method, it is possible to manufacture the semiconductor device according to this technology described above.

[0010] This is a schematic longitudinal cross-sectional view of a conventional semiconductor device. This is a schematic bottom view of a conventional semiconductor device. This is a schematic longitudinal cross-sectional view of a conventional semiconductor wafer. This is a diagram illustrating the problems of a conventional semiconductor device. This is an explanatory diagram of a first countermeasure that can be taken to resolve the problems of the conventional device. This is an explanatory diagram of a second countermeasure that can be taken to resolve the problems of the conventional device. This is a schematic longitudinal cross-sectional view of a semiconductor wafer as a first embodiment. This is an explanatory diagram of the state when a semiconductor wafer is diced as a first embodiment. This is a schematic longitudinal cross-sectional view of a semiconductor device as a first embodiment. This is a schematic bottom view of a semiconductor device as a first embodiment. This is a diagram illustrating an example of a manufacturing method for a semiconductor device as a first embodiment. This is a diagram illustrating an example of a manufacturing method for a semiconductor device as a first embodiment, together with Figure 11. This is a schematic longitudinal cross-sectional view of a semiconductor device as a modified example of the first embodiment. This is a diagram illustrating an example of a manufacturing method for a semiconductor device as a modified example of the first embodiment. This is a schematic longitudinal cross-sectional view of a semiconductor wafer as another modified example of the first embodiment. This is a schematic bottom view of a semiconductor wafer as a prior example assumed in the second embodiment. This is a cross-sectional view showing the cross-section when a semiconductor wafer as a prior example is cut along the line A-A' shown in Figure 16. This is a cross-sectional view showing the cross-sectional structure of the cut surface of a semiconductor wafer as a prior example. This is an explanatory diagram showing the process when a semiconductor wafer is diced as a prior example. This diagram is intended to explain the problems of a semiconductor device as a prior example. This is a schematic bottom view of a semiconductor device as the first example of the second embodiment. This is a side view showing the structure of the cut surface of a semiconductor device as the first example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the second example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the third example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the fourth example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the fifth example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the sixth example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the seventh example of the second embodiment. This is a side view showing the schematic structure of the cut surface of a semiconductor device as the eighth example of the second embodiment.This is a diagram illustrating an example of a semiconductor device manufacturing method as the first example. This is a diagram illustrating an example of a semiconductor device manufacturing method as the second example. This is a diagram illustrating an example of a semiconductor device manufacturing method as the fifth example. This is a diagram illustrating an example of a semiconductor device manufacturing method as the sixth example.

[0011] The embodiments of this technology will be described below in the following order: <Introduction. Conventional Semiconductor Devices> (Introduction 1. Example of Semiconductor Device Configuration) (Introduction 2. Problems with Conventional Examples) <1. Semiconductor Device as the First Embodiment> (1-1. Configuration and Manufacturing Method) (1-2. Modification of the First Embodiment) (1-3. Other Modifications) <2. Semiconductor Device as the Second Embodiment> (2-1. Semiconductor Device as a Prior Art Premise for the Second Embodiment and its Problems) (2-2. Example of Semiconductor Device Configuration as the Second Embodiment) (2-3. Manufacturing Method for the Semiconductor Device as the Second Embodiment) <3. Modifications> <4. Summary of Embodiments> <5. This Technology>

[0012] <Introduction. Conventional Semiconductor Devices> (Introduction 1. Example of Semiconductor Device Configuration) This technology relates to a semiconductor device using a WLCSP (Wafer Level Chip Scale Package) structure. As mentioned above, WLCSP refers to a semiconductor package manufactured by applying a package-like process to a semiconductor wafer with a circuit already formed on it, and finally separating it into individual packages.

[0013] While various specific device configurations for semiconductor devices using a WLCSP structure are conceivable, this example illustrates a semiconductor device using a WLCSP structure that functions as a pixel array used in image sensors such as CMOS (Complementary Metal Oxide Semiconductor) or CCD (Charge Coupled Device) types. In this case, the semiconductor device has a structure in which pixels, each having a photoelectric conversion element such as a photodiode, are arranged two-dimensionally in the planar direction.

[0014] Before describing the semiconductor device using the WLCSP structure, we will first explain a conventional semiconductor device 100.

[0015] Figure 1 shows a schematic longitudinal cross-sectional view of a conventional semiconductor device 100, and Figure 2 shows a schematic bottom view of the semiconductor device 100. Hereinafter, in this specification, the vertical direction for a WLCSP structure semiconductor device is defined as follows: that is, the vertical direction when the side facing the wiring board when the semiconductor device is mounted on the target wiring board (i.e., the side on which the external electrode layer is formed) is defined as the bottom surface (bottom surface).

[0016] As shown in Figure 1, the semiconductor device 100 is composed of a semiconductor layer 2 made of, for example, Si (silicon), a wiring layer 3 formed on the upper side of the semiconductor layer 2, an insulating layer 4 formed on the lower side of the semiconductor layer 2, and an external electrode layer 105 formed on the lower side of the insulating layer 4. The semiconductor device 100 is configured as a so-called semiconductor chip and has a rectangular, plate-like external shape.

[0017] In this example, where the semiconductor device 100 is configured as the pixel array portion of an image sensor, photoelectric conversion elements such as photodiodes are formed on the semiconductor layer 2. In addition, various wirings such as electrodes for various transistors constituting the pixel circuit, wiring for transmitting the light-receiving signal obtained by photoelectric conversion, and wiring for driving the transistors are formed on the wiring layer 3.

[0018] The insulating layer 4 is an insulating film formed by an oxide film formation treatment or a nitride film formation treatment on the semiconductor layer 2. In this example, the insulating layer 4 is composed of, for example, an ISO (silicon-doped indium oxide) film.

[0019] The external electrode layer 105 is a layer laminated to the semiconductor layer 2 via an insulating layer 4, and is composed of a plurality of external electrodes 6 for electrical connection with an external device, and an organic insulating film 7 covering the sides of the external electrodes 6 (see Figures 1 and 2). As shown in Figure 2, in this example, the external electrodes 6 are arranged discretely in two dimensions in the planar direction (direction perpendicular to the lamination direction). The external electrodes 6 are made of a metallic material, and in this example, they are made of Cu (copper).

[0020] The organic insulating film 7 is an insulating film made of an organic material that functions as a solder mask (solder resist), and is composed of a resin material such as epoxy resin.

[0021] As shown in Figure 2, in a conventional example, in the external electrode layer 105 of the semiconductor device 100, the organic insulating film 7 is formed in the entire region other than the region where the external electrode 6 is formed.

[0022] The thickness of the external electrode layer 105 is, for example, about 20 μm.

[0023] (Introduction 2. Problems with Conventional Examples) Figure 3 is a schematic longitudinal cross-sectional view of a conventional semiconductor wafer 110. The semiconductor wafer 110 is a semiconductor wafer before the semiconductor device 100 is separated into individual pieces, as in the conventional example.

[0024] In the semiconductor wafer 110, the area to be cut by dicing is defined as the dicing area. This dicing area can be described as the margin area defined between each region of the semiconductor wafer 110 that is to be divided into individual pieces as semiconductor device 100.

[0025] In conventional semiconductor wafers 110, the entire dicing area, that is, the area between each region to be diced into individual semiconductor devices 100, is formed of an organic insulating film 7. This is due to the uniform application of a resin material that serves as a solder mask on the insulating layer 4 during the formation process of the external electrode layer 105 in the semiconductor wafer 110.

[0026] Figure 4 is a diagram illustrating the problems of a conventional semiconductor device 100. In manufacturing the conventional semiconductor device 100, a semiconductor wafer 110 with the structure shown in Figure 3 is diced. In performing this dicing, first, a mounting process is carried out in which the semiconductor wafer 110 is fixed with a dicing tape 111, as shown in Figure 4A. That is, the semiconductor wafer 110 is fixed to a base portion (not shown) with a dicing tape 111. As shown in the figure, the dicing tape 111 has an adhesive material 111a formed on a base material 111b, and in the mounting process, the end face (i.e., bottom face) of the semiconductor wafer 110 on the side of the external electrode layer 105 is fixed to the adhesive material 111a.

[0027] Following the mounting process shown in Figure 4A, the dicing process shown in Figure 4B is performed. In the dicing process, the semiconductor wafer 110 is cut in the dicing area by the dicing blade 112. This results in the semiconductor device 100 being divided into individual pieces.

[0028] In the conventional semiconductor wafer 110, as described above, the entire dicing area of ​​the external electrode layer 105 is formed of an organic insulating film 7, so during dicing, the organic material is exposed on the cut surface. Consequently, in the conventional example, a problem arises in that dicing tape debris easily adheres to the outer end surface (cut surface) of the external electrode layer 105 as dust (foreign matter) after dicing (see Figure 4C).

[0029] If the organic insulating film 7 is exposed on the cut surface during dicing, dicing tape debris will adhere to the organic insulating film 7. Although a cleaning process is provided after the dicing process to remove dust generated by dicing, since both the dicing tape debris and the organic insulating film 7 are made of organic materials, the degree of adhesion of the dicing tape debris to the organic insulating film 7 increases, making it more likely that the dicing tape debris cannot be completely removed even after cleaning. As a result, in the semiconductor device 100 after dicing, dicing tape debris adhering to the outer end surface of the external electrode layer 105 tends to remain as dust.

[0030] As a measure to prevent dust from adhering to the outer end surface of the external electrode layer 105, one possible approach is to provide an opening 113 in the dicing area of ​​the external electrode layer 105, as shown in Figure 5. By mounting the dicing tape 111, the opening 113 is filled with adhesive material 111a, thereby preventing dicing tape scraps from adhering to the organic insulating film 7.

[0031] However, with this method, there is a possibility that the adhesive 111a may not be able to completely fill the opening 113, and thus it may not be possible to completely prevent dicing tape debris from adhering to the organic insulating film 7.

[0032] Therefore, as shown in Figure 6, it is conceivable to increase the thickness of the adhesive 111a so that the opening 113 can be completely filled. However, this method requires the use of a special dicing tape 111 with a thick adhesive 111a, which would lead to increased manufacturing costs. In addition, since a large amount of adhesive 111a would be cut, there is a risk that a large amount of viscous dust will adhere to the wiring layer 3, leading to a decrease in yield.

[0033] <1. Semiconductor device as a first embodiment> (1-1. Configuration and manufacturing method) In the first embodiment, in order to prevent the organic insulating film 7 from being exposed on the cut surface during dicing, the external electrode layer of the semiconductor wafer is formed such that an inorganic material is present on the cut surface during dicing.

[0034] Figure 7 is a schematic longitudinal cross-sectional view of a semiconductor wafer 10 as a first embodiment. In the following description, parts that are the same as those already described will be denoted by the same reference numerals and their description will be omitted.

[0035] As shown in the figure, semiconductor wafer 10 differs from semiconductor wafer 110 in that an external electrode layer 5 is formed in place of the external electrode layer 105. The external electrode layer 5 differs from the external electrode layer 105 in the following respect: at least a portion of the side surface of the external electrode layer 5 in the semiconductor device after dicing (semiconductor device 1 described later) is exposed as inorganic material. Specifically, in this example, the inorganic material 8' is formed such that a wall portion (inorganic material wall portion 8 described later) is formed around the outer edge of the external electrode layer 5. More specifically, in the semiconductor wafer 10 of this example, the entire dicing area of ​​the external electrode layer 5 is formed of inorganic material 8'.

[0036] In this embodiment, the inorganic material 8' is the same metallic material as the external electrode 6, and specifically in this example, the inorganic material 8' is made of Cu.

[0037] Figure 8 is an explanatory diagram showing the process when a semiconductor wafer 110 is diced as part of the first embodiment. As described above, in the semiconductor wafer 110, the entire dicing area of ​​the external electrode layer 5 is formed of inorganic material 8'. Therefore, when the dicing area is cut by the dicing blade 112, as shown in Figure 8A, inorganic material 8' is present on the cut surface. As a result, in the semiconductor device 1 as part of the first embodiment obtained by dicing the semiconductor wafer 110, as shown in Figure 8B, inorganic material 8' is exposed on the outer end surface of the external electrode layer 5, thus preventing dicing tape residue adhering to the outer end surface from remaining as dust.

[0038] Figure 9 shows a schematic longitudinal cross-sectional view of the semiconductor device 1, and Figure 10 shows a schematic bottom view of the semiconductor device 1. As can be seen by referring to Figures 9 and 10, in the semiconductor device 1, the outer edge of the external electrode layer 5 is formed of an inorganic material (inorganic material 8') all the way around, and a frame-shaped inorganic material wall portion 8 is formed on the outer periphery of the organic insulating film 7.

[0039] Figures 11 and 12 illustrate an example of a manufacturing method for a semiconductor device 1. Here, it is assumed that the lamination process of the wiring layer 3 and the lamination process of the insulating layer 4 on the semiconductor layer 2 in forming the semiconductor wafer 10 have already been completed.

[0040] First, as shown in Figure 11A, an external electrode 6 made of Cu and an inorganic material 8' are formed on the insulating layer 4 laminated on the semiconductor layer 2. In this example, the formation of these external electrodes 6 made of Cu and the inorganic material 8' is carried out, for example, by depositing Cu plating on the insulating layer 4 using an electroless plating method. At this time, the inorganic material 8' is formed over the entire dicing area defined on the wafer.

[0041] Here, the electrode formation process shown in Figure 11A corresponds to the inorganic material formation process, in which inorganic material 8' is formed on the semiconductor wafer 10 before the semiconductor device 1 is separated into individual pieces, such that inorganic material is exposed on at least a portion of the side surface of the external electrode layer 5 in the semiconductor device 1 after it has been separated into individual pieces. Specifically, the inorganic material 8' is formed such that an inorganic material wall portion 8 is formed around the outer edge of the external electrode layer 5 in the semiconductor device 1 after it has been separated into individual pieces.

[0042] In this example, the inorganic material 8' is the same metallic material as the external electrode 6, and the inorganic material formation process is carried out using the same process as the process for forming the external electrode 6. This improves the manufacturing efficiency of the semiconductor device 1 compared to the case where the inorganic material 8' is formed in a separate process from the process for forming the external electrode 6.

[0043] Next, an organic insulating film 7 is formed on the side of the wafer where the external electrode 6 and inorganic material 8' are formed, using the insulating film formation process shown in Figure 11B. Specifically, in this insulating film formation process, a resin that will be used to form the organic insulating film 7 is applied by a spin coating method or the like, and then the resin is cured by, for example, heat treatment or ultraviolet irradiation treatment.

[0044] Next, by the polishing process of FIG. 11C, the organic insulating film 7 formed on the external electrode 6 and the inorganic material 8' in the insulating film forming process is removed, and the external electrode 6 and the inorganic material 8' are exposed. This polishing process can be performed by, for example, CMP (Chemical Mechanical Polishing). By this polishing process, the semiconductor wafer 10 as the first embodiment is completed.

[0045] Next, by the mounting process shown in FIG. 12A, the semiconductor wafer 10 is mounted on the dicing tape 111, and by the dicing process shown in FIG. 12B, the semiconductor wafer 10 in the dicing area is cut using the dicing blade 112.

[0046] Next, by the cleaning process shown in FIG. 12C, the semiconductor wafer 10 in the state where the semiconductor device 1 is separated into individual pieces by the dicing process is cleaned to remove the dust generated by dicing.

[0047] Here, in order to prevent chipping of the inorganic material wall portion 8, a certain thickness of the inorganic material wall portion 8 should be ensured. For confirmation, it should be noted that the wall thickness of the inorganic material wall portion 8 means the thickness in the direction orthogonal to the side surface (cut surface) of the semiconductor device 1. Specifically, if the wall thickness of the inorganic material wall portion 8 is at least 5 μm or more, sufficient chipping resistance of the inorganic material wall portion 8 during dicing can be ensured. Considering this point, in the semiconductor device 1 of this example, the minimum value of the wall thickness of the inorganic material wall portion 8 is set to 5 μm or more.

[0048] In the current dicing process, the dicing blade 112 vibrates within a range of ±5 μm in its thickness direction. Considering this point, in the electrode formation process (inorganic material formation process) described in FIG. 11A, it is desirable to form the inorganic material 8' with the following width. That is, the inorganic material 8' is formed in the range of "half width of the dicing blade 112 + 5 μm" in both directions orthogonal to the blade traveling direction from the center line of dicing in the external electrode layer 5. For example, in this example, since the width of the dicing blade 112 = 50 μm, the inorganic material 8' is formed in the range of 25 μm + 10 μm = 35 μm in both directions orthogonal to the blade traveling direction from the center line of dicing.

[0049] Thereby, even when the dicing blade 112 vibrates by ±5 μm in the width direction during dicing, it becomes possible to ensure that the wall thickness of the inorganic material wall portion 8 in the semiconductor device 1 after singulation is 5 μm or more, and sufficient chipping resistance of the inorganic material wall portion 8 during dicing can be ensured.

[0050] (1-2. Modification of the First Embodiment) The modification of the first embodiment forms a flange portion on the inorganic material wall portion. FIG. 13 is a schematic longitudinal sectional view of a semiconductor device 1A as a modification in the first embodiment. In the semiconductor device 1A, the difference from the semiconductor device 1 is that an external electrode layer 5A is formed instead of the external electrode layer 5. The external electrode layer 5A is different from the external electrode layer 5 in that an inorganic material wall portion 8A is formed instead of the inorganic material wall portion 8.

[0051] The inorganic material wall portion 8A is different from the inorganic material wall portion 8 in that it has a flange portion 8Aa protruding inward at the end portion on the side in contact with the insulating layer 4 in the stacking direction of the semiconductor device 1A. Although not shown, the flange portion 8Aa is formed over a full circle in plan view.

[0052] Having this flange portion 8Aa makes it possible to increase the bonding strength of the inorganic material wall portion 8A to the insulating layer 4. Therefore, the possibility of chipping of the inorganic material wall portion 8A during dicing can be reduced, and the yield of semiconductor device 1A can be improved.

[0053] Figure 14 is a diagram illustrating an example of a manufacturing method for semiconductor device 1A. In a modified version of the first embodiment, in the manufacturing method for semiconductor device 1 described earlier in Figures 11 and 12, the process shown in Figures 14A and 14B is performed instead of the electrode formation process (inorganic material formation process) described in Figure 11A to form the external electrode 6 and the inorganic material 8A' which will become the inorganic material wall portion 8A.

[0054] First, a base layer 81 is formed on the insulating layer 4 by the base formation process shown in Figure 14A, which will serve as the base for forming the external electrode 6 and the inorganic material 8A'. At this time, the base layer 81 for forming the inorganic material 8A' is formed targeting the dicing area. When the external electrode 6 is formed by metal plating, as in this example, the base layer 81 is formed as the base layer for the plating.

[0055] Next, a metal film 82 is formed on the substrate layer 81 by the film formation process shown in Figure 14B to form the external electrode 6 and the inorganic material 8A'. At this time, the metal film 82 is formed to be narrower than the substrate layer 81 so that a stepped portion as a flange portion 8Aa is formed. In this example, where the external electrode 6 is a Cu electrode, the metal film 82 is formed by depositing a Cu film by electroless plating.

[0056] As can be seen by referring to Figure 14B, in this case, the external electrode 6 and the inorganic material 8A' are each composed of a base layer 81 and a metal film 82, respectively. In particular, in the inorganic material 8A', the portion of the base layer 81 that is wider than the metal film 82 functions as a flange portion 8Aa.

[0057] It is not essential to form a wide portion on the external electrode 6 that is similar to the flange portion 8Aa.

[0058] (1-3. Other Modifications) Herein, the first embodiment is not limited to the specific example described above, but a variety of modified configurations can be adopted. For example, the materials and shapes exemplified for each part constituting the semiconductor device are merely examples, and it goes without saying that other materials and shapes can be adopted within the scope of this technology.

[0059] Furthermore, although Cu was used as an example of the constituent material of the inorganic material wall portion (8 or 8A) in the embodiment described above, the inorganic material wall portion may also be composed of other metallic materials such as aluminum. Alternatively, the inorganic material wall portion may also be composed of inorganic materials other than metals, such as oxide films or nitride films.

[0060] Furthermore, although the above example shows the formation of an inorganic material (8' or 8A') over the entire dicing area, in order to prevent the adhesion of dicing tape debris, it is sufficient to ensure that the organic insulating film 7 is not present on the cut surface, and it is not essential to form the inorganic material 8' over the entire dicing area. For example, as shown in Figure 15, it is conceivable to form the organic insulating film 7 in a portion of the area including the center of the dicing area. In this case as well, in the external electrode layer (5 or 5A), by forming the inorganic material such that an inorganic material wall is formed around the outer edge of the external electrode layer in the semiconductor device after fragmentation, it is possible to prevent dicing tape debris from adhering to the outer edge of the external electrode layer and remaining as dust, similar to the first and second embodiments.

[0061] Furthermore, although not specifically mentioned above, the inorganic material wall could also be used to function as some kind of electrode. For example, the inorganic material wall could be connected to ground (GND) and function as a ground electrode. This would allow for a relatively wide ground area, thereby improving the electrical noise resistance of the semiconductor device.

[0062] <2. Semiconductor Device as a Second Embodiment> (2-1. Semiconductor Device as a Prior Example and its Problems as Premised in the Second Embodiment) Next, the second embodiment will be described. First, before describing the semiconductor device as a second embodiment, the semiconductor device 200 as a prior example that is premised in the second embodiment will be described.

[0063] Figure 16 is a schematic bottom view of the semiconductor wafer 210 before the semiconductor device 200 is separated into individual pieces, and Figure 17 is a cross-sectional view showing the cross-section when the semiconductor wafer 210 is cut along the line A-A' shown in Figure 16. As can be seen by referring to Figure 17, the semiconductor wafer 210 is formed in the same way as the semiconductor wafer 10 described in the first embodiment, in that a wiring layer 3, a semiconductor layer 2, and an insulating layer 4 are formed in order from the top side.

[0064] As shown in Figure 16, on the bottom surface of the semiconductor wafer 210, multiple external electrodes 6 are exposed in each region to be diced as a semiconductor device 200, in other words, in each region separated by the dicing area, and an organic insulating film 7 is formed to cover the sides of the external electrodes 6. This is also the same as the semiconductor wafer 10 described in the first embodiment. In the semiconductor wafer 210, the layer formed below the insulating layer 4 is the external electrode layer 205.

[0065] In the semiconductor wafer 210, test pads 211, which serve as electrode pads used for conductivity testing of the portion that will become the semiconductor device 200, are formed within the dicing area for each portion that will become the semiconductor device 200. As shown in the figure, in this case, multiple test pads 211 are formed for each portion that will become the semiconductor device 200, and in this example, they are formed in such a manner that they are arranged along each edge of the portion that will become the semiconductor device 200.

[0066] Each portion of the semiconductor wafer 210 that is to be separated into individual semiconductor devices 200 has a through-electrode 213 formed for each test pad 211 that penetrates the semiconductor layer 2, and a wiring portion 212 made of a metallic material is formed to electrically connect the test pad 211 and the through-electrode 213. In this example, the through-electrode 213 is formed as a TSV (Through Silicon Via). The wiring portion 212 is formed by patterning a metallic material on the lower surface of the insulating layer 4 and is in contact with the insulating layer 4. In this example, the wiring portion 212 is made of, for example, Cu. Each test pad 211 is electrically connected to a predetermined wiring in the wiring layer 3 via the corresponding wiring portion 212 and through-electrode 213.

[0067] Figure 18 is a cross-sectional view showing the cross-sectional structure of a cut surface (cut surface by dicing) of a semiconductor wafer 210 as a prior example. As shown in the figure, in the cut surface of the semiconductor wafer 210, the wiring portion 212 within the external electrode layer 205 is surrounded by an organic insulating film 7.

[0068] Here, as described above, the area around the wiring portion 212 within the external electrode layer 205 is covered with an organic insulating film 7. In the case of the semiconductor wafer 210 as a prior example, during dicing, as shown in the cross-sectional view of Figure 19, the area around the wiring portion 212 deforms relatively significantly as the dicing blade 112 rotates and moves. This is because the organic insulating film 7 is made of an organic material such as resin and is highly elastic. In this example, as shown in the figure, the rotation direction of the dicing blade 112 is from the upper surface to the lower surface of the semiconductor wafer 210, so the organic insulating film 7 deforms by being stretched downwards. At the same time, deformation of the organic insulating film 7 also occurs, which stretches in the direction of the dicing blade 112's movement.

[0069] Such deformation of the organic insulating film 7 could lead to the wiring portion 212 peeling off from the insulating layer 4 or cracks forming near the wiring portion 212 in the semiconductor device 200, as described in the prior example. Figure 20 shows an image of these peeling and cracks.

[0070] If the wiring portion 212 peels off or cracks occur near the wiring portion 212 as described above, moisture may enter the semiconductor device 200 through the peeled-off parts or gaps caused by the cracks, potentially leading to the internal circuitry being corroded and causing failure of the semiconductor device 200. In other words, this could lead to a decrease in the yield of the semiconductor device 200.

[0071] (2-2. Examples of Semiconductor Device Configurations as a Second Embodiment) The second embodiment aims to prevent peeling of the wiring portion 212 and the occurrence of cracks near the wiring portion 212 caused by the dicing described above. Below, eight examples of semiconductor device configurations as a second embodiment are given, from the first to the eighth example.

[0072] Figure 21 is a schematic bottom view of a semiconductor device 20 as a first example of the second embodiment. Similar to the prior example, the semiconductor device 20 has multiple external electrodes 6 exposed on its bottom surface, and the lateral periphery of the external electrodes 6 is covered with an organic insulating film 7. Also similar to the prior example, multiple sets of wiring portions 212 and through electrodes 213 are formed on each side. In Figure 21, the surface cut by dicing (i.e., the side surface of the semiconductor device 20) is schematically shown by dotted lines.

[0073] Figure 22 is a side view showing the schematic structure of the cut surface of the semiconductor device 20. In the semiconductor device 20, as in the prior example, the wiring layer 3, semiconductor layer 2, and insulating layer 4 are formed in order from the top side. In the semiconductor device 20, the layer below the insulating layer 4 is formed as the external electrode layer 25. In the external electrode layer 25, the wiring portion 212 is in contact with the insulating layer 4, as in the prior example.

[0074] In the semiconductor device 20, an inorganic material film 21, separate from the insulating layer 4, is formed on the side surface of the external electrode layer 25, around at least a portion of the wiring portion 212. Specifically, in the first example of the semiconductor device 20, the inorganic material film 21 is in contact with the wiring portion 212 and covers the entire periphery of the wiring portion 212. As shown in the figure, in this case, the lateral periphery of the inorganic material film 21 in the external electrode layer 25 is covered by an organic insulating film 7.

[0075] As described above, the formation of an inorganic material film 21 around at least a portion of the wiring portion 212 makes it possible to suppress deformation around the wiring portion 212 caused by the rotation and movement of the dicing blade 112 during dicing. This is because the inorganic material film 21 is less elastic than the organic insulating film 7. By suppressing deformation around the wiring portion 212, it is possible to prevent the test wiring portion 212 from peeling off from the insulating layer 4 or cracks from occurring near the wiring portion 212 due to dicing, thereby preventing a decrease in the yield of the semiconductor device 20.

[0076] In particular, in the semiconductor device 20 of the first example, since the inorganic material film 21 is in contact with the wiring portion 212, it is possible to make deformation around the wiring portion 212 less likely to occur during dicing compared to the case in which an organic insulating film 7 is interposed between the wiring portion 212 and the inorganic material film 21. Furthermore, since the inorganic material film 21 covers the entire area around the wiring portion 212, it is possible to prevent deformation around the wiring portion 212 during dicing, thereby increasing the effectiveness of preventing peeling of the wiring portion 212 from the insulating layer 4 and cracks near the wiring portion 212.

[0077] Next, we will explain the second and subsequent examples. Figures 23, 24, and 25 are side views showing the schematic structure of the cut surfaces of semiconductor device 20A as the second example, semiconductor device 20B as the third example, and semiconductor device 20C as the fourth example, respectively. In these second to fourth examples, the inorganic material film 21 is in contact with the wiring portion 212, similar to the first example, but the difference is that the inorganic material film 21 covers only a part of the area around the wiring portion 212, rather than the entire area around the wiring portion 212.

[0078] Specifically, in the semiconductor device 20A, shown in Figure 23 as a second example, the inorganic material film 21 covers only the area below the wiring portion 212 on the side surface of the external electrode layer 25. In the semiconductor device 20B, shown in Figure 24 as a third example, the inorganic material film 21 covers only the lateral periphery of the wiring portion 212 on the side surface of the external electrode layer 25. In the semiconductor device 20C, shown in Figure 25 as a fourth example, the inorganic material film 21 is formed only in the area around the wiring portion 212 that is on the side in the direction of travel of the dicing blade 112. Here, "direction of travel of the dicing blade" refers to the direction of travel of the dicing blade 112 when dicing is performed to form the side surface in which the inorganic material film 21 is exposed. In other words, the direction of travel of the dicing blade 112 when dicing is performed to form a side surface that is perpendicular to the side surface in question is excluded.

[0079] Since the inorganic material film 21 is formed at least on the side in the direction of travel of the dicing blade 112, deformation around the wiring portion 212 caused by the movement of the dicing blade 112 can be suppressed, and peeling of the wiring portion 212 and the occurrence of cracks near the wiring portion 212 caused by dicing can be prevented.

[0080] Figures 26, 27, 28, and 29 are side views showing the schematic structure of the cut surfaces of semiconductor devices 20D as the fifth example, 20E as the sixth example, 20F as the seventh example, and 20G as the eighth example, respectively. These fifth to eighth examples are examples in which an organic insulating film 7 is interposed between the wiring portion 212 and the inorganic material film 21. In other words, at least a portion of the area around the wiring portion 212 is indirectly covered by the inorganic material film 21, not directly, but via the organic insulating film 7.

[0081] Here, the wiring section 212 may expand due to thermal expansion when current is applied for testing. If the inorganic material film 21 is in contact with the wiring section 212, when thermal expansion occurs, the expansion pressure will be directly applied to the inorganic material film 21, which may cause cracks to form between the wiring section 212 and the inorganic material film 21. By interposing the organic insulating film 7 between the wiring section 212 and the inorganic material film 21 as described above, even if the wiring section 212 expands due to thermal expansion, the organic insulating film 7 will function as a cushioning material, preventing the expansion pressure from being directly applied to the inorganic material film 21 and thus preventing the occurrence of cracks. In other words, this configuration helps to prevent a decrease in the yield of semiconductor devices from both the perspective of preventing cracks from forming between the wiring section 212 and the inorganic material film 21 when current is applied for testing, and from preventing peeling and cracking of the wiring section 212 during dicing.

[0082] In the semiconductor device 20D, shown in Figure 26 as a fifth example, the inorganic material film 21 covers the entire periphery of the wiring portion 21 on the side surface of the external electrode layer 25. In other words, the inorganic material film 21 covers the area below and to the sides of the wiring portion 21 via the organic insulating film 7.

[0083] The sixth to eighth examples shown in Figures 27 to 29 are examples in which the inorganic material film 21 covers only a portion of the periphery of the wiring portion 21 on the side surface of the external electrode layer 25. Specifically, in the semiconductor device 20E, which is the sixth example shown in Figure 27, the inorganic material film 21 covers only the lower part of the wiring portion 21, and in the semiconductor device 20F, which is the seventh example shown in Figure 28, the inorganic material film 21 covers only the lateral periphery of the wiring portion 212. In the semiconductor device 20G, which is the eighth example shown in Figure 29, the inorganic material film 21 is formed on the side surface of the external electrode layer 25 only in the region around the wiring portion 212 that is on the side facing the direction of travel of the dicing blade 112.

[0084] To clarify, even when an organic insulating film 7 is interposed between the wiring portion 212 and the inorganic material film 21, forming the inorganic material film 21 in at least the region on the side of the dicing blade 112's direction of travel can help suppress deformation around the wiring portion 212 caused by the movement of the dicing blade 112.

[0085] Here, in all of the semiconductor devices (20 to 20G) of the second embodiment described above, the wiring portion 212 is exposed on the side surface of the external electrode layer 25. In other words, in the second embodiment as in the first embodiment, inorganic material is exposed on at least a part of the side surface of the external electrode layer 25. As can be understood from this point, the semiconductor device of the second embodiment also helps to suppress the adhesion of dicing tape debris.

[0086] (2-3. Manufacturing Method for Semiconductor Devices as a Second Embodiment) An example of a manufacturing method for semiconductor devices as a second embodiment described above will be explained. Figures 30 and 31 are diagrams illustrating an example of a manufacturing method for semiconductor device 20 as a first example and semiconductor device 20A as a second example, respectively, while Figures 32 and 33 are diagrams illustrating an example of a manufacturing method for semiconductor device 20D as a fifth example and semiconductor device 20E as a sixth example, respectively. In all of the semiconductor device manufacturing methods, it is common to prepare a laminated structure consisting of a wiring layer 3, a semiconductor layer 2, and an insulating layer 4.

[0087] First, with reference to Figure 30, an example of a manufacturing method for a semiconductor device 20 will be described. First, a pattern of metal material for forming wiring portions 212 is patterned on the insulating layer 4 of the laminated structure, as shown in the wiring pattern formation step in Figure 30A. Specifically in this example, a pattern of wiring material made of Cu is used. Note that this wiring pattern formation step can also be a common step with the formation step of the external electrode layer 25.

[0088] For clarification, the above wiring pattern formation process can be rephrased as the process of forming inorganic material that appears on the side surface of the external electrode layer of the semiconductor device after it has been separated into individual components, and is an example of the "inorganic material formation process" related to this technology.

[0089] Next, an inorganic material film 21 is formed to cover the entire periphery of the wiring portion 212 formed in the wiring pattern formation step described above, using the inorganic material film formation step shown in Figure 30B. Here, for example, an SiON film (silicon oxynitride film) can be used for the inorganic material film 21.

[0090] Next, an organic insulating film 7 is applied to cover the inorganic material film 21 in the organic insulating film coating step shown in Figure 30C, and then the organic insulating film 7 is planarized in the subsequent organic insulating film planarization step shown in Figure 30D, for example by a CMP polishing method. In this example, this planarization is carried out until the inorganic material film 21 is exposed. This organic insulating film coating step yields a semiconductor wafer 40 before the semiconductor device 20 is separated into individual pieces.

[0091] Although not shown in the diagram, a dicing process is performed on the semiconductor wafer 40 obtained in this way, in which a dicing area is cut using a dicing blade 112. Through this dicing process, the semiconductor device 20 is divided into individual pieces from the semiconductor wafer 40. Note that the dicing process is a common feature of all semiconductor device manufacturing methods in the second embodiment.

[0092] Next, with reference to Figure 31, a second example of a manufacturing method for semiconductor device 20A will be described. First, the wiring pattern formation process shown in Figure 31A is the same as that described in Figure 30A, so a redundant explanation will be avoided. In this case, following the wiring pattern formation process, the organic insulating film 7 is applied to cover the entire insulating layer 4 and the entire wiring portion 212 by the organic insulating film coating process shown in Figure 31B.

[0093] Next, the organic insulating film 7 is planarized by the organic insulating film planarization process shown in Figure 31C. This planarization is carried out until the wiring portion 212 is exposed, as shown in the figure.

[0094] Next, an inorganic material film 21 is formed in the inorganic material film formation step shown in Figure 31D so as to cover at least the wiring portion 212. Furthermore, in the subsequent organic insulating film coating step shown in Figure 31E, an organic insulating film 7 is applied so as to cover the entire inorganic material film 21 formed in the inorganic material film formation step and the entire organic insulating film 7 applied in the organic insulating film coating step shown in Figure 31B.

[0095] Next, the organic insulating film 7 coated in the organic insulating film coating step shown in Figure 31E is planarized by the organic insulating film planarization step shown in Figure 31F. This planarization is carried out in this example until the inorganic material film 21 is exposed, as shown in the figure. By performing this organic insulating film planarization step shown in Figure 31F, a semiconductor wafer 40A is obtained before the semiconductor device 20A is separated into individual pieces.

[0096] Although not shown in the diagram, the third example of semiconductor device 20B can be manufactured by, for example, performing the organic insulating film planarization step in Figure 30D until the wiring portion 212 is exposed, and then performing the organic insulating film coating step. The fourth example of semiconductor device 20C can be manufactured by, for example, forming the inorganic material film 21 only on the side in the direction of travel of the dicing blade 112 in the inorganic material film deposition step in Figure 30B, and then performing the organic insulating film coating step in Figure 30C, as well as performing the organic insulating film planarization step in Figure 30D until the wiring portion 212 is exposed, and then performing the organic insulating film coating step.

[0097] Figures 32 and 33 illustrate examples of manufacturing methods for semiconductor device 20D as the fifth example and semiconductor device 20E as the sixth example, respectively. In Figure 32, the wiring pattern formation process shown in Figure 32A is the same as that described in Figure 30A, so redundant explanation is avoided. In this case, following the wiring pattern formation process, the inorganic material film deposition process shown in Figure 32B is performed. In this inorganic material film deposition process, as shown in the figure, an inorganic material film 21 is deposited around the region surrounding the wiring portion 212 on the insulating layer 4, without touching the wiring portion 212. At this time, the inorganic material film 21 is deposited so that its thickness is greater than that of the wiring portion 212, as shown in the figure.

[0098] Next, in the organic insulating film coating step shown in Figure 32C, the organic insulating film 7 is applied so as to cover the entire insulating layer 4, the entire wiring portion 212, and the entire inorganic material film 21. Then, in the subsequent organic insulating film planarization step shown in Figure 32D, the organic insulating film 7 is planarized. This planarization is performed to the extent that the inorganic material film 21 is exposed, as shown in the figure, but the wiring portion 212 is not exposed. In other words, the state in which the wiring portion 212 is covered by the organic insulating film 7 is maintained.

[0099] Next, an inorganic material film 21 is formed on the surface planarized by the planarization process shown in Figure 32D, using the inorganic material film deposition process shown in Figure 32E. This inorganic material film deposition process yields a semiconductor wafer 40D before the semiconductor device 20D is separated into individual pieces.

[0100] Next, regarding the example of a manufacturing method for the semiconductor device 20E shown in Figure 33, the wiring pattern formation process in Figure 33A is the same as that described in Figure 30A, so a redundant explanation will be avoided. In this case, following the wiring pattern formation process, the organic insulating film 7 is applied in the organic insulating film coating process shown in Figure 33B so as to cover the entire insulating layer 4 and the entire wiring portion 212.

[0101] Next, the organic insulating film 7 is planarized by the organic insulating film planarization process shown in Figure 33C. This planarization is performed to the extent that the wiring portion 212 is not exposed, as shown in the figure. In other words, the thickness of the organic insulating film 7 after planarization is made thicker than the thickness of the wiring portion 212.

[0102] Next, an inorganic material film 21 is formed on the surface planarized by the planarization process shown in Figure 33C, using the inorganic material film deposition process shown in Figure 33D. This inorganic material film deposition process shown in Figure 33D yields a semiconductor wafer 40E before the semiconductor device 20E is separated into individual pieces.

[0103] Although not shown in the diagram, the seventh example of semiconductor device 20F can be manufactured by, for example, performing the manufacturing method described in Figure 32 up to the organic insulating film planarization step in Figure 32D. Furthermore, the eighth example of semiconductor device 20G can be manufactured by, for example, in the inorganic material film deposition step in Figure 32B, depositing the inorganic material film 21 only on the side in the direction of travel of the dicing blade 112, then performing the organic insulating film coating step in Figure 32C, and finally performing the organic insulating film planarization step in Figure 32D.

[0104] Herein, as with the first embodiment, the materials and shapes exemplified for each part constituting the semiconductor device are merely examples, and other materials and shapes may be adopted within the scope of this technology.

[0105] <3. Modifications> Here, the embodiments are not limited to the specific examples described above, but a variety of modified configurations can be adopted. In the above, an example was given in which this technology is applied to a semiconductor device that functions as a pixel array in an image sensor, but this technology can be broadly and suitably applied to semiconductor devices other than the pixel array in an image sensor, such as a semiconductor device that functions as a light-emitting part in a light-emitting device in which light-emitting elements such as VCSEL (Vertical Cavity Surface Emitting LASER) are arranged in an array, or a semiconductor device that functions as a pixel array in a distance measuring sensor formed by arranging pixels that receive light for distance measurement in two dimensions.

[0106] <4. Summary of Embodiments> As described above, the semiconductor device of the embodiment (1, 1A, 20, 20A to 20G) comprises a semiconductor layer (2), an external electrode layer (5, 5A, 25) which is a layer laminated to the semiconductor layer via an insulating layer (4), and has a plurality of external electrodes (6) for making an electrical connection with an external device, and an organic insulating film (7) covering the lateral periphery of the external electrodes, wherein an inorganic material (8', 8A', wiring portion 212) is exposed on at least a part of the side surface of the external electrode layer. As described above, if an inorganic material is exposed on at least a part of the side surface of the external electrode layer, then during the dicing process in manufacturing, the inorganic material will be present on at least a part of the cut surface of the external electrode layer. Since dicing tape debris is less likely to adhere to inorganic material compared to organic insulating film, the presence of inorganic material on at least a part of the cut surface makes it possible to suppress the adhesion of dicing tape debris to the cut surface more than when the entire cut surface is made of organic insulating film. Therefore, it is possible to suppress the decrease in yield of the semiconductor device due to dust adhesion.

[0107] Furthermore, in the semiconductor device of the embodiment (1, 1A), the outer edge of the external electrode layer is formed of inorganic material all around, and a frame-shaped inorganic material wall (8, 8A) is formed on the outer periphery of the organic insulating film. As described above, if the outer edge of the external electrode layer is formed of inorganic material wall all around, then during the dicing process in manufacturing, inorganic material will be present on the entire cut surface of the external electrode layer. Therefore, it is possible to prevent dicing tape scraps from adhering to the semiconductor device as dust, and to prevent a decrease in the yield of the semiconductor device due to dust adhesion.

[0108] Furthermore, in the semiconductor device of this embodiment, the inorganic material wall portion is made of a metallic material. This makes it possible to improve the ease of forming the inorganic material wall portion compared to when the inorganic material wall portion is formed by an oxide film or nitride film on the external electrode layer. Therefore, it is possible to improve the manufacturing efficiency of the semiconductor device.

[0109] Furthermore, in the semiconductor device of this embodiment, the inorganic material wall portion is made of the same metal material as the external electrodes. This makes it possible to form the inorganic material wall portion using the same process as the process for forming the external electrodes. Therefore, the manufacturing efficiency of the semiconductor device can be improved.

[0110] Furthermore, in the semiconductor device (1A) of the embodiment, the inorganic material wall portion (8A) has a flange portion (8Aa) that protrudes inward at the end on the side that contacts the insulating layer in the stacking direction. The flange portion makes it possible to increase the bonding strength of the inorganic material wall portion to the insulating layer side. Therefore, it is possible to reduce the possibility of chipping of the inorganic material wall portion during dicing and improve the yield of the semiconductor device.

[0111] Furthermore, in the semiconductor device of this embodiment, the minimum wall thickness of the inorganic material wall portion is set to 5 μm or more. By ensuring a wall thickness of at least 5 μm in the inorganic material wall portion in this way, sufficient chipping resistance of the inorganic material wall portion during dicing can be ensured, thereby improving the yield of the semiconductor device.

[0112] Furthermore, in the semiconductor devices of the embodiment (20, 20A to 20G), the inorganic material exposed on the side surface of the external electrode layer (25) is formed as a wiring portion (212) made of a metal material that is energized during the conductivity test performed at the semiconductor wafer stage. The wiring portion is in contact with the insulating layer on the side surface of the semiconductor device, and at least a portion of the area around the wiring portion on the side surface of the external electrode layer is covered with an inorganic material film (21) separate from the insulating layer. Since the inorganic material film is less elastic than an organic insulating film, the above configuration makes it possible to suppress deformation around the wiring portion caused by the rotation and movement of the dicing blade during semiconductor wafer dicing. Therefore, it is possible to prevent the test wiring portion from peeling off from the insulating layer or cracks from occurring near the wiring portion due to dicing, thereby preventing a decrease in the yield of the semiconductor device.

[0113] Furthermore, in the semiconductor device of the embodiment, the inorganic material film is formed on the side surface of the external electrode layer in at least the region surrounding the wiring portion that is on the side in the direction of the dicing blade's movement. As described above, by forming the inorganic material film at least on the side in the direction of the dicing blade's movement, deformation around the wiring portion caused by the movement of the dicing blade can be suppressed. Therefore, peeling of the wiring portion and the occurrence of cracks near the wiring portion caused by dicing can be prevented, and a decrease in the yield of the semiconductor device can be prevented.

[0114] Furthermore, in the semiconductor devices of the embodiment (20, 20A to 20C), the inorganic material film is in contact with the wiring portion. This makes it possible to reduce deformation around the wiring portion during dicing compared to the case where an organic insulating film is interposed between the wiring portion and the inorganic material film. Consequently, the possibility of delamination of the wiring portion or cracks occurring near the wiring portion due to dicing can be further reduced.

[0115] Furthermore, in the semiconductor device of the embodiment (20), an inorganic material film covers the entire perimeter of the wiring portion on the side surface of the external electrode layer. By configuring the inorganic material film to cover the entire perimeter of the wiring portion as described above, it is possible to enhance the effect of preventing peeling of the wiring portion from the insulating layer and cracking near the wiring portion. Therefore, it is possible to improve the effect of preventing a decrease in the yield of the semiconductor device.

[0116] Furthermore, in the semiconductor devices of the embodiment (20A to 20C), the inorganic material film covers only a portion of the periphery of the wiring portion on the side surface of the external electrode layer. By configuring the inorganic material film to cover only a portion of the periphery of the wiring portion as described above, it is possible to reduce the amount of inorganic material used in forming the inorganic material film. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0117] Furthermore, in the semiconductor devices of the embodiment (20D to 20G), an organic insulating film is interposed between the wiring portion and the inorganic material film. The wiring portion may expand due to thermal expansion when current is applied for testing. If the inorganic material film is in contact with the wiring portion, when thermal expansion occurs, the expansion pressure will be directly applied to the inorganic material film, which may cause cracks to form between the wiring portion and the inorganic material film. By interposing an organic insulating film between the wiring portion and the inorganic material film as described above, even if the wiring portion expands due to thermal expansion, the organic insulating film functions as a cushioning material, preventing the expansion pressure from being directly applied to the inorganic material film and thus preventing the occurrence of cracks. In other words, it is possible to prevent a decrease in the yield of semiconductor devices from both the point of preventing cracks from forming between the wiring portion and the inorganic material film when current is applied for testing, and from the point of preventing delamination and cracking of the wiring portion during dicing.

[0118] Furthermore, in the semiconductor device of the embodiment (20D), an inorganic material film covers the entire perimeter of the wiring portion on the side surface of the external electrode layer. By configuring the inorganic material film to cover the entire perimeter of the wiring portion as described above, it is possible to enhance the effect of preventing peeling of the wiring portion from the insulating layer and cracking near the wiring portion. Therefore, it is possible to improve the effect of preventing a decrease in the yield of the semiconductor device.

[0119] Furthermore, in the semiconductor devices of the embodiment (20E to 20G), the inorganic material film covers only a portion of the periphery of the wiring portion on the side surface of the external electrode layer. By configuring the inorganic material film to cover only a portion of the periphery of the wiring portion as described above, it is possible to reduce the amount of inorganic material used in forming the inorganic material film. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0120] A semiconductor device manufacturing method as an embodiment comprises a semiconductor layer and an external electrode layer, which is a layer laminated to the semiconductor layer via an insulating layer and has a plurality of external electrodes for making an electrical connection with an external device and an organic insulating film covering the sides of the external electrodes. The manufacturing method comprises at least an inorganic material formation step of forming an inorganic material on a semiconductor wafer before it is pulverized so that the inorganic material is exposed on at least a portion of the side surface of the external electrode layer in the semiconductor device after pulverization, and a dicing step of dicing the semiconductor wafer on which the inorganic material has been formed. This makes it possible to manufacture a semiconductor device in which the inorganic material is exposed on at least a portion of the side surface of the external electrode layer. Therefore, it is possible to suppress the adhesion of dicing tape scraps to the cut surface and to suppress the decrease in yield of the semiconductor device due to dust adhesion.

[0121] Furthermore, in the semiconductor device manufacturing method as described above, in the inorganic material formation step, the inorganic material is formed on the semiconductor wafer such that an inorganic material wall is formed around the outer edge of the external electrode layer of the semiconductor device after dicing. The formation of an inorganic material wall around the outer edge of the external electrode layer of the semiconductor device after dicing means that the organic insulating film is not exposed on the cut surface during the dicing process. Therefore, it is possible to prevent dicing tape scraps from adhering as dust to the outer edge of the external electrode layer, and to prevent a decrease in the yield of semiconductor devices due to dust adhesion.

[0122] Furthermore, in the semiconductor device manufacturing method as described above, the inorganic material is the same metallic material as the external electrodes, and the inorganic material formation process is carried out using the same process as the external electrode formation process. This improves the manufacturing efficiency of the semiconductor device compared to the case where the inorganic material is formed in a separate process from the external electrode formation process.

[0123] Furthermore, in the semiconductor device manufacturing method as described above, in the inorganic material formation step, the inorganic material is formed in the external electrode layer over a range of "half the width of the blade + 10 μm" in both directions perpendicular to the blade's direction of travel from the dicing centerline. This makes it possible to ensure a wall thickness of 5 μm or more for the inorganic material wall portion of the semiconductor device after dicing, even when the dicing blade vibrates by ±5 μm in the width direction (perpendicular to the direction of travel). Therefore, sufficient chipping resistance of the inorganic material wall portion during dicing can be ensured, and the yield of semiconductor devices can be improved.

[0124] Furthermore, in the semiconductor device manufacturing method as described above, the inorganic material formation step is a step of forming a wiring portion made of a metal material that is energized during a conductivity test performed on a semiconductor wafer, and which contacts the insulating layer on the side surface of the external electrode layer of the semiconductor device. The method further includes a film deposition step of forming an inorganic material film separate from the insulating layer on at least a portion of the area around the wiring portion on the side surface of the external electrode layer. By forming an inorganic material film on at least a portion of the area around the wiring portion on the side surface of the external electrode layer of the semiconductor device after fragmentation, it is possible to suppress deformation around the wiring portion caused by the rotation and movement of the dicing blade during semiconductor wafer dicing. Therefore, it is possible to prevent the test wiring portion from peeling off from the insulating layer or cracks from occurring near the wiring portion due to dicing, and to prevent a decrease in the yield of semiconductor devices.

[0125] Furthermore, the effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0126] <7. This Technology> This technology can also be configured as follows: (1) A semiconductor device comprising: a semiconductor layer; an external electrode layer, which is a layer laminated to the semiconductor layer via an insulating layer, and has a plurality of external electrodes for making an electrical connection with an external device, and an organic insulating film covering the lateral periphery of the external electrodes, wherein an inorganic material is exposed on at least a part of the side surface of the external electrode layer. (2) The semiconductor device according to (1), wherein the outer edge of the external electrode layer is formed of the inorganic material around its circumference, and a frame-shaped inorganic material wall is formed on the outer periphery of the organic insulating film. (3) The semiconductor device according to (2), wherein the inorganic material wall is made of a metallic material. (4) The semiconductor device according to (3), wherein the inorganic material wall is made of the same metallic material as the external electrodes. (5) The semiconductor device according to any one of (2) to (4), wherein the inorganic material wall has a flange portion that protrudes inward at the end on the side in contact with the insulating layer in the lamination direction. (6) The semiconductor device according to any one of (2) to (5), wherein the minimum wall thickness of the inorganic material wall portion is 5 μm or more. (7) The semiconductor device according to (1), wherein the inorganic material exposed on the side surface of the external electrode layer is formed as a wiring portion made of a metal material that is energized during a conductivity test performed at the semiconductor wafer stage, the wiring portion is in contact with the insulating layer on the side surface of the semiconductor device, and an inorganic material film separate from the insulating layer is formed on the side surface of the external electrode layer, at least a part of the periphery of the wiring portion. (8) The semiconductor device according to (7), wherein the inorganic material film is formed on the side surface of the external electrode layer in at least the region of the periphery of the wiring portion that is on the side in the direction of travel of the dicing blade. (9) The semiconductor device according to (7), wherein the inorganic material film is in contact with the wiring portion. (10) The semiconductor device according to (9), wherein the inorganic material film covers the entire periphery of the wiring portion on the side surface of the external electrode layer. (11) The semiconductor device according to (9), wherein on the side surface of the external electrode layer, the inorganic material film covers only a portion of the area around the wiring portion. (12) The semiconductor device according to (7), wherein an organic insulating film is interposed between the wiring portion and the inorganic material film.(13) The semiconductor device according to (12), wherein the inorganic material film covers the entire periphery of the wiring portion on the side surface of the external electrode layer. (14) The semiconductor device according to (12), wherein the inorganic material film covers only a part of the periphery of the wiring portion on the side surface of the external electrode layer. (15) A method for manufacturing a semiconductor device comprising a semiconductor layer and an external electrode layer, which is a layer laminated to the semiconductor layer via an insulating layer and has a plurality of external electrodes for making an electrical connection with an external device and an organic insulating film covering the lateral periphery of the external electrodes, the method comprising at least an inorganic material forming step of forming the inorganic material on a semiconductor wafer before the semiconductor device is separated into pieces, such that the inorganic material is exposed on at least a part of the side surface of the external electrode layer in the semiconductor device after separation, and a dicing step of dicing the semiconductor wafer on which the inorganic material has been formed. (16) The method for manufacturing a semiconductor device according to (15), wherein in the inorganic material forming step, an inorganic material is formed on the semiconductor wafer such that an inorganic material wall is formed around the outer edge of the external electrode layer in the semiconductor device after separation. (17) The method for manufacturing a semiconductor device according to (16), wherein the inorganic material is the same metallic material as the external electrode, and in the inorganic material formation step, the inorganic material is formed by a process common to the process for forming the external electrode. (18) The method for manufacturing a semiconductor device according to (16) or (17), wherein in the inorganic material formation step, the inorganic material is formed in the external electrode layer over a range of "half the width of the blade + 10 μm" in both directions perpendicular to the blade travel direction from the center line of the dicing. (19) The method for manufacturing a semiconductor device according to (15), wherein the inorganic material formation step is a step of forming a wiring portion made of a metallic material that is energized during a conductivity test performed on the semiconductor wafer, and the wiring portion is in contact with the insulating layer on the side surface of the external electrode layer of the semiconductor device, and further comprises a film formation step of forming an inorganic material film separate from the insulating layer on at least a part of the periphery of the wiring portion on the side surface of the external electrode layer.

[0127] 1,100 Semiconductor device 2 Semiconductor layer 3 Wiring layer 4 Insulating layer 5,5A,105 External electrode layer 6 External electrode 7 Organic insulating film 8',8A' Inorganic material 8,8A Inorganic material wall portion 8Aa Flange portion 10,10B,110 Semiconductor wafer 81 Underlayment 82 Metal film 111 Dicing tape 111a Adhesive 111b Substrate 112 Dicing blade 113 Aperture 210 Semiconductor wafer 200 Semiconductor device 211 Test pad 212 Wiring portion 213 Through electrode 205 External electrode layer 20,20A,20B,20C,20D,20E,20F,20G Semiconductor device 21 Inorganic material film 25 External electrode layer 40,40A,40D,40E Semiconductor wafer

Claims

1. A semiconductor device comprising: a semiconductor layer; an external electrode layer laminated to the semiconductor layer via an insulating layer, having a plurality of external electrodes for making an electrical connection with an external device, and an organic insulating film covering the lateral periphery of the external electrodes, wherein an inorganic material is exposed on at least a portion of the side surface of the external electrode layer.

2. The semiconductor device according to claim 1, wherein the outer edge of the external electrode layer is formed of the inorganic material around its circumference, and a frame-shaped inorganic material wall is formed on the outer periphery of the organic insulating film.

3. The semiconductor device according to claim 2, wherein the inorganic material wall portion is made of a metal material.

4. The semiconductor device according to claim 3, wherein the inorganic material wall portion is made of the same metallic material as the external electrode.

5. The semiconductor device according to claim 2, wherein the inorganic material wall portion has a flange portion that protrudes inward at the end portion on the side in contact with the insulating layer in the stacking direction.

6. The semiconductor device according to claim 2, wherein the minimum wall thickness of the inorganic material wall portion is 5 μm or more.

7. The semiconductor device according to claim 1, wherein the inorganic material exposed on the side surface of the external electrode layer is formed as a wiring portion made of a metal material that is energized during a conductivity test performed at the semiconductor wafer stage, the wiring portion is in contact with the insulating layer on the side surface of the semiconductor device, and an inorganic material film separate from the insulating layer is formed on the side surface of the external electrode layer around the wiring portion.

8. The semiconductor device according to claim 7, wherein the inorganic material film is formed on the side surface of the external electrode layer in at least the region of the surrounding area of ​​the wiring portion that is on the side in the direction of travel of the dicing blade.

9. The semiconductor device according to claim 7, wherein the inorganic material film is in contact with the wiring portion.

10. The semiconductor device according to claim 9, wherein the inorganic material film covers the entire periphery of the wiring portion on the side surface of the external electrode layer.

11. The semiconductor device according to claim 9, wherein, on the side surface of the external electrode layer, the inorganic material film covers only a portion of the area around the wiring portion.

12. The semiconductor device according to claim 7, wherein an organic insulating film is interposed between the wiring portion and the inorganic material film.

13. The semiconductor device according to claim 12, wherein the inorganic material film covers the entire periphery of the wiring portion on the side surface of the external electrode layer.

14. The semiconductor device according to claim 12, wherein, on the side surface of the external electrode layer, the inorganic material film covers only a portion of the area surrounding the wiring portion.

15. A method for manufacturing a semiconductor device, comprising: a semiconductor layer; an external electrode layer laminated to the semiconductor layer via an insulating layer, the external electrode layer having a plurality of external electrodes for making an electrical connection with an external device, and an organic insulating film covering the lateral periphery of the external electrodes, the method comprising at least an inorganic material forming step of forming an inorganic material on a semiconductor wafer before the semiconductor device is separated into individual pieces, such that the inorganic material is exposed on at least a portion of the side surface of the external electrode layer in the semiconductor device after separation; and a dicing step of dicing the semiconductor wafer on which the inorganic material has been formed.

16. The method for manufacturing a semiconductor device according to claim 15, wherein in the inorganic material formation step, an inorganic material is formed on the semiconductor wafer such that an inorganic material wall is formed around the outer edge of the external electrode layer of the semiconductor device after it has been separated into individual pieces.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the inorganic material is the same metallic material as the external electrode, and the inorganic material is formed in the inorganic material formation step by a step common to the step for forming the external electrode.

18. The method for manufacturing a semiconductor device according to claim 16, wherein in the inorganic material formation step, the inorganic material is formed in the external electrode layer over a range of "half the width of the blade + 10 μm" in both directions perpendicular to the blade travel direction from the center line of the dicing.

19. The method for manufacturing a semiconductor device according to claim 15, wherein the inorganic material formation step is a step of forming a wiring portion made of a metal material that is energized during a conductivity test performed on the semiconductor wafer, the inorganic material being a step of forming a wiring portion that is in contact with the insulating layer on the side surface of the external electrode layer of the semiconductor device, and further comprises a film formation step of forming an inorganic material film separate from the insulating layer on at least a part of the periphery of the wiring portion on the side surface of the external electrode layer.

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