Detection device
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-08-13
Smart Images
Figure JP2025045146_13082026_PF_FP_ABST
Abstract
Description
Detection device
[0001] The present invention relates to a detection device.
[0002] Detection devices capable of detecting fingerprint patterns and vein patterns are known (for example, Patent Document 1). In such a detection device, a configuration having a plurality of photodiodes using an organic semiconductor material as a photosensor is known. In Patent Document 2 below, a plurality of photosensors are provided between a backlight and a detection object, and in a configuration for generating image data of the detection object based on the detection values for each of the plurality of photosensors, a light shielding layer is provided between the backlight and the photodiode so that direct light irradiated from the backlight is not irradiated to the photodiode.
[0003] Japanese Patent Application Laid-Open No. 2009-32005 Japanese Patent Application Laid-Open No. 2023-12380
[0004] In Patent Document 2 above, the amount of light transmitted through the detection object is reduced by the light shielding layer, and the contrast of the image may be reduced.
[0005] An object of the present disclosure is to provide a detection device capable of acquiring a high-contrast image.
[0006] A detection device according to an aspect of the present disclosure includes a sensor region in which a plurality of photosensors are arranged, a backlight that is disposed opposite to the back surface of a substrate provided with the sensor region and irradiates light to a detection object through the sensor region, a detection circuit that generates an image of the detection object based on each detection value acquired by the plurality of photosensors, and a control circuit that controls the backlight and the detection circuit. The detection circuit has a detection upper limit value that can be detected in the detection circuit and a light intensity setting value of the backlight set in advance, controls the backlight by applying the light intensity setting value, and calculates a difference between each detection value acquired for each of the plurality of photosensors and the detection upper limit value as data for image generation.
[0007] Figure 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device according to an embodiment. Figure 2 is a plan view showing a detection device according to an embodiment. Figure 3 is a block diagram showing an example configuration of a detection device according to an embodiment. Figure 4 is a circuit diagram showing a detection device. Figure 5 is a circuit diagram showing a plurality of light sensors. Figure 6 is a timing waveform diagram showing an example of operation of the detection device. Figure 7 is a timing waveform diagram showing an example of operation during the readout period in Figure 6. Figure 8A is a schematic diagram showing the relationship between light intensity, which indicates the intensity of light emitted from the backlight, and the detected value acquired by the detection circuit. Figure 8B is a schematic diagram showing the relationship between light intensity, which indicates the intensity of light emitted from the backlight, and the detected value acquired by the detection circuit. Figure 8C is a schematic diagram showing the relationship between light intensity, which indicates the intensity of light emitted from the backlight, and the detected value acquired by the detection circuit. Figure 9 is a flowchart showing an example of initial setup processing in a detection device according to an embodiment. Figure 10 is a subflowchart showing an example of detection upper limit setting processing. Figure 11 is a subflowchart showing an example of light intensity setting processing. Figure 12 is a schematic diagram for explaining the operation in the initial setup processing. Figure 13 is a flowchart showing an example of detection processing in a detection device according to an embodiment.
[0008] Embodiments for carrying out the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components described below include those that are easily conceivable to those skilled in the art, and those that are substantially the same. Moreover, the components described below can be combined as appropriate. Furthermore, the disclosure is merely an example, and any modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. In addition, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and in each drawing, elements similar to those described above with respect to previously shown drawings are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.
[0009] Figure 1 is a cross-sectional view showing a schematic cross-sectional configuration of a detection device according to an embodiment. As shown in Figure 1, the detection device 1 includes an array substrate 2, a light guide unit 7, an adhesive layer 124, a cover member 125, and a backlight 121. The backlight 121, array substrate 2, light guide unit 7, adhesive layer 124, and cover member 125 are stacked in the order of the backlight 121, array substrate 2, light guide unit 7, adhesive layer 124, and cover member 125 in a direction perpendicular to the first main surface S1 of the array substrate 2.
[0010] The array substrate 2 is formed using the sensor substrate 21 as the base. The array substrate 2 has a plurality of photodiodes PD provided on the first main surface S1 side of the sensor substrate 21.
[0011] The light guide unit 7 is positioned opposite the plurality of photodiodes PD and between the plurality of photodiodes PD and the object to be detected, such as a finger Fg. The light guide unit 7 has a plurality of light guide paths and a light shielding portion provided around the plurality of light guide paths. At least a portion of the light guide paths overlaps the photodiodes PD. The light shielding portion has a higher light absorption rate than the light guide paths. The light guide unit 7 is an optical element that transmits the component of light L2 reflected by the object to be detected, such as a finger Fg, that travels in a predetermined direction toward the photodiodes PD. The light guide unit 7 is also called a collimated aperture or collimator. Note that the light guide unit 7 is not limited to a configuration in which the light guide paths are formed in a columnar shape, and various configurations can be applied.
[0012] The cover member 125 is a member for protecting the array substrate 2 and the light guide unit 7, and covers the array substrate 2 and the light guide unit 7. The cover member 125 is, for example, a glass substrate. However, the cover member 125 is not limited to a glass substrate, and may be a resin substrate or the like, or it may be a configuration consisting of multiple layers of these substrates stacked together. The cover member 125 is bonded to the surface of the light guide unit 7 via an adhesive layer 124. However, the adhesive layer 124 is optional. Alternatively, the cover member 125 may not be provided at all. In this case, a protective layer such as an insulating film is provided on the surfaces of the array substrate 2 and the light guide unit 7, and the finger Fg comes into contact with the protective layer of the detection device 1.
[0013] The backlight 121 is positioned opposite the second main surface S2 of the sensor substrate 21, which is opposite to the first main surface S1. The backlight 121 includes, for example, a light guide plate 122 and a light source 123 with multiple light-emitting elements arranged at one end of the light guide plate 122. Light emitted from the light source 123 travels through the inside of the light guide plate 122, and some of the light L1, L1a is emitted from the light guide plate 122 toward the object to be detected, such as a finger Fg. As the multiple light-emitting elements constituting the light source 123, for example, light-emitting diodes (LEDs) that emit light of a predetermined color are used.
[0014] In the detection device 1 according to this embodiment, the array substrate 2 is positioned between the backlight 121 and the object to be detected, such as a finger Fg, in a direction perpendicular to the first main surface S1. In other words, the detection device 1 is stacked in the following order: backlight 121, array substrate 2 provided with a plurality of photodiodes PD, and cover member 125 in contact with the object to be detected.
[0015] Light L1 emitted from the backlight 121 is mainly reflected by the surface of the object to be detected, such as a finger Fg, and incident on multiple photodiodes PD. This allows the detection device 1 to detect fingerprints by detecting the shape of the surface irregularities of the finger Fg. Alternatively, a portion of the light L1 emitted from the backlight 121 is reflected inside the finger Fg and incident on multiple photodiodes PD. This allows the detection device 1 to detect biological information inside the finger Fg. Biological information includes, for example, pulse waves, pulse rate, and vascular patterns of the fingers or palm. That is, the detection device 1 may be configured as a fingerprint detection device for detecting fingerprints or a vein detection device for detecting vascular patterns such as veins. The light L1 emitted from the backlight 121 is set to a wavelength (from the visible light region to the near-infrared light region) appropriate to the object to be detected. The light source 123 is not limited to one type, and multiple types with different wavelengths may be provided.
[0016] The configuration of the backlight 121 is merely an example and can be modified as appropriate. For example, the arrangement of the light source 123 is not limited to one end of the light guide plate 122, but may be arranged at both ends of the light guide plate 122. Various optical sheets, such as prism sheets and light diffusion sheets, may be laminated on the surface of the light guide plate 122 facing the second main surface S2. Furthermore, the backlight 121 is not limited to a configuration having a light guide plate 122. For example, if the detection device 1 is configured as a flexible sensor, a flexible OLED light source can be used as the backlight 121. A flexible OLED light source has a flexible light source substrate and an organic light-emitting diode (OLED) formed on the light source substrate as a light source.
[0017] In the configuration described above, the light L1 emitted from the backlight 121 passes through the light-transmitting region 2a of the array substrate 2 and reaches the object to be detected. The reflected light L2 reflected by the object to be detected, such as a finger Fg, is received by the photodiode PD via the light guide 7. On the other hand, the photodiode PD also receives the direct light L1a emitted from the backlight 121. Therefore, if there are any side effects from the direct light L1a emitted from the backlight 121, it is necessary to mitigate them.
[0018] Figure 2 is a plan view showing a detection device according to an embodiment. As shown in Figure 2, the detection device 1 includes a sensor substrate 21 (array substrate 2), a sensor area AA, a gate line drive circuit 15, a signal line selection circuit 16, an AFE (Analog Front End) circuit 48, a control circuit 102, and a power supply circuit 103.
[0019] The control board 101 is electrically connected to the sensor substrate 21 via a flexible printed circuit board 110. An AFE circuit 48 is provided on the flexible printed circuit board 110. A control circuit 102 and a power supply circuit 103 are provided on the control board 101.
[0020] The control circuit 102 is, for example, a control integrated circuit (IC) that outputs logic control signals. The control circuit 102 may also be a programmable logic device (PLD) such as an FPGA (Field Programmable Gate Array).
[0021] The control circuit 102 supplies control signals to the sensor area AA, the gate line drive circuit 15, and the signal line selection circuit 16 to control the detection operation of the object to be detected in the sensor area AA. The control circuit 102 also supplies control signals to the light source 123 to control whether the backlight 121 is lit or not.
[0022] The power supply circuit 103 supplies a voltage signal such as the sensor power supply potential VDDSNS (see Figure 4) to the sensor area AA, the gate line drive circuit 15, and the signal line selection circuit 16. The power supply circuit 103 also supplies the power supply voltage to the light source 123.
[0023] The gate line drive circuit 15 and the signal line selection circuit 16 are provided in an area outside the sensor area AA. Specifically, the gate line drive circuit 15 is provided in an area along the second direction Dy with respect to the sensor area AA. The signal line selection circuit 16 is provided in an area along the first direction Dx with respect to the sensor area AA (in the example shown in Figure 1, between the sensor area AA and the AFE circuit 48).
[0024] The first direction Dx is one direction in a plane parallel to the sensor substrate 21. The second direction Dy is one direction in a plane parallel to the sensor substrate 21 and is perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular to it. In this disclosure, "plan view" refers to the positional relationship when viewed from a direction perpendicular to the sensor substrate 21.
[0025] Figure 3 is a block diagram showing an example configuration of a detection device according to an embodiment. As shown in Figure 3, the detection device 1 further includes a detection control circuit 11 and a detection circuit 40. The detection control circuit 11 is included, for example, in the control circuit 102. The detection circuit 40 includes an AFE circuit 48.
[0026] The photodiode PD in sensor region AA is an organic photodiode (OPD), which outputs an electrical signal corresponding to the irradiated light as a detection signal Vdet to the signal line selection circuit 16. Sensor region AA also performs detection according to the gate drive signal Vgcl supplied from the gate line drive circuit 15.
[0027] The detection control circuit 11 is a circuit that supplies control signals to the gate line drive circuit 15, the signal line selection circuit 16, and the detection circuit 40, respectively, and controls their operation. The detection control circuit 11 supplies various control signals such as the start signal STV, the clock signal CK, and the reset signal RST1 to the gate line drive circuit 15. The detection control circuit 11 also supplies various control signals such as the selection signal ASW to the signal line selection circuit 16. Furthermore, the detection control circuit 11 supplies various control signals to the light source 123 to control the illumination and de-illumination of the backlight 121.
[0028] The gate line drive circuit 15 is a circuit that drives multiple gate lines GCL (see Figure 4) based on various control signals. The gate line drive circuit 15 sequentially or simultaneously selects multiple gate lines GCL and supplies a gate drive signal Vgcl to the selected gate lines GCL. As a result, the gate line drive circuit 15 selects multiple photodiodes PD connected to the gate lines GCL.
[0029] The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of signal lines SGL (see Figure 4). The signal line selection circuit 16 is, for example, a multiplexer. Based on the selection signal ASW supplied from the detection control circuit 11, the signal line selection circuit 16 electrically connects the selected signal line SGL to the AFE circuit 48. As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photodiode PD to the detection circuit 40.
[0030] The detection circuit 40 includes an AFE circuit 48, a signal processing circuit 44, a memory circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the AFE circuit 48 and the signal processing circuit 44 to operate synchronously based on a control signal supplied from the detection control circuit 11.
[0031] The AFE circuit 48 is, for example, an analog front-end IC.
[0032] The AFE circuit 48 is a signal processing circuit that has at least the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 amplifies the detection signal Vdet. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal at a predetermined sampling period.
[0033] In this disclosure, the signal processing circuit 44 and the memory circuit 46 are included in the control circuit 102.
[0034] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor area AA based on the output signal of the AFE circuit 48. For example, when a subject's finger or arm comes into contact with or is close to the detection surface, the signal processing circuit 44 can detect irregularities on the surface of the finger or palm based on the signal from the AFE circuit 48. The signal processing circuit 44 can also detect biological information based on the signal from the AFE circuit 48. This biological information includes, for example, vascular images of the finger or palm, pulse waves, pulse rate, and blood oxygen saturation.
[0035] The memory circuit 46 temporarily stores the signals processed by the signal processing circuit 44. The memory circuit 46 may include, for example, RAM (Random Access Memory), ROM (Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), etc. Alternatively, the memory circuit 46 may be a register circuit or the like.
[0036] Next, an example of the circuit configuration of the detection device 1 will be described. Figure 4 is a circuit diagram showing the detection device. As shown in Figure 4, the sensor area AA has a plurality of optical sensors PAA arranged in a planar manner.
[0037] Specifically, the multiple optical sensors PAA are arranged in a matrix, for example, aligned in a first direction Dx and a second direction Dy. However, the arrangement is not limited to this, and the multiple optical sensors PAA may be arranged in a staggered pattern within the sensor area AA.
[0038] Each of the multiple light sensors PAA is equipped with a photodiode PD. Each photodiode PD outputs an electrical signal (potential) corresponding to the light irradiated upon it.
[0039] In this disclosure, the detection circuit 40 acquires detection values for each of the multiple optical sensors PAA, and combines the acquired detection values for each of the multiple optical sensors PAA to generate two-dimensional information indicating the shape of the surface irregularities of fingers, etc., and two-dimensional information indicating the shape of the blood vessels of fingers and palms (hereinafter also referred to as "image data").
[0040] The gate line GCL extends in the first direction Dx and is connected to multiple optical sensors PAA arranged in the first direction Dx. Furthermore, the multiple gate lines GCL(1), GCL(2), ..., GCL(8) are arranged in the second direction Dy and are each connected to the gate line drive circuit 15. In the following explanation, when it is not necessary to distinguish between the multiple gate lines GCL(1), GCL(2), ..., GCL(8), they will simply be referred to as gate line GCL. Also, while Figure 4 shows eight gate lines GCL for clarity, this is merely an example, and there may be M gate lines GCL (where M is a natural number, for example, M = 256) arranged.
[0041] The signal line SGL extends in the second direction Dy and is connected to the photodiode PD of multiple light sensors PAA arranged in the second direction Dy. The multiple signal lines SGL(1), SGL(2), ..., SGL(12) are arranged in the first direction Dx and are connected to the signal line selection circuit 16 and the reset circuit 17, respectively. In the following description, when it is not necessary to distinguish between the multiple signal lines SGL(1), SGL(2), ..., SGL(12), they will simply be referred to as signal line SGL.
[0042] Also, for the sake of easy understanding, 12 signal lines SGL are shown, but this is merely an example, and the signal lines SGL may be arranged in N (N is a natural number, for example, N = 2123) lines. Also, in FIG. 3, a sensor region AA is provided between the signal line selection circuit 16 and the reset circuit 17. However, the present invention is not limited to this, and the signal line selection circuit 16 and the reset circuit 17 may be connected to the ends of the signal lines SGL in the same direction, respectively.
[0043] The gate line driving circuit 15 receives various control signals such as a start signal STV, a clock signal CK, and a reset signal RST1 from a control circuit 102 (see FIG. 2). Based on the various control signals, the gate line driving circuit 15 sequentially selects a plurality of gate lines GCL(1), GCL(2),..., GCL(8) in a time-sharing manner. The gate line driving circuit 15 supplies a gate driving signal Vgcl to the selected gate line GCL. Thereby, the gate driving signal Vgcl is supplied to a plurality of first switching elements Tr connected to the gate line GCL, and a plurality of optical sensors PAA arranged in the first direction Dx are selected as detection targets.
[0044] The signal line selection circuit 16 includes a plurality of selection signal lines Lsel, a plurality of output signal lines Lout, and a third switching element TrS. The plurality of third switching elements TrS are provided corresponding to the plurality of signal lines SGL, respectively. Six signal lines SGL(1), SGL(2),..., SGL(6) are connected to a common output signal line Lout1. Six signal lines SGL(7), SGL(8),..., SGL(12) are connected to a common output signal line Lout2. The output signal lines Lout1 and Lout2 are connected to the AFE circuit 48, respectively.
[0045] Here, the signal lines SGL(1), SGL(2),..., SGL(6) are defined as a first signal line block, and the signal lines SGL(7), SGL(8),..., SGL(12) are defined as a second signal line block. The plurality of selection signal lines Lsel are respectively connected to the gates of the third switching elements TrS included in one signal line block. Also, one selection signal line Lsel is connected to the gates of the third switching elements TrS of the plurality of signal line blocks.
[0046] Specifically, the selection signal lines Lsel1, Lsel2, …, Lsel6 are each connected to a third switching element TrS corresponding to a signal line SGL(1), SGL(2), …, SGL(6). Further, the selection signal line Lsel1 is connected to a third switching element TrS corresponding to the signal line SGL(1) and a third switching element TrS corresponding to the signal line SGL(7). The selection signal line Lsel2 is connected to a third switching element TrS corresponding to the signal line SGL(2) and a third switching element TrS corresponding to the signal line SGL(8).
[0047] The control circuit 102 (see FIG. 2) sequentially supplies the selection signal ASW to the selection signal line Lsel. Thereby, the signal line selection circuit 16 sequentially selects the signal lines SGL in a time-division manner in one signal line block by the operation of the third switching element TrS. Further, the signal line selection circuit 16 selects one signal line SGL from each of a plurality of signal line blocks. With such a configuration, the number of ICs (Integrated Circuit) including the AFE circuit 48 or the number of terminals of the IC can be reduced.
[0048] As shown in FIG. 4, the reset circuit 17 includes a reference signal line Lvr, a reset signal line Lrst, and a fourth switching element TrR. The fourth switching element TrR is provided corresponding to a plurality of signal lines SGL. The reference signal line Lvr is connected to one of the sources or drains of the plurality of fourth switching elements TrR. The reset signal line Lrst is connected to the gates of the plurality of fourth switching elements TrR.
[0049] The control circuit 102 supplies the reset signal RST2 to the reset signal line Lrst. Thereby, the plurality of fourth switching elements TrR are turned on, and the plurality of signal lines SGL are electrically connected to the reference signal line Lvr. The power supply circuit 103 supplies the reference signal COM to the reference signal line Lvr. Thereby, the reference signal COM is supplied to the capacitive elements Ca (see FIG. 5) included in the plurality of optical sensors PAA.
[0050] Figure 5 is a circuit diagram showing multiple light sensors. Figure 5 also shows the circuit configuration of the AFE circuit 48. As shown in Figure 5, the light sensor PAA includes a photodiode PD, a capacitive element Ca, and a first switching element Tr1. The capacitive element Ca is the capacitance (sensor capacitance) formed on the photodiode PD and is equivalently connected in parallel with the photodiode PD. Furthermore, the signal line capacitance Cc is a parasitic capacitance formed on the signal line SGL and is equivalently formed between the signal line SGL and one end of the anode of the photodiode PD and the capacitive element Ca.
[0051] Figure 5 shows two adjacent gate lines GCL(m) and GCL(m+1) aligned in the second direction Dy, among multiple gate lines GCL. It also shows two adjacent signal lines SGL(n) and SGL(n+1) aligned in the first direction Dx, among multiple signal lines SGL. The optical sensor PAA is the region enclosed by the gate lines GCL and the signal lines SGL.
[0052] The first switching element Tr is provided in correspondence with the photodiode PD. The first switching element Tr is composed of a thin-film transistor, and in this example, it is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT (Thin Film Transistor).
[0053] The gates of the first switching elements Tr belonging to the multiple photosensors PAA arranged in the first direction Dx are connected to the gate line GCL. The sources of the first switching elements Tr belonging to the multiple photosensors PAA arranged in the second direction Dy are connected to the signal line SGL. The drains of the first switching elements Tr are connected to the cathode and capacitive element Ca of the photodiode PD.
[0054] The anode of the photodiode PD is supplied with a sensor power supply signal (potential) VDDSNS from the power supply circuit 103. The cathode of the photodiode PD is supplied with a reference signal COM from the power supply circuit 103, which is the initial potential of the signal line SGL and the capacitive element Ca.
[0055] When light is shone on the light sensor PAA, a current corresponding to the amount of light flows through the photodiode PD, and a charge corresponding to the amount of light accumulates in the capacitive element Ca. When the first switching element Tr is turned on, a current flows through the signal line SGL according to the charge accumulated in the capacitive element Ca. The signal line SGL is connected to the AFE circuit 48 via the third switching element TrS of the signal line selection circuit 16. This makes it possible to detect a signal corresponding to the amount of light shone on the photodiode PD for each light sensor PAA.
[0056] The AFE circuit 48 is connected to the signal line SGL when the switch SSW is turned on during the readout period Pdet (see Figure 6). The detection signal amplification circuit 42 of the AFE circuit 48 converts the current supplied from the signal line SGL into a voltage and amplifies it. A reference potential (Vref) with a fixed potential is input to the non-inverting input (+) of the detection signal amplification circuit 42, and the signal line SGL is connected to the inverting input terminal (-). In this embodiment, the same signal as the reference signal COM is input as the reference potential (Vref) voltage. The detection signal amplification circuit 42 also has a capacitive element Cb and a reset switch RSW. During the reset period Prst (see Figure 6), the reset switch RSW is turned on, and the charge of the capacitive element Cb is reset.
[0057] Next, an example of the operation of the detection device 1 will be described. Figure 6 is a timing waveform diagram showing an example of the operation of the detection device. As shown in Figure 6, the detection device 1 has a reset period Prst, an exposure period Pex, and a readout period Pdet. The power supply circuit 103 supplies the sensor power supply signal VDDSNS to the anode of the photodiode PD over the reset period Prst, the exposure period Pex, and the readout period Pdet. The sensor power supply signal VDDSNS is a signal that applies a reverse bias between the anode and cathode of the photodiode PD. For example, a reference signal COM of approximately 0.75V is applied to the cathode of the photodiode PD, and the sensor power supply signal VDDSNS of approximately -1.25V is applied to the anode, so that the anode-cathode is reverse-biased to approximately 2.0V. The control circuit 102 sets the reset signal RST2 to "H" and then supplies the start signal STV and the clock signal CK to the gate line drive circuit 15, and the reset period Prst begins. During the reset period Prst, the control circuit 102 supplies a reference signal COM to the reset circuit 17 and turns on the fourth switching element TrR, which supplies the reset voltage, in response to the reset signal RST2. As a result, the reference signal COM is supplied to each signal line SGL as the reset voltage. The reference signal COM is, for example, 0.75V.
[0058] During the reset period Prst, the gate line drive circuit 15 sequentially selects gate lines GCL based on the start signal STV, the clock signal CK, and the reset signal RST1. The gate line drive circuit 15 sequentially supplies gate drive signals Vgcl{Vgcl(1) to Vgcl(M)} to the gate lines GCL. The gate drive signals Vgcl have a pulse-like waveform with a high-level voltage, which is the power supply voltage VDD, and a low-level voltage, which is the power supply voltage VSS. In Figure 6, M gate lines GCL (for example, M = 256) are provided, and gate drive signals Vgcl(1), ..., Vgcl(M) are sequentially supplied to each gate line GCL, causing the multiple first switching elements Tr to conduct sequentially for each row, and a reset voltage is supplied. For example, the voltage of the reference signal COM, 0.75V, is supplied as the reset voltage.
[0059] As a result, during the reset period Prst, all capacitive elements Ca of the optical sensor PAA are sequentially electrically connected to the signal line SGL, and the reference signal COM is supplied. This resets the capacitance of the capacitive elements Ca. It is also possible to reset the capacitance of only some of the capacitive elements Ca of the optical sensor PAA by partially selecting the gate line and the signal line SGL.
[0060] Examples of exposure timing include the gate line non-selection exposure control method and the continuous exposure control method. In the gate line non-selection exposure control method, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to all gate lines GCL connected to the photodiode PD to be detected, and a reset voltage is supplied to all photodiodes PD to be detected. Subsequently, when all gate lines GCL connected to the photodiode PD to be detected reach a low voltage (the first switching element Tr is off), exposure begins, and exposure is performed during the exposure period Pex. When exposure is complete, as described above, gate drive signals {Vgcl(1) to (M)} are sequentially supplied to the gate lines GCL connected to the photodiode PD to be detected, and reading is performed during the readout period Pdet. In the continuous exposure control method, it is also possible to control exposure during the reset period Prst and the readout period Pdet (continuous exposure control). In this case, the exposure period Pex(1) begins after the gate drive signal Vgcl(1) is supplied to the gate lines GCL during the reset period Prst. Here, the exposure period Pex{(1)...(M)} is defined as the period during which the photodiode PD charges the capacitive element Ca. During the reset period Prst, the charge charged in the capacitive element Ca is reversed by light irradiation, causing a current to flow in the photodiode PD in the reverse direction (from cathode to anode), and the potential difference of the capacitive element Ca decreases. Note that the actual exposure periods Pex(1), ..., Pex(M) for the photosensor PAA corresponding to each gate line GCL have different start and end timings. Each exposure period Pex(1), ..., Pex(M) starts during the reset period Prst when the gate drive signal Vgcl changes from the high-level power supply voltage VDD to the low-level power supply voltage VSS. Each exposure period Pex(1), ..., Pex(M) ends during the readout period Pdet when the gate drive signal Vgcl changes from the power supply voltage VSS to the power supply voltage VDD. The exposure times for each exposure period Pex(1), ..., Pex(M) are equal.
[0061] In the gate line non-selection exposure control method, during the exposure period Pex {(1)...(M)}, a current flows in each photosensor PAA in accordance with the light irradiated onto the photodiode PD. As a result, charge accumulates in each capacitive element Ca.
[0062] Before the start of the readout period Pdet, the control circuit 102 lowers the reset signal RST2 to a low voltage. This stops the operation of the reset circuit 17. The reset signal may be at a high voltage only during the reset period Prst. During the readout period Pdet, similar to the reset period Prst, the gate line drive circuit 15 sequentially supplies gate drive signals Vgcl(1), ..., Vgcl(M) to the gate line GCL.
[0063] Specifically, the gate line drive circuit 15 supplies a gate drive signal Vgcl(1) with a high-level voltage (power supply voltage VDD) to the gate line GCL(1) during period V(1). The control circuit 102 sequentially supplies selection signals ASW1, ..., ASW6 to the signal line selection circuit 16 during the period when the gate drive signal Vgcl(1) is at a high-level voltage (power supply voltage VDD). As a result, the signal lines SGL of the optical sensors PAA selected by the gate drive signal Vgcl(1) are connected to the AFE circuit 48 sequentially or simultaneously. Consequently, a detection signal Vdet is supplied to the AFE circuit 48 for each optical sensor PAA.
[0064] Similarly, the gate line drive circuit 15 supplies high-level voltage gate drive signals Vgcl(2), ..., Vgcl(M-1), and Vgcl(M) to the gate lines GCL(2), ..., GCL(M-1), and GCL(M), respectively, during periods V(2), ..., V(M-1), and V(M). That is, the gate line drive circuit 15 supplies the gate drive signal Vgcl to the gate line GCL for each period V(1), V(2), ..., V(M-1), and V(M). For each period when each gate drive signal Vgcl is at a high-level voltage, the signal line selection circuit 16 sequentially selects the signal line SGL based on the selection signal ASW. The signal line selection circuit 16 sequentially connects each signal line SGL to one AFE circuit 48. As a result, during the readout period Pdet, the detection device 1 can output the detection signals Vdet of all optical sensors PAA to the AFE circuit 48.
[0065] Figure 7 is a timing waveform diagram showing an example of operation during the readout period in Figure 6. The following explanation will refer to Figure 7 to describe an example of operation for one gate drive signal Vgcl(j) during the Readout period in Figure 6. In Figure 6, the first gate drive signal Vgcl(1) is labeled with the Readout sign, and the same applies to the other gate drive signals Vgcl(2), ..., Vgcl(M). j is a natural number from 1 to M.
[0066] As shown in Figures 7 and 5, the output voltage (Vout) of the third switching element TrS is reset to a reference potential (Vref) voltage. The reference potential (Vref) voltage is the reset voltage, for example, 0.75V. Next, the gate drive signal Vgcl(j) goes high, the first switching element Tr of that row turns on, and the signal line SGL of each row becomes a voltage corresponding to the charge stored in the capacitance (capacitive element Ca) of the optical sensor PAA. After a period t1 has elapsed from the rising edge of the gate drive signal Vgcl(j), a period t2 occurs in which the selection signal ASW(k) goes high. When the selection signal ASW(k) goes high and the third switching element TrS turns on, the output voltage (Vout) of the third switching element TrS (see Figure 5) changes to a voltage corresponding to the charge stored in the capacitance (capacitance element Ca) of the photosensor PAA connected to the AFE circuit 48 via the third switching element TrS (period t3). In the example in Figure 7, this voltage is lower than the reset voltage, as shown in period t3. Subsequently, when the switch SSW turns on (period t4, when the SSW signal is high level), the charge stored in the capacitance (capacitance element Ca) of the photosensor PAA moves to the capacitance (capacitance element Cb) of the detection signal amplification circuit 42 of the AFE circuit 48, and the output voltage of the detection signal amplification circuit 42 becomes a voltage corresponding to the charge stored in the capacitance element Cb. At this time, the inverting input of the detection signal amplification circuit 42 becomes an imaginary short-circuit potential of the operational amplifier, and returns to the reference potential (Vref). The output voltage of the detection signal amplification circuit 42 is read out by the A / D conversion circuit 43. In the example in Figure 7, when the waveforms of the selection signals ASW(k), ASW(k+1), ... corresponding to the signal lines SGL of each column go high, the third switching element TrS is turned on sequentially, and by performing the same operation sequentially, the charge accumulated in the capacitance (capacitance element Ca) of the optical sensor PAA connected to the gate line GCL is read out sequentially. Note that ASW(k), ASW(k+1), ... in Figure 7 are, for example, any of ASW1 to ASW6 in Figure 4.
[0067] Specifically, when the switch SSW is ON for a period t4, charge moves from the capacitance of the optical sensor PAA (capacitive element Ca) to the capacitance of the detection signal amplification circuit 42 of the AFE circuit 48 (capacitive element Cb). At this time, the non-inverting input (+) of the detection signal amplification circuit 42 is biased to a reference potential (Vref) voltage (for example, 0.75 [V]). Therefore, due to an imaginary short circuit between the inputs of the detection signal amplification circuit 42, the output voltage (Vout) of the third switching element TrS also becomes the reference potential (Vref) voltage. In addition, the voltage of the capacitive element Cb becomes a voltage corresponding to the charge accumulated in the capacitance of the optical sensor PAA (capacitive element Ca) at the point where the third switching element TrS is turned ON according to the selection signal ASW(k). The output voltage of the detection signal amplification circuit 42 becomes a voltage corresponding to the capacitance of the capacitive element Cb after the output voltage (Vout) of the third switching element TrS becomes the reference potential (Vref) voltage due to the imaginary short circuit, and this output voltage is read by the A / D conversion circuit 43. The voltage of the capacitive element Cb is, for example, the voltage between the two electrodes provided in the capacitor that constitutes the capacitive element Cb.
[0068] For example, period t1 is 20 [μs]. Period t2 is 60 [μs]. Period t3 is 44.7 [μs]. Period t4 is 0.98 [μs].
[0069] Figures 6 and 7 show an example in which the gate line drive circuit 15 individually selects gate lines GCL, but the circuit is not limited to this. The gate line drive circuit 15 may simultaneously select two or more predetermined gate lines GCL and sequentially supply a gate drive signal Vgcl for each predetermined number of gate lines GCL. The signal line selection circuit 16 may also simultaneously connect two or more predetermined signal lines SGL to a single AFE circuit 48. Furthermore, the gate line drive circuit 15 may scan by thinning out multiple gate lines GCL.
[0070] Figures 8A, 8B, and 8C are schematic diagrams showing the relationship between light intensity, which indicates the intensity of light emitted from the backlight, and the detected value acquired by the detection circuit. In Figures 8A, 8B, and 8C, the horizontal axis represents the light intensity, which indicates the intensity of light emitted from the backlight 121, and the vertical axis represents the detected value acquired by the detection circuit 40.
[0071] As described above, in the configuration of the detection device 1 according to the embodiment, the device may be affected by direct light emitted from the backlight 121. Let AL be the component due to direct light emitted from the backlight 121 (direct light component), and ARL be the component due to reflected light when the reflectance from the object to be detected is R (0 ≤ R ≤ 1). When the detection value (≒0) at a light intensity of 0 (when the backlight 121 is turned off) is used as a reference, the detection value ca is expressed by the following equation (1).
[0072] ca=AL+ARL=AL(1+R)...(1)
[0073] In the examples shown in Figures 8A and 8B, c1 is defined as the difference between the detected value ca1 obtained at light intensity a1 and the detected value ca2 obtained at light intensity a2. As shown in Figure 8A, when light intensities a1 and a2 are small, it is necessary to set a longer exposure time, which may cause blurring of the generated image data (blurring over time due to the displacement of the detected object) and a decrease in resolution. As shown in Figure 8B, when light intensities a1 and a2 are increased, the exposure time in the sensor area AA is shortened, and a high-resolution image with the effects of body movement suppressed can be obtained.
[0074] Furthermore, as the light intensities a1 and a2 are increased, the detected value ca1 obtained at intensity a1 and the detected value ca2 obtained at light intensity a2 become a constant c0 (hereinafter also referred to as the "maximum detected value c0"), as shown in Figure 8C. This indicates that each detected value ca1 and ca2 becomes the maximum detected value c0 due to a constant direct light component AL that does not depend on the reflectance of the object being detected. The maximum detected value c0 is given by equation (2) below.
[0075] c0 ≈ AL ... (2)
[0076] Here, let Ra and Rb be the reflectances at points a and b of the object being detected, respectively, and let caa and cab be the detected values at points a and b, respectively. Then, the contrast CRab(0) between the two points a and b, with reference to the detected value at light intensity 0 (≒0), is given by equation (3) below.
[0077] CRab(0)=caa / cab=AL(1+Ra) / AL(1+Rb)=(1+Ra) / (1+Rb)...(3)
[0078] On the other hand, when the detected value c1 is taken as the reference value from the maximum detected value c0, the detected value c1 is expressed by the following equation (4).
[0079] c1=ca-c0=(AL+ARL)-c0=ARL{1+(AL-c0) / ARL}...(4)
[0080] Applying equation (2) above to equation (4) above, we obtain equation (5) below: c1 ≈ ARL ... (5)
[0081] In this case, the contrast CRab(c0) between two different points a and b on the object to be detected is given by equation (6) below.
[0082] CRab(c0)=c1a / c1b=ALRa / ALRb=Ra / Rb...(6)
[0083] As shown in equation (6) above, the contrast CRab(c0) relative to the maximum detection value c0 is expressed as the ratio of the reflectances Ra and Rb at each point. In contrast, the contrast CRab(0) relative to the detection value at light intensity 0 (≒0) is expressed as the ratio of the reflectances Ra and Rb at each point plus 1, as shown in equation (3) above. The relationship between the magnitude of the contrast CRab(c0) relative to the maximum detection value c0 and the magnitude of the contrast CRab(0) relative to the detection value at light intensity 0 (≒0) is given by equation (7) below, when 0 < Rb < Ra < 1.
[0084] CRab(0)=(1+Ra) / (1+Rb)<Ra / Rb=CRab(c0)...(7)
[0085] As shown in equation (7) above, by calculating the detection value c1 based on the detection maximum value c0 and using this as image generation data for each of the multiple optical sensors PAA, high-contrast image data can be obtained.
[0086] Furthermore, by acquiring the detection value when the light intensity irradiated from the backlight 121 is relatively high, the exposure time can be shortened. As a result, a high-resolution image with the effects of body movement suppressed can be obtained.
[0087] In this embodiment, during the initial setup process before executing the detection operation of the object to be detected, the detection upper limit c0 in the detection circuit 40 and the setting value of the light intensity irradiated from the backlight 121 when executing the detection operation of the object to be detected (hereinafter also simply referred to as the "light intensity setting value") a_set are set. The initial setup process in the detection device 1 according to this embodiment will be described below.
[0088] Figure 9 is a flowchart showing an example of the initial setup process in the detection device according to the embodiment. As described above, the initial setup process shown in Figure 9 is performed before the detection operation of the object to be detected is executed. Specifically, the initial setup process in the detection device 1 according to the embodiment includes a detection upper limit setting process (step S100) and a light intensity setting process (step S200).
[0089] Figure 10 is a subflowchart showing an example of the detection upper limit setting process. In the detection upper limit setting process shown in Figure 10, the light intensity a is increased by Δa1 increments, and the detection value b at which the change in the detected value b |b - b'| becomes less than a small value Δb even when the light intensity a is increased by Δa1 is obtained as the detection upper limit c0.
[0090] In the detection upper limit setting process shown in Figure 10, the control circuit 102 initializes the light intensity a irradiated from the backlight 121 (a = a0, step S101) and obtains the detected value b at light intensity a (first light intensity) (step S102). Here, the detected value b may be the average value of the detected values for each of the multiple light sensors PAA within the sensor area AA, or it may be a representative value of the detected values for each of the multiple light sensors PAA within the sensor area AA.
[0091] Next, the control circuit 102 determines whether the difference between the detected value b (second detected value) at light intensity a (second light intensity) and the previous value b' (first detected value) at light intensity a - Δa1 (first light intensity) is greater than or equal to a small value Δb (step S103). Here, Δa1 is the range of change in light intensity a during the detection upper limit setting process.
[0092] Then, if the difference between the detected value b (second detected value) and the previous value b' (first detected value) is greater than or equal to a small value Δb (|b - b'| ≥ Δb, step S103; Yes), the control circuit 102 sets the detected value b (second detected value) to the previous value b' (first detected value), adds Δa1 to the light intensity a irradiated from the backlight 121 (b' = b, a = a + Δa1, step S104), and repeatedly executes the process from step S102 onward.
[0093] When the difference between the detected value b (second detected value) and the previous value b' (first detected value) becomes less than a small value Δb (|b - b'| < Δb, step S103; No), it is assumed that the detected value b (first detected value) has reached the detection upper limit c0. At this time, the control circuit 102 sets the detected value b (second detected value) as the detection upper limit c0 in the detection circuit 40 (c0 = b, step S105), and returns to the initial setup process shown in Figure 9.
[0094] Figure 11 is a subflowchart showing an example of the light intensity setting process. In the light intensity setting process shown in Figure 11, the light intensity a is decreased by Δa2 (<Δa1) in increments, and the light intensity a at which the change in the detected value b |b - b'| becomes greater than or equal to a small value Δb when the light intensity a is decreased by Δa2 is obtained as the light intensity setting value a_set when the detection operation of the object to be detected is performed.
[0095] The light intensity setting process shown in Figure 11 is executed after the detection upper limit setting process shown in Figure 10. In the light intensity setting process shown in Figure 11, the control circuit 102 reduces the light intensity a irradiated from the backlight 121 by Δa2 (a = a - Δa2, step S201) to obtain the detected value b (fourth detected value) (step S202). Here, Δa2 is the range of change of light intensity a in the light intensity setting process, and is a small value relatively small compared to the range of change of light intensity a Δa1 in the detection upper limit setting process.
[0096] Next, the control circuit 102 determines whether the difference between the detected value b (fourth detected value) at light intensity a (fourth light intensity) and the previous value b' (third detected value) at light intensity a + Δa2 (third light intensity) is less than a small value Δb (step S203).
[0097] If the difference between the detected value b (fourth detected value) and the previous value b' (third detected value) is less than a small value Δb (|b - b'| < Δb, step S203; Yes), the control circuit 102 sets the detected value b (fourth detected value) to the previous value b' (third detected value) (b' = b, step S204), and repeatedly executes the processes from step S201 onwards.
[0098] Then, when the difference between the detected value b (fourth detected value) and the previous value b' (third detected value) becomes a small value Δb or greater (|b - b'| ≥ Δb, step S203; No), the control circuit 102 sets the light intensity a (fourth light intensity) as the light intensity setting value a_set when executing the detection operation of the object to be detected (a_set = a, step S205), and returns to the initial setup process shown in Figure 9.
[0099] Here, we will explain a specific example of the operation in the initial setup process shown in Figure 9. Figure 12 is a schematic diagram illustrating the operation in the initial setup process.
[0100] In the detection upper limit setting process shown in Figure 10, after initializing the light intensity a emitted from the backlight 121 (a = a0, step S101), the control circuit 102 increases the light intensity a emitted from the backlight 121 by Δa1 until the difference between the detected value b (first detected value) and the previous value b' (second detected value) becomes less than a small value Δb (in the example shown in Figure 12, up to Fn + 3 frames).
[0101] Then, when the difference between the detected value b (second detected value) and the previous value b' (first detected value) becomes less than a small value Δb (|b - b'| < Δb, step S103; No), the control circuit 102 sets the detected value b (second detected value) as the upper detection limit c0 in the detection circuit 40 (step S105).
[0102] After executing the detection upper limit setting process shown in Figure 10, in the light intensity setting process shown in Figure 11, the control circuit 102 decreases the light intensity a irradiated from the backlight 121 by Δa2 until the difference between the detected value b (fourth detected value) and the previous value b' (third detected value) becomes a small value Δb or more (up to Fn+6 frames in the example shown in Figure 12).
[0103] When the difference between the detected value b (fourth detected value) and the previous value b' (third detected value) becomes a small value Δb or greater (|b - b'| ≥ Δb, step S203; No), the control circuit 102 sets the light intensity a (fourth light intensity) as the light intensity setting value a_set when performing the detection operation of the object to be detected (a_set = a, step S205).
[0104] It is desirable that Δa2 be a small value that does not affect the judgment accuracy in step S203. Specifically, for example, Δa2 is set to a value such that the detected value b acquired in the Fn+6 frame shown in Figure 12 is 90% or more of the detection upper limit c0.
[0105] In the above explanation, in the detection upper limit setting process shown in Figure 10, when the difference between the detected value b (second detected value) and the previous value b' (first detected value) becomes less than a small value Δb (|b - b'| < Δb, step S103; No), the detected value b (second detected value) is set as the detection upper limit c0 in the detection circuit 40 (step S105). However, it is also possible to set the previous value b' (first detected value) of the detected value as the detection upper limit c0 in the detection circuit 40.
[0106] Figure 13 is a flowchart showing an example of the detection process in the detection device according to the embodiment. As a prerequisite for the detection process shown in Figure 13, the detection upper limit value c0 and the light intensity setting value a_set, which were acquired in advance in the initial setup process described above, are set. The detection upper limit value c0 and the light intensity setting value a_set are stored, for example, in the memory circuit 46 of the detection circuit 40.
[0107] In the detection process shown in Figure 13, the control circuit 102 (detection control circuit 11) controls the light source 123 by applying the light intensity setting value a_set set in the initial setup process described above (a = a_set; step S301).
[0108] The signal processing circuit 44 acquires the detection value b for each of the multiple optical sensors PAA (step S302), and generates image generation data for each of the multiple optical sensors PAA based on the detection upper limit c0. More specifically, it calculates the difference between the detection value b acquired for each of the multiple optical sensors PAA and the detection upper limit c0 as image generation data for each of the multiple optical sensors PAA (c1 = b - c0, step S303). Thereafter, the process in step S302 is repeatedly executed.
[0109] This allows for the acquisition of high-contrast image data. Furthermore, it enables shorter exposure times, resulting in high-resolution image data with reduced effects from body movement.
[0110] In the embodiments described above, an example was given of acquiring image data such as vascular patterns, including veins, as vital data. However, the scope of application of the detection device 1 according to this disclosure is not limited to this, and it can be broadly applied to configurations that acquire various types of vital data.
[0111] Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each of the embodiments described above.
[0112] 1 Detection device 2 Array substrate 7 Light guide section 11 Detection control circuit 15 Gate line drive circuit 16 Signal line selection circuit 21 Sensor substrate 40 Detection circuit 42 Detection signal amplification circuit 43 A / D conversion circuit 44 Signal processing circuit 46 Memory circuit 47 Detection timing control circuit 48 AFE circuit 102 Control circuit 103 Power supply circuit 121 Backlight 122 Light guide plate 123 Light source AA Sensor area PAA Light sensor PD Photodiode
Claims
1. A detection device comprising: a sensor area on which multiple light sensors are arranged; a backlight positioned opposite to the back of a substrate on which the sensor area is provided, and which transmits light through the sensor area to illuminate an object to be detected; a detection circuit that generates an image of the object to be detected based on each detection value acquired by the multiple light sensors; and a control circuit that controls the backlight and the detection circuit, wherein the detection circuit has a preset detection upper limit value that can be detected by the detection circuit and a preset light intensity value for the backlight, and controls the backlight by applying the preset light intensity value, and calculates the difference between each detection value acquired for each of the multiple light sensors and the preset detection upper limit value as image generation data.
2. The detection device according to claim 1, wherein the detection upper limit is a detection value that is substantially constant regardless of the light intensity irradiated from the backlight, and the light intensity setting value is a value such that the maximum value of the detection value acquired in the sensor area is 90% or more of the detection upper limit.
3. The detection device according to claim 1, wherein the control circuit increases the light intensity irradiated onto the sensor area by a predetermined range of change, and sets the first detected value or the second detected value as the detection upper limit value when the difference between the first detected value obtained when the backlight is controlled by applying a first light intensity and the second detected value obtained when the backlight is controlled by applying a second light intensity greater than the first light intensity becomes less than a predetermined value.
4. The detection device according to claim 3, wherein the control circuit, after setting the detection upper limit, reduces the light intensity irradiated onto the sensor area by a predetermined range of change, and sets the fourth light intensity as the light intensity setting value when the difference between the third detection value obtained when the backlight is controlled by applying the third light intensity and the fourth detection value obtained when the backlight is controlled by applying a fourth light intensity smaller than the third light intensity becomes greater than or equal to a predetermined value.
5. The detection device according to claim 4, wherein the range of change in the light intensity irradiated onto the sensor area when setting the light intensity setting value is relatively small compared to the range of change in the light intensity irradiated onto the sensor area when setting the detection upper limit value.
6. The detection device according to any one of claims 1 to 5, wherein the sensor area comprises a plurality of optical sensors arranged in a matrix along a first direction and a second direction intersecting the first direction.
7. The detection device according to claim 6, wherein each of the multiple light sensors includes a photodiode.
8. The detection device according to claim 7, wherein the photodiode is an OPD (Organic Photodiode).