Semiconductor package
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-12-23
- Publication Date
- 2026-08-13
Smart Images
Figure JP2025045170_13082026_PF_FP_ABST
Abstract
Description
Semiconductor Package Cross - Reference to Related Applications
[0001] This application is based on Japanese Patent Application No. 2025 - 19443 filed in Japan on February 7, 2025, and the content of the base application is incorporated herein by reference in its entirety.
[0002] The disclosure in this specification relates to a semiconductor package.
[0003] Patent Document 1 discloses a semiconductor package. The description of the prior art document is incorporated herein by reference as an explanation of the technical elements in this specification.
[0004] Korean Registered Patent Publication No. 10 - 1674537
[0005] In Patent Document 1, first, the lead frame is etched from the back side to form a first groove, and the first groove is filled with a first resin. Then, after plating on both the front and back sides, the lead frame is etched from the non - plated part on the front side to form a second groove, for example, reaching the first groove. Thereby, the lead frame is partitioned into a plurality of small pieces. Next, after bonding a semiconductor chip to the die pad part among the small pieces, the front side is sealed with a second resin so as to cover the semiconductor chip while filling the second groove.
[0006] Thus, the semiconductor package of Patent Document 1 has a characteristic structure in which the first groove opening on the back side of the lead frame is filled with the first resin, and the second groove opening on the front side and reaching the first groove is filled with the second resin. In such a structure, solder may wet - spread over the plated layer provided on the entire front side and fall into the second groove. The falling of the solder may cause a decrease in the reliability of the semiconductor package. For example, migration may occur due to the fallen solder, and there is a risk of short - circuit between the die pad part and other small pieces. For example, the fallen solder may be interposed between the first resin and the second resin, and there is a risk of peeling of the second resin. From the above viewpoints or other viewpoints not mentioned, further improvement of the semiconductor package is required.
[0007] One of the purposes of this disclosure is to provide a semiconductor package that can improve reliability.
[0008] A semiconductor package in one aspect of the disclosure comprises a lead frame having a first groove opening on the back surface, a second groove opening on one surface opposite to the back surface and reaching the first groove, and a plurality of small pieces partitioned by the first groove and the second groove, including a die pad portion and a lead portion; a semiconductor chip disposed on one surface of the die pad portion and soldered to the die pad portion; a first resin portion filled in the first groove; a second resin portion formed using a different material from the first resin portion, filled in the second groove and in contact with the first resin portion, and sealing one surface of the lead frame so as to cover the semiconductor chip; and a plating portion laminated in the order of Ni, Pd, and Au, and disposed on one surface and the back surface, wherein the plating portion is provided only on a portion of the die pad portion including the solder joint portion of the semiconductor chip.
[0009] According to the disclosed semiconductor package, the plated portion is provided only on a part of the die pad portion, limiting the wetting and spreading of solder. Therefore, compared to a configuration in which the plated portion is provided on the entire surface of one side of the die pad portion, it is possible to suppress solder falling into the second groove portion and, consequently, improve reliability.
[0010] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings.
[0011] This is a plan view showing an example of a semiconductor package according to the first embodiment. This is a cross-sectional view along the line II-II in Figure 1. This is a diagram showing the arrangement of plated parts on one surface. This is a diagram showing the positional relationship between the die pad, plated parts, and semiconductor chip. This is a cross-sectional view showing a method for manufacturing a semiconductor package. This is a cross-sectional view showing a method for manufacturing a semiconductor package. This is a diagram showing a modified example. This is a plan view showing a modified example. This is a cross-sectional view corresponding to the line IX-IX in Figure 8. This is a diagram showing a modified example. This is a cross-sectional view showing an example of a semiconductor package according to the second embodiment. This is a diagram showing the arrangement of plated parts on one surface. This is a cross-sectional view showing a method for manufacturing a semiconductor package. This is a cross-sectional view showing an example of a semiconductor package according to the third embodiment. This is a cross-sectional view showing another example of a semiconductor package. This is a cross-sectional view showing an example of a semiconductor package according to the fourth embodiment.
[0012] Several embodiments will be described below with reference to the drawings. In each embodiment, the same reference numerals are used for corresponding components, and redundant explanations may be omitted. If only a part of the configuration is described in each embodiment, the configuration of other embodiments described earlier can be applied to the other parts of that configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations from multiple embodiments can be partially combined even if not explicitly stated, as long as there are no particular problems with the combination.
[0013] (First Embodiment) First, the semiconductor package according to this embodiment will be described.
[0014] <Semiconductor Package> Figure 1 is a plan view showing an example of a semiconductor package. Figure 1 is a plan view seen from one side. Figure 2 is a cross-sectional view along the line II-II in Figure 1. Figure 3 is a perspective view showing the arrangement of the plated portion on one surface. Figure 3 is a view seen from the Z1 direction shown in Figure 2. Figure 3 shows the structure below one surface, including the plated portion. For the second resin portion, the portion below the position flush with the first surface, shown by the dashed line, is shown. Figure 4 is a cross-sectional view showing the positional relationship between the die pad portion, the plated portion, and the semiconductor chip. Figure 4 is a view in which the second resin portion and bonding wire are omitted compared to Figure 2.
[0015] In the following, the thickness direction of the lead frame is defined as the Z direction. The direction perpendicular to the Z direction is defined as the X direction. The direction perpendicular to both the Z and X directions is defined as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape. The view from the Z direction is sometimes simply referred to as the planar view.
[0016] As shown in Figures 1 to 4, the semiconductor package 10 comprises a lead frame 20, a semiconductor chip 30, a first resin part 40, a second resin part 50, and a plated part 60. The semiconductor package 10 further comprises solder 70 and bonding wires 71.
[0017] The semiconductor package 10 is formed by resin-encapsulating a semiconductor chip 30 arranged on one surface of a lead frame 20. The semiconductor package 10 is sometimes referred to as a semiconductor device or electronic device. The semiconductor package 10 has a QFN-type leadless package structure. QFN is an abbreviation for Quad Flat Non lead package. The example semiconductor package 10 has a planar, approximately rectangular shape.
[0018] The lead frame 20 is made by processing a plate material of a predetermined thickness made of a metal with good conductivity, such as Cu or a Cu alloy. At least a portion of the lead frame 20 provides a wiring function. At least a portion of the lead frame 20 may also provide a heat dissipation function. At least a portion of the lead frame may also provide a reinforcement function. The example lead frame 20 has one surface 20a and one surface 20b. The surface 20b is the surface opposite to the one surface 20a in the Z direction, which is the thickness direction of the plate. The lead frame 20 includes a die pad portion 21, a lead portion 22, a first groove portion 23, and a second groove portion 24.
[0019] The die pad section 21 is the part of the lead frame 20 where other elements constituting the circuit are mounted, and where the circuit elements are soldered. The die pad section 21 supports the circuit elements fixed via solder 70. The die pad section 21 is sometimes referred to as an island.
[0020] The die pad portion 21 in the example is a portion that supports the semiconductor chip 30 fixed via solder 70. The die pad portion 21 has a substantially rectangular planar shape with sides along the X direction and sides along the Y direction. The lead frame 20 has only one die pad portion 21. However, it is not limited to this, and the lead frame 20 may have multiple die pad portions 21. In addition to the die pad portion 21, the lead frame 20 may also have die pad portions to which the semiconductor chip is bonded and fixed, for example, by Ag paste, die bonding film, etc.
[0021] The lead portion 22 is a terminal portion in the lead frame 20 that electrically connects a circuit element to an external device. In other words, the lead portion 22 is an external connection terminal. The example lead portion 22 is electrically connected to the semiconductor chip 30. The lead frame 20 has a plurality of lead portions 22. The lead portions 22 are electrically connected to the semiconductor chip 30 via bonding wires 71. Multiple lead portions 22 are provided for each of the four sides of the die pad portion 21. The plurality of lead portions 22 are arranged along the corresponding sides. The lead portions 22 have a substantially rectangular shape in plan with the direction of arrangement being the shorter side.
[0022] The first groove 23 and the second groove 24 are sometimes referred to as trenches. The first groove 23 opens to the back surface 20b of the lead frame 20 and has a predetermined depth that does not reach one surface 20a. The second groove 24 opens to one surface 20a of the lead frame 20 and has a predetermined depth that does not reach the back surface 20b. The second groove 24 is provided so as to reach the first groove 23. The second groove 24 is provided so as to communicate with the first groove 23. The second groove 24 is formed with the first resin portion 40 filled in the first groove 23 as its bottom. The second groove 24 is provided so as to expose a part of the first resin portion 40 to the side facing one surface 20a.
[0023] The lead frame 20 is divided into a plurality of small sections by a first groove 23 and a second groove 24. The plurality of small sections include the die pad portion 21 and the plurality of lead portions 22 described above. The exemplary first groove 23 is provided so as to overlap with the portion including the space between the die pad portion 21 and the lead portion 22 in a plan view in the Z direction. The first groove 23 is provided so as to overlap with the portion including the space between adjacent lead portions 22. The first groove 23 is provided so as to overlap with the outer peripheral edge of the die pad portion 21 in a plan view. The first groove 23 is provided so as to overlap with a part of the lead portion 22 in a plan view. As a result, the die pad portion 21 and the lead portion 22 have a thin-walled portion and a thick-walled portion, with the thickness reduced by the first groove 23. The second groove 24 is provided so as to overlap with the portion between the die pad portion 21 and the lead portion 22 in a plan view in the Z direction. The second groove 24 is provided so as to overlap with the portion between adjacent lead portions 22.
[0024] The semiconductor chip 30 is placed on one surface 20a of the die pad portion 21 and fixed to the die pad portion 21 via solder 70. The semiconductor chip 30 is solder-bonded to the die pad portion 21. The semiconductor chip 30 has a metal film (not shown) on the surface facing the one surface 20a. The semiconductor chip 30 may be an IC chip, for example, an ASIC chip. ASIC is an abbreviation for Application Specific Integrated Circuit. The semiconductor chip 30 may also be a vertical element in which MOSFETs, IGBTs, etc. are formed so that current flows in the Z direction. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.
[0025] The example semiconductor chip 30 is an ASIC chip. The semiconductor chip 30 is soldered to a die pad portion 21 that provides, for example, a ground potential. The semiconductor chip 30 is soldered to a die pad portion 21 that provides, for example, a heat dissipation function. The semiconductor chip 30 has a plurality of pads (not shown) on the side opposite to the side facing the die pad portion 21. Each pad is electrically connected to a corresponding lead portion 22 via a bonding wire 71.
[0026] The first resin part 40 is formed using an electrically insulating resin material. The first resin part 40 is filled into the first groove 23. The first resin part 40 fills the first groove 23. The first resin part 40 is positioned relative to the lead frame 20 such that a predetermined portion of the back surface 20b is exposed. In the example, the first resin part 40 is filled into the first groove 23 so as to be substantially flush with the back surface 20b. In plan view, a part of the first resin part 40 overlaps with the thin-walled portion of the die pad portion 21, and another part overlaps with the thin-walled portion of the lead portion 22. The first resin part 40 integrally holds multiple small pieces of the lead frame 20 while electrically separating them from each other. The first resin part 40 mechanically connects the multiple small pieces. The first resin part 40 reinforces the lead frame 20.
[0027] The second resin part 50 is formed using a different resin material than the first resin part 40. The second resin part 50 has a different coefficient of thermal expansion than the first resin part 40. The second resin part 50 is filled in the second groove 24 and is in contact with the first resin part 40. The second resin part 50 is in close contact with the first resin part 40 within the communication region formed by the first groove 23 and the second groove 24. The second resin part 50 seals one side 20a of the lead frame 20 so as to cover the semiconductor chip 30. The second resin part 50 is a sealing resin body that seals the semiconductor chip 30. In the example, the second resin part 50 seals the semiconductor chip 30, the plated part 601, the solder 70, and the bonding wire 71 on each side 20a. For example, the second resin part 50 is formed using epoxy, and the first resin part 40 is formed using polyimide.
[0028] The plated portion 60 is a PPF plated portion with layers of Ni, Pd, and Au stacked in that order. PPF is an abbreviation for Palladium Preplated Frame. The plated portion 60 includes at least three layers: a Ni layer, a Pd layer, and an Au layer. The Pd layer functions as a barrier against the diffusion of Au, allowing the thickness of the Au layer to be reduced. The plated portion 60 is located on one surface 20a and the back surface 20b. The plated portion 60 has a plated portion 601 provided on one surface 20a and a plated portion 602 provided on the back surface 20b. The plated portion 601 is provided on only a part of the one surface 20a. The plated portion 602 is provided on the entire back surface 20b.
[0029] In the example, the plated portion 601 is provided only on a portion of one surface 20a of the die pad portion 21, including the solder joint portion where the semiconductor chip 30 is soldered. The plated portion 601 is provided only on a portion of one surface 20a of the lead portion 22, including the portion where the bonding wire 71 is joined. The plated portion 601 is provided on one surface 20a of the die pad portion 21, at a position away from the end portion 211 adjacent to the second groove portion 24. The end portion 211 is the end of one surface 20a of the die pad portion 21.
[0030] As described above, the plated portion 60 is partially provided on one surface 20a of the lead frame 20. The semiconductor package 10 includes an unplated portion 61 on one surface 20a where the plated portion 60 is not provided. The unplated portion 61 is provided adjacent to the plated portion 601. In the example die pad portion 21, the unplated portion 61 surrounds the plated portion 601. The plated portion 601 is provided in the central part of the die pad portion 21, which has a substantially rectangular shape in plan. The unplated portion 61 is provided in the outer periphery adjacent to the central part and surrounding the central part. As shown in Figures 2 to 4, the size relationship in plan view is semiconductor chip 30 < plated portion 601 < die pad portion 21.
[0031] In the semiconductor package 10, the surface roughness of the plated portion 60 differs between one side 20a and the back side 20b. The surface roughness of the plated portion 60 is rougher on one side 20a than on the back side 20b. The plated portion 601 is roughened. For example, the roughness Sa of the plated portion 60 is greater on one side 20a than on the back side 20b. Roughness Sa is the arithmetic mean height. Roughness Sa is a parameter that indicates the average roughness of a surface in three-dimensional space. Roughness Sa can be measured, for example, by a laser microscope or AFM. AFM is an abbreviation for Atomic Force Microscope.
[0032] In the example semiconductor package 10, the roughness Sa of the plated portion 601 is in the range of 1.2 to 2.0. The roughness Sa of the plated portion 602 is smaller than the roughness Sa of the plated portion 601. The roughness Sa of the plated portion 602 is, for example, about 1.0.
[0033] <Method for Manufacturing Semiconductor Modules> Figures 5 and 6 show the method for manufacturing the exemplified semiconductor package. Figures 5 and 6 correspond to Figure 2.
[0034] First, as shown in Figure 5(a), a lead frame 20 is prepared. This lead frame 20 is in its pre-processed state, having a structure with multiple small pieces.
[0035] Next, as shown in Figure 5(b), the lead frame 20 is etched from the back surface 20b side to form the first groove 23. The etching creates the first groove 23, which opens at a predetermined position on the back surface 20b and has a predetermined depth that does not reach the surface 20a.
[0036] Next, as shown in Figure 5(c), the first resin portion 40 is formed. Here, the first resin portion 40 is formed on the back surface 20b so as to fill the first groove portion 23. The method for forming the first resin portion 40 is not particularly limited. For example, the first resin portion 40 may be formed by applying a resin such as polyimide.
[0037] Next, as shown in Figure 5(d), the unnecessary first resin portion 40 located on the back surface 20b is removed. For example, the first resin portion 40 on the back surface 20b is removed by grinding or polishing so that only the first resin portion 40 filling the first groove 23 remains. By removing only a portion, the first resin portion 40 becomes substantially flush with the back surface 20b.
[0038] Next, as shown in Figure 5(e), the lead frame 20 is etched from one side 20a to form a second groove 24. By using the first resin part 40 as an etching stopper, a second groove 24 is formed that opens at a predetermined position on one side 20a and reaches a predetermined depth to the first groove 23. The formation of the second groove 24 exposes the first resin part 40 to the side 20a. The formation of the second groove 24 divides the lead frame 20 into a plurality of small pieces. Each small piece includes the die pad part 21 and a plurality of lead parts 22. The plurality of small pieces are mechanically connected by the first resin part 40, and an integrated structure can be maintained even after the formation of the second groove 24.
[0039] Next, as shown in Figure 5(f), a resist is placed on one surface 20a and patterned to form a mask 80 for partial plating. The mask 80 is placed in the area where plating is not required. The mask 80 is placed at the position where the non-plated area 61 is to be formed.
[0040] Next, as shown in Figure 5(g), PPF plating is applied to form the plated portion 60. Specifically, a plated portion 601 is formed on one surface 20a, and a plated portion 602 is formed on the back surface 20b. Because a mask 80 is formed, the plated portion 601 is formed partially on one surface 20a. For example, the plated portion 601 is formed in the central part of the die pad portion 21, but not on the outer periphery. The plated portion 602 is formed over the entire surface of the back surface 20b. Since the plated portion 60 is formed on both one surface 20a and the back surface 20b in one step, the process can be simplified.
[0041] In addition, plating portions 601 and 602 are formed such that the roughness Sa of plating portion 601 is greater than the roughness Sa of plating portion 602. For example, after forming plating portion 60, a roughening treatment may be performed on plating portion 601. Alternatively, the plating portion on one surface 20a may be roughened in advance, and PPF plating may be deposited thereon.
[0042] Next, as shown in FIG. 6(a), mask 80 is removed. As a result, a non-plating portion 61 is formed in the portion of one surface 20a from which mask 80 has been removed. Non-plating portion 61 is formed adjacent to plating portion 601.
[0043] Next, as shown in FIG. 6(b), semiconductor chip 30 is joined to die pad portion 21 via solder 70. This process is referred to as die mounting, die bonding, etc. When including a semiconductor chip fixed to a die pad by a method other than solder bonding, the semiconductor chip is fixed to the die pad in this process.
[0044] Next, as shown in FIG. 6(c), wire bonding is performed. The pad of semiconductor chip 30 and the corresponding lead portion 22 are connected by bonding wire 71.
[0045] Next, as shown in FIG. 6(d), second resin portion 50 is formed. This process is referred to as a sealing process, a molding process, etc. For example, second resin portion 50 is formed by a transfer molding method or a compression molding method. Second resin portion 50 is formed so as to fill second groove portion 24 and seal semiconductor chip 30 together with one surface 20a. By the above-described processes, exemplary semiconductor package 10 can be formed.
[0046] <Summary of the First Embodiment>The semiconductor package 10 of this embodiment includes a lead frame 20, a semiconductor chip 30, a first resin portion 40, a second resin portion 50, and a plating portion 60. The lead frame 20 has a first groove portion 23 that opens to the back surface 20b, a second groove portion 24 that opens to one surface 20a and is provided so as to reach the first groove portion 23, and a plurality of small piece portions partitioned by the first groove portion 23 and the second groove portion 24. The plurality of small piece portions include a die pad portion 21 and a lead portion 22. The semiconductor chip 30 is disposed on one surface 20a of the die pad portion 21 and is joined to the die pad portion 21 via a solder 70. The first resin portion 40 is filled in the first groove portion 23. The second resin portion 50 is formed using a material different from that of the first resin portion 40. The second resin portion 50 is filled in the second groove portion 24, contacts the first resin portion 40, and seals one surface 20a so as to cover the semiconductor chip 30. The plating portion 60 is laminated in the order of Ni, Pd, and Au and is disposed on one surface 20a and the back surface 20b. The plating portion 60 is provided only on a part including the solder joint portion of the semiconductor chip 30 on one surface 20a of the die pad portion 21.
[0047] Thus, by providing the plating portion sixty only on a part of the die pad portion twenty-one, the wetting spread of the solder seventy can be restricted. Thereby, the fall of the solder seventy into the second groove portion twenty-four can be suppressed as compared with the configuration in which the plating portion sixty is provided on the entire one surface 20a of the die pad portion twenty-one. Therefore, in the characteristic structure in which the first resin portion forty is filled in the first groove portion twenty-three that opens to the back surface 20b side of the lead frame twenty, and the second resin portion fifty is filled in the second groove portion twenty-four that opens to the one surface 20a side and reaches the first groove portion twenty-three, the reliability can be improved.
[0048] For example, it is possible to suppress the occurrence of migration due to the dropped solder seventy and the short circuit between the die pad portion twenty-one and other small piece portions such as the lead portion twenty-two. For example, it is possible to suppress the peeling of the second resin portion fifty by the dropped solder seventy intervening between the first resin portion forty and the second resin portion fifty and inhibiting the adhesion of the second resin portion fifty to the first resin portion forty.
[0049] Furthermore, by providing the plated portion 60 only on a part of the die pad portion 21, the wetting and spreading of the solder 70 can be suppressed, and the solder thickness on the die pad portion 21 can be ensured. Thus, the connection reliability of the semiconductor chip 30 can also be improved.
[0050] As illustrated, the die pad portion 21 may have an unplated portion 61 adjacent to the plated portion 60 (601) on one surface 20a. In the unplated portion 61, which is the part where the plated portion 60 is not formed, for example, the oxide of the metal constituting the lead frame 20 is exposed. For this reason, the solder 70 is less likely to wet and spread over the unplated portion 61. The unplated portion 61 adjacent to the plated portion 60 can suppress the wetting and spreading of the solder 70.
[0051] As illustrated, the plated portion 60 may be provided on one surface 20a of the die pad portion 21 at a position away from the end portion 211 adjacent to the second groove portion 24. This makes it difficult for the solder 70 to reach the end portion 211. Therefore, the falling of solder 70 into the second groove portion 24 can be effectively suppressed.
[0052] In a characteristic structure where a first resin portion is filled into a first groove opening on the back side of the lead frame, and a second resin portion is filled into a second groove opening on one side and reaching the first groove, a triple junction is formed between the lead frame, the first resin portion, and the second resin portion. Thermal stress concentrates at the triple junction due to the difference in coefficients of linear expansion. Therefore, delamination of the second resin portion may occur near the triple junction on one side, potentially reducing reliability.
[0053] As illustrated, the surface roughness of the plated portion 60 may be made rougher on one surface 20a than on the back surface 20b. For example, the roughness Sa of the plated portion may be greater on one surface 20a than on the back surface 20b. Due to the anchoring effect, the adhesion force of the second resin portion 50 to the plated portion 60 (601) on one surface 20a is increased, and peeling of the second resin portion 50 due to thermal stress at the triple point can be suppressed. Therefore, reliability can be improved. In addition, as described above, by providing the plated portion 60 at a position away from the end 211, that is, at a position away from the triple point, the stress acting on the plated portion 60 can be reduced, and peeling of the second resin portion 50 can be suppressed.
[0054] As illustrated, the roughness Sa of the plated portion 601 may be set within the range of 1.2 to 2.0, and the roughness Sa of the plated portion 602 may be made smaller than the roughness Sa of the plated portion 601. This makes it possible to suppress peeling of the second resin portion 50 while ensuring, for example, the mountability of the semiconductor package 10 on the substrate.
[0055] As illustrated, the semiconductor package 10 may include bonding wires 71. The plated portion 60 may be provided on one surface 20a, including the solder joint of the semiconductor chip 30 and the joint of the bonding wires 71. This can increase the bonding strength of the bonding wires 71. It can also suppress the peeling of the second resin portion 50 from the joint of the bonding wires 71.
[0056] <Modifications> As illustrated, the plated portion 60 (602) may be provided on the entire surface of the back surface 20b exposed to the first resin portion 40. Alternatively, as shown in Figure 7, for example, the plated portion 60 may be provided only on the solder joint with the object to be connected on the back surface 20b exposed to the first resin portion 40. The plated portion 602 may be provided on only a part of the back surface 20b. Figure 7 corresponds to Figure 2.
[0057] The semiconductor package 10 may comprise a plurality of semiconductor chips 30. For example, as shown in Figures 8 and 9, the semiconductor chip 30 may include an ASIC chip 301 and a vertical element 302. Figure 8 shows the positional relationship between the lead frame 20, the components mounted on the lead frame 20, and the plated portion 60 (601). In Figure 8, the plated portion 601 is hatched for clarity. Figure 9 is a cross-sectional view of the semiconductor package corresponding to IX-IX in Figure 8. Component 35 is a passive component such as a capacitor or inductor. The clip 72 is a metal plate material that electrically connects the vertical element 302, such as a MOSFET, to a small piece that is electrically isolated from the small piece on which the vertical element is mounted. The ASIC chip 301 and the vertical element 302 are electrically connected via a bonding wire 71.
[0058] The plated portion 601 is provided on the lead frame 20 at the solder joints of the ASIC chip 301, the vertical element 302, the component 35, the clip 72, and the wire joints of the lead portion 22. The die pad portion 21 has an unplated portion 61 adjacent to the plated portion 601. The plated portion 601 is provided on the die pad portion 21 at a position away from the end portion 211. The connecting portion 25 is a wiring portion that connects the die pad portion 21 and the lead portion 22 on the lead frame 20. A first groove portion 23 is formed directly below the connecting portion 25 and filled with a first resin portion 40. The connecting portion 25 is a thin-walled portion on the lead frame 20. A second groove portion 24 is not formed at the location where the connecting portion 25 is formed.
[0059] Although an example has been shown in which one semiconductor chip 30 is placed on one die pad portion 21, the invention is not limited to this. If electrical isolation is not required, multiple semiconductor chips 30 may be placed on one die pad portion 21. For example, as shown in Figure 10, various arrangements are possible. Figure 10 shows an example in which three semiconductor chips 30 are provided.
[0060] In Figure 10(a), the die pad portion 21A is provided with one plated portion 601. The plated portion 601 encloses three semiconductor chips 30 in a plan view. The unplated portion 61 surrounds the plated portion 601. In Figure 10(b), the die pad portion 21B is provided with the same number of plated portions 601 as the semiconductor chips 30. The plated portions 601 are provided individually for each semiconductor chip 30. The unplated portion 61 surrounds each of the plated portions 601.
[0061] In Figure 10(c), the die pad portion 21C is provided with two plated portions 601. Both plated portions 601 have a roughly rectangular shape in plan view. One plated portion 601 contains two semiconductor chips 30, and the other plated portion 601 contains the remaining semiconductor chip 30. The unplated portion 61 surrounds each of the plated portions 601. In Figure 10(d), the die pad portion 21D is provided with two plated portions 601. One plated portion 601 has a roughly rectangular shape in plan view and contains one semiconductor chip 30. The other plated portion 601 has a roughly L-shape in plan view and contains two semiconductor chips 30. The unplated portion 61 surrounds each of the plated portions 601.
[0062] In Figure 10(e), the die pad portion 21E is provided with two plated portions 601. Both plated portions 601 have a roughly planar shape. Each plated portion 601 contains one semiconductor chip 30. The unplated portion 61 surrounds each plated portion 601. There is no plated portion 601 directly beneath one of the semiconductor chips 30. In Figure 10(f), the die pad portion 21F is provided with one plated portion 601. The plated portion 601 has a roughly planar shape. The plated portion 601 contains two semiconductor chips 30. The unplated portion 61 surrounds the plated portion 601. There is no plated portion 601 directly beneath one of the semiconductor chips 30.
[0063] (Second Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be referenced. In the preceding embodiment, a plated portion was provided on a part of the die pad by partial plating. In the preceding embodiment, a plated portion was provided at a position away from the end, and an unplated portion was provided around the plated portion. Alternatively, a plated portion may be provided on a part of the die pad by partially removing the plated portion. A plated portion may be provided in the central and peripheral parts, and an unplated portion may be provided between the central and peripheral parts.
[0064] Figure 11 is a cross-sectional view showing an example of a semiconductor package according to this embodiment. Figure 11 corresponds to Figure 2. Figure 12 is a perspective view showing the arrangement of the plated portion on one surface. Figure 12 corresponds to Figure 3. Figure 12 is a view from the Z2 direction shown in Figure 11. Figure 12 shows the structure of the surface and below, including the plated portion. For the second resin portion, the portion below the position flush with the surface shown by the dashed line is shown.
[0065] As shown in Figures 11 and 12, the plated portion 601 is provided on a part of the die pad portion 21. The plated portion 601 has a central portion 601C and a peripheral portion 601P on one surface 20a of the die pad portion 21. The central portion 601C is the portion that includes the solder joint portion of the semiconductor chip 30. The peripheral portion 601P is a portion that surrounds the central portion 601C with a predetermined gap between it and the central portion 601C. The unplated portion 61 is provided between the central portion 601C and the peripheral portion 601P, i.e., in the gap. The unplated portion 61 surrounds the central portion 601C. The peripheral portion 601P surrounds the unplated portion 61. The other configurations are the same as those described in the prior embodiment.
[0066] Figure 13 shows a method for manufacturing the illustrated semiconductor package 10. Figure 13 corresponds to Figure 11. Instead of the steps shown in Figures 5(f), 5(g), and 6(a) described in the prior embodiment, the steps shown in Figures 13(a) and 13(b) are performed.
[0067] Up to the step of forming the second groove 24, the manufacturing method is the same as described in the prior embodiment. Next, as shown in Figure 13(a), PPF plating is applied to form the plated portion 60. Specifically, a plated portion 601 is formed on one surface 20a, and a plated portion 602 is formed on the back surface 20b. Since no mask 80 is formed, the plated portion 601 is formed over the entire surface of the one surface 20a. The plated portion 602 is formed over the entire back surface 20b. Similar to the prior embodiment, the plated portions 601 and 602 are formed such that the roughness Sa of the plated portion 601 is greater than the roughness Sa of the plated portion 602.
[0068] Next, as shown in 13(b), a laser beam is irradiated to remove a portion of the plated portion 601. The plated portion 601 provided on the die pad portion 21 is irradiated with a laser beam to partially remove the plated portion 601 and form an unplated portion 61. As the laser, for example, a laser diode-pumped Nd:YAG laser can be used. From the step of joining the semiconductor chip 30 to the die pad portion 21 via solder 70, the manufacturing method is the same as described in the prior embodiment.
[0069] <Summary of the Second Embodiment> As illustrated, the die pad portion 21 may be provided with a central portion 601C and a peripheral portion 601P as the plated portion 60, and an unplated portion 61 may be provided between the central portion 601C and the peripheral portion 601P. In this way, by providing the plated portion 60 only on a part of the die pad portion 21, the wetting and spreading of the solder 70 can be limited. In particular, the wetting and spreading of the solder from the central portion outwards can be suppressed. This effectively suppresses the falling of solder 70 into the second groove portion 24 and improves reliability.
[0070] <Modification> An example of partially removing the plated portion 601 with a laser has been shown, but the method is not limited to this. For example, the formation position of the unplated portion 61 may be masked with a mask 80. The plated portion 601 may also be partially removed by removal means other than a laser.
[0071] (Third Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used by reference. In the preceding embodiment, the surface roughness of the plated portion was made rougher on one side than on the back side. Instead, the surface roughness of the plated portion was made rougher on one side than on the back side.
[0072] Figure 14 is a cross-sectional view showing an example of a semiconductor package according to this embodiment. Figure 14 corresponds to Figure 2. In the example semiconductor package 10, the plated portion 601 is not roughened. The surface roughness of the plated portion 60 is approximately the same for both the plated portion 601 and the plated portion 602. The roughness Sa of the plated portions 601 and 602 is, for example, about 1.0. The other configurations are the same as those described in the prior embodiment (see Figure 2).
[0073] <Summary of the Third Embodiment> As illustrated, the plated portion 601 may be configured not to be roughened. In this embodiment as well, since the plated portion 601 is provided only on a part of the die pad portion 21, the falling of solder 70 into the second groove portion 24 can be effectively suppressed, and reliability can be improved.
[0074] <Modification> The configuration in which the plated portion 601 is provided only on a part of the die pad portion 21 is not limited to the above example. For example, as shown in Figure 15, in a configuration in which the die pad portion 21 is provided with a central portion 601C and a peripheral portion 601P, and an unplated portion 61 is provided between the central portion 601C and the peripheral portion 601P, the plated portion 601 may not be roughened.
[0075] (Fourth Embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used by reference. In the preceding embodiment, the plated portion on one side was made rougher than the plated portion on the back side, and the plated portion was provided only on a part of the die pad portion. Alternatively, the plated portion on one side may be made rougher than the plated portion on the back side, regardless of the formation position of the plated portion on one side.
[0076] Figure 16 is a cross-sectional view showing an example of a semiconductor package according to this embodiment. Figure 16 corresponds to Figure 2. The semiconductor package 100, like the semiconductor package 10, includes a lead frame 20, a semiconductor chip 30, a first resin part 40, a second resin part 50, and a plated part 60. The plated part 601 is provided over the entire surface of one side 20a. The plated part 601 is provided over the entire surface of one side 20a of the die pad part 21. The plated part 602 is provided over the entire surface of the back surface 20b.
[0077] The surface roughness of the plated portion 60 is rougher on one surface 20a than on the back surface 20b. The roughness Sa of the plated portion 60 is greater on one surface 20a than on the back surface 20b. The roughness Sa of the plated portion 601 is in the range of 1.2 to 2.0. The roughness Sa of the plated portion 602 is less than the roughness Sa of the plated portion 601. The roughness Sa of the plated portion 602 is, for example, about 1.0. The other configurations are the same as those described in the prior embodiment.
[0078] <Summary of the Fourth Embodiment> In the characteristic structure in which the first resin part is filled into the first groove opening on the back side of the lead frame, and the second resin part is filled into the second groove opening on one side and reaching the first groove, a triple point is formed between the lead frame, the first resin part, and the second resin part. Thermal stress concentrates at the triple point due to the difference in the coefficient of linear expansion. Therefore, delamination of the second resin part may occur near the triple point on one side, which may reduce reliability.
[0079] In the semiconductor package 10 of this embodiment, the surface roughness of the plated portion 60 is made rougher on one surface 20a than on the back surface 20b. For example, the roughness Sa of the plated portion 60 is made greater on one surface 20a than on the back surface 20b. As a result, the adhesion force of the second resin portion 50 to the plated portion 60 (601) on one surface 20a is increased by the anchoring effect, and peeling of the second resin portion 50 due to thermal stress at the triple point can be suppressed. Therefore, reliability can be improved. For example, even if the plated portion 601 is provided over the entire surface of one surface 20a, peeling of the second resin portion 50 can be suppressed.
[0080] As illustrated, the roughness Sa of the plated portion 601 may be set within the range of 1.2 to 2.0, and the roughness Sa of the plated portion 602 may be made smaller than the roughness Sa of the plated portion 601. This makes it possible to suppress peeling of the second resin portion 50 while ensuring, for example, the mountability of the semiconductor package 10 on the substrate.
[0081] An example has been shown in which the roughened plating portion 601 is provided over the entire surface of one surface 20a, but the invention is not limited to this. As shown in Figures 2, 7, and 11, the roughened plating portion 601 may be provided on only a part of one surface 20a. In other words, the semiconductor package may have the configuration described in Appendix 1.
[0082] <Note 1> A lead frame (20) having a first groove (23) opening on the back surface (20b), a second groove (24) opening on one surface (20a) opposite to the back surface and reaching the first groove, and a plurality of small pieces partitioned by the first groove and the second groove, including a die pad portion (21) and a lead portion (22); a semiconductor chip (30) disposed on the one surface of the die pad portion and soldered to the die pad portion; a first resin portion (40) filled in the first groove; a second resin portion (50) formed using a different material from the first resin portion, filled in the second groove and in contact with the first resin portion, and sealing the one surface of the lead frame so as to cover the semiconductor chip; and a plating portion (60) laminated in the order of Ni, Pd, and Au and disposed on the one surface and the back surface. A semiconductor package wherein the surface roughness of the plated portion is rougher on one side than on the back side.
[0083] (Other Embodiments) The disclosures in this specification and drawings are not limited to the exemplary embodiments. The disclosures include the exemplary embodiments and variations thereof by those skilled in the art. For example, the disclosures are not limited to combinations of parts and / or elements shown in the embodiments. The disclosures are implementable in a variety of combinations. The disclosures may have additional parts that can be added to the embodiments. The disclosures include those in which parts and / or elements of an embodiment have been omitted. The disclosures include substitutions or combinations of parts and / or elements between one embodiment and another. The scope of the disclosed technical areas is not limited to the descriptions of the embodiments. Some of the scope of the disclosed technical areas are indicated by the descriptions of the claims and should be understood to include all modifications within the meaning and scope equivalent to the descriptions of the claims.
[0084] The disclosures in the specification and drawings are not limited by the claims. The disclosures in the specification and drawings encompass the technical ideas described in the claims and extend to a wider and more diverse range of technical ideas than those described in the claims. Therefore, a variety of technical ideas can be extracted from the disclosures in the specification and drawings without being bound by the claims.
[0085] When an element or layer is referred to as “on top of,” “connected to,” “linked to,” or “joined,” it may be directly on top of, connected to, or joined to another element or layer, and there may also be an intervening element or layer. In contrast, when an element is referred to as “directly on top of,” “directly connected to,” “directly linked to,” or “directly joined to” another element or layer, there is no intervening element or layer. Other words used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used in this specification, the term “and / or” includes any combination and all combinations relating to one or more of the enumerated items in question. That is, the statement A and / or B means at least one of A and B.
[0086] Spatially relative terms such as “inside,” “outside,” “back,” “below,” “low,” “above,” and “high” are used here to facilitate descriptions of the relationship between one element or feature and other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned upside down, an element described as “below” or “directly below” another element or feature will be oriented “above” the other element or feature. Thus, the term “below” can encompass both up and down orientations. The device may also be oriented in other directions (it may be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification will be interpreted accordingly.
[0087] (Disclosure of Technical Ideas) This specification discloses several technical ideas as described in the following paragraphs. Some paragraphs are written in a multiple dependent form, where subsequent paragraphs optionally refer to preceding paragraphs. Furthermore, some paragraphs are written in a multiple dependent form, where they refer to other multiple dependent forms. These paragraphs written in multiple dependent forms define several technical ideas.
[0088] <Technical Concept 1> A lead frame (20) having a first groove (23) opening on the back surface (20b), a second groove (24) opening on one surface (20a) opposite to the back surface and provided to reach the first groove, and a plurality of small pieces partitioned by the first groove and the second groove, including a die pad portion (21) and a lead portion (22); a semiconductor chip (30) disposed on the one surface of the die pad portion and soldered to the die pad portion; a first resin portion (40) filled in the first groove; a second resin portion (50) formed using a different material from the first resin portion, filled in the second groove and in contact with the first resin portion, and sealing the one surface of the lead frame so as to cover the semiconductor chip; and a plating portion (60) laminated in the order of Ni, Pd, and Au, and disposed on the one surface and the back surface. A semiconductor package in which the plated portion is provided only on a portion of the die pad portion, including the solder joint portion of the semiconductor chip, on one surface of the die pad portion.
[0089] <Technical Concept 2> The semiconductor package according to Technical Concept 1, wherein the die pad portion has a non-plated portion (61) provided adjacent to the plated portion on one surface of the die pad portion.
[0090] <Technical Concept 3> The semiconductor package according to Technical Concept 1 or Technical Concept 2, wherein the plated portion is provided on one surface of the die pad portion at a position away from the end portion (211) adjacent to the second groove portion.
[0091] <Technical Concept 4> The semiconductor package according to Technical Concept 2, wherein the plated portion has a central portion (601C) on one surface of the die pad portion that includes the solder joint portion of the semiconductor chip, and a peripheral portion (601P) that surrounds the central portion, and the unplated portion is provided between the central portion and the peripheral portion.
[0092] <Technical Concept 5> The semiconductor package according to any one of Technical Concepts 1 to 4, wherein the surface roughness of the plated portion is rougher on one side than on the back side.
[0093] <Technical Concept 6> The semiconductor package according to Technical Concept 5, wherein the roughness Sa of the plated portion is greater on one surface than on the back surface.
[0094] <Technical Concept 7> The semiconductor package according to Technical Concept 6, wherein the roughness Sa of the plated portion provided on one surface is in the range of 1.2 to 2.0, and the roughness Sa of the plated portion provided on the back surface is smaller than the roughness Sa of the plated portion provided on one surface.
[0095] <Technical Concept 8> A semiconductor package according to any one of Technical Concepts 1 to 7, comprising a bonding wire (71), wherein the plated portion is provided on one surface at the solder joint including the solder joint of the semiconductor chip and at the bonding wire joint.
[0096] <Technical Concept 9> The semiconductor package according to any one of Technical Concepts 1 to 8, wherein the plated portion is provided on the entire surface of the back surface that is exposed to the first resin portion.
[0097] <Technical Concept 10> The semiconductor package according to any one of Technical Concepts 1 to 8, wherein the plated portion is provided only at the solder joint with the object to be connected on the back surface exposed to the first resin portion.
Claims
1. A lead frame (20) having a first groove (23) opening on the back surface (20b), a second groove (24) opening on one surface (20a) opposite to the back surface and reaching the first groove, and a plurality of small pieces partitioned by the first groove and the second groove, including a die pad portion (21) and a lead portion (22); a semiconductor chip (30) disposed on the one surface of the die pad portion and soldered to the die pad portion; a first resin portion (40) filled in the first groove; a second resin portion (50) formed using a different material from the first resin portion, filled in the second groove and in contact with the first resin portion, and sealing the one surface of the lead frame so as to cover the semiconductor chip; and a plating portion (60) laminated in the order of Ni, Pd, and Au, and disposed on the one surface and the back surface. A semiconductor package in which the plated portion is provided only on a portion of the die pad portion, including the solder joint portion of the semiconductor chip, on one surface of the die pad portion.
2. The semiconductor package according to claim 1, further comprising a non-plated portion (61) provided adjacent to the plated portion on one surface of the die pad portion.
3. The semiconductor package according to claim 2, wherein the plated portion is provided on one surface of the die pad portion at a position away from the end portion (211) adjacent to the second groove portion.
4. The semiconductor package according to claim 2, wherein the plated portion has a central portion (601C) on one surface of the die pad portion that includes the solder joint portion of the semiconductor chip, and a peripheral portion (601P) that surrounds the central portion, and the unplated portion is provided between the central portion and the peripheral portion.
5. The semiconductor package according to claim 1, wherein the surface roughness of the plated portion is rougher on one surface than on the back surface.
6. The semiconductor package according to claim 5, wherein the roughness Sa of the plated portion is greater on one surface than on the back surface.
7. The semiconductor package according to claim 6, wherein the roughness Sa of the plated portion provided on one surface is in the range of 1.2 to 2.0, and the roughness Sa of the plated portion provided on the back surface is smaller than the roughness Sa of the plated portion provided on one surface.
8. A semiconductor package according to any one of claims 5 to 7, comprising a bonding wire (71), wherein the plated portion is provided on one surface at the solder joint portion including the solder joint portion of the semiconductor chip and at the joint portion of the bonding wire, respectively.
9. The semiconductor package according to claim 1, wherein the plated portion is provided on the entire surface of the back surface that is exposed to the first resin portion.
10. The semiconductor package according to claim 1, wherein the plated portion is provided only on the solder joint portion with the object to be connected on the back surface exposed to the first resin portion.