Imaging device

Abstract

This imaging device comprises: a semiconductor substrate including a first surface and a second surface; a first through via penetrating the semiconductor substrate; a second through via penetrating the semiconductor substrate; a first connection wire disposed in a position closer to the first surface than to the second surface; a second connection wire disposed in a position closer to the first surface than to the second surface; a third connection wire disposed in a position closer to the second surface than to the first surface; and a fourth connection wire disposed in a position closer to the second surface than to the first surface. The first through-electrode via is directly connected to the first connection wire and the third connection wire. The second through via is directly connected to the second connection wire and the fourth connection wire. In a plan view with respect to the semiconductor substrate, the first connection wire overlaps the second connection wire.

Description

Imaging device

[0001] The present disclosure relates to an imaging device.

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used (see, for example, Patent Document 1). Patent Document 1 describes a semiconductor device including a semiconductor substrate having a first surface and a second surface, a first TSV (Through Silicon Via) and a second TSV penetrating the semiconductor substrate, a first wiring layer disposed on the first surface of the semiconductor substrate, and a second wiring layer disposed on the second surface of the semiconductor substrate, and an imaging device including the same. The first TSV is directly connected to a certain wiring in the first wiring layer and a certain wiring in the second wiring layer, and the second TSV is directly connected to another wiring in the first wiring layer and another wiring in the second wiring layer.

[0003] Japanese Unexamined Patent Application Publication No. 2022-022123

[0004] By the way, for example, in an imaging device, as the number of pixels increases, the number of through vias penetrating the semiconductor substrate also increases, so the number of connection wirings directly connected to the through vias also increases. For this reason, a region for routing the connection wirings is required, so the area of the semiconductor substrate becomes large.

[0005] The present disclosure provides an imaging device capable of suppressing an increase in the area of the semiconductor substrate.

[0006] An imaging device according to one aspect of the present disclosure includes a semiconductor substrate including a first surface and a second surface, a first through-via penetrating the semiconductor substrate, a second through-via penetrating the semiconductor substrate, a first connection wiring positioned closer to the first surface than the second surface, a second connection wiring positioned closer to the first surface than the second surface, a third connection wiring positioned closer to the second surface than the first surface, and a fourth connection wiring positioned closer to the second surface than the first surface. The first through-via is directly connected to the first connection wiring and the third connection wiring. The second through-via is directly connected to the second connection wiring and the fourth connection wiring. The distance between the first connection wiring and the semiconductor substrate is different from the distance between the second connection wiring and the semiconductor substrate. In a plan view of the semiconductor substrate, the first connection wiring overlaps with the second connection wiring.

[0007] According to this disclosure, it is possible to provide an imaging device that can suppress an increase in the area of ​​the semiconductor substrate.

[0008] Figure 1 is a block diagram showing an example of the configuration of an imaging device according to one embodiment of the present disclosure. Figure 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device according to one embodiment of the present disclosure. Figure 3 is a cross-sectional view showing the device structure of an imaging device according to one embodiment of the present disclosure. Figure 4 is a plan view showing the structure of the first through electrode, the second through electrode, the first connecting wiring, and the second connecting wiring. Figure 5 is a flowchart showing a method for manufacturing the imaging device. Figure 6 is a cross-sectional view illustrating a method for manufacturing the imaging device. Figure 7 is a cross-sectional view illustrating a method for manufacturing the imaging device. Figure 8 is a cross-sectional view illustrating a method for manufacturing the imaging device. Figure 9 is a cross-sectional view illustrating a method for manufacturing the imaging device. Figure 10 is a cross-sectional view illustrating a method for manufacturing the imaging device. Figure 11 is a cross-sectional view showing the device structure of an imaging device of a first modified example. Figure 12 is a plan view showing the structure of the first through electrode, the second through electrode, the first connecting wiring, and the second connecting wiring. Figure 13 is a cross-sectional view showing the device structure of an imaging device of a second modified example. Figure 14 is a plan view showing the structure of the first through electrode, the second through electrode, the first connecting wiring, the second connecting wiring, and the wiring. Figure 15 is a cross-sectional view showing the device structure of the imaging device of the third modified example. Figure 16 is a cross-sectional view showing the device structure of the imaging device of the fourth modified example. Figure 17 is a cross-sectional view showing the device structure of the imaging device of the fifth modified example. Figure 18 is a cross-sectional view showing the device structure of the semiconductor device of the sixth modified example.

[0009] (Summary of this disclosure) The following are examples of imaging devices and semiconductor devices related to this disclosure.

[0010] (First Embodiment) For example, an imaging device according to the first embodiment of the present disclosure includes a semiconductor substrate including a first surface and a second surface, a first through-via penetrating the semiconductor substrate, a second through-via penetrating the semiconductor substrate, a first connection wiring positioned closer to the first surface than the second surface, a second connection wiring positioned closer to the first surface than the second surface, a third connection wiring positioned closer to the second surface than the first surface, and a fourth connection wiring positioned closer to the second surface than the first surface. The first through-via is directly connected to the first connection wiring and the third connection wiring. The second through-via is directly connected to the second connection wiring and the fourth connection wiring. The distance between the first connection wiring and the semiconductor substrate is different from the distance between the second connection wiring and the semiconductor substrate. In a plan view of the semiconductor substrate, the first connection wiring overlaps with the second connection wiring.

[0011] This allows the first and second connection lines, which are at different distances from the semiconductor substrate, to overlap in a plan view, thereby suppressing an increase in the area of ​​the semiconductor substrate. On the other hand, if the distances of the two connection lines from the semiconductor substrate are the same, it is necessary to route one connection line so that it does not come into contact with the other, which increases the area of ​​the semiconductor substrate.

[0012] Furthermore, since the first through-via is directly connected to the first and third connection lines, and the second through-via is directly connected to the second and fourth connection lines, the first and second through-vias can be easily placed close together. This makes it easy to suppress an increase in the area of ​​the semiconductor substrate. On the other hand, if the two through-vias are directly connected to, for example, a transistor or electrode that constitutes a pixel and has a fixed layout, the positions of the two through-vias are also fixed, making it difficult to bring the two through-vias closer together. This makes it difficult to suppress an increase in the area of ​​the semiconductor substrate.

[0013] (Second Embodiment) For example, in the imaging device according to the first embodiment, the first through via may be made of the same material as the first connecting wiring.

[0014] This allows the first through-via and the first connecting wire to be formed simultaneously, or in other words, in the same process.

[0015] (Third Embodiment) For example, in the imaging device according to the first or second embodiment, the second through via may be made of the same material as the second connecting wiring.

[0016] This allows the second through-via and the second connecting wire to be formed simultaneously, or in other words, in the same process.

[0017] (Fourth Embodiment) For example, in an imaging device according to any one of the first to third embodiments, the area of ​​the portion of the first through via connected to the first connecting wiring may be larger than the area of ​​the portion of the first through via connected to the third connecting wiring, and the area of ​​the portion of the second through via connected to the second connecting wiring may be larger than the area of ​​the portion of the second through via connected to the fourth connecting wiring.

[0018] Thus, overlapping two connection lines, namely the first and second connection lines, on the side with the larger via diameter significantly reduces the increase in the semiconductor substrate area. Specifically, even if one attempts to bring the first and second through-vias closer together by overlapping two connection lines, namely the third and fourth connection lines, on the side with the smaller via diameter, the distance between the first and second through-vias may be limited on the side with the larger via diameter. Therefore, overlapping the two connection lines on the side with the larger via diameter is more effective.

[0019] (Fifth Embodiment) For example, an imaging device according to the fifth embodiment of the present disclosure is an imaging device according to any one of the first to fourth embodiments, further comprising a pixel region including a plurality of pixels, and a peripheral region provided around the pixel region in a plan view. At least one selected from the group consisting of the first connection wiring and the second connection wiring may be arranged across the pixel region and the peripheral region.

[0020] This allows, for example, the distance between one through-via connected to a pixel region and the other through-via to be shortened, thereby suppressing an increase in the area of ​​the peripheral region. Therefore, an increase in the area of ​​the semiconductor substrate can be easily suppressed.

[0021] Furthermore, since the distance from the pixel to the through-via can be shortened, an imaging device that operates at low resistance and high speed can be obtained.

[0022] (Sixth aspect) For example, an imaging device according to the sixth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects, which may further include pixels, and at least one selected from the group consisting of the first connection wiring and the second connection wiring may be electrically connected to the pixels.

[0023] With this configuration, there are numerous connection wires, usually thousands or more, that are electrically connected to the pixels. By overlapping these connection wires, the effect of reducing the area of ​​the semiconductor substrate becomes significant.

[0024] Furthermore, since the distance from the pixel to the through-via can be shortened, an imaging device that operates at low resistance and high speed can be obtained.

[0025] (Seventh Embodiment) For example, an imaging device according to the seventh embodiment of the present disclosure is an imaging device according to the fifth or sixth embodiment, which may further include signal wiring electrically connected to the pixels. At least one selected from the group consisting of the first connection wiring and the second connection wiring may be electrically connected to the signal wiring.

[0026] With this configuration, there are numerous signal lines electrically connected to the pixels, usually thousands or more. By stacking these connection lines, the effect of reducing the area of ​​the semiconductor substrate becomes significant.

[0027] Furthermore, since the distance from the pixel to the through-via can be shortened, an imaging device that operates at low resistance and high speed can be obtained.

[0028] (Eighth aspect) For example, an imaging device according to the eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, further comprising a non-penetrating via directly connected to the second connecting wiring and not penetrating the semiconductor substrate, and a fifth connecting wiring directly connected to the non-penetrating via. The distance between the first connecting wiring and the semiconductor substrate may be different from the distance between the fifth connecting wiring and the semiconductor substrate. In the plan view, the first connecting wiring may overlap with the fifth connecting wiring.

[0029] This allows the first and fifth connection lines, which are at different distances from the semiconductor substrate, to be arranged so that they overlap in a plan view, thereby further suppressing the increase in the area of ​​the semiconductor substrate.

[0030] (Ninth aspect) For example, an imaging device according to the ninth aspect of the present disclosure is an imaging device according to any one of the first to eighth aspects, which may further include a non-penetrating via that is directly connected to the second connecting wiring and does not penetrate the semiconductor substrate. The first penetrating via may overlap the non-penetrating via in the plan view.

[0031] In this way, by arranging the first through-via and the non-through-via so that they overlap in a plan view, the increase in the area of ​​the semiconductor substrate can be further suppressed.

[0032] (Tenth Embodiment) For example, a semiconductor device according to the tenth embodiment of the present disclosure includes a semiconductor substrate including a first surface and a second surface, a first through-via penetrating the semiconductor substrate, a second through-via penetrating the semiconductor substrate, a first connection wiring positioned closer to the first surface than the second surface, a second connection wiring positioned closer to the first surface than the second surface, a third connection wiring positioned closer to the second surface than the first surface, and a fourth connection wiring positioned closer to the second surface than the first surface. The first through-via is directly connected to the first connection wiring and the third connection wiring. The second through-via is directly connected to the second connection wiring and the fourth connection wiring. The distance between the first connection wiring and the semiconductor substrate is different from the distance between the second connection wiring and the semiconductor substrate. In a plan view of the semiconductor substrate, the first connection wiring overlaps with the second connection wiring.

[0033] This allows the first and second connection lines, which are at different distances from the semiconductor substrate, to overlap in a plan view, thereby suppressing an increase in the area of ​​the semiconductor substrate. On the other hand, if the distances of the two connection lines from the semiconductor substrate are the same, it is necessary to route one connection line so that it does not come into contact with the other, which increases the area of ​​the semiconductor substrate.

[0034] Furthermore, since the first through-via is directly connected to the first and third connection wirings, and the second through-via is directly connected to the second and fourth connection wirings, the first and second through-vias can be easily placed close together. This makes it easy to suppress an increase in the area of ​​the semiconductor substrate. On the other hand, if the two through-vias are directly connected to, for example, a transistor or electrode that constitutes a pixel and has a fixed layout, the positions of the two through-vias are also fixed, making it difficult to bring the two through-vias closer together. This makes it difficult to suppress an increase in the area of ​​the semiconductor substrate.

[0035] (11th embodiment) For example, in the semiconductor device according to the 10th embodiment, the first through via may be made of the same material as the first connecting wiring.

[0036] This allows the first through-via and the first connecting wire to be formed simultaneously, or in other words, in the same process.

[0037] (Twelfth aspect) For example, in a semiconductor device according to the tenth or eleventh aspect, the second through via may be made of the same material as the second connecting wiring.

[0038] This allows the second through-via and the second connecting wire to be formed simultaneously, or in other words, in the same process.

[0039] (13th Embodiment) For example, in a semiconductor device according to any one of the 10th to 12th embodiments, the area of ​​the portion of the first through via connected to the first connection wiring may be larger than the area of ​​the portion of the first through via connected to the third connection wiring, and the area of ​​the portion of the second through via connected to the second connection wiring may be larger than the area of ​​the portion of the second through via connected to the fourth connection wiring.

[0040] Thus, overlapping two connection lines, namely the first and second connection lines, on the side with the larger via diameter significantly reduces the increase in the semiconductor substrate area. Specifically, even if one attempts to bring the first and second through-vias closer together by overlapping two connection lines, namely the third and fourth connection lines, on the side with the smaller via diameter, the distance between the first and second through-vias may be limited on the side with the larger via diameter. Therefore, overlapping the two connection lines on the side with the larger via diameter is more effective.

[0041] (14th aspect) For example, a semiconductor device according to the 14th aspect of the present disclosure is a semiconductor device according to any one of the 10th to 13th aspects, further comprising a non-penetrating via directly connected to the second connection wiring and not penetrating the semiconductor substrate, and a fifth connection wiring directly connected to the non-penetrating via. The distance between the first connection wiring and the semiconductor substrate may be different from the distance between the fifth connection wiring and the semiconductor substrate. In the plan view, the first connection wiring may overlap with the fifth connection wiring.

[0042] As a result, the first connection wiring and the fifth connection wiring having different distances from the semiconductor substrate can be arranged so as to overlap in a plan view, so that an increase in the area of the semiconductor substrate can be further suppressed.

[0043] (15th Aspect) For example, a semiconductor device according to the 15th aspect of the present disclosure is a semiconductor device according to any one of the 10th to 14th aspects, and may further include a non-through via that is directly connected to the second connection wiring and does not penetrate the semiconductor substrate. The first through via may overlap the non-through via in the plan view.

[0044] Thus, by arranging the first through via and the non-through via so as to overlap in a plan view, an increase in the area of the semiconductor substrate can be further suppressed.

[0045] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that each of the embodiments described below shows a comprehensive or specific example. The numerical values, shapes, materials, components, arrangements and connection forms of the components, steps, order of steps, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in this specification can be combined with each other as long as there is no contradiction. In each drawing, components having substantially the same function are denoted by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0046] In addition, various elements shown in the drawings are merely schematically shown for the purpose of understanding the present disclosure, and the dimensional ratios, appearances, etc. may be different from the actual ones. That is, each drawing is a schematic diagram and is not necessarily drawn precisely. Therefore, for example, the scales in each drawing do not necessarily match.

[0047] In addition, in this specification, terms indicating the relationship between elements such as vertical or parallel, terms indicating the shape of elements such as circular or rectangular, and numerical ranges are not expressions representing only a strict meaning, but are expressions meaning substantially equivalent ranges, for example, including a difference of about several percent.

[0048] Further, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by the relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is defined as "upper", and the side opposite to the light-receiving side is defined as "lower". Similarly, for the "upper surface" and "lower surface" of each member, the surface on the light-receiving side of the imaging device is defined as the "upper surface", and the surface on the side opposite to the light-receiving side is defined as the "lower surface". Note that the terms such as "upper", "lower", "upper surface", and "lower surface" are used only to specify the mutual arrangement between members and are not intended to limit the posture of the imaging device during use. Also, the terms "upper" and "lower" are applicable not only when two components are arranged at a distance from each other and there is another component between the two components, but also when two components are arranged in close contact with each other and the two components are in contact. Further, in this specification, "plan view" means when viewed from a direction perpendicular to the semiconductor substrate (in other words, the thickness direction of the semiconductor substrate).

[0049] (Embodiment) An imaging device according to an embodiment of the present disclosure will be described.

[0050] [Configuration] First, an overview of the configuration of an imaging device according to an embodiment of the present disclosure will be described. FIG. 1 is a block diagram showing an example of the configuration of an imaging device 100 according to an embodiment of the present disclosure.

[0051] As shown in Figure 1, the imaging device 100 comprises a first substrate 10 and a second substrate 20. In this embodiment, the first substrate 10 is provided with a pixel array 30 composed of a plurality of pixels 31 and a plurality of through electrodes 41. The second substrate 20 is provided with peripheral circuits 51. The plurality of through electrodes 41 connect the plurality of pixels 31 and the peripheral circuits 51. The peripheral circuits 51 include circuits for driving the plurality of pixels 31 and circuits for processing signals output by the plurality of pixels 31. In the example shown in Figure 1, it includes a vertical scanning circuit 52, a column signal processing circuit 53, a memory (not shown), and a control circuit (not shown). The signals output by the pixels 31 include, for example, voltage, potential, or charge. Note that some of the peripheral circuits 51 may be arranged on the first substrate 10. The through electrodes 41 may also connect peripheral circuits arranged on the first substrate 10 and peripheral circuits arranged on the second substrate 20.

[0052] As will be described in more detail later, the first substrate 10 and the second substrate 20 are stacked on top of each other. The electrical connection between the first substrate 10 and the second substrate 20 is made via a plurality of through electrodes 41.

[0053] The pixel array 30 includes a plurality of pixels 31 arranged in two dimensions. In this embodiment, the pixel array 30 includes a plurality of pixels 31 arranged in a matrix (matrix) in a planar view. Each of the plurality of pixels 31 includes a photoelectric conversion unit that converts light into electric charge and outputs a signal corresponding to the incidence of light on the photoelectric conversion unit.

[0054] Multiple pixels 31 are connected to an external power supply that provides voltage via through electrodes 41. At least a portion of the power supply may be provided in the imaging device 100.

[0055] The vertical scanning circuit 52 is connected to the multiple pixels 31 via control signal lines L1 provided for each row of pixels 31, and performs signal reading and resetting of the pixels 31 for each row of pixels 31. Figure 1 shows a diagram in which one control signal line L1 is provided for each row of pixels 31, but multiple control signal lines L1 may be provided for each row of pixels 31. The control signal line L1 is connected to the vertical scanning circuit 52 via through electrodes 41.

[0056] The column signal processing circuit 53 is connected to the multiple pixels 31 via vertical signal lines L2 provided for each column of the multiple pixels 31, and converts the analog signal output for each column of the multiple pixels 31 into a digital signal. The vertical signal lines L2 are connected to the column signal processing circuit 53 via through electrodes 41.

[0057] The memory (not shown) temporarily stores, for example, the digital signals converted by the column signal processing circuit 53.

[0058] A control circuit (not shown) controls the operation of the imaging device 100. The control circuit controls the operation of at least one of the memory, the vertical scanning circuit 52, and the column signal processing circuit 53. The control circuit may be implemented, for example, by a microcontroller or one or more processors. The functions of the control circuit may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing.

[0059] Figure 2 is a schematic diagram illustrating an exemplary circuit configuration of an imaging device 100 according to one embodiment of the present disclosure. In Figure 2, four pixels 31 arranged in two rows and two columns are shown as representative examples to avoid complexity in the drawing. Each of these pixels 31 is an example of the pixel 31 shown in Figure 1. Each of the pixels 31 has a photoelectric conversion unit 70 and includes a signal detection circuit 310 electrically connected to the photoelectric conversion unit 70.

[0060] The photoelectric conversion unit 70 generates positive and negative charges, typically hole-electron pairs, upon the incidence of light. The photoelectric conversion unit 70 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 11, or a photodiode formed on the semiconductor substrate 11. The photoelectric conversion units 70 of each pixel 31 are arranged continuously on the semiconductor substrate 11 without spacing between them. Alternatively, the photoelectric conversion units 70 of each pixel 31 may be spatially separated from each other.

[0061] Each pixel 31's photoelectric conversion unit 70 has a connection to a storage control line 331. When the imaging device 100 is operating, a predetermined voltage is applied to the storage control line 331. For example, if the positive charge among the positive and negative charges generated by photoelectric conversion is used as the signal charge, a positive voltage of, for example, about 10V may be applied to the storage control line 331 when the imaging device 100 is operating. The following example illustrates the case where a hole is used as the signal charge.

[0062] In the configuration illustrated in Figure 2, the signal detection circuit 310 includes a signal detection transistor 311, an address transistor 312, a reset transistor 313, and a protection transistor 314. The signal detection transistor 311, the address transistor 312, the reset transistor 313, and the protection transistor 314 are typically field-effect transistors (FETs) formed on the semiconductor substrate 11 supporting the photoelectric conversion unit 70. In the following, unless otherwise specified, examples using N-channel MOSFETs as transistors will be described.

[0063] As schematically shown in Figure 2, the gate of the signal detection transistor 311 is electrically connected to the photoelectric conversion unit 70. In the illustrated example, the charge storage node FD, which connects the gate of the signal detection transistor 311 to the photoelectric conversion unit 70, has the function of temporarily holding the charge generated by the photoelectric conversion unit 70. By applying a predetermined voltage to the storage control line 331 during operation, for example, holes can be stored in the charge storage node FD as signal charge. The charge storage node FD includes an impurity region formed on the semiconductor substrate 11 as part of its structure.

[0064] One of the drains and sources of the signal detection transistor 311 is connected to the power supply wiring 332. The power supply wiring 332 supplies a power supply voltage VDD1 to each pixel 31 when the imaging device 100 is operating. The power supply voltage VDD1 is, for example, 3.3V. The other of the drains and sources of the signal detection transistor 311 is connected to the vertical signal line L2 via the address transistor 312. By receiving the power supply voltage VDD1 on the other of the drains and sources, the signal detection transistor 311 outputs a signal voltage corresponding to the amount of signal charge stored in the charge storage node FD.

[0065] The gate of the address transistor 312, which is connected between the signal detection transistor 311 and the vertical signal line L2, is connected to the control signal line L1. The vertical scanning circuit 52 applies a row selection signal to the control signal line L1 to control the on and off states of the address transistor 312. This allows the output of the signal detection transistor 311 of the selected pixel 31 to be read out to the corresponding vertical signal line L2. Note that the arrangement of the address transistor 312 is not limited to the example shown in Figure 2, and may be between the drain of the signal detection transistor 311 and the power supply wiring 332.

[0066] The gate and drain of the protection transistor 314, and one of its sources, are connected to the charge storage node FD. The other of the drain and source of the protection transistor 314 is connected to the power supply wiring 337. The power supply wiring 337 supplies a power supply voltage VDD2 to each pixel 31 when the imaging device 100 is in operation. The power supply voltage VDD2 is, for example, 2.0V. When high-brightness light is incident on the photoelectric conversion unit 70, the amount of holes accumulated in the charge storage node FD increases. In that case, a bias exceeding, for example, 5V may occur in the charge storage node FD, potentially destroying the gate oxide film of the signal detection transistor 311 connected to the charge storage node FD. Therefore, when a high bias exceeding 5V occurs in the charge storage node FD, for example, the protection transistor 314 is made to conduct. This reduces the potential of the charge storage node FD by discharging the holes accumulated in it.

[0067] A load circuit 345 and a column signal processing circuit 347 are connected to each of the vertical signal lines L2. The load circuit 345, together with the signal detection transistor 311, forms a source follower circuit. The column signal processing circuit 347, also called a row signal storage circuit, performs noise suppression signal processing and analog-to-digital conversion, such as correlated double sampling. The column signal processing circuit 53 sequentially reads signals from the multiple column signal processing circuits 347 to the horizontal common signal line 349. The load circuit 345 and the column signal processing circuits 347 may be part of the peripheral circuit 51 described above.

[0068] A reset signal line 336, which has a connection to the vertical scanning circuit 52, is connected to the gate of the reset transistor 313. The reset signal line 336 is provided for each row of pixels 31, similar to the control signal line L1. The vertical scanning circuit 52 can select the pixels 31 to be reset on a row-by-row basis by applying a row selection signal to the control signal line L1. The vertical scanning circuit 52 can also switch the reset transistor 313 of the selected row on and off by applying a reset signal to the gate of the reset transistor 313 via the reset signal line 336. When the reset transistor 313 is turned on, the potential of the charge storage node FD is reset.

[0069] In this example, one of the drains and sources of the reset transistor 313 is connected to the charge storage node FD, and the other drain and source is connected to the corresponding feedback line 353 provided for each row of pixels 31. That is, in this example, the voltage of the feedback line 353 is supplied to the charge storage node FD as a reset voltage to initialize the charge of the photoelectric conversion unit 70.

[0070] In the configuration illustrated in Figure 2, the imaging device 100 has a feedback circuit 316 that includes an inverting amplifier 350 as part of the feedback path. As shown in Figure 2, an inverting amplifier 350 is provided for each row of pixels 31, and the above-mentioned feedback line 353 is connected to the corresponding output terminal of one of the multiple inverting amplifiers 350. The inverting amplifier 350 may be part of the peripheral circuit 51 described above.

[0071] As shown in Figure 2, the inverting input terminal of the inverting amplifier 350 is connected to the corresponding vertical signal line L2, and a reference voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 350 when the imaging device 100 is operating. By turning on the address transistor 312 and the reset transistor 313, a feedback path can be formed that negatively feeds back the output of the pixel 31. With the formation of the feedback path, the voltage of the vertical signal line L2 converges to the reference voltage Vref, which is the input voltage to the non-inverting input terminal of the inverting amplifier 350. In other words, with the formation of the feedback path, the voltage of the charge storage node FD is reset to a voltage such that the voltage of the vertical signal line L2 becomes the reference voltage Vref. The reference voltage Vref can be any voltage within the range of the power supply voltage and ground. The reference voltage Vref is, for example, a positive voltage of 1V or near 1V. With the formation of the feedback path, the reset noise that is generated when the reset transistor 313 is turned off can be reduced.

[0072] Next, the detailed device structure of the imaging device 100 according to this embodiment will be described with reference to Figure 3. Figure 3 is a cross-sectional view showing the device structure of the imaging device 100 according to one embodiment of this disclosure. Note that in Figure 3, for ease of viewing, hatching indicating the cross-section of the insulating layers 12 and 22 has been omitted. This is also the case in the cross-sectional views from Figure 3 onward.

[0073] As shown in Figure 3, the imaging device 100 includes a first substrate 10, a second substrate 20, a photoelectric conversion unit 70, a connecting electrode 75, an insulating layer 81, a cover metal film 82, a color filter (not shown), and a microlens (not shown). The photoelectric conversion unit 70, the insulating layer 81, the color filter (not shown), and the microlens (not shown) are included in each pixel 31 (see Figure 1).

[0074] The first substrate 10 and the second substrate 20 are stacked on top of each other. For example, in a plan view, the first substrate 10 and the second substrate 20 have the same shape and size, and their outer edges coincide. The first substrate 10 and the second substrate 20 are joined at the interface between them. The first substrate 10 and the second substrate 20 can be manufactured, for example, using a semiconductor manufacturing process.

[0075] The first substrate 10 has, in a plan view, a pixel region R1 in which a plurality of pixels 31 (see Figure 1) are arranged, and a peripheral region R2 provided around the pixel region R1. The pixel region R1 is the region in which the pixel array 30 (see Figure 1) is formed. The pixel region R1 is, for example, a rectangular region. The peripheral region R2 is, for example, arranged to surround the pixel region R1 in a plan view.

[0076] The first substrate 10 includes a semiconductor substrate 11 located in a pixel region R1 and a peripheral region R2, and an insulating layer 12 located above the semiconductor substrate 11 in the pixel region R1 and the peripheral region R2. In the example shown in Figure 3, the insulating layer 12 is located on the upper surface of the semiconductor substrate 11. Specifically, the semiconductor substrate 11 has a first surface 11a and a second surface 11b. The first surface 11a is one side (here, the upper side) of the semiconductor substrate 11. The second surface 11b is the other side (here, the lower side) of the semiconductor substrate 11. The insulating layer 12 is located on the first surface 11a of the semiconductor substrate 11.

[0077] The second substrate 20 includes a semiconductor substrate 21 and an insulating layer 22 located above the semiconductor substrate 21. In the example shown in Figure 3, the insulating layer 22 is located on the upper surface of the semiconductor substrate 21. The second substrate 20 is bonded to the second surface 11b of the semiconductor substrate 11. The orientation of the second substrate 20 may be reversed compared to the example shown in Figure 3.

[0078] The semiconductor substrates 11 and 21 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed. Wells may be formed in each of the semiconductor substrates 11 and 21. In this embodiment, the semiconductor substrates 11 and 21 are, for example, silicon substrates.

[0079] A detection circuit 32 for each pixel 31 is formed on the upper surface of the semiconductor substrate 11. A detection circuit 32 is provided for each pixel 31. Figure 3 shows a portion of the transistors in the detection circuit 32.

[0080] The insulating layer 12 is a layer formed of an insulating material such as silicon dioxide or tetraethyl orthosilicate (TEOS).

[0081] Wiring layers are arranged within the insulating layer 12. In the example shown in Figure 3, the imaging device 100 has a plurality of wiring layers 15 within the insulating layer 12. The plurality of wiring layers 15 include, in order from the semiconductor substrate 11 side, for example, wiring layers 151, 152, 153, 154, and 155. Each of the wiring layers 15 contains a plurality of wires. Wiring layer 152 contains wire 152A. Wiring 152A is a connecting wire that is directly connected to the first through electrode 41A, which will be described later. Also, for example, wiring layer 154 contains wire 154A. Wiring 154A is a connecting wire that is directly connected to the second through electrode 41B, which will be described later. In addition, each wiring layer 15 is connected to another wiring layer 15 via vias 18. In the example shown in Figure 3, via 18 connects wiring layer 151 and wiring layer 152, and also connects wiring layer 153 and wiring layer 154. However, via 18 can connect any two wiring layers 15. Wiring 152A is an example of the "first connection wiring" of this disclosure. Wiring 154A is an example of the "second connection wiring" of this disclosure. Hereinafter, wiring 152A may be referred to as the first connection wiring 152A, and wiring 154A may be referred to as the second connection wiring 154A.

[0082] The via 18 is a columnar conductor extending in the thickness direction of the semiconductor substrate 11. In the example shown in Figure 3, the imaging device 100 includes a pixel electrode 71, a via 18, and a contact plug 19. The via 18 connects the pixel electrode 71 to the wiring layer 15. The contact plug 19 is a columnar conductor extending in the thickness direction of the semiconductor substrate 11. The pixel electrode 71 is connected to the detection circuit 32, for example, via the via 18, the wiring layer 15, and the contact plug 19. The detection circuit 32 is electrically connected to the pixel electrode 71 of the photoelectric conversion unit 70 and detects a signal based on the charge generated by the photoelectric conversion unit 70.

[0083] Peripheral circuits 51 (see Figure 1) are formed on the upper surface of the semiconductor substrate 21. Note that in Figure 3, peripheral circuits 51 are omitted for the sake of simplifying the drawing.

[0084] The insulating layer 22 is made of an insulating material such as silicon dioxide. A wiring layer is arranged within the insulating layer 22. In the example shown in Figure 3, at least in the peripheral region R2, a plurality of wiring layers 25 are provided within the insulating layer 22. The plurality of wiring layers 25 include, for example, wiring layers 251 and 252 in order from the semiconductor substrate 21 side. Each wiring layer 25 contains a plurality of wirings. For example, wiring 252 includes wirings 252A and 252B formed by the same wiring layer 252. Wiring 252A is a connecting wiring that is directly connected to the first through electrode 41A, which will be described later. Wiring 252B is a connecting wiring that is directly connected to the second through electrode 41B, which will be described later. Wiring 252A is an example of the "third connecting wiring" of this disclosure. Wiring 252B is an example of the "fourth connecting wiring" of this disclosure. Hereafter, wiring 252A may be referred to as the third connection wiring 252A, and wiring 252B may be referred to as the fourth connection wiring 252B.

[0085] Furthermore, for example, each wiring layer 25 is connected to a peripheral circuit 51 via vias and contact plugs (not shown). Also, the wiring layer 25 (here, wiring layer 252) is connected to the first connection wiring 152A and the second connection wiring 154A of the first substrate 10 via through electrodes 41.

[0086] Specifically, the through electrode 41 includes a first through electrode 41A and a second through electrode 41B that is positioned adjacent to the first through electrode 41A in a plan view. The first through electrode 41A connects the first connecting wire 152A and the third connecting wire 252A. The second through electrode 41B connects the second connecting wire 154A and the fourth connecting wire 252B. The first through electrode 41A is an example of the "first through via" of this disclosure. The second through electrode 41B is an example of the "second through via" of this disclosure.

[0087] The wiring layers 15, 25, vias, and contact plugs, which are located within the insulating layer 12 and the insulating layer 22, are formed of, for example, metal. The wiring layers 15, 25, vias, and contact plugs are formed using, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum.

[0088] The photoelectric conversion unit 70 generates positive and negative charges upon the incidence of light. In other words, the photoelectric conversion unit 70 converts light into electric charge. The photoelectric conversion unit 70 includes a pixel electrode 71, a counter electrode 72, and a photoelectric conversion layer 73. The photoelectric conversion unit 70 may further include other layers, such as a charge blocking layer, a buffer layer, or a charge transport layer, at least one of the spaces between the pixel electrode 71 and the photoelectric conversion layer 73, and between the photoelectric conversion layer 73 and the counter electrode 72.

[0089] The pixel electrode 71 is located on the upper surface of the insulating layer 12 in the pixel region R1. The pixel electrode 71 is a film-like electrode. The pixel electrode 71 may contain at least one selected from metals, metal compounds, and polysilicon doped with impurities to impart conductivity. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 71 may contain metal nitride as its main component.

[0090] The photoelectric conversion layer 73 is located above the pixel electrode 71 and covers the pixel electrode 71. The photoelectric conversion layer 73 is also positioned above the insulating layer 12. The photoelectric conversion layer 73 contains an organic semiconductor material and, upon receiving light incident via the counter electrode 72, generates positive and negative charges through photoelectric conversion. In other words, the photoelectric conversion layer 73 converts light into electric charge. The photoelectric conversion layer 73 may also contain an inorganic semiconductor material such as amorphous silicon. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 73 is formed continuously across, for example, multiple pixels 31. The photoelectric conversion layer 73 is shared by multiple pixels 31. The photoelectric conversion layer 73 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0091] The counter electrode 72 is located above the photoelectric conversion layer 73 and covers the photoelectric conversion layer 73. The counter electrode 72 is a film-like electrode. In the example shown in Figure 3, the counter electrode 72 and the photoelectric conversion layer 73 are aligned in terms of their side surfaces when viewed from above. The counter electrode 72 is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving surface side of the photoelectric conversion layer 73. The counter electrode 72 is formed continuously across multiple pixels 31, similar to the photoelectric conversion layer 73. That is, the counter electrodes 72 of multiple pixels 31 are electrically connected to each other. The counter electrodes 72 may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0092] The potential of the counter electrode 72 is controlled via the connecting electrode 75. When the imaging device 100 is in operation, the potential of the counter electrode 72 is controlled to make it different from the potential of the pixel electrode 71, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 71. The signal charge collected by the pixel electrode 71 is stored in a charge storage region connected to the pixel electrode 71 and detected by the detection circuit 32.

[0093] The insulating layer 81 is formed above the counter electrode 72. The insulating layer 81 is made of an insulating material such as silicon dioxide, silicon oxynitride, and aluminum oxide. A color filter (not shown) is located above the counter electrode 72 and faces the counter electrode 72 via the insulating layer 81. The color filter (not shown) is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. A microlens (not shown) is located above the color filter (not shown) and faces the color filter (not shown). The microlens (not shown) is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used.

[0094] The connecting electrode 75 is positioned in the peripheral region R2. The connecting electrode 75 is located on the upper surface of the insulating layer 12 in the peripheral region R2. The connecting electrode 75 is a film-like electrode. In the example shown in Figure 3, the connecting electrode 75 is located in the same layer as the pixel electrode 71. This allows the connecting electrode 75 to be formed simultaneously using the same process as the pixel electrode 71, thereby simplifying the manufacturing process of the imaging device 100. In this specification, "located in the same layer" means that the distance from the semiconductor substrate 11 is the same.

[0095] The material used for the connecting electrode 75 can be the same material used for the pixel electrode 71. The connecting electrode 75 may contain the same material as the material used for the pixel electrode 71. In this embodiment, the material of the connecting electrode 75 and the material of the pixel electrode 71 are the same. This allows for the common use of materials for the pixel electrode 71 and the connecting electrode 75, thereby reducing the number of materials used in the manufacture of the imaging device 100.

[0096] In the example shown in Figure 3, the connecting electrode 75 is electrically connected to the counter electrode 72 via a conductive cover metal film 82. Specifically, the connecting electrode 75 is electrically connected to the cover metal film 82 on its upper surface, and the counter electrode 72 is electrically connected to the cover metal film 82 on the side facing the connecting electrode 75. The cover metal film 82 is in contact with the upper surface of the connecting electrode 75 and the side of the counter electrode 72. Note that the connecting electrode 75 may also be connected to the counter electrode 72 via a conductor other than the cover metal film 82, as long as it is electrically connected to the counter electrode 72.

[0097] The cover metal film 82 covers at least a portion of the counter electrode 72 from above. In this embodiment, the cover metal film 82 covers the connecting electrode 75 and a portion of the counter electrode 72 from above. In the pixel region R1, the cover metal film 82 is located above the insulating layer 81 and faces the counter electrode 72.

[0098] Furthermore, the cover metal film 82 covers the sides of the insulating layer 81, the counter electrode 72, and the photoelectric conversion layer 73. In other words, the cover metal film 82 is formed from the connecting electrode 75, through the sides of the insulating layer 81, the counter electrode 72, and the photoelectric conversion layer 73, up to the upper surface of the insulating layer 81. The cover metal film 82 electrically connects the connecting electrode 75 and the counter electrode 72. In addition, there may be a protective film on the side of the photoelectric conversion layer 73, and the cover metal film 82 may cover the side of the photoelectric conversion layer 73 via the protective film.

[0099] The cover metal film 82 includes at least one selected from the group consisting of metals and metal compounds. The cover metal film 82 is formed of a metal. For example, the cover metal film 82 includes at least one selected from the group consisting of titanium, titanium nitride, tantalum, and tungsten.

[0100] The through-electrode 41 is, for example, located in the peripheral region R2. The number of through-electrodes 41 is not limited to the example shown in Figure 3, but may be three or more, for example.

[0101] The through-electrode 41 is a via that penetrates the semiconductor substrate 11. The through-electrode 41 is, for example, a TSV (Through Silicon Via). An insulating layer (not shown) is placed between the through-electrode 41 and the semiconductor substrate 11, and the through-electrode 41 and the semiconductor substrate 11 are separated by the insulating layer.

[0102] The through electrode 41 is formed of a metal. The through electrode 41 includes, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. In this embodiment, the through electrode 41 mainly contains copper.

[0103] The structure of the imaging device 100 of this embodiment will be described in more detail with reference to Figures 3 and 4. Figure 4 is a plan view showing the structure of the first through electrode 41A, the second through electrode 41B, the first connecting wiring 152A, and the second connecting wiring 154A.

[0104] As shown in Figure 3, the imaging device 100 includes, as described above, a semiconductor substrate 11, a first through electrode 41A, a second through electrode 41B, a first connecting wire 152A, a second connecting wire 154A, a third connecting wire 252A, and a fourth connecting wire 252B.

[0105] The first connection wiring 152A and the second connection wiring 154A are positioned closer to the first surface 11a of the semiconductor substrate 11 than to the second surface 11b. In other words, the first connection wiring 152A and the second connection wiring 154A are positioned on the first surface 11a side of the semiconductor substrate 11. The third connection wiring 252A and the fourth connection wiring 252B are positioned closer to the second surface 11b of the semiconductor substrate 11 than to the first surface 11a. In other words, the third connection wiring 252A and the fourth connection wiring 252B are positioned on the second surface 11b side of the semiconductor substrate 11. The first through-electrode 41A is directly connected to the first connection wiring 152A and the third connection wiring 252A. The second through-electrode 41B is directly connected to the second connection wiring 154A and the fourth connection wiring 252B. Furthermore, the distance L11 between the first connection wiring 152A and the semiconductor substrate 11 is different from the distance L12 between the second connection wiring 154A and the semiconductor substrate 11. In this embodiment, distance L11 is smaller than distance L12.

[0106] In this embodiment, as shown in Figures 3 and 4, in a plan view of the semiconductor substrate 11, the first connection wiring 152A overlaps with the second connection wiring 154A. In this embodiment, "in a plan view, one element overlaps with another element" means that at least a part of one element overlaps with at least a part of the other element. In other words, in a plan view, one element and the other element do not necessarily have to encompass the other. Also, in a plan view, the first through electrode 41A overlaps with the second connection wiring 154A. In this embodiment, in a plan view, the entire first through electrode 41A overlaps with the second connection wiring 154A. In other words, in this embodiment, in a plan view, the first through electrode 41A is contained inside the second connection wiring 154A. In other words, in a plan view, the first through electrode 41A is contained inside the second connection wiring 154A.

[0107] Furthermore, in this embodiment, the first through electrode 41A is made of the same material as the first connecting wire 152A. However, the first through electrode 41A may be made of a different material than the first connecting wire 152A.

[0108] Furthermore, in this embodiment, the second through electrode 41B is made of the same material as the second connecting wiring 154A. However, the second through electrode 41B may be made of a different material than the second connecting wiring 154A.

[0109] Furthermore, in this embodiment, the area of ​​the portion of the first through electrode 41A connected to the first connecting wiring 152A is larger than the area of ​​the portion of the first through electrode 41A connected to the third connecting wiring 252A. In other words, the area of ​​the surface of the first through electrode 41A connected to the first connecting wiring 152A is larger than the area of ​​the surface of the first through electrode 41A connected to the third connecting wiring 252A. Specifically, the via diameter, which is the diameter of the first through electrode 41A, gradually increases from the position in contact with the third connecting wiring 252A towards the position in contact with the first connecting wiring 152A. For example, the first through electrode 41A is formed in the shape of an inverted frustocone.

[0110] Furthermore, in this embodiment, the area of ​​the portion of the second through electrode 41B connected to the second connecting wiring 154A is larger than the area of ​​the portion of the second through electrode 41B connected to the fourth connecting wiring 252B. In other words, the area of ​​the surface of the second through electrode 41B connected to the second connecting wiring 154A is larger than the area of ​​the surface of the second through electrode 41B connected to the fourth connecting wiring 252B. Specifically, the via diameter, which is the diameter of the second through electrode 41B, gradually increases from the position in contact with the fourth connecting wiring 252B towards the position in contact with the second connecting wiring 154A. For example, the second through electrode 41B is formed in the shape of an inverted frustocone. The via diameter, which is the diameter of the largest portion (here, the upper end) of the first through electrode 41A and the second through electrode 41B, is several to tens of times larger than the via diameter, which is the diameter of the via 18.

[0111] In this embodiment, at least one of the first connection wiring 152A and the second connection wiring 154A is arranged across the pixel area R1 and the peripheral area R2. In this embodiment, both the first connection wiring 152A and the second connection wiring 154A are arranged across the pixel area R1 and the peripheral area R2.

[0112] Furthermore, at least one of the first connection wiring 152A and the second connection wiring 154A is electrically connected to the pixel 31. In this embodiment, both the first connection wiring 152A and the second connection wiring 154A are electrically connected to the pixel 31. Specifically, at least one of the first connection wiring 152A and the second connection wiring 154A is a signal wiring (here, a control signal line L1 or a vertical signal line L2) electrically connected to the pixel 31. In this embodiment, both the first connection wiring 152A and the second connection wiring 154A are signal wiring (here, a control signal line L1 or a vertical signal line L2) electrically connected to the pixel 31. Also, the pixel 31 to which the first connection wiring 152A and the second connection wiring 154A are connected may be the same pixel 31 or may be different pixels 31.

[0113] Furthermore, a plurality of first through electrodes 41A, a plurality of second through electrodes 41B, a plurality of first connecting wires 152A, and a plurality of second connecting wires 154A are provided. For example, at least one of the first through electrodes 41A, the second through electrodes 41B, the first connecting wires 152A, and the second connecting wires 154A may be provided, for example, for each row or column of a plurality of pixels 31.

[0114] Furthermore, the overlapping of the first connection wiring 152A and the second connection wiring 154A may be the same or different, for example. Also, the pitch of the first through electrode 41A and / or the pitch of the second through electrode 41B may be the same as or different from the pitch of the pixel 31.

[0115] [Manufacturing Method] The manufacturing method of the imaging device 100 of this embodiment will be described with reference to Figures 5 to 10. Figure 5 is a flowchart illustrating the manufacturing method of the imaging device 100. Figures 6 to 10 are cross-sectional views illustrating the manufacturing method of the imaging device 100. In the manufacturing of the imaging device 100, conventionally known methods such as semiconductor integrated circuit formation processes can be used for the method of forming impurity regions in the semiconductor substrate, as well as for forming insulating layers, wiring, vias, electrodes, etc.

[0116] As shown in Figure 5, in step S1, the first substrate 10 and the second substrate 20 are stacked. Specifically, as shown in Figure 6, the first substrate 10 is prepared with an insulating layer 12a which will become an insulating layer 12, a wiring layer 151 and a contact plug 19, etc., provided on top of the semiconductor substrate 11. The second substrate 20 is prepared with an insulating layer 22 and wiring 25, etc., provided on top of the semiconductor substrate 21. Then, the first substrate 10 and the second substrate 20 are stacked and connected to each other. The connection between the first substrate 10 and the second substrate 20 can be performed using known techniques, such as those disclosed in Japanese Patent Application Publication No. 2020-31074 and Japanese Patent No. 6907944.

[0117] Next, in step S2, as shown in Figure 7, a first through-electrode 41A and a wiring layer 152 penetrating the semiconductor substrate 11 are formed by the dual damascene method. At this time, vias 18 connecting the wiring layer 152 and the wiring layer 151 are also formed. Specifically, recesses are formed from the top surface of the first substrate 10 to a depth midway through the second substrate 20 so as to penetrate the semiconductor substrate 11. More specifically, recesses for forming the first through-electrode 41A are formed from the top surface of the first substrate 10 to the top surface of the wiring 252A. At this time, recesses for forming the vias 18 and the wiring layer 152 are also formed. Then, by filling the recesses with metal, the first through-electrode 41A, a part of the vias 18 and the wiring layer 152 are formed.

[0118] Next, in step S3, as shown in Figure 8, an insulating layer 12b is formed to cover the upper part of the first through electrode 41A. Specifically, the wiring layer 153 and the insulating layer 12b, which will become the insulating layer 12, are formed above the insulating layer 12a.

[0119] Next, in step S4, as shown in Figure 9, a second through-electrode 41B and a wiring layer 154 penetrating the semiconductor substrate 11 are formed by the dual damascene method. At this time, vias 18 connecting the wiring layer 154 and the wiring layer 153 are also formed. Specifically, recesses are formed from the top surface of the first substrate 10 to a depth midway through the second substrate 20 so as to penetrate the semiconductor substrate 11. More specifically, recesses for forming the second through-electrode 41B are formed from the top surface of the first substrate 10 to the top surface of the wiring 252B. At this time, recesses for forming the vias 18 and the wiring layer 154 are also formed. Then, by filling the recesses with metal, the second through-electrode 41B, a part of the vias 18 and the wiring layer 154 are formed.

[0120] Next, in step S5, as shown in Figure 10, an insulating layer 12 is formed so as to cover the upper part of the second through electrode 41B. At this time, a wiring layer 155 and the like are formed on the first substrate 10. Specifically, an insulating layer 12c is formed so as to cover the upper part of the insulating layer 12b. Thus, the insulating layer 12 is formed by the insulating layers 12a, 12b and 12c. Also, when forming the insulating layer 12c, the wiring layer 155 is formed. Then, vias 18, pixel electrodes 71 and connection electrodes 75 are formed. Note that the pixel electrodes 71 and connection electrodes 75 may be formed by doping a predetermined area of ​​the insulating layer 12c with impurities.

[0121] Next, in step S6, the photoelectric conversion unit 70, the insulating layer 81, and the cover metal film 82 are formed in a predetermined area of ​​the first substrate 10. The photoelectric conversion unit 70, the insulating layer 81, and the cover metal film 82 can be manufactured using known techniques.

[0122] In this way, the imaging device 100 shown in Figure 3 is manufactured.

[0123] As described above, the imaging device 100 according to this embodiment includes a semiconductor substrate 11 having a first surface 11a and a second surface 11b, a first through electrode 41A and a second through electrode 41B penetrating the semiconductor substrate 11, a first connection wiring 152A and a second connection wiring 154A positioned closer to the first surface 11a than to the second surface 11b of the semiconductor substrate 11, and a third connection wiring 252A and a fourth connection wiring 252B positioned closer to the second surface 11b than to the first surface 11a of the semiconductor substrate 11. The first through electrode 41A is directly connected to the first connection wiring 152A and the third connection wiring 252A, and the second through electrode 41B is directly connected to the second connection wiring 154A and the fourth connection wiring 252B. The distance L11 between the first connection wiring 152A and the semiconductor substrate 11 is different from the distance L12 between the second connection wiring 154A and the semiconductor substrate 11. In a plan view of the semiconductor substrate 11, the first connection wiring 152A overlaps with the second connection wiring 154A.

[0124] This allows the first connection wiring 152A and the second connection wiring 154A, which are at different distances from the semiconductor substrate 11, to overlap in a plan view, thereby suppressing an increase in the area of ​​the semiconductor substrate 11. On the other hand, if the distances of the two connection wirings from the semiconductor substrate 11 are the same, it is necessary to route one connection wiring so that it does not come into contact with the other connection wiring, which increases the area of ​​the semiconductor substrate 11.

[0125] Furthermore, since the first through-electrode 41A is directly connected to the first connection wiring 152A and the third connection wiring 252A, and the second through-electrode 41B is directly connected to the second connection wiring 154A and the fourth connection wiring 252B, the first through-electrode 41A and the second through-electrode 41B can be placed close together. This makes it possible to suppress an increase in the area of ​​the semiconductor substrate 11. On the other hand, if the two through-electrodes, which are through-vias, are directly connected to, for example, a transistor or electrode that constitutes a pixel 31 and has a fixed layout, the positions of the two through-vias are also fixed, making it difficult to bring the two through-vias closer together. This makes it difficult to suppress an increase in the area of ​​the semiconductor substrate 11.

[0126] Furthermore, in the imaging device 100, the first through electrode 41A is made of the same material as the first connecting wiring 152A.

[0127] This allows the first through electrode 41A and the first connecting wiring 152A to be formed simultaneously in the same process. Furthermore, in this embodiment, the first through electrode 41A, the first connecting wiring 152A, the via 18, and other wirings in the wiring layer 152 can also be formed simultaneously in the same process.

[0128] Furthermore, in the imaging device 100, the second through electrode 41B is made of the same material as the second connecting wiring 154A.

[0129] This allows the second through electrode 41B and the second connecting wiring 154A to be formed simultaneously in the same process. Furthermore, in this embodiment, the second through electrode 41B, the second connecting wiring 154A, the via 18, and other wirings of the wiring layer 154 can also be formed simultaneously in the same process.

[0130] Furthermore, in the imaging device 100, the area of ​​the portion where the first through electrode 41A is connected to the first connecting wiring 152A is larger than the area of ​​the portion where the first through electrode 41A is connected to the third connecting wiring 252A, and the area of ​​the portion where the second through electrode 41B is connected to the second connecting wiring 154A is larger than the area of ​​the portion where the second through electrode 41B is connected to the fourth connecting wiring 252B.

[0131] In this way, overlapping the two connection lines, namely the first connection line 152A and the second connection line 154A, on the side with the larger via diameter significantly reduces the effect of increasing the area of ​​the semiconductor substrate 11. Specifically, even if one attempts to bring the first through electrode 41A and the second through electrode 41B closer together by overlapping the two connection lines, namely the third connection line 252A and the fourth connection line 252B, on the side with the smaller via diameter, the distance between the first through electrode 41A and the second through electrode 41B may be limited on the side with the larger via diameter. Therefore, overlapping the two connection lines on the side with the larger via diameter is more effective.

[0132] Furthermore, the imaging device 100 includes a pixel region R1 containing a plurality of pixels 31, and a peripheral region R2 provided around the pixel region R1 in a plan view. At least one of the first connecting wire 152A and the second connecting wire 154A is arranged to span the pixel region R1 and the peripheral region R2.

[0133] This allows, for example, the distance between one through-via (e.g., first through-electrode 41A) and the other through-via (e.g., second through-electrode 41B) connected to the pixel region R1 to be shortened, thereby suppressing an increase in the area of ​​the peripheral region R2. For this reason, an increase in the area of ​​the semiconductor substrate 11 can be easily suppressed.

[0134] Furthermore, the imaging device 100 includes pixels 31, and at least one of the first connection wiring 152A and the second connection wiring 154A is electrically connected to the pixels 31.

[0135] With this configuration, there are a large number of connection wires, usually several thousand or more, that are electrically connected to the pixel 31. By overlapping these connection wires, the effect of reducing the area of ​​the semiconductor substrate 11 becomes significant.

[0136] Furthermore, since the distance from the pixel 31 to the through electrode 41 can be shortened, an imaging device 100 that operates at low resistance and high speed can be obtained.

[0137] [First Modified Example] Next, a first modified example of the imaging device 100 according to the above embodiment will be described with reference to Figures 11 and 12. Figure 11 is a cross-sectional view showing the device structure of the imaging device 100 of the first modified example. Figure 12 is a plan view showing the structure of the first through electrode 41A, the second through electrode 41B, the first connecting wiring 152A, and the second connecting wiring 154A.

[0138] As shown in Figure 11, in the first modified example, unlike the above embodiment, at least one of the first connecting wire 152A and the second connecting wire 154A is not formed up to the pixel region R1. In the first modified example, both the first connecting wire 152A and the second connecting wire 154A are not formed up to the pixel region R1.

[0139] Note that at least one of the first connection wiring 152A and the second connection wiring 154A does not need to be electrically connected to the pixel 31. In the first modified example, neither the first connection wiring 152A nor the second connection wiring 154A is electrically connected to the pixel 31.

[0140] Furthermore, as shown in Figure 12, similar to the above embodiment, in a plan view, the first connecting wire 152A overlaps with the second connecting wire 154A. Also, in a plan view, the first through electrode 41A overlaps with the second connecting wire 154A. Also, similar to the above embodiment, in a plan view, the entire first through electrode 41A overlaps with the second connecting wire 154A.

[0141] The other structures, manufacturing methods, and effects of the first modified example are the same as those of the embodiments described above.

[0142] [Second Modification] Next, a second modification of the imaging device 100 according to the above embodiment will be described with reference to Figures 13 and 14. Figure 13 is a cross-sectional view showing the device structure of the imaging device 100 of the second modification. Figure 14 is a plan view showing the structure of the first through electrode 41A, the second through electrode 41B, the first connecting wiring 152A, the second connecting wiring 154A, and the wiring 153A.

[0143] As shown in Figure 13, in the second modified example, unlike the embodiments described above, at least one of the first connection wiring 152A and the second connection wiring 154A is electrically connected to the signal wiring. Here, the second connection wiring 154A is electrically connected to the signal wiring. Specifically, the wiring layer 153 includes wiring 153A. Wiring 153A is a control signal line L1 or a vertical signal line L2 electrically connected to the pixel 31. The second connection wiring 154A is connected to wiring 153A via via 18A. Via 18A is directly connected to the second connection wiring 154A and wiring 153A. Via 18A, which is connected to the second connection wiring 154A and wiring 153A, is an example of a "non-through via" in this disclosure. Wiring 153A is an example of a "signal wiring" and a "fifth connection wiring" in this disclosure.

[0144] The distance L11 between the first connection wiring 152A and the semiconductor substrate 11 is different from the distance L13 between the wiring 153A and the semiconductor substrate 11.

[0145] Furthermore, as shown in Figures 13 and 14, in a plan view, the first connecting wire 152A overlaps with the second connecting wire 154A. Also, the first connecting wire 152A overlaps with wire 153A. Also, in a plan view, the first through electrode 41A overlaps with the second connecting wire 154A. In the second modified example, in a plan view, the first through electrode 41A overlaps with wire 153A. Also, in the second modified example, in a plan view, the first through electrode 41A overlaps with via 18A connecting wire 153A and the second connecting wire 154A.

[0146] The other structures and manufacturing methods of the second modified example are the same as those of the embodiments described above.

[0147] As described above, the imaging device 100 of the second modified example includes a wiring 153A which is a signal wiring electrically connected to the pixel 31, and at least one of the first connection wiring 152A and the second connection wiring 154A (in this case, the second connection wiring 154A) is electrically connected to the wiring 153A which is a signal wiring.

[0148] With this configuration, there are many signal lines 153A that are electrically connected to the pixels 31, usually thousands or more. By stacking the connection lines connected to these, the effect of reducing the area of ​​the semiconductor substrate 11 becomes significant.

[0149] Furthermore, since the distance from the pixel 31 to the through electrode 41 can be easily shortened, an imaging device 100 that operates at low resistance and high speed can be easily obtained.

[0150] Furthermore, the imaging device 100 includes a via 18A that is directly connected to the second connecting wiring 154A and does not penetrate the semiconductor substrate 11, and a wiring 153A that is directly connected to the via 18A. The distance L11 between the first connecting wiring 152A and the semiconductor substrate 11 is different from the distance L13 between the wiring 153A and the semiconductor substrate 11. In a plan view, the first connecting wiring 152A overlaps with the wiring 153A.

[0151] This allows the first connecting wiring 152A and wiring 153A, which are at different distances from the semiconductor substrate 11, to be arranged so that they overlap in a plan view, thereby further suppressing an increase in the area of ​​the semiconductor substrate 11.

[0152] Furthermore, the imaging device 100 is directly connected to the second connection wiring 154A and includes a via 18A that does not penetrate the semiconductor substrate 11. The first through electrode 41A overlaps with the via 18A in a plan view.

[0153] In this way, by arranging the first through electrode 41A and the via 18A to overlap in a plan view, the increase in the area of ​​the semiconductor substrate 11 can be further suppressed.

[0154] [Third Modification] Next, a third modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 15. Figure 15 is a cross-sectional view showing the device structure of the imaging device 100 of the third modification.

[0155] As shown in Figure 15, in the third modified example, unlike the embodiments described above, the through electrode 41 includes a third through electrode 41C that is positioned adjacent to the first through electrode 41A or the second through electrode 41B.

[0156] Furthermore, in the third modified example, the multiple wiring layers 15 include wiring layers 156 and 157 in addition to wiring layers 151 to 155. Wiring layer 156 includes, for example, wiring 156A. Wiring 156A is a connecting wire that is directly connected to the third through electrode 41C. Also, wiring layer 252 includes wiring 252C. Wiring 252C is a connecting wire that is directly connected to the third through electrode 41C. Hereinafter, wiring 156A may be referred to as the sixth connecting wire 156A, and wiring 252C may be referred to as the seventh connecting wire 252C.

[0157] The third through electrode 41C is directly connected to the sixth connecting wire 156A and the seventh connecting wire 252C.

[0158] In the third modified example, the distance L14 between the sixth connection wiring 156A and the semiconductor substrate 11 is different from the distance L11 between the first connection wiring 152A and the semiconductor substrate 11. Also, the distance L14 is different from the distance L12 between the second connection wiring 154A and the semiconductor substrate 11.

[0159] In a plan view, the first connecting wire 152A, the second connecting wire 154A, and the sixth connecting wire 156A overlap.

[0160] In the third modified example, the first through electrode 41A overlaps with the first connecting wire 152A, the second connecting wire 154A, the via 18A connected to the second connecting wire 154A, the sixth connecting wire 156A, and the via 18B connected to the sixth connecting wire 156A.

[0161] Furthermore, at least one of the first connection wiring 152A, the second connection wiring 154A, and the sixth connection wiring 156A may be directly connected to the pixel 31.

[0162] The other structures and manufacturing methods of the third modified example are the same as those of the embodiments described above.

[0163] As described above, in the imaging device 100 of the third modified example, the first connection wiring 152A, the second connection wiring 154A, and the sixth connection wiring 156A overlap. This further suppresses the increase in the area of ​​the semiconductor substrate 11.

[0164] Furthermore, the first through-electrode 41A overlaps with the first connection wiring 152A, the second connection wiring 154A, the via 18A connected to the second connection wiring 154A, the sixth connection wiring 156A, and the via 18B connected to the sixth connection wiring 156A. This further suppresses the increase in the area of ​​the semiconductor substrate 11.

[0165] [Fourth Modification] Next, a fourth modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 16. Figure 16 is a cross-sectional view showing the device structure of the imaging device 100 of the fourth modification.

[0166] As shown in Figure 16, in the fourth modification, similar to the third modification, the through electrode 41 includes a third through electrode 41C positioned adjacent to the first through electrode 41A or the second through electrode 41B. However, in the fourth modification, the height of the third through electrode 41C is different from that of the third modification. This will be explained in detail below.

[0167] In the fourth modified example, the multiple wiring layers 15 include wiring layers 151 to 155, but do not include wiring layers 156 and 157. Wiring layer 154 includes wiring 154A as well as wiring 154B. Wiring 154B is a connecting wire that is directly connected to the third through electrode 41C. Hereinafter, wiring 154B may be referred to as the sixth connecting wire 154B.

[0168] The wiring layer 252 includes a seventh connecting wiring 252C, similar to the third modified example.

[0169] The third through electrode 41C is directly connected to the sixth connecting wire 154B and the seventh connecting wire 252C.

[0170] In the fourth modified example, the distance L15 between the sixth connection wiring 154B and the semiconductor substrate 11 is the same as the distance L12 between the second connection wiring 154A and the semiconductor substrate 11. On the other hand, the distance L15 between the sixth connection wiring 154B and the semiconductor substrate 11 is different from the distance L11 between the first connection wiring 152A and the semiconductor substrate 11.

[0171] In a plan view, the first connection wiring 152A overlaps with the second connection wiring 154A. Also, the first connection wiring 152A overlaps with the sixth connection wiring 154B. On the other hand, in a plan view, the second connection wiring 154A and the sixth connection wiring 154B do not overlap.

[0172] In the fourth modified example, the first through electrode 41A overlaps with the first connecting wire 152A, the sixth connecting wire 154B, and the via 18C connected to the sixth connecting wire 154B.

[0173] Furthermore, at least one of the first connection wiring 152A, the second connection wiring 154A, and the sixth connection wiring 154B may be directly connected to the pixel 31.

[0174] The other structures and manufacturing methods of the fourth modification are the same as those of the third modification described above.

[0175] As described above, in the imaging device 100 of the fourth modified example, the first connection wiring 152A overlaps with the second connection wiring 154A and also with the sixth connection wiring 154B. This further suppresses the increase in the area of ​​the semiconductor substrate 11.

[0176] Furthermore, the first through-electrode 41A overlaps with the first connection wiring 152A, the sixth connection wiring 154B, and the via 18C connected to the sixth connection wiring 154B. This further suppresses the increase in the area of ​​the semiconductor substrate 11.

[0177] [Fifth Modification] Next, a fifth modification of the imaging device 100 according to the above embodiment will be described with reference to Figure 17. Figure 17 is a cross-sectional view showing the device structure of the imaging device 100 of the fifth modification. In the fifth modification, unlike the above embodiment, an example will be described in which the third and fourth connecting wires, which are located closer to the second surface 11b than the first surface 11a of the semiconductor substrate 11, overlap. In the fifth modification, a part of the first modification shown in Figure 11 will be modified for explanation, but for example, a part of the above embodiment or other modifications may be modified.

[0178] As shown in Figure 17, in the fifth modified example, unlike the above embodiment, the third connecting wire, wire 251A, and the fourth connecting wire, wire 252B, overlap in a plan view. Specifically, in the fifth modified example, the wiring layer 251 includes wire 251A. Wiring 251A is a connecting wire that is directly connected to the first through electrode 41A. Wiring 251A is an example of the "third connecting wire" in this disclosure. Hereinafter, wiring 251A may be referred to as the third connecting wire 251A.

[0179] In the fifth modified example, the third connecting wire 251A, which is directly connected to the first through electrode 41A, and the fourth connecting wire 252B, which is directly connected to the second through electrode 41B, overlap in a plan view.

[0180] The other structures and manufacturing methods of the fifth modified example are the same as those of the embodiments described above.

[0181] As described above, in the imaging device 100 of the fifth modified example, the third connection wiring 251A and the fourth connection wiring 252B overlap in a plan view. This further suppresses the increase in the area of ​​the semiconductor substrate 11.

[0182] [Sixth Modification] Next, with reference to Figure 18, a semiconductor device 110 according to the sixth modification of the present disclosure will be described. Figure 18 is a cross-sectional view showing the device structure of the semiconductor device 110 of the sixth modification. In the sixth modification, unlike the above embodiments, an example will be described in which the present disclosure is a semiconductor device 110 instead of an imaging device 100. In the sixth modification, a part of the first modification shown in Figure 11 will be modified for explanation, but for example, a part of the above embodiment or other modifications may be modified.

[0183] As shown in Figure 18, in the sixth modified example, the semiconductor device 110 comprises the semiconductor substrate 11 described above, a first through electrode 41A, a second through electrode 41B, a first connection wiring 152A, a second connection wiring 154A, a third connection wiring 252A or 251A, and a fourth connection wiring 252B.

[0184] On the other hand, the semiconductor device 110 does not include pixels 31 and a photoelectric conversion unit 70, etc. The semiconductor device 110 is a semiconductor device other than the imaging device 100, such as a memory.

[0185] The other structures, manufacturing methods, and effects of the sixth modified example are the same as those of the embodiments described above.

[0186] (Other Embodiments) The imaging apparatus and semiconductor device relating to the present disclosure have been described above based on embodiments and modifications, but the present disclosure is not limited to these embodiments. Without departing from the spirit of the present disclosure, various modifications to the embodiments that a person skilled in the art could conceive of, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of the present disclosure.

[0187] For example, in the above embodiments, the imaging device 100 includes a first substrate 10 and a second substrate 20, but is not limited thereto. For example, the imaging device according to this disclosure may include only the first substrate 10 as a substrate, and the pixels 31 may be connected to a device or element other than the imaging device and semiconductor device according to this disclosure via a through electrode 41.

[0188] Furthermore, although the above embodiments describe an example in which the first through electrode 41A and the second through electrode 41B are provided in the peripheral region R2, the disclosure is not limited thereto. For example, the first through electrode 41A and the second through electrode 41B may be provided in the pixel region R1.

[0189] Furthermore, while the above embodiments show examples of overlapping connecting wiring positioned on the side with the larger via diameter of the through-electrode, which is a through-via, the present disclosure is not limited to this. For example, connecting wiring positioned on the side with the smaller via diameter of the through-electrode, which is a through-via, may be overlapped. In other words, for example, in the above embodiments, the via diameters of the first through-electrode 41A and the second through-electrode 41B may gradually decrease towards the top.

[0190] Furthermore, although the above embodiment shows an example in which the photoelectric conversion unit 70, which includes an organic semiconductor material, is provided on the insulating layer 12, the disclosure is not limited thereto. The photoelectric conversion unit may also be provided on the semiconductor substrate 11.

[0191] Furthermore, although the above embodiment shows an example where the semiconductor substrate 11 is a silicon substrate, this disclosure is not limited to this, and the semiconductor substrate 11 may be a substrate other than a silicon substrate.

[0192] Furthermore, the imaging device 100 may be used in camera systems such as smartphones, digital cameras, video cameras, and in-vehicle cameras. Such a camera system may include, for example, an imaging device, a lens optical system that focuses light onto the imaging device, a system controller consisting of a CPU (Central Processing Unit) or the like, and a camera signal processing circuit that processes the output signal from the imaging device.

[0193] Furthermore, each of the above embodiments may be modified, replaced, added, omitted, etc., within the scope of the claims or their equivalents.

[0194] This disclosure can be applied, for example, to imaging devices and semiconductor devices having multiple through-vias penetrating a semiconductor substrate.

[0195] 10 First substrate 11, 21 Semiconductor substrate 11a First surface 11b Second surface 12, 12a, 12b, 12c, 22, 81 Insulating layer 15, 151, 152, 153, 154, 155, 156, 157 Wiring layer 18 Via 18A, 18B, 18C Via (non-through via) 19 Contact plug 20 Second substrate 25, 251, 252 Wiring layer 30 Pixel array 31 Pixel 32 Detection circuit 41 Through electrode 41A First through electrode (first through via) 41B Second through electrode (second through via) 41C Third through electrode 51 Peripheral circuit 52 Vertical scanning circuit 53 Column signal processing circuit 70 Photoelectric conversion unit 71 Pixel electrode 72 Opposing electrode 73 Photoelectric conversion layer 75 Connection electrodes 82 Cover metal film 100 Imaging device 110 Semiconductor device 152A Wiring (first connection wiring) 153A Wiring (signal wiring, fifth connection wiring) 154A Wiring (second connection wiring) 154B, 156A Wiring (sixth connection wiring) 251A, 252A Wiring (third connection wiring) 252B Wiring (fourth connection wiring) 252C Wiring (seventh connection wiring) 310 Signal detection circuit 311 Signal detection transistor 3 312 Address transistor 313 Reset transistor 314 Protection transistor 316 Feedback circuit 331 Accumulation control line 332, 337 Power supply wiring 336 Reset signal line 345 Load circuit 347 Column signal processing circuit 349 Horizontal common signal line 350 Inverting amplifier 353 Feedback line FD Charge accumulation node L1 Control signal line L2 Vertical signal line L11, L12, L13, L14, L15 Distance R1 Pixel area R2 Peripheral area

Claims

1. An imaging device comprising: a semiconductor substrate including a first surface and a second surface; a first through-via penetrating the semiconductor substrate; a second through-via penetrating the semiconductor substrate; a first connection wiring positioned closer to the first surface than the second surface; a second connection wiring positioned closer to the first surface than the second surface; a third connection wiring positioned closer to the second surface than the first surface; and a fourth connection wiring positioned closer to the second surface than the first surface, wherein the first through-via is directly connected to the first and third connection wirings, the second through-via is directly connected to the second and fourth connection wirings, the distance between the first connection wiring and the semiconductor substrate is different from the distance between the second connection wiring and the semiconductor substrate, and in a plan view of the semiconductor substrate, the first connection wiring overlaps with the second connection wiring.

2. The imaging apparatus according to claim 1, wherein the first through via is made of the same material as the first connecting wiring.

3. The imaging apparatus according to claim 2, wherein the second through via is made of the same material as the second connecting wiring.

4. The imaging apparatus according to any one of claims 1 to 3, wherein the area of ​​the portion of the first through via connected to the first connecting wiring is greater than the area of ​​the portion of the first through via connected to the third connecting wiring, and the area of ​​the portion of the second through via connected to the second connecting wiring is greater than the area of ​​the portion of the second through via connected to the fourth connecting wiring.

5. The imaging device according to any one of claims 1 to 3, further comprising: a pixel region containing a plurality of pixels; and a peripheral region provided around the pixel region in a plan view, wherein at least one selected from the group consisting of the first connection wiring and the second connection wiring is arranged across the pixel region and the peripheral region.

6. The imaging apparatus according to any one of claims 1 to 3, further comprising a pixel, wherein at least one selected from the group consisting of the first connection wiring and the second connection wiring is electrically connected to the pixel.

7. The imaging apparatus according to claim 6, further comprising signal wiring electrically connected to the pixel, wherein at least one selected from the group consisting of the first connection wiring and the second connection wiring is electrically connected to the signal wiring.

8. The imaging apparatus according to any one of claims 1 to 3, further comprising: a non-penetrating via directly connected to the second connecting wiring and not penetrating the semiconductor substrate; and a fifth connecting wiring directly connected to the non-penetrating via, wherein the distance between the first connecting wiring and the semiconductor substrate is different from the distance between the fifth connecting wiring and the semiconductor substrate, and in the plan view, the first connecting wiring overlaps with the fifth connecting wiring.

9. The imaging apparatus according to any one of claims 1 to 3, further comprising a non-penetrating via that is directly connected to the second connecting wiring and does not penetrate the semiconductor substrate, wherein the first penetrating via overlaps with the non-penetrating via in the plan view.

Images