Capacitor assembly and method for manufacturing capacitor assembly

Abstract

In the present invention, a plurality of capacitors are arranged in a capacitor formation region in a plan view from the thickness direction of a silicon wafer. Each of the plurality of capacitors includes a first porous portion, an insulator portion, a dielectric layer, and a conductor layer. The first porous portion has a plurality of first pores extending along the thickness direction of the silicon wafer. The insulator portion surrounds the first porous portion in the plan view from the thickness direction of the silicon wafer. At least one process monitoring portion includes a second porous portion. The second porous portion includes a first porous region and a second porous region. The first porous region has a plurality of second pores extending along the thickness direction of the silicon wafer. The second porous region surrounds the first porous region and has a plurality of third pores extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer.

Description

Capacitor assembly, and method for manufacturing a capacitor assembly

[0001] This disclosure relates to a capacitor assembly and a method for manufacturing a capacitor assembly, and more particularly to a capacitor assembly having a plurality of capacitors formed on a silicon wafer, and a method for manufacturing a capacitor assembly having a plurality of capacitors formed on a silicon wafer.

[0002] Patent Document 1 discloses a method for manufacturing a capacitor.

[0003] In the capacitor manufacturing method disclosed in Patent Document 1, a porous portion is formed by anodic oxidation treatment of a silicon substrate, a dielectric layer is formed, and then a conductive layer is formed.

[0004] International Publication No. 2022 / 131048

[0005] A capacitor assembly according to one aspect of the present disclosure comprises a plurality of capacitors formed on a silicon wafer. The capacitor assembly includes a capacitor formation region and a non-capacitor formation region. The plurality of capacitors are arranged in the capacitor formation region in a plan view from the thickness direction of the silicon wafer. The non-capacitor formation region surrounds the capacitor formation region in a plan view from the thickness direction of the silicon wafer. Each of the plurality of capacitors includes a first porous portion, an insulating portion, a dielectric layer, and a conductive layer. The first porous portion is formed on the silicon wafer. The first porous portion has a plurality of first pores extending along the thickness direction of the silicon wafer. The insulating portion is located within the silicon wafer and surrounds the first porous portion in a plan view from the thickness direction of the silicon wafer. The dielectric layer is located on the surface of the first porous portion. The conductive layer is laminated on the dielectric layer. The capacitor assembly further comprises at least one process monitor portion located in the capacitor formation region. The at least one process monitor unit includes a second porous region formed in the silicon wafer. The second porous region includes a first porous region and a second porous region. The first porous region has a plurality of second pores extending along the thickness direction of the silicon wafer. The second porous region surrounds the first porous region and has a plurality of third pores extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer.

[0006] A method for manufacturing a capacitor assembly according to this disclosure is a method for manufacturing a capacitor assembly in which a plurality of capacitors are formed on a silicon wafer. The capacitor assembly includes a capacitor formation region and a non-capacitor formation region. The plurality of capacitors are arranged in the capacitor formation region in a plan view from the thickness direction of the silicon wafer. The non-capacitor formation region surrounds the capacitor formation region in a plan view from the thickness direction of the silicon wafer. Each of the plurality of capacitors includes a first porous portion, an insulator portion, a dielectric layer, and a conductor layer. The first porous portion is formed on the silicon wafer. The first porous portion has a plurality of first pores extending along the thickness direction of the silicon wafer. The insulator portion is located within the silicon wafer and surrounds the first porous portion in a plan view from the thickness direction of the silicon wafer. The dielectric layer is arranged on the surface of the first porous portion. The conductor layer is laminated on the dielectric layer. The capacitor assembly further includes at least one process monitor portion located in the capacitor formation region. The at least one process monitor unit includes a second porous unit formed on the silicon wafer. The second porous unit includes a first porous region and a second porous region. The first porous region has a plurality of second pores extending along the thickness direction of the silicon wafer. The second porous region surrounds the first porous region and has a plurality of third pores extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer. The method for manufacturing the capacitor assembly comprises an insulating layer formation step, an anodizing step, and an inspection step. In the insulating layer formation step, an insulating layer having a first opening for forming the first porous unit and a second opening for forming the second porous unit is formed on the main surface of the silicon wafer. In the anodizing step, the silicon wafer is anodized using the insulating layer as a mask to form the first porous unit of each of the plurality of capacitors and the second porous unit of the at least one process monitor unit.In the inspection step, a quality determination is made based on an estimation result obtained by estimating the formation depth of the first porous portion based on the width of the second porous region in the second porous portion of the silicon wafer in a plan view from the thickness direction.

[0007] According to the capacitor assembly and the method for manufacturing the capacitor assembly described in the above-mentioned embodiments of this disclosure, it is possible to reduce costs.

[0008] Figure 1 is a plan view of a capacitor assembly according to Embodiment 1. Figure 2 is a partial cross-sectional view of the capacitor assembly according to Embodiment 1 along line II-II in Figure 1. Figure 3 is a plan view of a capacitor in the capacitor assembly according to Embodiment 1. Figure 4 is a partial cross-sectional view of a silicon wafer prepared in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 5 is a partial cross-sectional view illustrating the groove formation process in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 6 is a partial cross-sectional view illustrating the insulating layer formation process in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 7 is a partial cross-sectional view illustrating the anodizing process in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 8 is a partial cross-sectional view illustrating the dielectric layer formation process in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 9 is a partial cross-sectional view illustrating the conductive layer formation process in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 10 is a schematic diagram of a photograph of the region corresponding to the capacitor after the anodizing treatment has been completed in the manufacturing method of the capacitor assembly according to Embodiment 1, observed with a microscope. Figure 11 is a schematic diagram of a photograph of the region corresponding to the process monitor section after the anodizing treatment is completed in the manufacturing method of the capacitor assembly according to Embodiment 1, observed with a microscope. Figure 12 is a plan view of the region corresponding to the process monitor section after the anodizing treatment is completed in the manufacturing method of the capacitor assembly according to Embodiment 1. Figure 13 is a plan view of the capacitor assembly according to Embodiment 2. Figure 14 is a plan view of the capacitor assembly according to Embodiment 3. Figure 15 is a plan view of the capacitor assembly according to Embodiment 4. Figure 16 is a cross-sectional view of the main part of the capacitor assembly according to Embodiment 5.

[0009] In the capacitor manufacturing method disclosed in Patent Document 1, it is not possible to non-destructively measure the formation depth (corresponding to the depth of pores) of the porous portion formed on the silicon substrate (silicon wafer) after the anodizing process is completed, without damaging the silicon substrate. In the capacitor manufacturing method disclosed in Patent Document 1, in order to inspect the formation depth of the porous portion, it is necessary to either break the silicon substrate after the anodizing process is completed and perform the inspection, or to carry out the capacitor manufacturing method to the final step and then measure the electrical characteristics of the capacitor formed on the silicon substrate, which can increase manufacturing costs.

[0010] This disclosure provides a capacitor assembly that can be manufactured at a lower cost, and a method for manufacturing the capacitor assembly.

[0011] The embodiments will be described below with reference to the drawings. The drawings referenced in the following embodiments are schematic diagrams, and the size and thickness of the components shown in the drawings do not necessarily reflect the actual dimensions, nor do the size ratios and thickness ratios between components necessarily reflect the actual dimensional ratios.

[0012] (Embodiment 1) (1) Capacitor Assembly Hereinafter, the capacitor assembly 1 according to Embodiment 1 will be described with reference to Figures 1 to 3.

[0013] As shown in Figure 1, the capacitor assembly 1 according to Embodiment 1 has a plurality of capacitors 10 formed on a silicon wafer 2. As shown in Figure 1, in a plan view from the thickness direction D1 (see Figure 2) of the silicon wafer 2, the capacitor assembly 1 is substantially circular in shape. The capacitor assembly 1 includes a capacitor formation region 11 and a non-capacitor formation region 12.

[0014] In the capacitor formation region 11, multiple capacitors 10 are arranged in a plan view from the thickness direction D1 (see Figure 2) of the silicon wafer 2.

[0015] The non-capacitor formation region 12 surrounds the capacitor formation region 11 in a plan view from the thickness direction of the silicon wafer 2.

[0016] Each of the multiple capacitors 10 includes a first porous portion 23, an insulating portion 4, a dielectric layer 5, and a conductive layer 6, as shown in Figure 2.

[0017] The first porous portion 23 is formed on the silicon wafer 2. The first porous portion 23 has a plurality of first pores 230 that extend along the thickness direction D1 of the silicon wafer 2.

[0018] The insulating portion 4 is located within the silicon wafer 2 and surrounds the first porous portion 23 when viewed from the thickness direction of the silicon wafer 2 in a plan view.

[0019] The dielectric layer 5 is located on the surface 231 of the first porous portion 23. The conductive layer 6 is laminated on the dielectric layer 5.

[0020] Furthermore, each of the multiple capacitors 10 further includes a first external connection electrode 7 and a second external connection electrode 8.

[0021] The first external connection electrode 7 is in contact with the main surface 21 of the silicon wafer 2 and is electrically connected to the silicon wafer 2. The second external connection electrode 8 is placed on the conductive layer 6 and is electrically connected to the conductive layer 6.

[0022] As shown in Figure 1, the capacitor assembly 1 further comprises a plurality (five in the illustrated example) of process monitor units 20 located in the capacitor formation region 11.

[0023] Each of the multiple process monitoring units 20 includes a second porous portion 24 formed on the silicon wafer 2, as shown in Figure 2. Each of the multiple process monitoring units 20 is a PCM (Process Control Monitor).

[0024] The second porous region 24 includes a first porous region 25 and a second porous region 26. The first porous region 25 has a plurality of second pores 250 extending along the thickness direction D1 of the silicon wafer 2. The second porous region 26 surrounds the first porous region 25 and has a plurality of third pores 260 extending along an oblique direction inclined with respect to the thickness direction D1 of the silicon wafer 2.

[0025] The capacitor assembly 1 according to Embodiment 1 will be described in more detail below.

[0026] As shown in Figure 2, the silicon wafer 2 has a main surface 21 (hereinafter also referred to as the first main surface 21) and a second main surface 22 on the opposite side of the first main surface 21.

[0027] In a plan view from the thickness direction D1 of the silicon wafer 2, the silicon wafer 2 has the same approximately circular shape as the capacitor assembly 1. An orientation flat is formed on the silicon wafer 2. The diameter of the silicon wafer 2 is, for example, 100 mm or more and 300 mm or less. The thickness of the silicon wafer 2 is, for example, 300 μm or more and 1 mm or less.

[0028] The silicon wafer 2 is a p-type silicon wafer. The silicon wafer 2 contains, for example, boron as an impurity, but may also contain indium instead of boron as an impurity.

[0029] The capacitor formation region 11 is, for example, a substantially circular region having a diameter smaller than the diameter of the silicon wafer 2 when viewed from a plan view from the thickness direction D1 of the silicon wafer 2. In the capacitor formation region 11, a plurality of capacitors 10 are arranged in a two-dimensional array when viewed from a plan view from the thickness direction D1 of the silicon wafer 2 (see Figure 2).

[0030] The non-capacitor formation region 12 is the region between the capacitor formation region 11 and the outer edge of the silicon wafer 2 when viewed from a plan view from the thickness direction D1 of the silicon wafer 2. The distance between the capacitor formation region 11 and the outer edge of the silicon wafer 2 is, for example, 10 mm, but is not limited to 10 mm.

[0031] The plurality of first porous portions 23 and the plurality of second porous portions 24 are made of porous silicon and are formed as part of the silicon wafer 2 by anodizing. In this embodiment, the capacitor assembly 1 includes an insulating layer 3 having a plurality of first openings 31 for forming the plurality of first porous portions 23 and a plurality of second openings 32 for forming the plurality of second porous portions 24. The insulating layer 3 is disposed on the main surface 21 of the silicon wafer 2.

[0032] As shown by the dashed line in Figure 3, in a plan view from the thickness direction D1 of the silicon wafer 2, each of the multiple first openings 31 of the insulating layer 3 has a rectangular shape. Also, in a plan view from the thickness direction D1 of the silicon wafer 2, each of the multiple second openings 32 (see Figure 2) of the insulating layer 3 has a rectangular shape. The opening shapes of each first opening 31 and each second opening 32 are not limited to rectangular shapes; for example, they may be circular.

[0033] As shown in Figure 2, each of the multiple first porous portions 23 has multiple first pores 230 that extend along the thickness direction D1 of the silicon wafer 2. In the first porous portion 23, the spacing between two adjacent first pores 230 is non-uniform in the thickness direction D1 of the silicon wafer 2.

[0034] In each of the multiple first porous portions 23, the multiple first pores 230 are formed to extend inward from the first main surface 21 of the silicon wafer 2. Each of the multiple first pores 230 is a hole whose depth in the thickness direction D1 of the silicon wafer 2 from the first main surface 21 of the silicon wafer 2 is longer than the opening width of the first pore 230 on the first main surface 21 of the silicon wafer 2. The multiple first pores 230 are formed to extend along the thickness direction D1 of the silicon wafer 2 from the first main surface 21 of the silicon wafer 2 and do not reach the second main surface 22 of the silicon wafer 2. In other words, the multiple first pores 230 do not penetrate the silicon wafer 2 in the thickness direction D1 of the silicon wafer 2. That is, the multiple first pores 230 are spaced apart from the second main surface 22 of the silicon wafer 2. The opening width of each of the multiple first pores 230 on the first main surface 21 of the silicon wafer 2 is, for example, 0.03 μm or more and 3 μm or less. Furthermore, the depth of the multiple first pores 230 is smaller than the thickness of the silicon wafer 2. The depth of each of the multiple first pores 230 in the thickness direction D1 of the silicon wafer 2 is, for example, 1 μm or more and 100 μm or less, and more preferably 5 μm or more and 50 μm or less. The upper limit of the depth of the multiple first pores 230 can be appropriately determined, for example, by the opening width of the multiple first pores 230, the formation method of the dielectric layer 5 and the conductive layer 6, etc. The formation depth Dp23 of the first porous portion 23 of the silicon wafer 2 is determined from a microscope image obtained by observing the cross-section of the capacitor assembly 1 with a microscope.

[0035] The surface 231 of the first porous portion 23 includes the inner surfaces of each of the plurality of first pores 230 formed on the first main surface 21 of the silicon wafer 2, and a part of the first main surface 21 of the silicon wafer 2.

[0036] In each of the multiple capacitors 10, the greater the depth of the multiple first pores 230 in the first porous portion 23, the larger the surface area of ​​the surface 231 of the first porous portion 23 can be, and thus the larger the capacitance of the capacitor 10 can be. Also, in each of the multiple capacitors 10, the greater the number of first pores 230 in the first porous portion 23, the larger the surface area of ​​the surface 231 of the first porous portion 23 can be, and thus the larger the capacitance of the capacitor 10 can be.

[0037] In each of the multiple capacitors 10, as described above, the spacing between two adjacent first pores 230 is non-uniform in the thickness direction D1 of the silicon wafer 2. In each of the multiple capacitors 10, the surface area of ​​the surface 231 of the first porous portion 23 can be increased compared to the case where the spacing between two adjacent first pores 230 is uniform in the thickness direction D1 of the silicon wafer 2. In addition, in each of the multiple capacitors 10, the opening width of each of the multiple first pores 230 is non-uniform in the thickness direction D1 of the silicon wafer 2.

[0038] Each of the multiple second porous portions 24 has a first porous region 25 with a plurality of second pores 250 that extend along the thickness direction D1 of the silicon wafer 2. In the first porous region 25, the spacing between two adjacent second pores 250 is non-uniform in the thickness direction D1 of the silicon wafer 2.

[0039] In each of the plurality of first porous regions 25, the plurality of second pores 250 are formed so as to extend inward from the first main surface 21 of the silicon wafer 2. Each of the plurality of second pores 250 is a pore whose depth in the thickness direction D1 of the silicon wafer 2 from the first main surface 21 of the silicon wafer 2 is longer than the opening width of the second pore 250 on the first main surface 21 of the silicon wafer 2. The plurality of second pores 250 are formed so as to extend along the thickness direction D1 of the silicon wafer 2 from the first main surface 21 of the silicon wafer 2 and do not reach the second main surface 22 of the silicon wafer 2. In other words, the plurality of second pores 250 do not penetrate the silicon wafer 2 in the thickness direction D1 of the silicon wafer 2. That is, the plurality of second pores 250 are separated from the second main surface 22 of the silicon wafer 2. The opening width of each of the plurality of second pores 250 on the first main surface 21 of the silicon wafer 2 is, for example, 0.03 μm or more and 3 μm or less. Further, the depth of the plurality of second pores 250 is smaller than the thickness of the silicon wafer 2. The depth of each of the plurality of second pores 250 in the thickness direction D1 of the silicon wafer 2 is, for example, 1 μm or more and 100 μm or less, and more preferably 5 μm or more and 50 μm or less. The depth of the second pores 250 in the first porous region 25 of the silicon wafer 2 is obtained from a microscope image obtained by observing a cross section of the process monitor unit 20 with a microscope.

[0040] In each of the plurality of second porous regions 26, the plurality of third pores 260 are formed so as to extend along an oblique direction inclined with respect to the thickness direction of the silicon wafer 2. The plurality of third pores 260 overlap a part of the insulating layer 3 in a plan view from the thickness direction D1 of the silicon wafer 2.

[0041] The surface 241 of the second porous portion 24 includes the inner surfaces of the plurality of second pores 250, a part of the first main surface 21 of the silicon wafer 2, and the inner surfaces of the plurality of third pores 260.

[0042] The dielectric layer 5 is disposed across the respective surfaces 231 of the plurality of first porous portions 23, the main surface 30 of the insulating layer 3, and the respective surfaces 241 of the plurality of second porous portions 24. More specifically, the dielectric layer 5 has a shape that covers the respective surfaces 231 of the plurality of first porous portions 23, the main surface 30 of the insulating layer 3, and the respective surfaces 241 of the plurality of second porous portions 24.

[0043] The thickness of the dielectric layer 5 is, for example, 1 nm or more and 100 nm or less. The upper limit of the thickness of the dielectric layer 5 is limited by the opening width of each of the first pores 230 of the plurality of first porous portions 23 in one direction along the first main surface 21 of the silicon wafer 2, the thickness of the conductor layer 6 in the above one direction within the first pores 230, and the like.

[0044] The dielectric layer 5 has a multilayer film structure in which a plurality of dielectric films are laminated, but is not limited thereto, and may be a single dielectric layer. When the dielectric layer 5 has a multilayer film structure, for example, it includes a first dielectric film (for example, a first silicon oxide film), a second dielectric film (for example, a silicon nitride film) on the first dielectric film, and a third dielectric film (for example, a second silicon oxide film) on the second dielectric film. The materials of the first silicon oxide film and the second silicon oxide film are, for example, silicon dioxide (SiO ２ ). It is not essential that the composition of each of the first silicon oxide film and the second silicon oxide film is exactly SiO ２ . Also, the composition of the first silicon oxide film and the composition of the second silicon oxide film may be different. When the dielectric layer 5 is composed of a single dielectric film, the material of the dielectric film is, for example, silicon oxide. The material of the dielectric film is not limited to silicon oxide, and may be, for example, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, or aluminum oxide.

[0045] The conductor layer 6 is laminated on the dielectric layer 5. In a plan view from the thickness direction D1 of the silicon wafer 2, the conductor layer 6 overlaps the first porous portion 23, a part of the insulating layer 3, and the second porous portion 24.

[0046] The conductor layer 6 is, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer is, for example, 1×10 １８ cm－３ 1×10 or less ２１ cm －３ and 5×10 or more １８ cm －３ 1×10 or more ２０ cm －３ and 1×10 or less is more preferable. The impurity of the conductive polysilicon layer contains, for example, one kind selected from the group consisting of boron, indium, phosphorus, arsenic, and antimony. The conductor layer 6 is not limited to the conductive polysilicon layer, and may be, for example, a metal electrode layer. The material of the metal electrode layer contains, for example, at least one kind selected from the group consisting of ruthenium, titanium, tantalum, tungsten, and aluminum. More specifically, the material of the metal electrode layer is ruthenium, titanium, tantalum, tungsten, aluminum, or an alloy mainly composed of any of these metals, etc.

[0047] The conductor layer 6 has a first portion 61 that overlaps the first porous portion 23 in the thickness direction D1 of the silicon wafer 2, and a second portion 62 that overlaps the insulating layer 3. The first portion 61 of the conductor layer 6 includes a plurality of columnar portions 611 located in a plurality of first pores 230 of the first porous portion 23 of the silicon wafer 2, and a portion 612 where the plurality of columnar portions 611 are connected. Note that the conductor layer 6 is separated from the first portion 61 and the second portion 62, and further has a third portion 63 that overlaps the second porous portion 24 and the insulating layer 3.

[0048] As shown in FIGS. 2 and 3, the first external connection electrode 7 is disposed on the main surface 21 of the silicon wafer 2. The first external connection electrode 7 is connected to the silicon wafer 2 through a contact hole formed in the stacked film of the dielectric layer 5 and the insulating layer 3. The first external connection electrode 7 is electrically connected to the silicon wafer 2. "The first external connection electrode 7 is electrically connected to the silicon wafer 2" means that the first external connection electrode 7 and the silicon wafer 2 are in ohmic contact.

[0049] In a plan view from the thickness direction D1 of the silicon wafer 2, the outer edge of the first external connection electrode 7 is, for example, square-shaped (see Figure 3), but is not limited to a square shape; for example, it may be circular. The first external connection electrode 7 does not overlap with the first porous portion 23 in a plan view from the thickness direction D1 of the silicon wafer 2.

[0050] The material of the first external connection electrode 7 includes, for example, aluminum, but is not limited to aluminum; it may also include, for example, gold, platinum, ruthenium, etc.

[0051] The thickness of the first external connection electrode 7 is, for example, 1 μm or more and 3 μm or less.

[0052] The second external connection electrode 8 is connected to the conductive layer 6. In the capacitor assembly 1, the second external connection electrode 8 is electrically connected to the conductive layer 6. "The second external connection electrode 8 is electrically connected to the conductive layer 6" means that the second external connection electrode 8 and the conductive layer 6 are in ohmic contact. In a plan view from the thickness direction D1 of the silicon wafer 2, the second external connection electrode 8 overlaps with a part of the insulating layer 3 but does not overlap with the first porous portion 23.

[0053] The material of the second external connection electrode 8 may include, for example, aluminum, but is not limited to aluminum; it may also include, for example, gold, platinum, ruthenium, etc. The material of the second external connection electrode 8 is the same as the material of the first external connection electrode 7, but may also be a different material from the material of the first external connection electrode 7.

[0054] The thickness of the second external connection electrode 8 is, for example, 1 μm or more and 3 μm or less. The thickness of the second external connection electrode 8 is the same as the thickness of the first external connection electrode 7, but it may be a different thickness from the thickness of the first external connection electrode 7.

[0055] (2) Method for manufacturing the capacitor assembly The method for manufacturing the capacitor assembly 1 according to Embodiment 1 includes, for example, a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, and a seventh step. The method for manufacturing the capacitor assembly 1 will be described below with reference to Figures 4 to 9.

[0056] In the first step, a silicon wafer 2 (see Figure 4) is prepared. The silicon wafer 2 has a first main surface 21 and a second main surface 22. The first main surface 21 of the silicon wafer 2 is, for example, a (100) plane, but is not limited to a (100) plane; for example, it may be a (110) plane or a (111) plane. The first main surface 21 of the silicon wafer 2 may also be a crystal plane whose off-angle from the (100) plane is greater than 0° and 5° or less. Here, "off-angle" is the inclination angle of the first main surface 21 with respect to the (100) plane. Therefore, if the off-angle is 0°, the first main surface 21 is a (100) plane. The resistivity of the silicon wafer 2 is, for example, 0.0001 Ωcm or more and 500 Ωcm or less, and more preferably 0.001 Ωcm or more and 300 Ωcm or less from the viewpoint of improving the shape of the first porous portion 23.

[0057] In the second step, multiple grooves 28 (only one is shown in Figure 5) are formed on the first main surface 21 of the silicon wafer 2, surrounding the areas to be formed for each of the multiple first porous portions 23 (see Figure 5). In this embodiment, the second step is a groove formation step for forming multiple grooves 28. In the second step, a mask layer (not shown) of a first predetermined pattern is formed on the first main surface 21 of the silicon wafer 2, and grooves 28 are formed on the first main surface 21 of the silicon wafer 2 by, for example, Deep RIE (Reactive Ion Etting) (see Figure 5). The mask layer has multiple openings that expose the areas to be formed for each of the multiple grooves 28 on the first main surface 21 of the silicon wafer 2. The depth of the grooves 28 is deeper than the predetermined depth of each first pore 230 of the first porous portion 23, and does not reach the second main surface 22 of the silicon wafer 2. The depth of the grooves 28 is deeper than the formation depth Dp23 of the first porous portion 23 described above. In the second step, the mask layer is removed by etching.

[0058] In the third step, as shown in Figure 6, a second predetermined pattern of insulating layer 3 is formed that covers the first main surface 21 of the silicon wafer 2 and the inner surfaces of multiple (only one shown in Figure 6) grooves 28. The insulating layer 3 has multiple (only one shown in Figure 6) first openings 31 and multiple (only one shown in Figure 6) second openings 32. In this embodiment, the third step is an insulating layer formation step in which the insulating layer 3 is formed. The insulating layer 3 is, for example, a silicon oxide film.

[0059] In the fourth step, as shown in Figure 7, a plurality of first porous portions 23 (only one is shown in Figure 7) and a plurality of second porous portions 24 (only one is shown in Figure 7) are formed on the silicon wafer 2. The fourth step is an anodizing step in which an anodizing treatment is performed. In the fourth step, the silicon wafer 2 is anodized while current is passed between an electrode (not shown) placed on the second main surface 22 of the silicon wafer 2 and a cathode facing the first main surface 21 of the silicon wafer 2 and the insulating layer 3 in an electrolyte solution containing hydrofluoric acid, thereby forming a plurality of first porous portions 23 and a plurality of second porous portions 24. More specifically, in the fourth step, the silicon wafer 2 is used as the anode, and an anodizing treatment is performed on the silicon wafer 2 to form a silicon wafer 2 (see Figure 7) including a plurality of first porous portions 23 and a plurality of second porous portions 24. In the anodizing process, the cathode is positioned opposite the first main surface 21 and the insulating layer 3 of the silicon wafer 2 in an electrolyte, and a current of a predetermined current density is passed between the anode and cathode with the silicon wafer 2 as the anode for a predetermined time. As a result, the anodizing process makes a portion of the silicon wafer 2 porous, thereby forming a plurality of first porous portions 23 and a plurality of second porous portions 24. The electrolyte is, for example, a mixture of hydrofluoric acid, alcohol, and water. The alcohol is, for example, ethanol, but is not limited to ethanol; isopropanol (IPA), methanol, propanol, etc., may also be used. Instead of alcohol, an organic solvent such as dimethylformamide (DMF), dimethyl sulfoxide (DMSO), or diethyl ether may be used in the electrolyte. In the fourth step, the shape and depth of the first pores 230 in each of the plurality of first porous portions 23 can be controlled by changing at least one of the concentration of hydrofluoric acid in the electrolyte, a predetermined current density, and a predetermined time. The concentration of hydrogen fluoride in the electrolyte is, for example, 1 wt% to 80 wt%, and more preferably 1 wt% to 25 wt%. In addition, in the manufacturing method of the capacitor assembly 1, the shape of the first pores 230 in each of the plurality of first porous portions 23 can be changed by changing the resistivity of the silicon wafer 2. The cathode has resistance to the electrolyte. The cathode is, for example, a platinum electrode.In the fourth step, after forming a plurality of first porous portions 23 and a plurality of second porous portions 24, the electrodes on the second main surface 22 of the silicon wafer 2 are etched off to obtain the structure shown in Figure 7.

[0060] In the fifth step, a dielectric layer 5 is formed as shown in Figure 8. In this embodiment, the fifth step is a dielectric layer formation step for forming the dielectric layer 5. In the fifth step, the first silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method, the silicon nitride film of the dielectric layer 5 is formed by, for example, a CVD method, and the second silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method. The first silicon oxide film may also be formed by a thermal oxidation method.

[0061] In the sixth step, as shown in Figure 9, a conductive layer 6 is formed on the dielectric layer 5. In this embodiment, the sixth step is a conductive layer formation step for forming the conductive layer 6. More specifically, in the sixth step, first, a conductive material layer that will become the conductive layer 6 is formed on the dielectric layer 5. In the sixth step, the conductive material layer is formed by, for example, a CVD method, and then, for example, a conductive layer 6 consisting of a part of the conductive material layer is formed by patterning the conductive material layer using photolithography and etching techniques.

[0062] In the seventh step, a capacitor assembly 1 having the structure shown in Figure 2 is obtained by forming a plurality of first external connection electrodes 7 (only one is shown in Figure 2) and a plurality of second external connection electrodes 8 (only one is shown in Figure 2). That is, a capacitor assembly 1 including a plurality of capacitors 10 and a plurality of process monitor units 20 can be obtained. In this embodiment, the seventh step is an electrode formation step in which a plurality of first external connection electrodes 7 and a plurality of second external connection electrodes 8 are formed. In the seventh step, a plurality of first external connection electrodes 7 and a plurality of second external connection electrodes 8 are formed using a thin film formation method, photolithography technology, etching technology, etc. The thin film formation method is, for example, a vapor deposition method, a sputtering method, or a CVD method.

[0063] In the method for manufacturing the capacitor 10, after the seventh step, the capacitor assembly 1 can be cut using, for example, a dicing saw or a laser dicing device to obtain multiple capacitors 10.

[0064] (3) Inspection step after the anodizing step The method for manufacturing the capacitor assembly 1 further comprises an inspection step performed between the anodizing step and the dielectric layer formation step.

[0065] After the anodizing process is completed, in the wafer including the silicon wafer 2 and the insulating layer 3, in the regions corresponding to each of the multiple capacitors 10 (regions where the capacitors 10 are formed), the first porous portion 23 is formed inside the insulating portion 4 as shown in Figure 10, whereas in the region corresponding to the process monitor portion 20, the second porous portion 24 is formed extending in a direction parallel to the in-plane direction parallel to the first main surface 21 of the silicon wafer 2 (see Figure 2), as shown in Figure 11. In a plan view from the thickness direction D1 of the silicon wafer 2, the shortest distance (minimum value of distance L4) between the inner edge of the first opening 31 of the insulating layer 3 and the insulating portion 4 is smaller than the predetermined depth of the first pore 230 of the first porous portion 23. In a plan view from the thickness direction D1 of the silicon wafer 2, the distance L4 between the inner edge of the first opening 31 of the insulating layer 3 and the insulating portion 4 is, for example, 0.1 μm or more and 5 μm or less.

[0066] In the manufacturing method of the capacitor assembly 1, an insulating portion 4 is formed in the region corresponding to each of the multiple capacitors 10. Since the insulating portion 4 surrounds the first opening 31 of the insulating layer 3 in a plan view from the thickness direction D1 of the silicon wafer 2, the downward spreading of the first porous portion 23 formed in the anodizing process is suppressed. In other words, in the region of the silicon wafer 2 corresponding to each of the multiple capacitors 10, downward side etching of the peripheral portion of the first opening 31 in the insulating layer 3 is suppressed.

[0067] On the other hand, in the manufacturing method of the capacitor assembly 1, the second porous portion 24 formed in the region corresponding to the process monitor portion 20 during the anodizing process extends downward to the peripheral portion of the second opening 32 in the insulating layer 3 (see Figure 11). In other words, in the manufacturing method of the capacitor assembly 1, when the second porous portion 24 is formed by the anodizing process, side etching occurs, and a second porous region 26 having a plurality of third pores 260 inclined with respect to the thickness direction D1 of the silicon wafer 2 is formed downward to the peripheral portion of the second opening 32 in the insulating layer 3.

[0068] In the inspection process, a wafer including an insulating layer 3 and a silicon wafer 2 on which a plurality of first porous portions 23 and a plurality of second porous portions 24 are formed is observed using a microscope from a direction along the thickness direction D1 of the silicon wafer 2. At this time, the second porous region 26 of the second porous portion 24 is visible. Therefore, in the inspection process, the width H26 (see Figure 12) of the second porous region 26 in the second porous portion 24 can be measured in a plan view from the thickness direction D1 of the silicon wafer 2.

[0069] In the inspection process, a pass / fail judgment is made based on an estimation result in which the formation depth Dp23 (see Figure 7) of the first porous portion 23 is estimated based on the width H26 (see Figure 12) of the second porous region 26 in the second porous portion 24 in a plan view from the thickness direction D1 of the silicon wafer 2. The relationship between the width H26 of the second porous region 26 and the formation depth Dp23 of the first porous portion 23 can be determined from a microscope image obtained by cutting a sample wafer that has undergone the same processes as the manufacturing method of the capacitor assembly 1 according to Embodiment 1 up to the anodizing step, and observing the cross-section with a microscope, before carrying out the manufacturing method of the capacitor assembly 1 according to Embodiment 1. The formation depth Dp23 of the first porous portion 23 is the distance between the first main surface 21 of the silicon wafer 2 and the envelope of the bottom surface of the plurality of first pores 230 in the thickness direction D1 of the silicon wafer 2. In this embodiment, under process conditions where the ratio of the width H26 of the second porous region 26 to the formation depth Dp23 of the first porous portion 23 is approximately 1:1, the width H26 of the second porous region 26 is estimated as the formation depth Dp23 of the first porous portion 23. Since the thickness of the silicon wafer 2 is known in advance, by estimating the formation depth Dp23 of the first porous portion 23, the distance L22 between the first porous portion 23 and the second main surface 22 of the silicon wafer 2 can also be estimated.

[0070] (4) Layout In this embodiment, the plurality (five) process monitor units 20 include a first process monitor unit 201 located at the center of the capacitor formation region 11 and four second process monitor units 202 located on the outer periphery of the capacitor formation region 11. The center of the capacitor formation region 11 is the same as the center of the silicon wafer 2. The "first process monitor unit 201 located at the center of the capacitor formation region 11" is not limited to a process monitor unit 20 located at the center of the silicon wafer 2, but may be a process monitor unit 20 in which there is no capacitor 10 between it and the center of the silicon wafer 2. The four second process monitor units 202 include a pair of second process monitor units 202 located symmetrically with respect to the first process monitor unit 201 located at the center of the silicon wafer 2.

[0071] (5) Advantages The capacitor assembly 1 according to Embodiment 1 has a plurality of capacitors 10 formed on a silicon wafer 2. The capacitor assembly 1 includes a capacitor formation region 11 and a non-capacitor formation region 12. The capacitor formation region 11 has a plurality of capacitors 10 arranged in a plan view from the thickness direction of the silicon wafer 2. The non-capacitor formation region 12 surrounds the capacitor formation region 11 in a plan view from the thickness direction of the silicon wafer 2. Each of the plurality of capacitors 10 includes a first porous portion 23, an insulator portion 4, a dielectric layer 5, and a conductor layer 6. The first porous portion 23 is formed on the silicon wafer 2. The first porous portion 23 has a plurality of first pores 230 that extend along the thickness direction of the silicon wafer 2. The insulator portion 4 is located inside the silicon wafer 2 and surrounds the first porous portion 23 in a plan view from the thickness direction of the silicon wafer 2. The dielectric layer 5 is arranged on the surface 231 of the first porous portion 23. The conductor layer 6 is laminated on the dielectric layer 5. The capacitor assembly 1 further comprises at least one process monitoring unit 20 located in the capacitor formation region 11. The at least one process monitoring unit 20 includes a second porous region 24 formed in the silicon wafer 2. The second porous region 24 includes a first porous region 25 and a second porous region 26. The first porous region 25 has a plurality of second pores 250 extending along the thickness direction of the silicon wafer 2. The second porous region 26 surrounds the first porous region 25 and has a plurality of third pores 260 extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer 2.

[0072] With the above configuration, it becomes possible to estimate the formation depth of the first porous portion 23 non-destructively using the process monitoring unit 20 during manufacturing, thereby reducing costs.

[0073] The method for manufacturing a capacitor assembly 1 according to Embodiment 1 is a method for manufacturing a capacitor assembly 1 in which a plurality of capacitors 10 are formed on a silicon wafer 2. The capacitor assembly 1 includes a capacitor formation region 11 and a non-capacitor formation region 12. The capacitor formation region 11 has a plurality of capacitors 10 arranged in a plan view from the thickness direction of the silicon wafer 2. The non-capacitor formation region 12 surrounds the capacitor formation region 11 in a plan view from the thickness direction of the silicon wafer 2. Each of the plurality of capacitors 10 includes a first porous portion 23, an insulator portion 4, a dielectric layer 5, and a conductor layer 6. The first porous portion 23 is formed on the silicon wafer 2. The first porous portion 23 has a plurality of first pores 230 that extend along the thickness direction of the silicon wafer 2. The insulator portion 4 is located inside the silicon wafer 2 and surrounds the first porous portion 23 in a plan view from the thickness direction of the silicon wafer 2. The dielectric layer 5 is arranged on the surface 231 of the first porous portion 23. The conductive layer 6 is laminated on the dielectric layer 5. The capacitor assembly 1 further comprises at least one process monitoring unit 20 located in the capacitor formation region 11. The at least one process monitoring unit 20 includes a second porous region 24 formed on the silicon wafer 2. The second porous region 24 includes a first porous region 25 and a second porous region 26. The first porous region 25 has a plurality of second pores 250 extending along the thickness direction of the silicon wafer 2 in a region corresponding to the second opening 32 of the insulating layer 3. The second porous region 26 surrounds the first porous region 25 and has a plurality of third pores 260 extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer 2. The method for manufacturing the capacitor assembly 1 comprises an insulating layer formation step, an anodizing step, and an inspection step. In the insulating layer formation process, an insulating layer 3 is formed on the main surface 21 of the silicon wafer 2, having a first opening 31 for forming a first porous portion 23 and a second opening 32 for forming a second porous portion 24. In the anodizing process, the silicon wafer 2 is anodized using the insulating layer 3 as a mask to form the first porous portion 23 of each of the multiple capacitors 10 and the second porous portion 24 of at least one process monitor portion 20.In the inspection process, a pass / fail judgment is made based on the estimation result, which estimates the formation depth Dp23 of the first porous portion 23 based on the width H26 of the second porous region 26 in the second porous portion 24 in a plan view from the thickness direction of the silicon wafer 2.

[0074] According to the manufacturing method of the capacitor assembly 1 in Embodiment 1, the silicon wafer 2 up to the anodizing process can be non-destructively judged as good or bad during the inspection process, and silicon wafers 2 in which the formation depth Dp23 of the first porous portion 23 is presumed to be outside a predetermined range can be removed midway through the process, thereby reducing manufacturing costs. Furthermore, it becomes possible to estimate the formation rate of the first pores 230 (corresponding to the etching rate) for each silicon wafer 2 up to the anodizing process, and it becomes possible to adjust the process conditions of the anodizing process for the silicon wafer 2 that will undergo the anodizing process next.

[0075] (Embodiment 2) Hereinafter, the capacitor assembly 1A according to Embodiment 2 will be described with reference to Figure 13.

[0076] (1) The capacitor assembly 1A according to the second embodiment differs from the capacitor assembly 1 according to the first embodiment (see Figures 1 and 2) in that it has only one process monitor unit 20, which is located in the center of the capacitor formation region 11. With respect to the capacitor assembly 1A according to the second embodiment, components that are the same as those in the capacitor assembly 1 according to the first embodiment (see Figures 1 and 2) are denoted by the same reference numerals and their descriptions are omitted.

[0077] (2) Advantages The capacitor assembly 1A according to Embodiment 2 can be made more cost-effective, similar to the capacitor assembly 1 according to Embodiment 1.

[0078] Furthermore, in the capacitor assembly 1A according to Embodiment 2, the number of process monitor units 20 can be reduced, shortening the time required for the inspection process, and enabling cost reduction by increasing the number of capacitors 10 obtained from a single capacitor assembly 1A.

[0079] (Embodiment 3) The capacitor assembly 1B according to Embodiment 3 will be described with reference to Figure 14.

[0080] (1) The capacitor assembly 1B according to Embodiment 3 differs from the capacitor assembly 1 according to Embodiment 1 (see Figures 1 and 2) in that it comprises nine process monitor units 20. With respect to the capacitor assembly 1B according to Embodiment 3, components that are the same as those in the capacitor assembly 1 according to Embodiment 1 (see Figures 1 and 2) are denoted by the same reference numerals and their descriptions are omitted.

[0081] The nine process monitor units 20 include one first process monitor unit 201, four second process monitor units 202, and four third process monitor units 203. The four third process monitor units 203 correspond one-to-one with the four second process monitor units 202. Each of the four third process monitor units 203 is positioned between the corresponding second process monitor unit 202 from the four second process monitor units 202 and the first process monitor unit 201. One or more capacitors 10 are positioned between the third process monitor unit 203 and the first process monitor unit 201, and one or more capacitors 10 are positioned between the third process monitor unit 203 and the second process monitor unit 202.

[0082] (2) Advantages: The capacitor assembly 1B according to Embodiment 3 can be made more cost-effective, similar to the capacitor assembly 1 according to Embodiment 1.

[0083] Furthermore, in the capacitor assembly 1B according to Embodiment 3, the plurality of process monitor units 20 include a first process monitor unit 201, a second process monitor unit 202, and a third process monitor unit 203. The first process monitor unit 201 is located at the center of the capacitor formation region 11. The second process monitor unit 202 is located on the outer periphery of the capacitor formation region 11. The third process monitor unit 203 is located between the first process monitor unit 201 and the second process monitor unit 202.

[0084] According to the above configuration, it becomes possible to estimate the in-plane variation of the silicon wafer 2 regarding the formation depth Dp23 of the first porous portion 23.

[0085] (Embodiment 4) The capacitor assembly 1C according to Embodiment 4 will be described with reference to Figure 15.

[0086] (1) In the capacitor assembly 1C according to the configuration embodiment 4, a plurality of process monitor units 20 are arranged on scribe lines B1 within the capacitor formation region 11. Note that in Figure 15, only one of the plurality of scribe lines B1 is shown. The positions of the plurality of scribe lines B1 are determined in the dicing process for dicing the capacitor assembly 1C based on the orientation flat of the silicon wafer 2 and a plurality (for example, two) of alignment marks formed on the first main surface 21 of the silicon wafer 2 after the silicon wafer 2 has been prepared during the manufacturing of the capacitor assembly 1C.

[0087] (2) Advantages The capacitor assembly 1C according to Embodiment 4 can be made more cost-effective, similar to the capacitor assembly 1 according to Embodiment 1.

[0088] Furthermore, in the capacitor assembly 1C according to Embodiment 4, the multiple process monitor units 20 are arranged on the scribe line B1 within the capacitor formation region 11.

[0089] With the above configuration, it becomes possible to increase the number of capacitors 10.

[0090] Furthermore, each individual capacitor 10 cut out by the dicing process may include a part of the process monitoring unit 20.

[0091] (Embodiment 5) The capacitor assembly 1D according to Embodiment 5 will be described with reference to Figure 16.

[0092] (1) Capacitor Assembly Configuration The capacitor assembly 1D according to Embodiment 5 differs from the capacitor assembly 1 according to Embodiment 1 in that the dielectric layer 5 is also formed on the inner surface of the groove 28, and the portion of the dielectric layer 5 formed on the inner surface of the groove 28 also serves as an insulator that surrounds the first porous portion 23 around its entire circumference.

[0093] (2) Method for manufacturing the capacitor assembly The method for manufacturing the capacitor assembly 1D according to Embodiment 5 is substantially the same as the method for manufacturing the capacitor assembly 1 according to Embodiment 1, and differs from the method for manufacturing the capacitor assembly 1 according to Embodiment 1 in that the insulating layer 3 and insulating part 4 are removed after the anodic oxidation process before forming the dielectric layer 5.

[0094] In this embodiment, the inspection step after the anodizing process may be performed after removing the insulating layer 3 but before forming the dielectric layer 5.

[0095] (3) Advantages The capacitor assembly 1D according to Embodiment 5 can be made more cost-effective, similar to the capacitor assembly 1 according to Embodiment 1.

[0096] (Modifications) Embodiments 1 to 5 are merely one of many embodiments of the present disclosure. Embodiments 1 to 5 can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0097] In capacitor assemblies 1, 1A, 1B, and 1C, the insulating portion 4 surrounds the first porous portion 23 all around when viewed from the thickness direction D1 of the silicon wafer 2. However, it is not essential that the insulating portion 4 surrounds the first porous portion 23 all around.

[0098] (Aspects) The following aspects are disclosed herein.

[0099] A capacitor assembly (1; 1A; 1B; 1C; 1D) according to the first embodiment has a plurality of capacitors (10) formed on a silicon wafer (2). The capacitor assembly (1; 1A; 1B; 1C; 1D) includes a capacitor formation region (11) and a non-capacitor formation region (12). The capacitor formation region (11) has a plurality of capacitors (10) arranged in a plan view from the thickness direction (D1) of the silicon wafer (2). The non-capacitor formation region (12) surrounds the capacitor formation region (11) in a plan view from the thickness direction (D1) of the silicon wafer (2). Each of the plurality of capacitors (10) includes a first porous portion (23), an insulator portion (4), a dielectric layer (5), and a conductor layer (6). The first porous portion (23) is formed on the silicon wafer (2). The first porous portion (23) has a plurality of first pores (230) extending along the thickness direction (D1) of the silicon wafer (2). The insulating portion (4) is located within the silicon wafer (2) and surrounds the first porous portion (23) in a plan view from the thickness direction (D1) of the silicon wafer (2). The dielectric layer (5) is disposed on the surface (231) of the first porous portion (23). The conductive layer (6) is laminated on the dielectric layer (5). The capacitor assembly (1) further comprises at least one process monitor portion (20) located in the capacitor formation region (11). The at least one process monitor portion (20) includes a second porous portion (24) formed in the silicon wafer (2). The second porous portion (24) includes a first porous region (25) and a second porous region (26). The first porous region (25) has a plurality of second pores (250) extending along the thickness direction (D1) of the silicon wafer (2). The second porous region (26) surrounds the first porous region (25) and has a plurality of third pores (260) extending along an oblique direction inclined with respect to the thickness direction (D1) of the silicon wafer (2).

[0100] This embodiment makes it possible to reduce costs.

[0101] In the capacitor assembly (1; 1B; 1C; 1D) according to the second embodiment, in the first embodiment, the at least one process monitor unit (20) is located on the outer periphery of the capacitor formation region (11).

[0102] According to this embodiment, it is possible to estimate the formation depth (Dp23) of the first porous portion (23) formed on the outer periphery of the capacitor formation region (11), where the formation depth (Dp23) of the first porous portion (23) tends to vary.

[0103] In the capacitor assembly (1; 1B; 1C; 1D) according to the third embodiment, in the second embodiment, the at least one process monitor unit (20) includes a plurality of process monitor units (second process monitor units 202). The plurality of process monitor units (second process monitor units 202) include a pair of process monitor units (second process monitor units 202) that are symmetrically arranged with respect to the center of the capacitor formation region (11).

[0104] According to this embodiment, it is possible to estimate the in-plane variation (Dp23) of the first porous portion (23) within the silicon wafer (2).

[0105] In the capacitor assembly (1A) according to the fourth embodiment, in the first embodiment, the at least one process monitor unit (20) is one process monitor unit (20). The one process monitor unit (20) is located in the center of the capacitor formation region (11).

[0106] According to this embodiment, the number of process monitoring units (20) can be reduced, and the time required for the inspection process can be shortened.

[0107] In the capacitor assembly (1; 1B; 1C; 1D) according to the fifth embodiment, in the first embodiment, the at least one process monitor unit (20) includes a plurality of process monitor units (20).

[0108] According to this embodiment, it is possible to estimate the variation in the formation depth (Dp23) of the first porous portion (23).

[0109] In the capacitor assembly (1B) according to the sixth embodiment, in the fifth embodiment, the plurality of process monitor units (20) include a first process monitor unit (201), a second process monitor unit (202), and a third process monitor unit (203). The first process monitor unit (201) is located in the center of the capacitor formation region (11). The second process monitor unit (202) is located on the outer periphery of the capacitor formation region (11). The third process monitor unit (203) is located between the first process monitor unit (201) and the second process monitor unit (202).

[0110] According to this embodiment, it is possible to estimate the in-plane variation (Dp23) of the first porous portion (23) within the silicon wafer (2).

[0111] In the capacitor assembly (1C) according to the seventh embodiment, in the first embodiment, the at least one process monitor unit (20) is arranged on a scribe line (B1) within the capacitor formation region (11).

[0112] According to this embodiment, it is possible to increase the number of capacitors (10).

[0113] A method for manufacturing a capacitor assembly (1; 1A; 1B; 1C; 1D) according to the eighth aspect is a method for manufacturing a capacitor assembly (1; 1A; 1B; 1C; 1D) in which a plurality of capacitors (10) are formed on a silicon wafer (2). The capacitor assembly (1; 1A; 1B; 1C; 1D) includes a capacitor formation region (11) and a non-capacitor formation region (12). The capacitor formation region (11) has a plurality of capacitors (10) arranged in a plan view from the thickness direction (D1) of the silicon wafer (2). The non-capacitor formation region (12) surrounds the capacitor formation region (11) in a plan view from the thickness direction (D1) of the silicon wafer (2). Each of the plurality of capacitors (10) includes a first porous portion (23), an insulator portion (4), a dielectric layer (5), and a conductor layer (6). The first porous portion (23) is formed on the silicon wafer (2). The first porous portion (23) has a plurality of first pores (230) extending along the thickness direction (D1) of the silicon wafer (2). The insulator portion (4) is located within the silicon wafer (2) and surrounds the first porous portion (23) in a plan view from the thickness direction (D1) of the silicon wafer (2). The dielectric layer (5) is disposed on the surface (231) of the first porous portion (23). The conductive layer (6) is laminated on the dielectric layer (5). The capacitor assembly (1; 1A; 1B; 1C; 1D) further comprises at least one process monitor portion (20) located in the capacitor formation region (11). The at least one process monitor portion (20) includes a second porous portion (24) formed in the silicon wafer (2). The second porous portion (24) includes a first porous region (25) and a second porous region (26). The first porous region (25) has a plurality of second pores (250) extending along the thickness direction (D1) of the silicon wafer (2). The second porous region (26) surrounds the first porous region (25) and has a plurality of third pores (260) extending along an oblique direction inclined with respect to the thickness direction (D1) of the silicon wafer (2). The method for manufacturing the capacitor assembly (1; 1A; 1B; 1C; 1D) comprises an insulating layer formation step, an anodizing step, and an inspection step. In the insulating layer formation step, an insulating layer (3) is formed on the main surface (21) of the silicon wafer (2).The insulating layer (3) has a first opening (31) for forming a first porous portion (23) and a second opening (32) for forming a second porous portion (24). In the anodizing process, the silicon wafer (2) is anodized using the insulating layer (3) as a mask to form the first porous portion (23) of each of the multiple capacitors (10) and the second porous portion (24) of at least one process monitor portion (20). In the inspection process, a pass / fail judgment is made based on an estimation result in which the formation depth (Dp23) of the first porous portion (23) is estimated based on the width of the second porous region (26) in the second porous portion (24) in a plan view from the thickness direction (D1) of the silicon wafer (2).

[0114] According to this embodiment, the silicon wafer (2) up to the anodizing process can be non-destructively judged as good or bad during the inspection process, and silicon wafers (2) whose formation depth (Dp23) of the first porous portion (23) is presumed to be outside a predetermined range can be removed midway through the process, thereby reducing manufacturing costs. Furthermore, it becomes possible to estimate the formation rate of the first pores (230) for each silicon wafer (2) up to the anodizing process, and it becomes possible to adjust the process conditions of the anodizing process for the silicon wafer (2) that will undergo the anodizing process next.

[0115] 1, 1A, 1B, 1C, 1D Capacitor Assembly 11 Capacitor Formation Region 12 Non-Capacitor Formation Region 2 Silicon Wafer 21 Main Surface (First Main Surface) 22 Second Main Surface 23 First Porous Region 230 First Pore 231 Surface 24 Second Porous Region 241 Surface 25 First Porous Region 250 Second Pore 26 Second Porous Region 260 Third Pore 28 Groove 3 Insulating Layer 30 Main Surface 31 First Opening 32 Second Opening 4 Insulator Region 5 Dielectric Layer 6 Conductive Layer 61 First Part 611 Columnar Part 612 Part 62 Second Part 63 Third Part 7 First External Connection Electrode 8 Second External Connection Electrode 10 Capacitor 20 Process Monitor Section 201 First Process Monitor Section 202 Second Process Monitor Section 203 Third Process Monitor Section B1 Scribe Line D1 Thickness Direction Dp23 Formation Depth H26 Width L4 Distance L22 Distance

Claims

1. A capacitor assembly comprising a plurality of capacitors formed on a silicon wafer, comprising: a capacitor formation region in which the plurality of capacitors are arranged in a plan view from the thickness direction of the silicon wafer; and a non-capacitor formation region surrounding the capacitor formation region in a plan view from the thickness direction of the silicon wafer, wherein each of the plurality of capacitors comprises: a first porous portion formed on the silicon wafer and having a plurality of first pores extending along the thickness direction of the silicon wafer; an insulating portion located within the silicon wafer and surrounding the first porous portion in a plan view from the thickness direction of the silicon wafer; a dielectric layer disposed on the surface of the first porous portion; and a conductive layer laminated on the dielectric layer, further comprising at least one process monitor portion disposed in the capacitor formation region, wherein the at least one process monitor portion comprises a second porous portion formed on the silicon wafer, and the second porous portion comprises a first porous region having a plurality of second pores extending along the thickness direction of the silicon wafer, A capacitor assembly comprising: a second porous region surrounding the first porous region and having a plurality of third pores extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer.

2. The capacitor assembly according to claim 1, wherein the at least one process monitoring unit is located on the outer periphery of the capacitor formation region.

3. The capacitor assembly according to claim 2, wherein the at least one process monitoring unit includes a plurality of process monitoring units, and the plurality of process monitoring units include a pair of process monitoring units arranged symmetrically with respect to the center of the capacitor formation region.

4. The capacitor assembly according to claim 1, wherein the at least one process monitoring unit is one process monitoring unit, and the one process monitoring unit is located at the center of the capacitor formation region.

5. The capacitor assembly according to claim 1, wherein the at least one process monitoring unit includes a plurality of process monitoring units.

6. The capacitor assembly according to claim 5, wherein the plurality of process monitoring units include a first process monitoring unit located at the center of the capacitor formation region, a second process monitoring unit located on the outer periphery of the capacitor formation region, and a third process monitoring unit located between the first process monitoring unit and the second process monitoring unit.

7. The capacitor assembly according to claim 1, wherein the at least one process monitoring unit is arranged on a scribe line within the capacitor formation region.

8. A method for manufacturing a capacitor assembly having a plurality of capacitors formed on a silicon wafer, wherein the capacitor assembly includes a capacitor formation region in which the plurality of capacitors are arranged in a plan view from the thickness direction of the silicon wafer, and a non-capacitor formation region surrounding the capacitor formation region in a plan view from the thickness direction of the silicon wafer, and each of the plurality of capacitors includes a first porous portion formed on the silicon wafer and having a plurality of first pores extending along the thickness direction of the silicon wafer, an insulating portion located within the silicon wafer and surrounding the first porous portion in a plan view from the thickness direction of the silicon wafer, a dielectric layer disposed on the surface of the first porous portion, and a conductive layer laminated on the dielectric layer, and further comprises at least one process monitor portion disposed in the capacitor formation region, the at least one process monitor portion includes a second porous portion formed on the silicon wafer, and the second porous portion includes a first porous region having a plurality of second pores extending along the thickness direction of the silicon wafer, A method for manufacturing a capacitor assembly comprising: a first porous region surrounding the first porous region and having a plurality of third pores extending along an oblique direction inclined with respect to the thickness direction of the silicon wafer; an insulating layer forming step of forming an insulating layer having a first opening for forming the first porous region and a second opening for forming the second porous region on the main surface of the silicon wafer; an anodic oxidation step of forming the first porous region of each of the plurality of capacitors and the second porous region of at least one process monitor portion by anodic oxidation of the silicon wafer using the insulating layer as a mask; and an inspection step of performing a quality determination based on an estimation result obtained by estimating the formation depth of the first porous region based on the width of the second porous region in the second porous region in a plan view of the silicon wafer from the thickness direction.

Images