Semiconductor integrated circuit device

Abstract

In the present invention, a gated clock cell (C1) comprises: transistors; a first input terminal which is constituted by wiring (13) formed on a rear wiring layer and to which a clock signal is input; a signal terminal which is constituted by wiring (51) formed on a metal wiring layer and to which an enable signal for controlling the passage and blocking of the clock signal is input; and a first output terminal which is constituted by wiring (52) formed on the metal wiring layer and from which the clock signal, the passage and blocking of which are controlled by the enable signal, is output.

Description

Semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device.

[0002] As a method of forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method is a method of designing an LSI chip by preparing basic units (for example, inverters, latches, flip - flops, full - adders, etc.) having specific logic functions in advance as standard cells, arranging a plurality of standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] In Patent Document 1, a gated clock circuit is disclosed as a circuit for reducing the power consumption of a semiconductor integrated circuit device. In the gated clock circuit, the passage / blocking of a clock signal is controlled by an enable signal.

[0004] In Patent Document 2, a semiconductor integrated circuit device is disclosed that includes a standard cell provided on the surface wiring layer side of a transistor as an input / output terminal of a standard cell and a standard cell provided on the back - side wiring layer side, and the input / output terminals of these standard cells are connected by wiring for reducing the area of the semiconductor integrated circuit device.

[0005] Japanese Patent Application Laid - Open No. 9 - 284101U.S. Patent Application Publication No. 2022 / 0344255

[0006] In Patent Document 1, regarding the gated clock circuit, it is not examined which wiring layer should be provided with input / output terminals.

[0007] An object of the present disclosure is to provide a layout of a semiconductor integrated circuit device including a gated clock circuit.

[0008] A first aspect of the present disclosure is a semiconductor integrated circuit device including a plurality of standard cells, wherein the plurality of standard cells include a first standard cell on which a gated clock circuit is configured, and the first standard cell comprises a transistor and a first input terminal to which a clock signal is input, comprising a first wiring formed in a back wiring layer below the transistor in the depth direction, comprising a second wiring formed in a metal wiring layer above the transistor in the depth direction, comprising a signal terminal to which an enable signal is input to control the passage and blocking of the clock signal, comprising a third wiring formed in the metal wiring layer, comprising a first output terminal to which the passage and blocking of the clock signal controlled by the enable signal is output.

[0009] According to this disclosure, a first wiring constituting a first input terminal to which a clock signal is input is formed on the back wiring layer. A second wiring constituting an enable signal terminal to which an enable signal is input, and a third wiring constituting a clock output terminal to which a clock signal is output are formed on the metal wiring layer. This makes it possible to realize a semiconductor integrated circuit device equipped with a gated clock circuit.

[0010] A second aspect of the present disclosure provides a semiconductor integrated circuit apparatus including a plurality of standard cells, wherein the plurality of standard cells include a first standard cell configured with a gated clock circuit and a second standard cell configured with a buffer circuit, the second standard cell comprising a transistor and a first wiring formed in a back wiring layer below the transistor in the depth direction, and comprising an input terminal to which a clock signal is input and a second wiring formed in the back wiring layer, and comprising an output terminal to which the clock signal is output, the second wiring being connected to the first standard cell.

[0011] According to this disclosure, a layout for a semiconductor integrated circuit device equipped with a gated clock circuit can be provided.

[0012] A plan view showing the layout structure of a gated clock cell according to the embodiment. A cross-sectional view showing the layout structure of a gated clock cell according to the embodiment. A circuit diagram showing the configuration of a gated clock cell according to the embodiment. A plan view showing the layout structure of a buffer cell according to the embodiment. A circuit diagram showing the configuration of a buffer cell according to the embodiment. A plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the embodiment.

[0013] The embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor integrated circuit device comprises a plurality of standard cells. At least some of these standard cells are nanosheet FETs.

[0014] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0015] (Embodiment) (Configuration of a gated clock cell) Figure 1 is a plan view showing the layout structure of a gated clock cell according to an embodiment, and Figure 2 is a cross-sectional view showing the layout structure of a gated clock cell according to an embodiment. Specifically, Figure 1(a) shows the lower part of the cell, i.e., the wiring layer (back wiring layer) provided on the back of the semiconductor chip on which the transistor is formed, Figure 1(b) shows the upper part of the cell, i.e., the part including the transistor, Figure 2(a) is a cross-section along the line Y1-Y1' in Figure 1, Figure 2(b) is a cross-section along the line Y2-Y2' in Figure 1, and Figure 2(c) is a cross-section along the line Y3-Y3' in Figure 1.

[0016] In the following explanation, in plan views such as Figure 1, the horizontal direction of the drawing is referred to as the X direction, the vertical direction as the Y direction, and the direction perpendicular to the substrate surface as the Z direction (corresponding to the depth direction). Also, in the following explanation, the same symbol refers to the same thing, and explanations may be omitted.

[0017] Furthermore, in plan views such as Figure 1, the solid lines surrounding the cells indicate the cell frame (outer edge of the standard cell) of the standard cell. Standard cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0018] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0019] Figure 3 is a circuit diagram showing the configuration of a gated clock cell according to an embodiment. As shown in Figures 1 to 3, the gated clock cell C1 includes a gated clock circuit composed of P-type transistors P1 to P10 and N-type transistors N1 to N10.

[0020] In a gated clock circuit, the enable signal input to the enable signal terminal CEN controls whether the clock signal input to the clock input terminal CLK is output from the clock output terminal GCLK (passed through or blocked). Specifically, if the enable signal input to the enable signal terminal CEN is high level, the clock signal input to the clock input terminal CLK is output from the clock output terminal GCLK (passed through). If the enable signal input to the enable signal terminal CEN is low level, the clock signal input to the clock input terminal CLK is not output from the clock output terminal GCLK (blocked).

[0021] The layout structure of the gated clock cell C1 in Figures 1 and 2 can be easily inferred from the circuit diagram in Figure 3, so explanations will be omitted as appropriate.

[0022] As shown in Figure 1(a), the BM0 (Backside Metal 0) wiring layer, which is the back wiring layer, has power supply wiring 11, 12 and wiring 13 extending in the X direction. Power supply wiring 11 is formed at the upper end of the cell and supplies the power supply voltage VDD. Power supply wiring 12 is formed at the lower end of the cell and supplies the power supply voltage VSS.

[0023] Wiring 13 is formed in the center of the cell diagram. Wiring 13 corresponds to the wiring that constitutes the clock input terminal CLK to which the clock signal is input. Wiring 13 is connected to gate wirings 32 and 33 via vias.

[0024] As shown in Figure 1(b), the P-type transistor region has active regions that constitute the channel, source, and drain of the P-type transistor. Specifically, active regions 2P1 to 2P4 are formed in the P-type transistor region. In a plan view, the active regions 2P1 to 2P4 overlap with the power supply wiring 11.

[0025] P-type transistors P1 to P10 are formed in the P-type transistor region. Transistors P1 to P10, as channels, consist of three overlapping sheet structures in a planar view, and each has nanosheets 21a to 30a extending in the X direction.

[0026] The source portion of transistor P1 in active region 2P1, the source portion of transistor P4 in active region 2P2, the source portion of transistor P5 in active region 2P2, the source portion of transistor P6 in active region 2P3, the source portion of transistor P7 in active region 2P3, the source portion of transistor P8 in active region 2P4, the source portion of transistor P9 in active region 2P4, and the source portion of transistor P10 in active region 2P4 are connected to the power supply wiring 11 via vias.

[0027] Active regions constituting the channel, source, and drain of an N-type transistor are formed within the N-type transistor region. Specifically, active regions 2N1 to 2N4 are formed within the N-type transistor region. In a plan view, active regions 2N1 to 2N4 overlap with the power supply wiring 12.

[0028] N-type transistors N1 to N10 are formed in the N-type transistor region. Transistors N1 to N10, as channels, consist of three overlapping sheet structures in a planar view, and each has nanosheets 21b to 30b extending in the X direction.

[0029] The source portion of transistor N1 in active region 2N1, the source portion of transistor N4 in active region 2N2, the source portion of transistor N5 in active region 2N2, the source portion of transistor N6 in active region 2N3, the source portion of transistor N7 in active region 2N3, the source portion of transistor N9 in active region 2N4, and the source portion of transistor N10 in active region 2N4 are connected to the power supply wiring 12 via vias.

[0030] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0031] Gate wirings 31 to 33 extending in the Y direction are formed. Nanosheets 21a and 21b overlap with gate wiring 31 in a plan view. Nanosheets 27a and 27b overlap with gate wiring 32 in a plan view. Nanosheets 28a and 28b overlap with gate wiring 33 in a plan view. Gate wiring 31 corresponds to the gates of transistors P1 and N1. Gate wiring 32 corresponds to the gates of transistors P7 and N7. Gate wiring 33 corresponds to the gates of transistors P8 and N8.

[0032] Local interconnects (LI) 41 extending in the Y direction are formed in the local interconnect layer. The local interconnects 41 are connected to the drain portion of transistor P10 in the active region 2P4 and to the drain portion of transistor N10 in the active region 2N4.

[0033] The M0 wiring layer, which is a metal wiring layer located above the local wiring layer, has wirings 51 and 52 extending in the X direction. Wiring 51 corresponds to the wiring that constitutes the enable signal terminal CEN, to which the enable signal is input. Wiring 51 is connected to the gate wiring 31 via a via. Wiring 52 corresponds to the wiring that constitutes the clock output terminal GCLK, which outputs a clock signal. Wiring 52 is connected to the local wiring 41 via a via.

[0034] With the above configuration, wiring 13 constituting the clock input terminal CLK, to which a clock signal is input, is formed on the BM0 wiring layer, which is the back wiring layer. Wiring 51 constituting the enable signal terminal CEN, to which an enable signal is input, and wiring 52 constituting the clock output terminal GCLK, to which a clock signal is output, are formed on the M0 wiring layer, which is the metal wiring layer. This makes it possible to realize a semiconductor integrated circuit device equipped with a gated clock circuit.

[0035] Furthermore, the wiring 13 that constitutes the clock input terminal CLK, into which the clock signal is input, has a wider wiring width than the wiring 52 that constitutes the clock output terminal GCLK, which outputs the clock signal. This reduces the resistance of the clock input terminal CLK, thereby enabling the semiconductor integrated circuit device to be operated at a higher speed.

[0036] Furthermore, no signal wiring other than wiring 13 is formed on the BM0 wiring layer. This suppresses crosstalk between the clock signal input to the clock input terminal CLK, the enable signal input to the enable signal terminal CEN, the clock signal output from the clock output terminal GCLK, and other signals, thereby reducing clock skew.

[0037] (Buffer Cell Configuration) Figure 4 is a plan view showing the layout structure of the buffer cell according to the embodiment. Specifically, Figure 4(a) shows the lower part of buffer cell C2, Figure 4(b) shows the upper part of buffer cell C2, Figure 4(c) shows the lower part of buffer cell C3, Figure 4(d) shows the upper part of buffer cell C3, Figure 4(e) shows the lower part of buffer cell C4, Figure 4(f) shows the upper part of buffer cell C4, Figure 4(g) shows the lower part of buffer cell C5, and Figure 4(h) shows the upper part of buffer cell C5.

[0038] Figure 5 is a circuit diagram showing the configuration of a buffer cell according to the embodiment. As shown in Figures 4 and 5, buffer cells C2 to C5 each include a buffer circuit composed of P-type transistors P11 and P12 and N-type transistors N11 and N12, respectively. The buffer circuit has a clock input terminal CKIN to which a clock signal is input and a clock output terminal CKOUT to which a clock signal is output.

[0039] (Configuration of buffer cell C2) As shown in Figure 4(a), power supply wiring 111, 112 and wiring 113, 114 extending in the X direction are formed in the BM0 wiring layer of buffer cell C2. Power supply wiring 111 is formed at the upper end of the cell and supplies the power supply voltage VDD. Power supply wiring 112 is formed at the lower end of the cell and supplies the power supply voltage VSS.

[0040] Wires 113 and 114 are formed in the center of the cell diagram. Wire 113 corresponds to the wiring that constitutes the clock input terminal CKIN to which the clock signal is input. Wire 113 is connected to gate wiring 131 via a via. Wire 114 corresponds to the wiring that constitutes the clock output terminal CKOUT to which the clock signal is output. Wire 114 is connected to local wiring 142 via a via.

[0041] As shown in Figure 4(b), an active region 3P is formed in the P-type transistor region. In a plan view, the active region 3P overlaps with the power supply wiring 111.

[0042] In the active region 3P, P-type transistors P11 and P12 are formed. The transistors P11 and P12 each have nanosheets 121a and 122a extending in the X direction as channels.

[0043] The portions serving as sources of the transistors P11 and P12 in the active region 3P are connected to the power supply wiring 111 via vias.

[0044] In the N-type transistor region, an active region 3N is formed. The active region 3N overlaps the power supply wiring 112 in plan view.

[0045] In the active region 3N, N-type transistors N11 and N12 are formed. The transistors N11 and N12 each have nanosheets 121b and 122b extending in the X direction as channels.

[0046] The portions serving as sources of the transistors N11 and N12 in the active region 3N are connected to the power supply wiring 112 via vias.

[0047] Gate wirings 131 and 132 extending in the Y direction are formed. The nanosheets 121a and 121b overlap the gate wiring 131 in plan view. The nanosheets 122a and 122b overlap the gate wiring 132 in plan view. The gate wiring 131 corresponds to the gates of the transistors P11 and N11. The gate wiring 132 corresponds to the gates of the transistors P12 and N12.

[0048] In the local wiring layer, local wirings 141 and 142 extending in the Y direction are formed. The local wiring 141 is connected to the portion serving as the drain of the transistor P11 in the active region 3P and the portion serving as the drain of the transistor N11 in the active region 3N. The local wiring 142 is connected to the portion serving as the drain of the transistor N12 in the active region 3P and the portion serving as the drain of the transistor N12 in the active region 3N.

[0049] A wiring 151 extending in the X direction is formed in the M0 wiring layer. The wiring 151 is connected to the gate wiring 132 and the local wiring 141 via vias.

[0050] In buffer cell C2, wiring 113 corresponding to the clock input terminal CKIN and wiring 114 corresponding to the clock output terminal CKOUT are formed in the BM0 wiring layer.

[0051] (Configuration of buffer cell C3) Compared to buffer cell C2 shown in Figures 4(a) and 4(b), buffer cell C3 shown in Figures 4(c) and 4(d) omits the wiring 114 formed in the BM0 wiring layer, and has wiring 152 formed in the M0 wiring layer.

[0052] As shown in Figure 4(d), a wiring 152 extending in the X direction is formed on the M0 wiring layer of buffer cell C3. The wiring 152 corresponds to the wiring that constitutes the clock output terminal CKOUT, to which the clock signal is output. The wiring 152 is connected via vias and local wiring 142 to the drain portion of transistor P12 in the active region 3P and to the drain portion of transistor N12 in the active region 3N.

[0053] In buffer cell C3, wiring 113 corresponding to the clock input terminal CKIN is formed in the BM0 wiring layer, and wiring 152 corresponding to the clock output terminal CKOUT is formed in the M0 wiring layer.

[0054] (Configuration of buffer cell C4) Compared to buffer cell C2 shown in Figures 4(a) and 4(b), buffer cell C4 shown in Figures 4(e) and 4(f) has wiring 152 formed on the M0 wiring layer.

[0055] As shown in Figure 4(f), a wiring 152 extending in the X direction is formed on the M0 wiring layer of buffer cell C4. The wiring 152 corresponds to the wiring that constitutes the clock output terminal CKOUT, to which the clock signal is output. The wiring 152 is connected via vias and local wiring 142 to the drain portion of transistor P12 in the active region 3P and to the drain portion of transistor N12 in the active region 3N.

[0056] In buffer cell C4, wiring 113 corresponding to the clock input terminal CKIN is formed in the BM0 wiring layer, and wirings 114 and 152 corresponding to the clock output terminals CKOUT are formed in the BM0 wiring layer and the M0 wiring layer, respectively.

[0057] (Configuration of buffer cell C5) Compared to buffer cell C2 shown in Figures 4(a) and 4(b), buffer cell C5 shown in Figures 4(g) and 4(h) omits the wirings 113 and 114 formed in the BM0 wiring layer, and has wirings 152 and 153 formed in the M0 wiring layer.

[0058] As shown in Figure 4(h), wirings 152 and 153 extending in the X direction are formed on the M0 wiring layer of buffer cell C5. Wiring 152 corresponds to the wiring that constitutes the clock output terminal CKOUT, to which the clock signal is output. Wiring 152 is connected via vias and local wiring 142 to the drain portion of transistor P12 in the active region 3P and to the drain portion of transistor N12 in the active region 3N. Wiring 153 corresponds to the wiring that constitutes the clock input terminal CKIN to which the clock signal is input. Wiring 153 is connected via vias to gate wiring 131 (gates of transistors P11 and N11).

[0059] In buffer cell C5, wiring 153 corresponding to the clock input terminal CKIN and wiring 152 corresponding to the clock output terminal CKOUT are formed in the M0 wiring layer.

[0060] (Block Layout) Figure 6 is a plan view showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to the embodiment. The block layout in Figure 6 includes a gated clock cell C1 and buffer cells C2 to C5.

[0061] Note that Figure 6 also shows other cells besides gated clock cell C1, but these are not shown. Furthermore, gated clock cell C1 located on the left side of Figure 6 is sometimes referred to as gated clock cell C1a, and gated clock cell C1 located at the top of Figure 6 is sometimes referred to as gated clock cell C1b.

[0062] In Figure 6, the gated clock cell C1 and buffer cells C2 to C5 are connected via the wiring (front wiring and rear wiring) of the wiring layers on the illustrated side. Specifically, the output terminals provided on the front (rear) side are connected to the input terminals provided on the front (rear) side. In Figure 6, the buffer cells to be arranged are appropriately selected from buffer cells C2 to C5 depending on the side (front or rear) on which the input and output terminals to be connected are provided. Furthermore, the wiring formed on the rear wiring layer (rear wiring) includes wiring formed on one or more wiring layers and vias connecting wiring formed on different wiring layers. Furthermore, the wiring formed on the metal wiring layer (front wiring) includes wiring formed on one or more wiring layers and vias connecting wiring formed on different wiring layers.

[0063] In Figure 6, the input source clock signal CK is supplied to circuits such as flip-flops (not shown) via gated clock cell C1 and buffer cells C2 to C5.

[0064] Specifically, wirings 211, 212, and 213 are formed in the rear wiring layer. Wirings 251 to 257 are formed in the metal wiring layer.

[0065] Wiring 211 is connected to wiring 113 (clock input terminal CKIN) formed in the BM0 wiring layer of buffer cell C2. Wiring 211 supplies the input original clock signal CK.

[0066] The wiring 212 is connected to the wiring 114 (clock output terminal CKOUT) formed in the BM0 wiring layer of buffer cell C2, the wiring 13 (clock input terminal CLK) formed in the BM0 wiring layer of gated clock cell C1a, and the wiring 113 (clock input terminal CKIN) formed in the BM0 wiring layer of buffer cell C4.

[0067] Wiring 213 is connected to wiring 114 (clock output terminal CKOUT) formed in the BM0 wiring layer of buffer cell C4, wiring 13 (clock input terminal CLK) formed in the BM0 wiring layer of gated clock cell C1b, and wiring 113 (clock input terminal CKIN) formed in the BM0 wiring layer of buffer cell C3.

[0068] Wiring 251 is connected to wiring 152 (clock output terminal CKOUT) formed in the M0 wiring layer of buffer cell C4, and wiring 153 (clock input terminal CKIN) formed in the M0 wiring layer of buffer cell C5.

[0069] Wiring 252 is connected to wiring 152 (clock output terminal CKOUT) formed in the M0 wiring layer of buffer cell C5.

[0070] Wiring 253 is connected to wiring 152 (clock output terminal CKOUT) formed in the M0 wiring layer of buffer cell C3.

[0071] Wiring 254 is connected to wiring 51 (enable signal terminal CEN) formed on the M0 wiring layer of gated clock cell C1a. Wiring 254 supplies the enable signal CEN1.

[0072] The wiring 255 is connected to the wiring 52 (clock output terminal GCLK) formed on the M0 wiring layer of the gated clock cell C1a.

[0073] Wiring 256 is connected to wiring 51 (enable signal terminal CEN) formed on the M0 wiring layer of gated clock cell C1b. Wiring 256 supplies the enable signal CEN2.

[0074] Wiring 257 is connected to wiring 52 (clock output terminal GCLK) formed on the M0 wiring layer of gated clock cell C1b.

[0075] In gated clock cell C1a, the enable signal CEN1 supplied to wiring 51 (enable signal terminal CEN) formed in the M0 wiring layer controls whether or not the clock signal input to wiring 13 (clock input terminal CLK) formed in the BM0 wiring layer is output from wiring 52 (clock output terminal GCLK) formed in the M0 wiring layer (pass or block).

[0076] In gated clock cell C1b, the enable signal CEN2 supplied to wiring 51 (enable signal terminal CEN) formed in the M0 wiring layer controls whether or not the clock signal input to wiring 13 (clock input terminal CLK) formed in the BM0 wiring layer is output from wiring 52 (clock output terminal GCLK) formed in the M0 wiring layer (pass or block).

[0077] With the above configuration, the wiring 211-213 that supplies the input source clock signal CK to the gated clock cell C1 is formed on the rear wiring layer, and the other wiring is formed on the metal wiring layer, so that crosstalk between the input source clock signal CK and other signals can be suppressed. In particular, since crosstalk with respect to clock signals that are circuit-wise closer to the input source clock signal CK can be suppressed, clock skew can be reduced more effectively.

[0078] In the embodiments and modifications described above, each transistor is provided with three nanosheets, but some or all of the transistors may be provided with one, two, or four or more nanosheets.

[0079] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0080] Furthermore, in the above-described embodiment, the power supply wiring for VDD and VSS is formed in the BM0 wiring layer, but the wiring layer on which the power supply wiring is formed is not limited to this. For example, either one or both of the power supply wiring for VDD and the power supply wiring for VSS may be formed in the M0 wiring layer.

[0081] Furthermore, while the transistors in the embodiments described above are nanosheet FETs, the invention is not limited to these. For example, fin FETs or other types of transistors may also be used.

[0082] This disclosure enables the realization of a semiconductor integrated circuit device layout equipped with a gated clock circuit.

[0083] 11, 12, 111, 112 Power wiring 21a-30a, 21b-30b, 121a, 122a, 121b, 122b Nanosheets 31-33, 131, 132 Gate wiring 41, 141, 142 Local wiring 13, 14, 51, 52, 113, 114, 152, 153 Wiring 2P1-2P4, 2N1-2N4, 3P, 3N Active region P1-P12, N1-N12 Transistor C1 (C1a, C1b) Gated clock cell C2-C5 Buffer cell

Claims

1. A semiconductor integrated circuit device comprising a plurality of standard cells, wherein the plurality of standard cells include a first standard cell on which a gated clock circuit is configured, and the first standard cell comprises a transistor, a first input terminal to which a clock signal is input and which is composed of a first wiring formed in a back wiring layer below the transistor in the depth direction, a signal terminal to which an enable signal is input to control the passage and blocking of the clock signal, and a first output terminal to which the clock signal, whose passage and blocking are controlled by the enable signal is output and which is composed of a third wiring formed in the metal wiring layer.

2. A semiconductor integrated circuit apparatus according to claim 1, wherein the first wiring has a wider wiring width than the second wiring.

3. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells include a second standard cell having a buffer circuit, and the second standard cell comprises a second input terminal to which the clock signal is input, and a second output terminal to which the clock signal is output, comprising a fourth wiring formed in the back wiring layer.

4. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells include a second standard cell having a buffer circuit, and the second standard cell comprises a second input terminal to which the clock signal is input, and a second output terminal to which the clock signal is output, comprising a fifth wiring formed in the metal wiring layer.

5. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells include a second standard cell having a buffer circuit, and the second standard cell comprises a second input terminal to which the clock signal is input, which is composed of a fourth wiring formed in the back wiring layer, a second output terminal to which the clock signal is output, which is composed of a fifth wiring formed in the back wiring layer, and a third output terminal to which the clock signal is output, which is composed of a sixth wiring formed in the metal wiring layer.

6. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells include a second standard cell having a buffer circuit, and the second standard cell comprises a second input terminal to which the clock signal is input, and a second output terminal to which the clock signal is output, comprising a fourth wiring formed in the metal wiring layer.

7. A semiconductor integrated circuit apparatus according to claim 1, wherein the plurality of standard cells further include a second standard cell having a buffer circuit, the second standard cell comprising a fourth wiring formed in the back wiring layer and having a second input terminal to which the clock signal is input, and a fifth wiring formed in the back wiring layer and having a second output terminal to which the clock signal is output, the fifth wiring being connected to the first wiring in the first standard cell, the semiconductor integrated circuit apparatus.

8. A semiconductor integrated circuit apparatus according to claim 7, wherein the plurality of standard cells further include a third standard cell having a buffer circuit, the second standard cell is composed of a sixth wiring formed in the metal wiring layer and has a third output terminal to which the clock signal is output, the third standard cell is composed of a seventh wiring formed in the metal wiring layer and has a third input terminal to which the clock signal is input, and an eighth wiring formed in the metal wiring layer and has a fourth output terminal to which the clock signal is output, the seventh wiring is connected to the sixth wiring, the semiconductor integrated circuit apparatus.

9. A semiconductor integrated circuit device comprising a plurality of standard cells, wherein the plurality of standard cells include a first standard cell configured with a gated clock circuit and a second standard cell configured with a buffer circuit, the second standard cell comprising a transistor, an input terminal configured with a first wiring formed in a back wiring layer below the transistor in the depth direction, to which a clock signal is input, and an output terminal configured with a second wiring formed in the back wiring layer to which the clock signal is output, the second wiring being connected to the first standard cell, the semiconductor integrated circuit device.

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