Photodetection element and electronic device

Abstract

The present technology relates to a photodetection element and an electronic device with which it is possible to improve the degree of freedom of element arrangement. A photodetection element according to the present technology comprises: a first semiconductor substrate in which a plurality of pixel regions are formed; an inter-pixel separation part that separates adjacent pixel regions in the first semiconductor substrate; a first conductive part that is formed in the inter-pixel separation part; and a second conductive part that is formed on a light-receiving surface of the first semiconductor substrate and is connected to the first conductive part. The present technology can be applied to, for example, a solid-state imaging device.

Description

Optical Detection Element and Electronic Device

[0001] The present technology relates to an optical detection element and an electronic device, and particularly to an optical detection element and an electronic device that can improve the degree of freedom in arranging elements.

[0002] Conventionally, there is an image sensor in which trenches are formed at the boundaries of pixels to separate the photoelectric conversion portions of each pixel for the purpose of suppressing color mixing and ensuring the saturation charge amount when the pixels are miniaturized (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-47438

[0004] As the pixels are miniaturized, the space for arranging pixel transistors and wirings becomes smaller. As a result, it may be necessary to lower the performance of the pixel transistors, or it may not be possible to mount elements for adding functions to the pixels.

[0005] The present technology has been made in view of such a situation, and aims to improve the degree of freedom in arranging elements.

[0006] The first optical detection element of the present technology includes a first semiconductor substrate on which a plurality of pixel regions are formed, a pixel separation portion that separates between the adjacent pixel regions on the first semiconductor substrate, a first conductive portion formed within the pixel separation portion, and a second conductive portion formed on the light receiving surface of the first semiconductor substrate and connected to the first conductive portion.

[0007] The second optical detection element of the present technology includes a pixel region formed on a semiconductor substrate, a floating diffusion region to which the charge accumulated in the pixel region is transferred, a pixel separation portion that separates between the pixel region and another pixel region adjacent to the semiconductor substrate, and a plurality of conductive portions individually formed within the pixel separation portion and capable of applying arbitrary voltages to the side surfaces of the pixel regions.

[0008] In the first photodetector of this technology, a plurality of pixel regions are formed on a semiconductor substrate, an inter-pixel separation portion is formed on the semiconductor substrate to separate adjacent pixel regions, a first conductive portion is formed within the inter-pixel separation portion, and a second conductive portion connected to the first conductive portion is formed on the light-receiving surface of the semiconductor substrate.

[0009] In the second photodetector of this technology, a pixel region is formed on a semiconductor substrate, a floating diffusion region is formed to which the charge accumulated in the pixel region is transferred, an inter-pixel isolation section is formed to separate the pixel region from other adjacent pixel regions on the semiconductor substrate, and a plurality of conductive sections are individually formed within the inter-pixel isolation section, each capable of applying an arbitrary voltage to the side surface of the pixel region.

[0010] This figure shows a schematic example of the configuration of a photodetector element to which this technology is applied. This figure shows a basic example of the side cross-section (cross-section in the substrate thickness direction) of a pixel of a photodetector element. This is a plan view of the pixel substrate according to the first embodiment of this technology, as seen from the back side. This is a side cross-sectional view of the pixel substrate near the first conductive part. This is the first figure illustrating an example of a method for connecting the first conductive part 102 and the p-well. This is the second figure illustrating an example of a method for connecting the first conductive part 102 and the p-well. This figure shows a first example of the laminated structure of the substrate. This figure shows a second example of the laminated structure of the substrate. This figure shows a third example of the laminated structure of the substrate. This figure shows a fourth example of the laminated structure of the photodetector element. This figure shows a first modified example of the configuration of the inter-pixel separation part. This figure shows an example of the arrangement of the first conductive part connected to the first conductive part in Figure 11. This figure shows another example of the arrangement of the first conductive part connected to the first conductive part in Figure 11. This figure shows a second modified example of the configuration of the inter-pixel separation part. This figure shows a third modified example of the configuration of the inter-pixel separation part. This figure shows a fourth modified example of the configuration of the inter-pixel separation part. This is the first figure illustrating a method for forming a pixel having a conductive part according to the first embodiment. This is a second figure illustrating a method for forming a pixel having a conductive portion according to the first embodiment. This is a third figure illustrating a method for forming a pixel having a conductive portion according to the first embodiment. This is a plan view showing the configuration of a pixel substrate according to the second embodiment of this technology. This is a plan view of the vicinity of the pixel transistor as seen from the front side of the semiconductor layer. This is a side cross-sectional view of the vicinity of the pixel transistor of the pixel substrate. This is a figure showing an example of the arrangement position of the pixel transistor. This is a side cross-sectional view of the vicinity of the pixel transistor in Figure 23. This is a figure showing a first modified example of the pixel transistor. This is a figure showing a second modified example of the pixel transistor. This is a figure showing a third modified example of the pixel transistor. This is a side cross-sectional view of the vicinity of the pixel transistor in Figure 27. This is a figure showing a fourth modified example of the pixel transistor. This is the first figure showing a fifth modified example of the pixel transistor. This is the second figure showing a fifth modified example of the pixel transistor. This is a first figure illustrating a method for forming a pixel having a conductive portion and a pixel transistor according to the second embodiment. This is a second figure illustrating a method for forming a pixel having a conductive portion and a pixel transistor according to the second embodiment.This is a third figure illustrating a method for forming a pixel having a conductive part and a pixel transistor according to a second embodiment. This is a fourth figure illustrating a method for forming a pixel having a conductive part and a pixel transistor according to a second embodiment. This figure shows the configuration of a pixel substrate according to a third embodiment of this technology. This figure shows an example of the shape of a pixel region. This figure shows a first modified example of an inter-pixel isolation part in which a p-well is formed. This figure shows a second modified example of an inter-pixel isolation part in which a p-well is formed. This figure shows a third modified example of an inter-pixel isolation part in which a p-well is formed. This figure shows a fourth modified example of an inter-pixel isolation part in which a p-well is formed. This figure shows an example of the arrangement of the first conductive part when the photodetector is constructed by stacking a pixel substrate and a transistor substrate. This is a side cross-sectional view of the photodetector near the pixel region. This figure shows another example of the arrangement of the first conductive part when the photodetector is constructed by stacking a pixel substrate and a transistor substrate. This is a side cross-sectional view of the photodetector near the pixel region. This is a first figure showing an example of the arrangement of the second conductive part. This is a second figure showing an example of the arrangement of the second conductive part. This is a first figure illustrating a method for forming a pixel 2 having a p-well according to a third embodiment. This is a second figure illustrating a method for forming a pixel 2 having a p-well according to a third embodiment. This is a first figure illustrating a method for forming a pixel 2 having a p-well and FD according to a third embodiment. This is a second figure illustrating a method for forming a pixel 2 having a p-well and FD according to a third embodiment. This figure shows an example of the configuration of a pixel according to a fourth embodiment of this technology. This figure schematically shows the way light is incident on the pixel region. This figure shows an example of the voltage applied by each electrode during charge transfer. This figure illustrates the electrode formation surface in the semiconductor layer. This is a first figure showing an example of the voltage applied to each electrode during charge discharge, charge accumulation, and charge transfer. This is a second figure showing an example of the voltage applied to each electrode during charge discharge, charge accumulation, and charge transfer. This figure shows a first modified example of the pixel configuration. This figure shows a second modified example of the pixel configuration. This figure shows a third modified example of the pixel configuration. This figure illustrates the electrode formation surface in the semiconductor layer of Figure 60. This is a first figure showing an example of the voltage applied by each electrode during charge discharge, charge accumulation, and charge transfer in the pixel of Figure 60.Figure 60 is a second figure showing examples of voltages applied by each electrode during charge discharge, charge accumulation, and charge transfer in the pixel. Figure 60 is a figure showing a fourth modified example of the pixel configuration. Figure 60 is a figure showing a fifth modified example of the pixel configuration. Figure 7 is a figure showing a sixth modified example of the pixel configuration. This is a timing chart explaining the operation flow of the pixel. Figure 8 is a figure showing a seventh modified example of the pixel configuration. This is a block diagram showing an example of the configuration of an imaging device as an electronic device to which the technology of this disclosure is applied. This is a figure showing an example of use using a solid-state imaging device. This is a figure showing an example of the schematic configuration of an endoscopic surgical system. This is a block diagram showing an example of the functional configuration of a camera head and a CCU. This is a block diagram showing an example of the schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit.

[0011] The following describes the embodiments for implementing this technology. The explanation will proceed in the following order: 1. Outline configuration of the photodetector element 2. First embodiment 3. Second embodiment 4. Third embodiment 5. Fourth embodiment 6. Application example to electronic equipment 7. Example of use of the photodetector element 8. Application example to endoscopic surgical systems 9. Application example to mobile devices

[0012] <1. Schematic Configuration of Photodetector> Figure 1 shows an example of the schematic configuration of a photodetector 1 to which this technology is applied.

[0013] The photodetector element 1 in Figure 1 is configured with a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array on a pixel substrate 12 made of silicon (Si) as a semiconductor, and a peripheral circuit section around it. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0014] Pixel 2 includes a photodiode as a photoelectric conversion element, multiple pixel transistors, etc. The multiple pixel transistors are composed of four MOS transistors, for example, a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor.

[0015] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the photodetector 1. In other words, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0016] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 10, supplies pulses to the selected pixel drive wiring 10 to drive the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a pixel signal based on the signal charge generated in the photoelectric conversion element of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0017] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0018] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0019] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform various digital signal processing such as black level adjustment and column variation correction. The input / output terminal 13 exchanges signals with the outside.

[0020] The photodetector element 1 configured as described above has a structure called a column AD method, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each pixel row. Furthermore, the photodetector element 1 is a back-illuminated photodetector element in which light is incident from the back side opposite to the front side of the pixel substrate 12 on which the pixel transistors are formed.

[0021] The photodetector 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array 3 and outputs it to the outside. The photodetector 1 can be used, for example, as a light-receiving device in a solid-state imaging device that detects the distribution of incident light amounts of visible light or infrared light and captures it as an image, or as a light-receiving device in a distance measuring system that receives light (reflected light) reflected from an object when infrared light is irradiated as active light, and measures the distance to the subject using a direct ToF or indirect ToF method.

[0022] Figure 2 shows an example of the basic configuration of a side cross-section (cross-section in the substrate thickness direction) of a pixel 2 of the photodetector element 1.

[0023] As shown in Figure 2, the pixel substrate 41 (corresponding to the pixel substrate 12 in Figure 1) has a semiconductor layer 51 (semiconductor substrate) made of silicon, for example, as the semiconductor, and a wiring layer 52 formed on its front surface. In Figure 2, the upper surface of the semiconductor layer 51 is the back surface of the semiconductor layer 51, and is the light-receiving surface (light incident surface) to which light is incident. In Figure 2, the lower surface of the semiconductor layer 51 is the front surface, and is the circuit formation surface on which the wiring layer 52 is formed. Hereafter, viewing the pixel substrate 41 from a direction perpendicular to the front or back surface of the pixel substrate 41 (substrate thickness direction) is also called a plan view, and viewing the pixel substrate 41 from a direction parallel to the front or back surface is also called a cross-sectional view. In other words, Figure 2 is a cross-sectional view, and Figure 3 is a plan view.

[0024] In the semiconductor layer 51, a pixel region 61 is formed for each pixel 2, on which photodiodes, pixel transistors, etc., are formed.

[0025] Between each pixel 2 of the semiconductor layer 51, an inter-pixel isolation section 63 is formed to electrically isolate the pixel region 61 of adjacent pixels 2. The inter-pixel isolation section 63 is configured, for example, as an FFTI (Front Full Trench Isolation) in which an insulating film or the like is embedded in a trench that penetrates from the back surface to the front surface of the semiconductor layer 51.

[0026] A color filter 42 is formed on the back surface of the semiconductor layer 51, which is the light-receiving surface. For example, a red, green, or blue color filter 42 is formed for each pixel. The color filter 42 is formed by, for example, rotary coating of a photosensitive resin containing a pigment or dye. The red, green, and blue color filters 42 are arranged, for example, in a Bayer array, but they may be arranged by other methods.

[0027] Between each color filter 42, an inter-pixel light-shielding film 43 is formed to prevent light leakage to adjacent pixels 2. For the inter-pixel light-shielding film 43, a single-layer metal film such as titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), or tungsten nitride (WN) can be used. Alternatively, a multilayer film of these metals (for example, a multilayer film of titanium and tungsten, or a multilayer film of titanium nitride and tungsten) may be used as the inter-pixel light-shielding film 43.

[0028] An on-chip lens 44 is formed on the color filter 42 for each pixel 2. The on-chip lens 44 is made of a resin-based material such as styrene resin, acrylic resin, styrene-acrylic copolymer resin, or siloxane resin. The on-chip lens 44 focuses the incident light, and the focused light is efficiently incident on the pixel area 61 via the color filter 42.

[0029] The wiring layer 52 is constructed, for example, by forming multiple transistors and wiring within an insulating film.

[0030] A p-well (p-type well contact) 71 is formed on the front side of the semiconductor layer 51. The p-well 71 is a region in which the impurity concentration of the pixel region 61 is controlled to be p-type, and is a well contact to which a fixed potential (e.g., GND potential) is applied. The p-well 71 is connected to the metal wiring 73 in the wiring layer 52 via a contact 72 in the wiring layer 52. The p-well 71 is connected to the fixed potential via the contact 72 and the metal wiring 73.

[0031] Within the wiring layer 52, a pixel transistor 74 is formed for each pixel 2. The pixel transistor 74 is connected to the metal wiring 76 within the wiring layer 52 via a contact 75 within the wiring layer 52.

[0032] As described above, in pixel 2 of Figure 2, the p-well 71 formed on the front side of the semiconductor layer 51, and the contacts and metal wiring connected to the pixel transistor 74, are formed on the front side of the semiconductor layer 51. As pixels become smaller, the space for arranging pixel transistors and wiring decreases. This sometimes necessitates lowering the performance of the pixel transistors or makes it impossible to mount elements to add functionality to the pixels.

[0033] This technology was developed in view of the above circumstances, and aims to improve the degree of freedom in the arrangement of elements by forming a first conductive portion within an inter-pixel separation portion 63 that separates adjacent pixels 2 (pixel regions 61) in the semiconductor layer 51, and forming a second conductive portion connected to the first conductive portion on the light-receiving surface of the semiconductor layer 51. Here, "on the light-receiving surface of the semiconductor layer 51" means the position on the outer side of the back surface of the semiconductor layer 51 to which the light detected by the photodetector 1 is incident. Note that "on the circuit formation surface of the semiconductor layer 51" means the position on the outer side of the front surface opposite to the light-receiving surface (back surface) of the semiconductor layer 51.

[0034] <2. First Embodiment> - The substrate configuration diagram 3 is a plan view of the pixel substrate 41 according to the first embodiment of this technology, as seen from the back side.

[0035] As shown in Figure 3, the inter-pixel separation portion 63, formed in a grid pattern along the boundary of the pixel 2, has a plurality of intersections and a plurality of straight sections located between two adjacent intersections. Within the insulating film 62 formed on the entire back surface of the semiconductor layer 51, the second conductive portion 101 is formed in a grid pattern so as to follow the inter-pixel separation portion 63 in a plan view. Within a predetermined intersection of the inter-pixel separation portion 63, for example, a cylindrical first conductive portion 102 is formed. The second conductive portion 101 and the first conductive portion 102 are electrically connected.

[0036] The first conductive portion 102 and the second conductive portion 101 are made of metallic materials such as tungsten (W), aluminum (Al), copper (Cu), and titanium (Ti), or transparent oxide semiconductors (transparent oxide films) that transmit light (e.g., visible light) detected by the photodetector 1. The transparent oxide semiconductor is a single-layer or multilayer film containing at least one of InO, IGZO, ITO, IZO, ZnO, SnO, and CdO. When the first conductive portion 102 and the second conductive portion 101 are made of transparent oxide films, the shape of the second conductive portion 101 is not limited to a shape that follows the inter-pixel separation portion 63, but can be any shape. When the first conductive portion 102 and the second conductive portion 101 are made of transparent oxide films, for example, the entire surface of the back surface of the semiconductor layer 51 may be covered by the second conductive portion 101. The first conductive portion 102 and the second conductive portion 101 may be made of the same material or different materials.

[0037] Figure 4 is a side cross-sectional view of the pixel substrate 41 near the first conductive portion 102.

[0038] As shown in Figure 4, the inter-pixel separation portion 63 according to the first embodiment is constructed by embedding a first conductive portion 102 and an insulating film 103 in a trench that penetrates from the back surface to the front surface of the semiconductor layer 51 and completely separates them. The insulating film 103 is formed between the pixel region 61 and the first conductive portion 102. An insulating film 62 is formed between the semiconductor layer 51 and the second conductive portion 101. The insulating film 62 and the insulating film 103 are formed of a material that transmits light and has insulating properties, for example. As the material for the insulating film 62 and the insulating film 103, silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), HfxZr1-xO2, etc. can be used.

[0039] As shown in Figure 4A, the first conductive portion 102 is formed from the back surface of the semiconductor layer 51 to a depth that reaches the wiring layer 52, and is connected, for example, to a transfer transistor 121 in the wiring layer 52. The transfer transistor 121 has an embedded gate electrode embedded in the pixel region 61 from the front surface in the direction of the substrate thickness, and is an element that applies a voltage to the semiconductor layer 51. An insulating film is formed between the gate electrode of the transfer transistor 121 and the pixel region 61.

[0040] As shown in Figure 4B, the first conductive portion 102 is formed from the back surface of the semiconductor layer 51 to a depth that reaches the wiring layer 52, and is connected, for example, to a transfer transistor 122 in the wiring layer 52. The transfer transistor 122 is an element that has a planar gate electrode and applies a voltage to the semiconductor layer 51. An insulating film is formed between the gate electrode of the transfer transistor 122 and the pixel region 61.

[0041] As shown in Figure 4C, the first conductive portion 102 is formed, for example, from the back surface to the front surface of the semiconductor layer 51 and is connected to a contact 124 formed directly above the front surface of the semiconductor layer 51. The contact 124 is connected to a p-well 123 formed on the front surface side within the pixel region 61. The contact 124 is made of a metallic material such as tungsten, aluminum, copper, or titanium, or a transparent oxide film, and is connected so as to span the p-wells 123 formed in each of the four pixel regions 61 that are in contact with the intersection of the inter-pixel separation portion 63 where the first conductive portion 102 is formed.

[0042] As described above, the first conductive portion 102 is formed on the front surface side of the semiconductor layer 51 and is connected to an element that modulates a potential (applies a voltage), an element through which current flows at a fixed potential, and the like. Examples of the element connected to the first conductive portion 102 include a transfer transistor, an amplification transistor, a selection transistor, a reset transistor, a capacitance switching transistor, a well contact, a floating diffusion region (FD), and a capacitor.

[0043] These elements are connected to a pad portion or the like provided in the peripheral circuit portion around the pixel array portion 3 via the first conductive portion 102 and the second conductive portion 101, and are connected to a fixed potential such as a GND potential or a negative bias. By forming the first conductive portion 102 and the second conductive portion 101 for connecting an element formed on the front surface side of the semiconductor layer 51 to a GND potential, a negative bias, or the like, inside the pixel isolation portion 63 and on the back surface of the semiconductor layer 51, contacts and metal wirings that should have been connected to the element do not need to be formed on the front surface side of the semiconductor layer 51. As a result, a wide space for arranging pixel transistors and wirings can be secured on the front surface side of the semiconductor layer 51, and the degree of freedom in arranging elements can be improved.

[0044] FIGS. 5 and 6 are diagrams for explaining an example of a connection method between the first conductive portion 102 and the p-well.

[0045] In the example of A in FIG. 5, the first conductive portion 102 is connected to the p-well 123 (corresponding to the p-well 71 in FIG. 2) via a contact 124 formed directly above the surface side of the semiconductor layer 51.

[0046] In the example of B in FIG. 5, the first conductive portion 102 is connected to the p-well 123 via a contact 125 embedded in the pixel isolation portion 63 from the front surface side of the semiconductor layer 51 to a predetermined depth. The contact 125 is connected to the p-well 123 in the pixel region 61 on the side surface of the trench of the pixel isolation portion 63. Such a connection method is called a side contact.

[0047] In the example of C in FIG. 5, the first conductive portion 102 is formed so as to straddle a plurality of pixel regions 61. In other words, the first conductive portion 102 is directly connected within the pixel isolation portion 63 to a p-well 126 that is shared by the plurality of pixel regions 61.

[0048] In the example of A in FIG. 6, the first conductive portion 102 is connected to the p-well 123 via a metal wiring 141 formed of tungsten, copper, or the like in the wiring layer 52. The metal wiring 141 has a C-shaped cross-sectional view with both ends protruding, and the protruding portions are connected to the p-well 123. Here, the first conductive portion 102 is formed to a depth reaching the wiring layer 52 from the back side of the semiconductor layer 51 and is connected to the metal wiring 141 within the wiring layer 52.

[0049] In the example of B in FIG. 6, the first conductive portion 102 is connected to the p-well 123 via a metal wiring 142 formed of tungsten, copper, or the like in the wiring layer 52. The metal wiring 142 has an E-shaped cross-sectional view with both ends and the center protruding, and the protruding portions at both ends are connected to the p-well 123. Here, the first conductive portion 102 is formed from the back side to the front side of the semiconductor layer 51 and is connected to the protruding portion at the center of the metal wiring 142 at the boundary between the semiconductor layer 51 and the wiring layer 52.

[0050] In the example of C in FIG. 6, the first conductive portion 102 is connected to the p-well 123 via a metal wiring 143 formed of tungsten, copper, or the like embedded in the pixel isolation portion 63 to a predetermined depth from the front side of the semiconductor layer 51. Here, the first conductive portion 102 is formed to a depth reaching the metal wiring 143 from the back side of the semiconductor layer 51 and is connected to the metal wiring 143 within the pixel isolation portion 63.

[0051] FIG. 7 is a diagram showing a first example of the stacked structure of a substrate.

[0052] The photodetector 1 may be configured by laminating two or more semiconductor substrates. In the example of FIG. 7, a transistor substrate 201, which is a substrate on which transistors and the like are formed, is joined (stacked) on the front surface of the pixel substrate 41.

[0053] In the pixel substrate 41, p-wells 123 are formed in the corner portions of the pixel regions 61 that are in contact with a certain intersection of the inter-pixel separation portion 63, and FDs 211 are formed in the other corner portions of the pixel regions 61 that are in contact with other intersections of the inter-pixel separation portion 63. Furthermore, in the pixel substrate 41, the four p-wells 123 formed in each of the four pixel regions 61 that are in contact with predetermined intersections of the inter-pixel separation portion 63 are connected to one contact 124. In addition, in the pixel substrate 41, the four FDs 211 formed in each of the four pixel regions 61 that are in contact with other intersections of the inter-pixel separation portion 63 are connected to one contact 212.

[0054] Figure 7A shows an example of the configuration of a side cross-section of pixel 2 when the first conductive portion 102 and the second conductive portion 101 are not formed.

[0055] If the first conductive portion 102 and the second conductive portion 101 are not formed, as shown in Figure 7A, the contact 124 is connected to the metal wiring 222 of the transistor substrate 201 via a contact 221 that penetrates the semiconductor region 227 of the transistor substrate 201 in the substrate thickness direction. The metal wiring 222 is formed on the lower side of the transistor substrate 201 (the side opposite to the junction with the semiconductor layer 51) and is connected to, for example, the GND potential.

[0056] Furthermore, contact 212 is connected to metal wiring 224 of the transistor substrate 201 via contact 223, which penetrates the semiconductor region 227 of the transistor substrate 201 in the substrate thickness direction. Metal wiring 224 is formed on the lower side of the transistor substrate 201 and is connected to the amplifying transistor 225, which is also formed on the lower side of the transistor substrate 201, via contact 226. In other words, FD211 is connected to the amplifying transistor 225 via contact 212, contact 223, metal wiring 224, and contact 226.

[0057] Thus, if the first conductive portion 102 and the second conductive portion 101 are not formed, it becomes necessary to excavate the semiconductor region 227 of the transistor substrate 201 in order to form the contact 221, which reduces the area of ​​the semiconductor region 227 on which the transistor and the like are formed.

[0058] Figure 7B shows an example of the configuration of a side cross-section of pixel 2 when the first conductive portion 102 and the second conductive portion 101 are formed.

[0059] When the first conductive portion 102 and the second conductive portion 101 are formed, as shown in Figure 7B, the contact 124 is connected to, for example, the GND potential via the first conductive portion 102 formed in the inter-pixel separation portion 63.

[0060] Furthermore, the contact 212 is connected to the amplifying transistor 225 via a contact 223 or the like that penetrates the semiconductor region 227 of the transistor substrate 201 in the substrate thickness direction, similar to the case where the first conductive portion 102 and the second conductive portion 101 are not formed.

[0061] In this way, when the first conductive portion 102 and the second conductive portion 101 are formed, it becomes unnecessary to excavate the semiconductor region 227 of the transistor substrate 201 in order to form the contact 221, and it becomes possible to secure a larger area for the semiconductor region 227.

[0062] Figure 8 shows a second example of a substrate stacked structure.

[0063] In the example shown in Figure 8, a transistor substrate 201 is bonded (stacked) onto the front surface of the pixel substrate 41, and a logic substrate 202 is bonded (stacked) onto the underside of the transistor substrate 201 (the side opposite to the surface bonded to the semiconductor layer 51).

[0064] In the pixel substrate 41, a p-well 126 is formed that spans the corner portions of the four pixel regions 61 that are in contact with the intersection of the inter-pixel separation portion 63, in other words, a p-well shared by the four pixel regions 61 is formed that spans the corner portions of the four pixel regions 61 that are in contact with the other intersection of the inter-pixel separation portion 63, in other words, a p-well 215 shared by the four pixel regions 61 is formed.

[0065] Figure 8A shows an example of the configuration of a side cross-section of pixel 2 when the first conductive portion 102 and the second conductive portion 101 are not formed.

[0066] If the first conductive portion 102 and the second conductive portion 101 are not formed, as shown in Figure 8A, the FD215 is connected to the amplifying transistor 225 on the transistor substrate 201 via a Cu-Cu junction formed by directly joining, for example, a Cu wiring 241 exposed on the front surface of the pixel substrate 41 and a Cu wiring 251 exposed on the upper surface of the transistor substrate 201 (the bonding surface with the pixel substrate 41).

[0067] In detail, FD215 is connected to Cu wiring 241 via metal wiring 242, and Cu wiring 251 is connected to metal wiring 224 formed on the lower surface (the junction surface with logic board 202) of the transistor board 201 via contact 223 that penetrates the semiconductor region 227 of the transistor board 201 in the board thickness direction. Metal wiring 224 is connected to the amplifying transistor 225. Furthermore, metal wiring 224 is also connected to the circuit portion of logic board 202 via a Cu-Cu junction formed by directly joining Cu wiring 252 exposed on the lower surface of transistor board 201 and Cu wiring 261 exposed on the upper surface (the junction surface with transistor board 201) of logic board 202.

[0068] Furthermore, for example, the p-well 126 is connected to a metal wiring 222 formed on the lower side of the transistor substrate 201 via a Cu-Cu junction, which is formed by directly joining a Cu wiring 243 exposed on the lower surface of the pixel substrate 41 and a Cu wiring 253 exposed on the upper surface of the transistor substrate 201 (the junction surface with the pixel substrate 41).

[0069] In detail, the p-well 126 is connected to the Cu wiring 243 via the metal wiring 244, and the Cu wiring 253 is connected to the metal wiring 222 via a contact 221 that penetrates the semiconductor region 227 of the transistor substrate 201 in the substrate thickness direction. The metal wiring 222 is connected to, for example, the GND potential.

[0070] Figure 8B shows an example of the configuration of a side cross-section of pixel 2 when the first conductive portion 102 and the second conductive portion 101 are formed.

[0071] When the first conductive portion 102 and the second conductive portion 101 are formed, as shown in Figure 8B, the p-well 126 is connected to, for example, the GND potential via the first conductive portion 102 formed in the inter-pixel separation portion 63.

[0072] Furthermore, FD215 is connected to the amplifier transistor 225 on the transistor substrate 201 and the circuit section of the logic substrate 202 via a Cu-Cu junction or the like, similar to the case where the first conductive portion 102 and the second conductive portion 101 are not formed.

[0073] In this way, when the first conductive portion 102 and the second conductive portion 101 are formed, it becomes unnecessary to excavate the semiconductor region 227 of the transistor substrate 201 in order to form the contact 221, and it becomes possible to secure a larger area for the semiconductor region 227.

[0074] Figure 9 shows a third example of a substrate stacked structure.

[0075] Figure 9 illustrates an example in which a p-well 281 is formed on the upper side (the side where it connects with the pixel substrate 41) of the semiconductor region 227 of the transistor substrate 201, as described with reference to Figure 8.

[0076] As shown in Figure 9A, if the first conductive portion 102 and the second conductive portion 101 are not formed, it is necessary to excavate the semiconductor region 227 to form the contact 221, which reduces the area of ​​the semiconductor region 227 and the p-well 281. Furthermore, since it is necessary to excavate the semiconductor region 227 from below to form a contact for applying the GND potential to the p-well 281, the area of ​​the semiconductor region 227 becomes even smaller.

[0077] As shown in Figure 9B, when the first conductive portion 102 and the second conductive portion 101 are formed, the p-well 281 is connected to, for example, the GND potential via the third conductive portion 291 formed in the inter-pixel separation portion 63.

[0078] More specifically, the third conductive portion 291 is a conductive portion formed at an intersection other than, for example, the intersection of the inter-pixel separation portion 63 that is in contact with the corner portion of the pixel region 61 in which the p-well 123 is formed, or another intersection of the inter-pixel separation portion 63 that is in contact with the corner portion of the pixel region 61 in which the FD 211 is formed. The third conductive portion 291 is formed from the back surface of the semiconductor layer 51 to a depth that reaches the p-well 281 of the transistor substrate 201, and is directly connected to the p-well 281. The third conductive portion 291 is also connected to the second conductive portion 101. In other words, the p-well 281 is connected to the same potential (GND potential) as the p-well 123 via the third conductive portion 291 and the second conductive portion 101.

[0079] In this way, by forming a third conductive portion 291 within the inter-pixel separation portion 63 that functions as a contact for connecting the p-well 281 to the GND potential, it becomes unnecessary to form a contact for connecting the p-well 281 to the GND potential, and it becomes possible to secure a larger area for the semiconductor region 227.

[0080] Figure 10 shows a fourth example of the stacked structure of the photodetector element 1. The left side of Figure 10 shows an example of the configuration of a side cross-section of the pixel 2, and the right side shows a plan view of the contact 124 as seen from above.

[0081] As shown on the left side of Figure 10, the first conductive portion 102 may be connected to both the p-well 123 of the semiconductor layer 51 and the p-well 281 of the transistor substrate 201. More specifically, as shown on the upper right side of Figure 10, the contact 124 has, for example, a rectangular through-hole H1 formed therein, and a portion of the first conductive portion 102 is formed to a depth that reaches the p-well 281 through the through-hole H1 (through the contact 124) and is directly connected to the p-well 281.

[0082] As shown in the lower right of Figure 10, the first conductive portion 102 may be formed by extending from the back surface of the semiconductor layer 51 across the contact 124 to a depth that reaches the p-well 281, and directly connected to the p-well 281.

[0083] Figure 11 shows a first modified example of the configuration of the inter-pixel separation section 63. Figure 11 shows a cross-sectional view of the vicinity of the intersection of the inter-pixel separation section 63 as seen from above.

[0084] As shown in Figure 11, the intersection of the pixel separation portion 63 is constructed by embedding an insulating film 103A or the like in the through hole H11, and the straight portion of the pixel separation portion 63 is constructed by embedding an insulating film 103B or the like in the trench T1. In the example in Figure 11, the through hole H11 and the trench T1 are formed to be discontinuous.

[0085] A cylindrical first conductive portion 102A is formed inside the through hole H11, and a thin plate-shaped first conductive portion 102B is formed inside the trench T1.

[0086] Figure 12 shows an example of the arrangement of the first conductive parts connected to the first conductive parts 102A and 12B in Figure 11. Figure 12 shows a plan view of the pixel substrate 41 as seen from above.

[0087] As shown in Figure 12, adjacent first conductive portions 102A-1 and 102A-2 are connected to a second conductive portion 101A formed on the pixel region 61 or on the inter-pixel separation portion 63, so as to connect the intersection of the inter-pixel separation portion 63. The second conductive portion 101A is connected to, for example, the GND potential.

[0088] The first conductive portion 102B-2 formed above the first conductive portion 102A-1 in the figure, the first conductive portion 102B-4 formed between the first conductive portion 102A-1 and the first conductive portion 102A-2, and the first conductive portion 102B-5 formed above the first conductive portion 102A-2 in the figure are connected to the second conductive portion 101B-1 formed on the pixel region 61 or on the inter-pixel separation portion 63, so as to connect the straight sections of the inter-pixel separation portion 63 on which these first conductive portions 102B are formed along the second conductive portion 101A. The second conductive portion 101B-1 is connected, for example, to a negative bias.

[0089] The first conductive part 102B-1 formed to the left of the first conductive part 102A-1 in the figure, the first conductive part 102B-3 formed below the first conductive part 102A-1 in the figure, the first conductive part 102B-6 formed below the first conductive part 102A-2 in the figure, and the first conductive part 102B-7 formed to the right of the first conductive part 102A-2 in the figure are connected to the second conductive part 101B-2 formed on the pixel region 61 or on the inter-pixel separation section 63, so as to connect the straight sections of the inter-pixel separation section 63 on which these first conductive parts 102B are formed along the second conductive part 101A. The second conductive part 101B-2 is connected, for example, to a negative bias.

[0090] Figure 13 shows another example of the arrangement of the first conductive parts connected to the first conductive parts 102A and 102B in Figure 11. Figure 13 shows a side cross-sectional view near the pixel region 61.

[0091] As shown in Figure 13, the second conductive portion 101B connected to the first conductive portion 102B is formed on the pixel region 61 or the inter-pixel separation portion 63 within the insulating film 62, so as to avoid the first conductive portion 102A.

[0092] The second conductive portion 101A, which is connected to the first conductive portion 102A, is formed in a position that overlaps with the first conductive portion 102B in the insulating film 62 in the vertical direction (substrate thickness direction).

[0093] The first conductive portion 102B functions as an electrode that applies a negative bias (negative voltage) to the side surface of the pixel region 61. By applying a negative bias to the side surface of the pixel region 61, pinning on the side surface of the pixel region 61 can be strengthened, and the generation of dark current can be suppressed.

[0094] As described above, the first conductive portion 102A and the first conductive portion 102B may be formed on the same plane or on different planes.

[0095] Figure 14 shows a second modified example of the configuration of the inter-pixel separation section 63. Figure 14 shows a cross-sectional view of the vicinity of the intersection of the inter-pixel separation section 63 as seen from above.

[0096] As shown in Figure 14A, the through-hole H11 constituting the intersection of the inter-pixel separation portion 63 and the trench T1 constituting the straight portion of the inter-pixel separation portion 63 may be formed to be continuous. In this case, an insulating film 103 is formed between the first conductive portion 102A and the first conductive portion 102B.

[0097] As shown in Figure 14B, a through-hole H12, in which the first conductive portion 102A and the insulating film are embedded, may be formed as a part of the straight portion of the inter-pixel separation portion 63. In this case, the intersection portion and the other parts of the straight portion of the inter-pixel separation portion 63 are formed by a trench T1 in which the insulating film 103 or the like is embedded. The through-hole H12 and the trench T1 are formed to be continuous, for example.

[0098] As shown in Figure 14C, a through-hole H13 in which the first conductive portion 102A and the insulating film 103A are embedded may be formed within the pixel region 61. In this case, a grid-like first conductive portion 102B along the inter-pixel separation portion 63 is embedded in the trench T1 that constitutes the inter-pixel separation portion 63. The insulating film 103B is formed between the pixel region 61 and the first conductive portion 102B.

[0099] Figure 15 shows a third modified example of the configuration of the inter-pixel separation section 63. Figure 15 shows a cross-sectional view of the vicinity of the intersection of the inter-pixel separation section 63 as seen from above.

[0100] The first conductive portion 102A formed at the intersection of the inter-pixel separation portion 63 may have a cross shape in cross-sectional view, as shown in Figure 15A, or a rectangular shape, as shown in Figure 15B.

[0101] Figure 16 shows a fourth modified example of the configuration of the inter-pixel separation section 63. The left side of Figure 16 shows a cross-sectional view of the vicinity of the intersection of the inter-pixel separation section 63 as seen from above, the upper right side of Figure 16 shows an example of the A-A' cross-section on the left side of Figure 16, and the lower right side of Figure 16 shows an example of the B-B' cross-section on the left side of Figure 16.

[0102] As shown in Figure 16, a first conductive portion 102 with the same grid shape as the inter-pixel separation portion 63 may be formed within the inter-pixel separation portion 63.

[0103] By making the shape of the first conductive part 102 the same grid shape as the inter-pixel separation part 63, misalignment and contact resistance that occur during the manufacturing process can be reduced, and the number of steps in the manufacturing process can also be reduced.

[0104] Next, with reference to Figures 17 to 19, a method for forming a pixel 2 having a conductive portion according to the first embodiment will be described.

[0105] First, a trench 321 (FFTI) of a predetermined depth is formed by etching or the like, as shown in the center of Figure 17, on the front surface (upper surface in the figure) of the semiconductor substrate 311 shown on the left side of Figure 17.

[0106] Next, as shown on the right side of Figure 17, p-wells 123 are formed by doping p-type impurities into the corner portions of the semiconductor substrate 311 that are in contact with the trench 321 using ion implants or the like. Additionally, contacts 124 are formed directly above the front surface of the semiconductor substrate 311.

[0107] Next, a wiring layer 52 is formed by forming an insulating film over the entire surface of the front side of the semiconductor substrate 311. After the front side process described above is completed, the back side process is carried out.

[0108] In the back surface process, first, as shown on the left side of Figure 18, the back surface (upper surface in the figure) of the semiconductor substrate 311 is polished until the material embedded in the trench 321 is exposed. The semiconductor substrate 311 separated by the trench 321 becomes the pixel region 61.

[0109] Next, as shown in the center of Figure 18, the material in the trench 321 is removed, and an insulating film 312 is formed to cover the bottom and sides of the trench 321 and the entire back surface of the semiconductor substrate 311. This forms a portion of the insulating film 62 on the back surface of the pixel substrate 41 and the insulating film 103 in the inter-pixel separation portion 63.

[0110] Next, as shown on the right side of Figure 18, a resist 313 is formed on the insulating film 62. An opening is formed in the resist 313 to expose the bottom surface of the trench 321 (the upper surface of the contact 124 (the connection surface with the first conductive part 102)).

[0111] Next, as shown on the left side of Figure 19, the insulating film 312 on the bottom surface of the trench 321 is removed.

[0112] Next, the resist 313 is removed, and as shown on the right side of Figure 19, a first conductive portion 102 is formed to fill the trench 321, and a second conductive portion 101 is formed on the insulating film 62. After the first conductive portion 102 and the second conductive portion 101 are formed, the insulating film 62 is further formed, and the color filter 42, inter-pixel light-shielding film 43, on-chip lens 44, etc. shown in Figure 2 are formed on the insulating film 62. By performing the above front-side and back-side processes, a pixel 2 having a conductive portion according to the first embodiment can be formed.

[0113] <3. Second Embodiment> The substrate configuration diagram 20 is a plan view showing the configuration of the pixel substrate 41 according to the second embodiment of this technology. The left side of Figure 20 shows a plan view of the semiconductor layer 51 as seen from the front side, and the right side of Figure 20 shows a plan view of the pixel substrate 41 as seen from the back side.

[0114] As shown on the left side of Figure 20, on the front side of the semiconductor layer 51 within the linear portion of the inter-pixel separation portion 63, a pixel transistor 401 is formed that spans the edges of two adjacent pixel regions 61, in other words, is shared by two adjacent pixel regions 61.

[0115] As shown on the right side of Figure 20, a first conductive portion 102 is formed on the side opposite to the pixel transistor 401 in the substrate thickness direction in the linear portion of the inter-pixel separation portion 63. The first conductive portion 102 is connected to the gate region of the pixel transistor 401 and functions as the gate contact of the pixel transistor 401.

[0116] The second conductive portion 101 is formed, for example, on the pixel region 61 or on the inter-pixel separation portion 63 so as to connect the first conductive portions 102 which are arranged horizontally in the figure, and is connected to a plurality of first conductive portions 102 which are arranged horizontally in the figure.

[0117] Figure 21 is a plan view of the vicinity of the pixel transistor 401 as seen from the front side of the semiconductor layer 51.

[0118] As shown in Figure 21, the pixel transistor 401 is composed of a gate region 421, two source-drain regions 422, and a channel region 423.

[0119] The gate region 421 and the channel region 423 are formed within the inter-pixel separation section 63. The gate region 421 is made of a material such as polysilicon, and the channel region 423 is made of an epitaxial layer or the like. An oxide film 431 is formed between the gate region 421 and the pixel region 61. The channel region 423 is connected to the pixel region 61 and the source-drain region 422 formed within the pixel region 61. In the example shown in Figure 21, in a plan view, the gate region 421 and the channel region 423 overlap in the depth direction (substrate thickness direction), and the cross-sectional shape of the gate region 421 is smaller than the cross-sectional shape of the channel region 423.

[0120] The source-drain region 422 is a region in which the impurity concentration of the pixel region 61 is controlled in an n-type manner. Two source-drain regions 422 are formed one on the front side of two adjacent pixel regions 61, with one acting as the source and the other as the drain.

[0121] Figure 22 is a side cross-sectional view of the pixel substrate 41 near the pixel transistor 401. Part A of Figure 22 shows an example of the A-A' cross-section in Figure 21, and part B of Figure 22 shows an example of the B-B' cross-section in Figure 21.

[0122] As shown in Figure 22A, the channel region 423 is embedded in the pixel isolation portion 63 to a predetermined depth from the front side (upper side in the figure) of the semiconductor layer 51. Below the channel region 423, a gate region 421 is formed with an oxide film 431 in between. Directly below the gate region 421, a first conductive portion 102 is formed. The gate region 421 is connected to, for example, a negative bias via the first conductive portion 102 and the second conductive portion 101.

[0123] In the example shown in Figure 22, a fixed charge film 441 made of aluminum oxide or the like and an insulating film 103 made of silicon oxide or the like are formed between the pixel region 61 and the first conductive portion 102.

[0124] As shown in Figure 22B, in the inter-pixel separation portion 63, an oxide film 431 is embedded in the portion where the pixel transistor 401 and the first conductive portion 102 are not formed, to the same depth as the connection surface between the gate region 421 and the second conductive portion 101, from the front surface of the semiconductor layer 51. In addition, an insulating film 103 is embedded in the same portion, from the back surface of the semiconductor layer 51 to the same depth as the connection surface between the gate region 421 and the second conductive portion 101.

[0125] As described above, by forming at least a portion of the pixel transistor 401 and the first conductive portion 102, which serves as a gate contact connected to the gate region 421, within the inter-pixel isolation portion 63, it becomes unnecessary to form a portion of the pixel transistor 401 and the gate contact on the front side of the semiconductor layer 51. This allows for a wider space to be secured on the front side of the semiconductor layer 51 for arranging other pixel transistors and wiring, thereby improving the degree of freedom in element arrangement. The contact connected to the source-drain region 422 is formed on the front surface of the semiconductor layer 51 (within the wiring layer 52).

[0126] Figure 23 shows an example of the arrangement of the pixel transistors 401. Figure 23 also shows a plan view of the semiconductor layer 51 as seen from the front side.

[0127] As shown in Figure 23, the pixel transistor 401 may be formed on the front side of the semiconductor layer 51 within the intersection of the inter-pixel separation portion 63.

[0128] In detail, for example, as shown in Figure 23A, the gate region 421 of the pixel transistor 401 is formed within the intersection of the inter-pixel separation portion 63, and the source-drain region 422 of the pixel transistor 401 is formed within the linear portion of the inter-pixel separation portion 63.

[0129] Furthermore, for example, as shown in Figure 23B, the gate region 421 of the pixel transistor 401 is formed within or on the intersection of the inter-pixel isolation portion 63 on the surface side of the semiconductor layer 51, and the source-drain region 422 of the pixel transistor 401 is formed at the corner portion of the pixel region 61 that is in contact with the intersection of the inter-pixel isolation portion 63.

[0130] When the pixel transistor 401 is formed within the intersection of the inter-pixel separation portion 63, the first conductive portion 102 is also formed within the intersection of the inter-pixel separation portion 63, and the second conductive portion 101 is formed on the inter-pixel separation portion 63.

[0131] Figure 24 is a side cross-sectional view of the vicinity of the pixel transistor 401 in Figure 23. Figure 24A shows an example of the A-A' cross-section in Figure 23, and Figure 24B shows an example of the C-C' cross-section in Figure 23.

[0132] As shown in Figure 24A, the source-drain region 422 is formed on the upper surface (front surface of the semiconductor layer 51) of the oxide film 431 embedded in the inter-pixel separation portion 63.

[0133] As shown enclosed by the vertical ellipse #1 in section B of Figure 24, only the corner portion of the pixel region 61 is affected by the connection of a negative bias to the first conductive portion 102. Therefore, the effect on the pixel region 61 due to the connection of a negative bias to the first conductive portion 102 is small. Also, as shown enclosed by the horizontal ellipse #2 in section B of Figure 24, the second conductive portion 101 does not come into contact with the pixel region 61. Therefore, the pixel region 61 is not affected by the connection of a negative bias to the second conductive portion 101.

[0134] Figure 25 shows a first modified example of the pixel transistor 401. The left side of Figure 25 shows a plan view of the vicinity of the pixel transistor 401 as seen from the front side of the semiconductor layer 51, and the right side of Figure 24 shows an example of the B-B' cross section on the left side of Figure 25.

[0135] As shown in Figure 25, a groove 423A extending in the direction connecting the two source-drain regions 422 (the direction in which the channel is formed) may be formed on the lower side of the channel region 423 (the side facing the gate region 421). In this case, a protrusion 425 extending along the groove 423A is formed on the upper side (the side facing the channel region 423) as part of the gate region 421.

[0136] By forming a protrusion 425 in the gate region 421, noise in the pixel transistor 401 can be reduced, and it is expected that the performance of amplification transistors and other components that are particularly susceptible to noise will be improved.

[0137] Figure 26 shows a second modified example of the pixel transistor 401.

[0138] As shown in Figure 26, the gate region 421 may not be formed, and the first conductive portion 102 may be in contact with the oxide film 431. In other words, the gate region 421 may be formed from the same material as the first conductive portion 102. This makes it possible to reduce the process of manufacturing the gate region 421.

[0139] Figure 27 shows a third modified example of the pixel transistor 401.

[0140] As shown in Figure 27, the gate region 421 of the pixel transistor 401 may be formed by extending it so that, in a plan view, the gate region 421 of the pixel transistor 401 extends beyond the channel region 423 in the direction of extension of the inter-pixel separation portion 63. In this case, the first conductive portion 102 is formed in a position that does not overlap with the channel region 423 in a plan view.

[0141] In the example shown in Figure 27, the gate region 421 is formed by extending outwards from the lower part of the pixel separation portion 63 in the figure, and the first conductive portion 102 is formed in a position that is shifted downward in the figure from the position where it overlaps with the channel region 423 in a plan view.

[0142] Figure 28 is a side cross-sectional view of the vicinity of the pixel transistor 401 in Figure 27. Part A of Figure 28 shows an example of the A-A' cross-section in Figure 27, and part B of Figure 28 shows an example of the B-B' cross-section in Figure 27.

[0143] The configuration of the side cross-section A in Figure 28 is the same as the configuration of the side cross-section A in Figure 23, as explained with reference to Figure 23.

[0144] As shown in Figure 28B, the gate region 421 is formed by extending to the right in the figure along the extension direction of the inter-pixel separation portion 63. The first conductive portion 102 is not connected to the gate region 421 at a position below the channel region 423, but rather at a position shifted to the right in the figure from the position below the channel region 423.

[0145] Figure 29 shows a fourth modified example of the pixel transistor 401. Figure 29 shows an inter-pixel separation portion 63 in the same cross-sectional direction as the inter-pixel separation portion 63 shown in Figure 28.

[0146] The gate region 421 may not be formed within the inter-pixel isolation portion 63, but rather on the inter-pixel isolation portion 63 on the front side of the semiconductor layer 51, as shown in Figure 29A. In this case, an insulating film 103 is embedded in the portion of the inter-pixel isolation portion 63 where the pixel transistor 401 and the first conductive portion 102 are not formed.

[0147] As shown in Figure 29B, the gate region 421 is formed by extending to the right in the figure along the stretching direction of the inter-pixel separation portion 63. An oxide film 431 is formed between the gate region 421 and the channel region 423, and between the gate region 421 and the insulating film 103.

[0148] The first conductive portion 102 is formed from the back surface of the semiconductor layer 51, penetrating the oxide film 431 to a depth that reaches the gate region 421, and is connected to the gate region 421. The first conductive portion 102 is not connected to the gate region 421 at a position on the channel region 423, but rather at a position shifted from the position on the channel region 423 in the direction of extension of the gate region 421 (to the right in the figure) to the gate region 421.

[0149] Figures 30 and 31 show a fifth modified example of the pixel transistor 401. Figure 30 shows an inter-pixel separation portion 63 in the same cross-sectional direction as the inter-pixel separation portion 63 shown in Figure 28A, and Figure 31 shows an inter-pixel separation portion 63 in the same cross-sectional direction as the inter-pixel separation portion 63 shown in Figure 28B.

[0150] As shown in Figure 30, the gate region 421 may be formed both within the inter-pixel isolation portion 63 and on the inter-pixel isolation portion 63 on the front side of the semiconductor layer 51. In this case, an insulating film 103 is embedded in the portion of the inter-pixel isolation portion 63 where the pixel transistor 401 and the first conductive portion 102 are not formed.

[0151] As shown in Figure 31A, the gate region 421A formed within the inter-pixel separation portion 63 is formed extending to the right in the figure along the stretching direction of the inter-pixel separation portion 63. Similarly, the gate region 421B formed on the inter-pixel separation portion 63 on the front side of the semiconductor layer 51 is formed extending to the right in the figure along the stretching direction of the inter-pixel separation portion 63, just like the gate region 421A. An oxide film 431 is formed between the gate region 421A and the channel region 423, between the gate region 421B and the channel region 423, and between the gate region 421A and the gate region 421B.

[0152] The first conductive portion 102 is formed from the back surface of the semiconductor layer 51, penetrating through the gate region 421A to a depth that reaches the gate region 421B, and is connected to both the gate region 421A and the gate region 421B. The first conductive portion 102 is connected to the gate regions 421A and 421B at a position away from the channel region 423 in the direction of extension of the gate regions 421A and 421B (to the right in the figure) so as not to penetrate the channel region 423.

[0153] As shown in Figure 31B, the gate region 421 may be formed to have a U-shape in cross-sectional view, sandwiching the channel region 423. The gate region 421 has a portion formed within the inter-pixel isolation portion 63 and a portion formed on the inter-pixel isolation portion 63 on the front side of the semiconductor layer 51, extending beyond the inter-pixel isolation portion 63. An oxide film 431 is formed between the gate region 421 and the channel region 423.

[0154] The first conductive portion 102 is formed from the back surface of the semiconductor layer 51 to a depth that reaches the portion of the gate region 421 that protrudes from the interpixel separation portion 63, and is connected to the gate region 421. The first conductive portion 102 is connected to the gate region 421 at a position away from the channel region 423 so as not to penetrate the channel region 423.

[0155] As shown in Figure 31C, the gate region 421 may be formed to have a rectangular frame shape in cross-sectional view that surrounds the channel region 423. The gate region 421 has a portion formed within the inter-pixel isolation portion 63 and a portion formed on the inter-pixel isolation portion 63 on the front side of the semiconductor layer 51 that extends beyond the inter-pixel isolation portion 63. An oxide film 431 is formed between the gate region 421 and the channel region 423.

[0156] The first conductive portion 102 is formed from the back surface of the semiconductor layer 51 to a depth that reaches the portion of the gate region 421 that protrudes from the interpixel separation portion 63, and is connected to the gate region 421. The first conductive portion 102 is connected to the gate region 421 at a position away from the channel region 423 so as not to penetrate the channel region 423.

[0157] In this way, by forming the gate region 421 both within the inter-pixel isolation portion 63 and on the inter-pixel isolation portion 63 on the front side of the semiconductor layer 51, it becomes possible to improve the modulation power of the pixel transistor 401.

[0158] Pixel Formation Method Next, with reference to Figures 32 to 35, a method for forming a pixel 2 having a conductive portion and a pixel transistor 401 according to the second embodiment will be described. In Figures 32, 33, the upper part of Figure 34, and the middle part of Figure 34, the left side shows a side cross-sectional view of the pixel substrate 41 near the pixel transistor 401, and the right side shows a plan view of the semiconductor layer 51 as seen from the front side. Also, the middle part of Figure 34 and Figure 35 show a side cross-sectional view of the pixel substrate 41 near the pixel transistor 401.

[0159] Here, it is assumed that polysilicon 461 is embedded on the back side of the trench 321 which forms the inter-pixel separation portion 63, and silicon oxide 462 is embedded on the front side of the trench 321.

[0160] First, as shown in the upper part of Figure 32, the silicon oxide 462 in the trench 321 is etched back to a predetermined depth from the front side (upper side in the figure) of the semiconductor layer 51, thereby forming a groove that will be filled with the oxide film 431.

[0161] Next, as shown in the middle section of Figure 32, a gate region 421 is formed directly above the silicon oxide 462 in the trench 321.

[0162] Next, an oxide film 431 is formed to fill the groove in the trench 321 and then flattened. As shown in the lower part of Figure 32, the oxide film 431 is etched back to a depth where the gate region 421 is not exposed, thereby forming an opening for the channel region 423.

[0163] Next, as shown in the upper part of Figure 33, an epitaxial layer 471 is formed by embedding silicon in the opening using epitaxial growth.

[0164] Next, as shown in the middle section of Figure 33, channel regions 423 are formed by doping the epitaxial layer 471 with impurities using an ion implant or the like.

[0165] Next, as shown in the lower part of Figure 33, the source-drain region 422 is formed by doping the portion of the pixel region 61 in contact with the channel of the channel region 423 with n-type impurities using an ion implant or the like.

[0166] Next, as shown in the upper part of Figure 34, contacts connected to the source-drain region 422 are formed. After the above front-side processes are completed, the back-side processes are carried out. In the back-side processes, the first conductive portion 102 is formed in the region within the inter-pixel separation portion 63 (trench 321) that is on the opposite side of the pixel transistor 401 in the substrate thickness direction, as shown by the dashed line enclosed in the right side of the middle part of Figure 34.

[0167] In the back-side process, first, the polysilicon 461 in the trench 321 is removed, and silicon oxide 462 or the like is embedded in the trench 321 from the back side of the semiconductor layer 51 to form the insulating film 103 in the inter-pixel separation portion 63. Then, as shown in the lower part of Figure 34, the insulating film 103 is etched back to a depth in which the gate region 421 is exposed, thereby forming an opening in the trench 321 for forming the first conductive portion 102.

[0168] Next, as shown in the upper part of Figure 35, a fixed charge film 441 and an insulating film 465 are formed to cover the entire side surface of the opening for forming the first conductive portion 102 and the entire back surface of the semiconductor layer 51. This forms a portion of the insulating film 62 on the back surface of the pixel substrate 41, and an insulating film 103 between the pixel region 61 and the first conductive portion 102.

[0169] Next, as shown in the middle section of Figure 25, the first conductive portion 102 is formed to fill the opening, and the second conductive portion 101 is formed on the insulating film 62.

[0170] Next, as shown in the lower part of Figure 25, an insulating film 62 is further formed to cover the entire back surface of the semiconductor layer 51, and a color filter 42, an inter-pixel light-shielding film 43, an on-chip lens 44, etc. are formed on the insulating film 62. By performing the above front surface and back surface processes, a pixel 2 having a conductive part and a pixel transistor 401 according to the second embodiment can be formed.

[0171] The second conductive portion 101 is connected, for example, to a metal wiring 485 of a negative bias application portion 481 provided in the peripheral circuit portion around the pixel array portion 3. As shown by the arrow in the lower part of Figure 25, the negative bias application portion 481 can apply a negative bias to the gate region 421 of the pixel transistor 401 via the metal wiring 485, the second conductive portion 101, and the first conductive portion 102.

[0172] <4. Third Embodiment> The substrate configuration diagram 36 is a diagram showing the configuration of the pixel substrate 41 according to the third embodiment of the present technology. The left side of Figure 36 shows a side cross-sectional view of the pixel substrate 41 near the inter-pixel separation portion 63, and the right side of Figure 36 shows an example of the A-A' cross-section on the left side of Figure 36.

[0173] As shown on the left side of Figure 36, the first conductive portion 102 formed within the inter-pixel separation portion 63 is connected to a p-well 501 formed at a position deeper than the front surface of the semiconductor layer 51 within the inter-pixel separation portion 63.

[0174] In detail, the p-well 501 is formed on the bottom surface (top surface in the figure) of the first trench 561, which is formed on the front side of the semiconductor layer 51 so that its shape when viewed from the front surface is lattice-like. An etching stopper film is formed between the p-well 501 and the bottom surface of the first trench 561, and the p-well 501 is connected to the pixel region 61 on the side surface of the first trench 561. An insulating film 503 is embedded inside the first trench 561.

[0175] The first conductive portion 102 is formed in a second trench 571, which is formed on the back side of the semiconductor layer 51, such that its shape when viewed from the back side is lattice-like. The first trench 561 and the second trench 571 are connected on the front side of the semiconductor layer 51. That is, the inter-pixel separation portion 63 is constructed by embedding an insulating film or the like in the first trench 561 and the second trench 571. The inner diameter of the bottom surface of the second trench 571 (the opening surface of the bottom surface of the first trench) is narrower than the inner diameter of the bottom surface of the first trench 561. A p-well 501 is formed so as to straddle the resulting step portion (bottom surface of the first trench 561).

[0176] As shown on the right side of Figure 36, the p-well 501 is formed to span, for example, the corner portions of four pixel regions 61 that are in contact with the intersection of the inter-pixel separation portion 63 in which the p-well 501 is formed. In other words, the p-well 501 is shared by the four pixel regions 61.

[0177] In the pixel substrate 41, the FD is formed near the front surface of the semiconductor layer 51. By forming the p-well 501 at a position deeper than the front surface of the semiconductor layer 51 within the inter-pixel separation portion 63, the distance between the p-well 501 and the FD can be secured, making it possible to mitigate the electric field between the p-well 501 and the FD.

[0178] Figure 37 shows an example of the shape of the pixel region 61. Figure 37 shows a pixel array 3 with the same cross-sectional direction as the pixel array 3 shown on the right side of Figure 36.

[0179] As shown in Figure 37A, the pixel region 61 in which the p-well 501 is formed in part may have a rectangular shape in plan view.

[0180] As shown in Figure 37B, a single pixel 2 may have two pixel regions 61A and 61B that share the same p-well 501. In this case, the inter-pixel separation portion 63 has a protruding portion that electrically separates a portion between pixel region 61A and pixel region 61B.

[0181] Figure 38 shows a first modified example of the inter-pixel separation section 63 in which the p-well 501 is formed. The left side of Figure 38 shows a side cross-sectional view of the pixel substrate 41 near the inter-pixel separation section 63, the upper right side of Figure 38 shows an example of the A-A' cross-section on the left side of Figure 38, and the lower right side of Figure 38 shows an example of the B-B' cross-section on the left side of Figure 38.

[0182] As shown in the lower part of Figure 38, the FD 502 may be formed below the p-well 501 formed in the inter-pixel separation section 63.

[0183] In detail, the FD 502 is formed so as to overlap the p-well 501 in the substrate thickness direction in a plan view, and is formed at a shallower position from the front surface of the semiconductor layer 51 than the p-well 501 within the first trench 561 (inter-pixel separation portion 63). An insulating film 503 is formed between the p-well 501 and the FD 502. The FD 502 is connected to the pixel region 61 on the side of the first trench 561, and the lower surface of the FD 502 (the surface facing the front surface of the semiconductor layer 51) is connected to a contact 504 formed in the wiring layer 52.

[0184] As shown on the right side of Figure 38, the FD 502 is formed within the same intersection as the intersection of the inter-pixel separation portion 63 in which the p-well 501 is formed, and is formed to span the corner portions of the four pixel regions 61 that are in contact with that intersection. In other words, the FD 502 is shared by the four pixel regions 61.

[0185] Figure 39 shows a second modified example of the inter-pixel separation section 63 in which the p-well 501 is formed. The left side of Figure 39 shows a side cross-sectional view of the pixel substrate 41 near the inter-pixel separation section 63, the upper right side of Figure 39 shows an example of the A-A' cross-section on the left side of Figure 39, and the lower right side of Figure 39 shows an example of the B-B' cross-section on the left side of Figure 39.

[0186] As shown on the left side of Figure 39, a depletion layer 505 may be formed between the p-well 501 and the FD 502. The depletion layer 505 in Figure 39 is composed of depleted polysilicon or the like. For example, the p-well 501, the depletion layer 505, and the FD 502 are formed by doping polysilicon, which is an insulating film embedded in the first trench 561, with p-type or n-type impurities at different depths using ion implants or the like to make it conductive.

[0187] When polysilicon is made conductive to form p-wells 501 and FD 502, as shown on the right side of Figure 39, on the front side of the semiconductor layer 51, each pixel region 61 is separated by an inter-pixel separation portion 63 in which polysilicon as an insulating film is embedded.

[0188] Figure 40 shows a third modified example of the inter-pixel separation section 63 in which the p-well 501 is formed. The left side of Figure 40 shows a side cross-sectional view of the pixel substrate 41 near the inter-pixel separation section 63, the upper right side of Figure 40 shows an example of the A-A' cross-section on the left side of Figure 40, and the lower right side of Figure 40 shows an example of the B-B' cross-section on the left side of Figure 40.

[0189] In Figure 40, a depletion layer 505 is formed between the p-well 501 and the FD 502, similar to the modified example described with reference to Figure 39. On the other hand, in the example of Figure 40, the first trench 561 is not formed on the front side of the semiconductor layer 51. Therefore, for example, the p-well 501, the depletion layer 505, and the FD 502 are formed by doping the semiconductor layer 51 with p-type or n-type impurities at different depths from the front side using ion implants or the like.

[0190] When the semiconductor layer 51 is doped with impurities to form p-wells 501 and FD 502, as shown on the right side of Figure 40, on the front side of the semiconductor layer 51, each pixel region 61 is separated by an inter-pixel separation portion 63 formed, for example, by doping the semiconductor layer 51 with impurities.

[0191] Figure 41 shows a fourth modified example of the inter-pixel separation section 63 in which the p-well 501 is formed. The left side of Figure 41 shows a side cross-sectional view of the pixel substrate 41 near the inter-pixel separation section 63, the upper right side of Figure 41 shows an example of the A-A' cross-section on the left side of Figure 41, and the lower right side of Figure 41 shows an example of the B-B' cross-section on the left side of Figure 41.

[0192] As shown on the left side of Figure 41, the FD 511 may be formed on the front side within the pixel region 61. In this case, the FD 511 is connected to a contact 513 formed in the wiring layer 52 via a contact formed directly above the front surface of the semiconductor layer 51 so as to overlap with the p-well 501 in the substrate thickness direction in a plan view.

[0193] Furthermore, the FD511 is formed at a position shallower from the surface of the semiconductor layer 51 than the p-well 501 within the semiconductor layer 51.

[0194] As shown on the right side of Figure 41, the contact 512 is formed directly above the same intersection of the inter-pixel separation section 63 where the p-well 501 is formed, and is connected across the FD 521 formed at the corners of the four pixel regions 61 that are in contact with that intersection. In other words, each FD 521 is connected to the other FD 521 via the contact 512.

[0195] Figure 42 shows an example of the arrangement of the first conductive portion 102 when the photodetector 1 is constructed by stacking a pixel substrate 41 and a transistor substrate 201.

[0196] In the following explanation, we will focus on the 4x4 pixel regions 61-1 to 61-16, which are denoted by reference numerals, among the multiple pixel regions 61 of the pixel array 3.

[0197] As shown in Figure 42, a first conductive portion 102A is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-2, 61-3, 61-6, and 61-7, and this first conductive portion 102A is connected to a p-well 501 formed within the intersection. Similarly, a first conductive portion 102A is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-10, 61-11, 61-14, and 61-15, and this first conductive portion 102A is connected to a p-well 501 formed within the intersection.

[0198] On the other hand, a first conductive portion 102B is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-5, 61-6, 61-9, and 61-10, and this first conductive portion 102B is connected to a well (well contact) 521 formed on the transistor substrate 201. Furthermore, a first conductive portion 102B is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-7, 61-8, 61-11, and 61-12, and this first conductive portion 102B is connected to a well 521 formed on the transistor substrate 201.

[0199] Figure 43 is a side cross-sectional view of the photodetector 1 near the pixel region 61-6. Figure 43 shows an example of the A-A' cross-section in Figure 42.

[0200] As shown in Figure 43, a transistor substrate 201, which consists of a semiconductor region (semiconductor layer) 227 and a wiring layer 228, is bonded (stacked) on the front surface of the pixel substrate 41.

[0201] In the example shown in Figure 43A, one end of the first conductive portion 102A is connected to a p-well 501 formed within the inter-pixel separation portion 63, and the other end is connected to a second conductive portion 101A formed on the pixel region 61 within the insulating film 62 or on the inter-pixel separation portion 63, avoiding the first conductive portion 102B.

[0202] One end of the first conductive portion 102B is connected to a well 531 formed on the front side of the semiconductor layer 51 within the inter-pixel separation portion 63, and the other end is connected to a second conductive portion 101B formed in the insulating film 62 at a position that overlaps with the first conductive portion 102A in the vertical direction (substrate thickness direction). Since the insulating film 532 is formed between the well 531 and the pixel region 61, the well 531 is not connected to the pixel region 61.

[0203] Well 531 is connected to metal wiring 533 in the wiring layer 228 of the transistor substrate 201 via a contact 534 that penetrates the wiring layer 52 of the pixel substrate 41 and the semiconductor region 227 of the transistor substrate 201. The metal wiring 533 is connected to well 521 in the semiconductor region 227 of the transistor substrate 201 via a contact 535. In other words, one end of the first conductive portion 102B is connected to well 521 via well 531, contact 534, metal wiring 533, and contact 535.

[0204] In addition, in the example of Figure 43B, one end of the first conductive portion 102A is connected to the p-well 501 formed in the inter-pixel separation portion 63, and the other end is connected to the second conductive portion 101A, which is formed in the same manner as in the example of Figure 43A.

[0205] The first conductive portion 102B is formed to a depth that extends from the back surface of the semiconductor layer 51 to a well 521 formed in the wiring layer 228 of the transistor substrate 201, and one end of the first conductive portion 102B is directly connected to the well 521. The other end of the first conductive portion 102B is connected to a second conductive portion 101B, which is formed in the same manner as in example A of Figure 43.

[0206] In this way, by connecting the first conductive part 102B to the well 521 of the transistor substrate 201, it becomes possible to extract the potential of the well 521 in the transistor substrate 201 to the back side of the semiconductor layer 51. Furthermore, it becomes possible to reduce the number of contacts and metal wiring formed in the wiring layer 228 of the transistor substrate 201.

[0207] Figure 44 shows another example of the arrangement of the first conductive portion 102 when the photodetector element 1 is constructed by stacking a pixel substrate 41 and a transistor substrate 201. Among the configurations shown in Figure 44, the same reference numerals are used for components that are the same as those in Figure 42. Repetitive explanations are omitted as appropriate.

[0208] As shown in Figure 44, a first conductive portion 102C is formed within the intersection of the inter-pixel separation portion 63 that contacts pixel regions 61-1, 61-2 and other pixel regions 61 other than pixel regions 61-1 to 61-16, and this first conductive portion 102C is connected to a dummy well (dummy well contact) 541 formed within the intersection. A first conductive portion 102C is also formed within the intersection of the inter-pixel separation portion 63 that contacts pixel regions 61-3, 61-4 and other pixel regions 61 other than pixel regions 61-1 to 61-16, and this first conductive portion 102C is connected to a dummy well 541 formed within the intersection.

[0209] A first conductive portion 102C is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-13, 61-14 and other pixel regions 61 other than pixel regions 61-1 to 61-16, and this first conductive portion 102C is connected to a dummy well 541 formed within the intersection. A first conductive portion 102C is formed within the intersection of the inter-pixel separation portion 63 that is in contact with pixel regions 61-15, 61-16 and other pixel regions 61 other than pixel regions 61-1 to 61-16, and this first conductive portion 102C is connected to a dummy well 541 formed within the intersection.

[0210] As shown in Figure 44, by arranging the first conductive portion 102, one pair of diagonals of all pixel regions 61 will be in contact with the intersection of the inter-pixel separation portion 63 where the first conductive portion 102 is formed. This maintains the optical symmetry between the pixel regions 61.

[0211] Figure 45 is a side cross-sectional view of the photodetector 1 near pixel regions 61-3 and 61-6. Figure 45 shows an example of the A-A' cross-section in Figure 44. Among the components shown in Figure 45, components identical to those in component A of Figure 43 are denoted by the same reference numerals. Repetitive explanations are omitted as appropriate.

[0212] One end of the first conductive portion 102C is connected to a dummy well 541 formed on the front side of the semiconductor layer 51 within the inter-pixel separation portion 63, and the other end is connected to the second conductive portion 101B. Since an insulating film 542 is formed between the dummy well 541 and the pixel region 61, the dummy well 541 is not connected to the pixel region 61.

[0213] Figures 46 and 47 show examples of the arrangement of the second conductive portion 101. Figures 46 and 47 show a plan view of the semiconductor layer 51 as seen from above.

[0214] As shown in Figure 46A, on the back surface of the semiconductor layer 51, the second conductive portion 101 is formed extending in the vertical direction in the figure, for example, along the straight portion of the inter-pixel separation portion 63 between adjacent pixel regions 61 in the horizontal direction in the figure. In the example of Figure 46A, the second conductive portions 101-1 and 101-3 are connected to the first conductive portion 102B, and the second conductive portion 101-2 is connected to the first conductive portion 102A.

[0215] As shown in Figure 46B, on the back surface of the semiconductor layer 51, the second conductive portion 101 is formed extending in the lateral direction in the figure, for example, along the straight portion of the inter-pixel separation portion 63 between adjacent pixel regions 61 in the vertical direction in the figure. In the example of Figure 46B, the second conductive portions 101-1' and 101-3' are connected to the first conductive portion 102A, and the second conductive portion 101-2' is connected to the first conductive portion 102B.

[0216] As shown in Figure 47, on the back surface of the semiconductor layer 51, for example, the second conductive portion 101-2 connected to the first conductive portion 102A is formed extending in the vertical direction in the figure, and the second conductive portion 101-2' connected to the first conductive portion 102B is formed extending in the horizontal direction in the figure. The second conductive portion 101-2 is formed along the inter-pixel separation portion 63, while the second conductive portion 101-2' is formed to cross the pixel region 61.

[0217] The second conductive portion 101 connected to the p-well 501 formed in the inter-pixel separation portion 63 and the second conductive portion 101 connected to the well 521 in the transistor substrate 201 may be formed on the same plane as shown in Figure 46, or they may be formed on different planes as shown in Figure 47.

[0218] Next, with reference to Figures 48 and 49, a method for forming a pixel 2 having a p-well 501 according to the third embodiment will be described.

[0219] First, a first trench 561 (STI: Shallow Trench Isolation) of a predetermined depth is formed by etching or the like, as shown second from the left in Figure 48, on the front surface (upper surface in the figure) of the semiconductor substrate 311, as shown first from the left in Figure 48.

[0220] Next, as shown in the third image from the left in Figure 48, an etching stopper film 562 is formed on the bottom surface of the first trench 561, and a p-well 501 is formed on the etching stopper film 562 inside the first trench 561.

[0221] Next, as shown in the fourth position from the left in Figure 48, an insulating film 503 is formed to fill the first trench 561. After the above front-side processes are carried out, the back-side processes are performed.

[0222] In the back surface process, first, the back surface (upper surface in the figure) of the semiconductor substrate 331, as shown first from the left in Figure 49, is polished. Next, as shown second from the left in Figure 49, a second trench 571 is formed from the back surface of the semiconductor substrate 331 to a depth that reaches the etching stopper film 562 in the first trench 561, by etching or the like.

[0223] Next, as shown in the third image from the left in Figure 49, an insulating film 572 is formed to cover the entire surface of the side of the second trench 571 and the back surface of the semiconductor substrate 311 (semiconductor layer 51). This forms a portion of the insulating film 62 on the back surface of the pixel substrate 41 and an insulating film 103 within the inter-pixel separation portion 63.

[0224] Next, as shown fourth from the left in Figure 49, a resist 573 is formed on the insulating film 62. An opening is formed in the resist 573 to expose the upper surface of the p-well 501 (the connection surface with the first conductive portion 102). Next, the etching stopper film on the bottom surface of the second trench 571 is removed.

[0225] Next, the resist 573 is removed, and as shown fifth from the left in Figure 49, the first conductive portion 102 is formed to fill the second trench 571, and the second conductive portion 101 is formed on the insulating film 62. After the first conductive portion 102 and the second conductive portion 101 are formed, the insulating film 62 is further formed, and the color filter 42, inter-pixel light-shielding film 43, on-chip lens 44, etc. shown in Figure 2 are formed on the insulating film 62. By performing the above front-side and back-side processes, a pixel 2 having a p-well 501 according to the third embodiment can be formed.

[0226] Referring to Figures 50 and 51, a method for forming a pixel 2 having a p-well 501 and an FD 503 according to a third embodiment will be described.

[0227] First, a first trench 561 of a predetermined depth is formed by etching or the like, as shown second from the left in Figure 50, on the front surface (upper surface in the figure) of the semiconductor substrate 311, as shown first from the left in Figure 50.

[0228] Next, as shown in the third image from the left in Figure 50, an etching stopper film 562 is formed on the bottom surface of the first trench 561, and a p-well 501 is formed on the etching stopper film 562 inside the first trench 561.

[0229] Next, as shown in the fourth image from the left in Figure 50, an insulating film 503 is formed to fill the first trench 561. An opening for forming the FD 502 is formed in the insulating film 503.

[0230] Next, as shown in the fifth image from the left in Figure 50, FD502 is formed by embedding, for example, conductive polysilicon into the opening. After the above front-side processes are completed, the back-side processes are carried out.

[0231] In the back surface process, first, the back surface (upper surface in the figure) of the semiconductor substrate 331, as shown first from the left in Figure 51, is polished. Next, as shown second from the left in Figure 51, a second trench 571 is formed from the back surface of the semiconductor substrate 331 to a depth that reaches the etching stopper film 562 in the first trench 561, by etching or the like.

[0232] Next, as shown in the third image from the left in Figure 51, an insulating film 572 is formed to cover the entire surface of the side of the second trench 571 and the back surface of the semiconductor substrate 311. This forms a portion of the insulating film 62 on the back surface of the pixel substrate 41 and an insulating film 103 within the inter-pixel separation portion 63.

[0233] Next, as shown fourth from the left in Figure 51, a resist 573 is formed on the insulating film 62. An opening is formed in the resist 573 to expose the upper surface of the p-well 501 (the connection surface with the first conductive portion 102). Next, the etching stopper film on the bottom surface of the second trench 571 is removed.

[0234] Next, the resist 573 is removed, and as shown fifth from the left in Figure 51, the first conductive portion 102 is formed to fill the second trench 571, and the second conductive portion 101 is formed on the insulating film 62. After the first conductive portion 102 and the second conductive portion 101 are formed, the insulating film 62 is further formed, and the color filter 42, inter-pixel light-shielding film 43, on-chip lens 44, etc. shown in Figure 2 are formed on the insulating film 62. By performing the above front-side and back-side processes, a pixel 2 having a p-well 501 and FD 502 according to the third embodiment can be formed.

[0235] <5. Fourth Embodiment> Figure 52 is a diagram showing an example of the configuration of pixel 2 according to the fourth embodiment of the present technology.

[0236] As shown in Figure 52, the pixel 2 has a structure such that, for example, a square-shaped pixel region 61 is surrounded by an inter-pixel separation portion 63.

[0237] In the center of the pixel region 61, the gate electrode of the transfer transistor 602 is embedded from the front side of the pixel region 61. A p-well 603, which will be the contact area for the anode of pixel 2, is formed in the lower left side of the pixel region 61 in the diagram. An FD 604 is formed in the upper right side of pixel 2 in the diagram, as part of the pixel region 61 and the inter-pixel separation area 63.

[0238] The p-wells 603 and FD 604 are formed on the front side of the semiconductor layer 51. The transfer transistor 602, p-wells 603, and FD 604 are connected to contacts (within the wiring layer 52) formed on the front surface of the semiconductor layer 51.

[0239] The inter-pixel isolation portion 63 is constructed, for example, by embedding an insulating film in a trench that penetrates from the front surface to the back surface of the semiconductor layer 51. Electrodes 611A are formed in the straight section of the inter-pixel isolation portion 63 that is in contact with the upper side surface of the pixel region 61 in the figure, and electrodes 611B are formed in the straight section of the inter-pixel isolation portion 63 that is in contact with the right side surface of the pixel region 61 in the figure. Electrode 611C is formed in the straight section of the inter-pixel isolation portion 63 that is in contact with the lower side surface of the pixel region 61 in the figure, and electrode 611D is formed in the straight section of the inter-pixel isolation portion 63 that is in contact with the left side surface of the pixel region 61 in the figure.

[0240] The transfer transistor 602 modulates the potential of the pixel region 61, thereby transferring the charge accumulated in the photodiode 601 within the pixel region 61 by photoelectric conversion to the FD 604. The electrodes 611A to 611D are conductive parts formed of, for example, a transparent oxide film, to which an arbitrary voltage can be applied to the side surface of the pixel region 61. By applying an arbitrary voltage to the side surface of the pixel region 61 and modulating the potential of the portion of the pixel region 61 near the electrodes, the electrodes 611A to 611D can assist the transfer transistor 602 in transferring the charge to the FD 604.

[0241] The electrodes 611A to 611D assist in charge transfer, thereby improving the charge transfer capability of the pixel 2. Furthermore, the assistance of electrodes 611A to 611D in charge transfer allows for the placement of the transfer transistor 602 in a location other than the center of the pixel region 61, thereby improving the robustness of the pixel design. In addition, a wider distance can be secured between the transfer transistor 602 and the FD 604, which allows for the mitigation of the electric field between the transfer transistor 602 and the FD 604.

[0242] Figure 53 is a schematic diagram showing the behavior of light incident on the pixel region 61.

[0243] When the inter-pixel separation section 63 is formed of an opaque material, as shown in Figure 53A, some of the light incident obliquely on the inter-pixel separation section 63 is absorbed by the inter-pixel separation section 63 and does not reach the photodiode 601.

[0244] When the inter-pixel separation portion 63 is formed of a transparent material, as shown in Figure 53B, light incident obliquely on the inter-pixel separation portion 63 passes through the inter-pixel separation portion 63 and enters the photodiode 601. In the fourth embodiment, electrodes 611A to 611D made of a transparent oxide film are formed inside the inter-pixel separation portion 63 of the pixel 2, so in particular, light incident on electrodes 611A to 611D passes through electrodes 611A to 611D and enters the photodiode 601.

[0245] In this way, by forming electrodes 611A to 611D with a transparent oxide film within the inter-pixel separation section 63, it is possible to increase the amount of light incident on the photodiode 601 and improve the quantization efficiency of the pixel 2.

[0246] Figure 54 shows an example of the voltage applied by each electrode during charge transfer. Below, we will focus on the four photodiodes 601-1 to 601-4 that share the same FD604.

[0247] In Figure 54, the photodiode 601-1 located on the lower left side of the figure, the photodiode 601-2 located on the upper left side of the figure, the photodiode 601-3 located on the upper right side of the figure, and the photodiode 601-4 located on the lower right side of the figure all share the FD604 located in the center of the figure.

[0248] In the example shown in Figure 54, the pixel 2 is configured such that four electrodes can apply voltage to one photodiode 601 (pixel region 61). In other words, four electrodes are formed for the inter-pixel separation portion 63 that defines one pixel region 61 (pixel 2). Specifically, electrode 611A is formed between photodiode 601-1 and photodiode 601-2, electrode 611B is formed between photodiode 601-1 and photodiode 601-4. Electrode 611C is formed below photodiode 601-1 in the figure, and electrode 611D is formed to the left of photodiode 601-1 in the figure. Electrode 611E is formed to the left of photodiode 601-2 in the figure, and electrode 611F is formed above photodiode 601-2 in the figure. Electrode 611G is formed between photodiode 601-2 and photodiode 601-3.

[0249] Electrode 611H is formed above photodiode 601-3 in the figure, and electrode 611I is formed to the right of photodiode 601-3 in the figure. Electrode 611J is formed between photodiode 601-3 and photodiode 601-4. Electrode 611K is formed to the right of photodiode 601-4 in the figure, and electrode 611L is formed below photodiode 601-4 in the figure.

[0250] In the following, electrodes 611A to 611L will simply be referred to as electrode 611 unless there is a need to distinguish between them.

[0251] Here, electrodes 611A, 611B, 611G, and 611J are electrodes formed closer to FD604 than the other electrodes 611, and are also closer to FD604 than the transfer transistor 602. Electrodes 611 other than electrodes 611A, 611B, 611G, and 611J are electrodes formed further from FD604 than the transfer transistor 602.

[0252] During charge transfer of photodiode 601-1, a positive bias is applied only by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is connected by electrodes 611A and 611B, and a negative bias is applied by the other electrodes 611. As a result, as shown by the white arrows in Figure 54, a transfer path is formed from the vicinity of electrodes 611C and 611D, to transfer transistor 602-1, and a transfer path is formed from transfer transistor 602-1 through the vicinity of electrodes 611A and 611B, to FD604.

[0253] Figure 55 is a diagram illustrating the formation surface of the electrode 611 in the semiconductor layer 51. Part A of Figure 55 shows an example of the A-A' cross section in Figure 54, and part B of Figure 55 shows an example of the B-B' cross section in Figure 54.

[0254] As shown in Figure 55A, electrodes 611A and 611B, which apply a positive bias during charge transfer, are formed on the front side (upper side in the figure) of the semiconductor layer 51 within the inter-pixel separation section 63. In this case, the gate contact 631 for applying voltage to the transfer transistor 602-1, the contact 632 for applying voltage to electrode 611A, and the contact 633 for applying voltage to electrode 611B are formed on the front surface of the semiconductor layer 51, that is, within the wiring layer 52.

[0255] When a positive bias is applied to electrodes 611A and 611B formed on the front side of the semiconductor layer 51, the shallow electric field of the photodiode 601-1 is strengthened, making it easier for charge to be transferred.

[0256] Furthermore, electrodes 611G and 611J are formed on the front side of the semiconductor layer 51 within the inter-pixel separation section 63, similar to electrodes 611A and 611B.

[0257] On the other hand, as shown in Figure 55B, electrodes 611C and 611D, which apply a negative bias during charge transfer, are formed on the back side (lower side in the figure) of the semiconductor layer 51 within the inter-pixel separation section 63. In this case, contacts 634 for applying voltage to electrode 611C and contacts 635 for applying voltage to electrode 611D are formed on the back side of the semiconductor layer 51, that is, within the insulating film 62.

[0258] The electrodes 611C and 611D formed on the back side of the semiconductor layer 51 within the inter-pixel separation portion 63 correspond to the first conductive portion 102, and the contacts 634 and 635 formed on the back surface of the semiconductor layer 51 correspond to the second conductive portion 101.

[0259] When a negative bias is applied to electrodes 611C and 611D formed on the back side of the semiconductor layer 51, the deep electric field of the photodiode 601-1 is strengthened, making it easier for charge to be transferred.

[0260] Furthermore, electrodes 611E, 611F, 611H, 611I, 611K, and 611L are formed on the back side of the semiconductor layer 51 within the inter-pixel separation section 63, similar to electrodes 611C and 611D.

[0261] Figures 56 and 57 show examples of voltages applied to each electrode 611 during charge discharge, charge accumulation, and charge transfer.

[0262] As shown on the left side of Figure 56, during charge discharge, a positive bias is applied by all transfer transistors 602-1 to 602-4. A positive bias is applied by electrodes 611A, 611B, 611G, and 611J, while a negative bias is applied by the other electrodes 611.

[0263] As shown on the right side of Figure 56, during charge accumulation, a negative bias is applied by all transfer transistors 602-1 to 602-4, and a negative bias is applied by all electrodes 611A to 611L.

[0264] As shown on the left side of Figure 57, during charge transfer of photodiode 601-1, a positive bias is applied by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrodes 611A and 611B, and a negative bias is applied by the other electrodes 611.

[0265] As shown on the right side of Figure 57, during charge transfer of photodiode 601-2, a positive bias is applied by transfer transistor 602-2, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrodes 611A and 611G, and a negative bias is applied by the other electrodes 611.

[0266] As described above, when four electrodes 611 are formed on an inter-pixel separation portion 63 that defines one pixel region 61, the electrodes 611 that are closer to the FD 611 than the transfer transistor 602 are formed on the front side of the semiconductor layer 51 and a positive bias is applied during charge transfer. On the other hand, the electrodes 611 that are further from the FD 604 than the transfer transistor 602 are formed on the back side of the semiconductor layer 51 and a negative bias is applied during charge transfer.

[0267] Figure 58 shows a first modified example of the configuration of pixel 2.

[0268] In the first modified example of pixel 2, electrodes 611 are formed only on two of the four linear sections of the inter-pixel separation section 63 that are in contact with the side surface of the pixel region 61, specifically on the sections where a portion of the FD 604 is formed. In other words, two electrodes are formed on the inter-pixel separation section 63 that defines one pixel region 61 (pixel 2). In the example of Figure 58A, only electrodes 611A between photodiode 601-1 and photodiode 601-2, electrode 611B between photodiode 601-1 and photodiode 601-4, electrode 611G between photodiode 601-2 and photodiode 601-3, and electrode 611J between photodiode 601-3 and photodiode 601-4 are formed.

[0269] In this case, during charge transfer of photodiode 601-1, a positive bias is applied by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrodes 611A and 611B, and a negative bias is applied by the other electrodes 611. As a result, as shown by the white arrow A in Figure 58, a transfer path is formed from transfer transistor 602-1 to FD604, passing through the vicinity of electrodes 611A and 611B, which are receiving a positive bias.

[0270] As shown in Figure 58B, electrodes 611A and 611B, which apply a positive bias during charge transfer, are formed on the front side (upper side in the figure) of the semiconductor layer 51 within the inter-pixel separation section 63. In this case, the contact 632 for applying voltage to electrode 611A and the contact 633 for applying voltage to electrode 611B are formed on the front surface of the semiconductor layer 51, that is, within the wiring layer 52.

[0271] Figure 59 shows a second modified example of the configuration of pixel 2.

[0272] In the second modified pixel 2, similar to the first modified pixel 2 described with reference to Figure 58, only electrodes 611A, 611B, 611G, and 611J are formed within the inter-pixel separation portion 63. On the other hand, in the second modified pixel 2, unlike the first modified pixel 2, as shown in Figure 59B, electrodes 611A, 611B, 611G, and 611J are formed on the back side (lower side in the figure) of the semiconductor layer 51 within the inter-pixel separation portion 63.

[0273] Therefore, the contact 632 for applying voltage to electrode 611A and the contact 633 for applying voltage to electrode 611B are formed on the back surface of the semiconductor layer 51, that is, within the insulating film 62.

[0274] In this case, during charge transfer of photodiode 601-1, as shown in Figure 59A, a positive bias is applied by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A negative bias is applied by all electrodes 611. As a result, as shown by the white arrows in Figure 59A, transfer paths are formed from the vicinity of electrodes 611A and 611B, to transfer transistor 602-1, and from transfer transistor 602-1 to FD604.

[0275] Figure 60 shows a third modified example of the configuration of pixel 2.

[0276] In the third modified pixel 2, similar to the first modified pixel 2 described with reference to Figure 58, only electrodes 611A, 611B, 611G, and 611J are formed within the inter-pixel separation portion 63.

[0277] On the other hand, in the pixel 2 according to the third modified example, the transfer transistors 602-1 and 602-2 are formed closer to the electrode 611A, rather than in the center of the photodiode 601 in a plan view. Also, in the pixel 2 according to the third modified example, the transfer transistors 602-3 and 602-4 are formed closer to the electrode 611J, rather than in the center of the photodiode 601 in a plan view.

[0278] In this case, during charge transfer of the photodiode 601-1, as shown in Figure 60, a positive bias is applied by the transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrode 611A, and a negative bias is applied by the other electrodes 611. Specifically, of the two electrodes 611 formed in the linear portion of the inter-pixel separation portion 63 that is in contact with the side surface of the photodiode 601-1, the electrode 611B that is farther from the transfer transistor 602-1 is subjected to a negative bias, and the electrode 611A that is closer to the transfer transistor 602-1 is subjected to a positive bias.

[0279] As a result, as shown by the white arrows in Figure 60, a transfer path is formed from the vicinity of the electrode 611B to which a negative bias is applied, toward the transfer transistor 602-1, and a transfer path is formed from the transfer transistor 602-1 toward the FD 604. That is, the charge accumulated in the photodiode 601-1 is transferred to the FD 604 by moving counterclockwise within the photodiode 601-1, as shown by the solid arrows in Figure 60.

[0280] Figure 61 is a diagram illustrating the formation surface of the electrode 611 in the semiconductor layer 51 of Figure 60. Part A of Figure 61 shows an example of the A-A' cross section in Figure 60, and part B of Figure 61 shows an example of the B-B' cross section in Figure 60.

[0281] As shown in Figure 61A, the electrode 611A that applies a positive bias during charge transfer is formed on the front side (upper side in the figure) of the semiconductor layer 51 within the inter-pixel isolation section 63. In this case, the contact 632 for applying voltage to the electrode 611A is formed on the front surface of the semiconductor layer 51, that is, within the wiring layer 52.

[0282] Furthermore, electrode 611J is formed on the front side of the semiconductor layer 51 within the inter-pixel separation section 63, similar to electrode 611A.

[0283] On the other hand, the electrode 611B that applies a negative bias during charge transfer is formed on the back side (lower side in the figure) of the semiconductor layer 51 within the inter-pixel separation section 63. In this case, the contact 633 for applying voltage to the electrode 611B is formed on the back side of the semiconductor layer 51, that is, within the insulating film 62.

[0284] Furthermore, the electrode 611G, like the electrode 611B, is formed on the back side of the semiconductor layer 51 within the inter-pixel separation section 63.

[0285] In the example shown in Figure 61, the transfer transistor 602-1 has a planar gate electrode, rather than an embedded gate electrode embedded in the substrate thickness direction from the front side of the photodiode 601-1.

[0286] As shown in Figure 61A, the charge accumulated in the deep part (back side) of the photodiode 601-1 moves toward the shallow part (front side), toward the transfer transistor 602-1 and electrode 611A, toward the positive bias applied by electrode 611B, when a negative bias is applied. As shown in Figure 61B, the charge that has moved toward the shallow part of the photodiode 601-1 moves further toward FD604.

[0287] The contact 604 connected to the FD 604 is formed on the front surface of the semiconductor layer 51, that is, within the wiring layer 52.

[0288] Figures 62 and 63 show examples of the voltages applied by each electrode 611 during charge discharge, charge accumulation, and charge transfer in pixel 2 of Figure 60.

[0289] As shown on the left side of Figure 62, during charge discharge, a positive bias is applied by all transfer transistors 602-1 to 602-4. A positive bias is applied by electrodes 611A and 611J, and a negative bias is applied by electrodes 611B and 611G.

[0290] As shown on the right side of Figure 62, during charge accumulation, a negative bias is applied by all transfer transistors 602-1 to 602-4, and a negative bias is applied by all electrodes 611A to 611L.

[0291] As shown on the left side of Figure 63, during charge transfer of photodiode 601-1, a positive bias is applied by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrode 611A, and a negative bias is applied by the other electrodes 611.

[0292] As shown on the right side of Figure 63, during charge transfer of photodiode 601-2, a positive bias is applied by transfer transistor 602-2, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrode 611A, and a negative bias is applied by the other electrodes 611.

[0293] Figure 64 shows a fourth modified example of the configuration of pixel 2.

[0294] The fourth modified pixel 2 has a configuration in which, compared to the third modified pixel 2 described with reference to Figure 60, an electrode 611 is further formed in the linear portion closer to the transfer transistor 602 of the two linear portions of the inter-pixel separation portion 63 where a portion of the FD 604 is not formed. In other words, three electrodes are formed for the inter-pixel separation portion 63 that defines one pixel region 61 (pixel 2).

[0295] In the example shown in Figure 64, the left electrode 611D of photodiode 601-1, the left electrode 611E of photodiode 601-2, the right electrode 611I of photodiode 601-3, and the right electrode 611K of photodiode 601-4 are formed within the inter-pixel separation section 63.

[0296] In this case, during charge transfer of photodiode 601-1, a positive bias is applied by transfer transistor 602-1, and a negative bias is applied by the other transfer transistors 602. A positive bias is applied by electrodes 611A and 611D, and a negative bias is applied by the other electrodes 611. Specifically, of the three electrodes 611 formed in the linear portion of the inter-pixel separation portion 63 that is in contact with the side surface of photodiode 601-1, electrode 611B, which is farther from transfer transistor 602-1, is subjected to a negative bias, while electrodes 611A and 611D, which are closer to transfer transistor 602-1, are subjected to a positive bias.

[0297] The electrodes 611D, 611E, 611I, and 611K, which apply a positive bias during charge transfer, are formed on the front side of the semiconductor layer 51 within the inter-pixel separation section 63.

[0298] Figure 65 shows a fifth modified example of the configuration of pixel 2.

[0299] In the pixel 2 according to the fifth modified example, three electrodes are formed for the inter-pixel separation portion 63 that defines one pixel region 61 (pixel 2), similar to the pixel 2 according to the fourth modified example described with reference to Figure 64. On the other hand, in the pixel 2 according to the fifth modified example, as shown in A of Figure 65, a transfer transistor 602 is not formed.

[0300] In this case, during charge transfer of the photodiode 601-1, a positive bias is applied by electrodes 611A and 611D, and a negative bias is applied by the other electrodes 611. More specifically, of the three electrodes 611 formed in the linear portion of the inter-pixel separation portion 63 that is in contact with the photodiode 601-1, electrode 611B, formed on the back side of the semiconductor layer 51, is subjected to a negative bias, while electrodes 611A and 611D, formed on the front side of the semiconductor layer 51, are subjected to a positive bias.

[0301] As a result, as shown by the white arrows in Figure 65, a transfer path is formed from the vicinity of electrode 611B, to which a negative bias is applied, to the vicinity of electrode 611D, to which a positive bias is applied, and from the vicinity of electrode 611D, passing through the vicinity of electrode 611D to FD604. In other words, the charge accumulated in photodiode 601-1 is transferred to FD604 by moving counterclockwise within photodiode 601-1, as shown by the solid arrows in Figure 65.

[0302] Figure 65B schematically shows the positions in the substrate thickness direction where electrodes 611A, 611B, and 611D are formed.

[0303] As shown in Figure 65B, of the electrodes 611 formed on the front surface side of the semiconductor layer 51, the electrode 611D that is further from the FD 604 is formed deeper from the front surface of the semiconductor layer 51 to the pixel separation portion 63 than the electrode 611A that is closer to the FD 604. In other words, the electrodes 611 formed on the front surface side of the semiconductor layer 51 are formed deeper from the front surface of the semiconductor layer 51 the further they are from the FD 604.

[0304] As shown by the white arrow in Figure 65B, the charge accumulated in the deeper part (back side) of the photodiode 601-1 is formed in a position deeper from the front surface when a negative bias is applied to electrode 611B, and moves toward electrode 611D to which a positive bias is applied. Next, the charge is formed in a position shallower from the front surface than electrode 611D, and moves toward electrode 611A to which a positive bias is applied. In this way, the charge that has moved to the shallower part (front side) of the photodiode 601-1 further moves toward FD604.

[0305] Figure 66 is a schematic diagram showing an example of the structure of the inter-pixel separation section 63 in which the electrode 611 is formed.

[0306] As shown on the left side of Figure 66, the inter-pixel separation portion 63 may be configured as an FFTI 671 that penetrates from the front surface to the back surface of the semiconductor layer 51.

[0307] As shown in the center of Figure 66, the inter-pixel isolation portion 63 may be configured as an RDTI (Rear Deep Trench Isolation) 672 formed from the back surface of the semiconductor layer 51 to a depth that does not penetrate the semiconductor layer 51. In this case, for example, the electrode 611B formed on the front surface side of the semiconductor layer 51 is formed by embedding a metallic material or a transparent oxide film into the RDTI 672 through an STI 673 formed from the front surface of the semiconductor layer 51 so as to connect with the RDTI 672.

[0308] As shown on the right side of Figure 66, the inter-pixel isolation portion 63 may be configured as an FDTI (Front Deep Trench Isolation) 674 formed from the front surface of the semiconductor layer 51 to a depth that does not penetrate the semiconductor layer 51. In this case, for example, the electrode 611D formed on the back side of the semiconductor layer 51 is formed by embedding a metallic material or a transparent oxide film into the FDTI 674 through an STI 675 formed from the back surface of the semiconductor layer 51 so as to connect with the FDTI 674.

[0309] The depth to which the electrodes 611 are formed within the inter-pixel separation section 63 is arbitrary.

[0310] Figure 67 shows a sixth modified example of the configuration of pixel 2.

[0311] The pixel 2 in the sixth modification is a pixel having two photodiodes 701 (pixel region 61) that share the same FD 704. In this case, the inter-pixel separation portion 63 has a protruding portion that protrudes to electrically separate a part of the space between the two photodiodes 701.

[0312] In the following section, we will focus on the four photodiodes 701-1 to 701-4 that share the same FD704.

[0313] On the left side of Figure 67, photodiode 701-1 located in the lower left of the figure, photodiode 701-2 located in the lower right of the figure, photodiode 701-3 located in the upper left of the figure, and photodiode 701-4 located in the upper right of the figure all share FD704 located in the center of the figure.

[0314] The photodiodes 701-1 and 701-2, and the photodiodes 701-3 and 701-4 are partially electrically isolated by the protruding portion of the inter-pixel isolation section 63. The photodiodes 701-1 and 701-3, and the photodiodes 701-2 and 701-4 are completely isolated by the linear portion of the inter-pixel isolation section 63.

[0315] In a plan view, transfer transistor 702-1 is formed near FD704 of photodiode 701-1, and transfer transistor 702-2 is formed near FD704 of photodiode 701-2. In a plan view, transfer transistor 702-3 is formed near FD704 of photodiode 701-3, and transfer transistor 702-4 is formed near FD704 of photodiode 701-4.

[0316] An electrode 711A is formed in the left-hand inter-pixel separation portion 63 of photodiode 701-1, and an electrode 711B is formed in the inter-pixel separation portion 63 between photodiode 701-1 and photodiode 701-3. An electrode 711C is formed in the inter-pixel separation portion 63 (protruding portion) between photodiode 701-1 and photodiode 701-2. An electrode 711D is formed in the inter-pixel separation portion 63 between photodiode 701-2 and photodiode 701-4, and an electrode 711E is formed in the right-hand inter-pixel separation portion 63 of photodiode 701-2.

[0317] An electrode 711F is formed in the left-hand inter-pixel separation portion 63 of photodiode 701-3, an electrode 711G is formed in the inter-pixel separation portion 63 (protruding portion) between photodiode 701-3 and photodiode 701-4, and an electrode 711H is formed in the right-hand inter-pixel separation portion 63 of photodiode 701-4.

[0318] In the following, electrodes 711A to 611H will simply be referred to as electrode 711 unless there is a need to distinguish between them. Electrode 711 corresponds to electrode 611 as described with reference to Figure 54, etc. Also, transfer transistors 702-1 to 701-4 will simply be referred to as transfer transistor 702 unless there is a need to distinguish between them.

[0319] The electrodes 711C and 711G formed on the protruding portion of the inter-pixel separation section 63 are, for example, always subjected to a negative bias. This creates overflow paths between photodiodes 701-1 and 701-2, and between photodiodes 701-3 and 701-4. Electrodes 711C and 711G may be formed on either the front or back side of the semiconductor layer 51 within the inter-pixel separation section 63. Whether electrodes 711C and 711G are formed on the front or back side of the semiconductor layer 51 determines whether the overflow paths are formed on the front or back side of the semiconductor layer 51.

[0320] During charge transfer by photodiode 701-1, a positive bias is applied by transfer transistor 702-1, and a negative bias is applied by the other transfer transistors 702. A positive bias is applied by electrodes 711A, 711B, and 711E, and a negative bias is applied by electrodes 711D, 711F, and 711H.

[0321] On the right side of Figure 67, an example of the A-A' section on the left side of Figure 67 is shown.

[0322] As shown on the right side of Figure 67, for example, electrodes 711A and 711B are formed on the front side (upper side in the figure) of the semiconductor layer 51 within the inter-pixel separation section 63. Of the electrodes 711 formed on the front side of the semiconductor layer 51, electrode 611A, which is further from FD 704, is formed deeper in the inter-pixel separation section 63 from the front surface of the semiconductor layer 51 than electrode 711B, which is closer to FD 704.

[0323] Furthermore, electrodes 711F and 711H are formed on the front side of the semiconductor layer 51 within the inter-pixel separation section 63, similar to electrodes 711A and 711B.

[0324] Figure 68 is a timing chart illustrating the operation flow of pixel 2.

[0325] First, at time t1, the voltage applied to the selection transistor of pixel 2 rises. Next, between time t1 and time t2, the voltage applied to the reset transistor of pixel 2 rises.

[0326] Next, at time t2, the voltages applied to electrodes 711A and 711E, and electrodes 711F and 711H rise (a positive bias is applied by electrodes 711F and 711H). Then, at time t3, the voltages applied to electrodes 711F and 711H fall (a negative bias is applied by electrodes 711F and 711H). As a result, charge discharge from photodiodes 701-3 and 701-4 begins.

[0327] Next, at time t4, the voltage applied to electrode 711B rises (positive bias is applied by electrode 711B). This initiates charge discharge from photodiode 701-1. Then, between time t5 and time t6, the voltage applied to the reset transistor falls. The period from when the voltage applied to the reset transistor rises to when it falls is the period for charge discharge and charge reset of pixel 2.

[0328] The period from after the charge discharge and charge reset of pixel 2 until before the charge transfer (the period including time t6) is the P-phase period for reading the reset level of the pixel signal voltage VSL. Next, at time t7, the voltage applied to electrode 711D rises (a positive bias is applied by electrode 711D). This starts the charge transfer of photodiode 701-2. As the charge transfer starts, the pixel signal voltage VSL drops.

[0329] Next, at time t8, the voltage applied to electrode 711D falls (a negative bias is applied by electrode 711D). This completes the charge transfer of photodiode 701-2. Then, at time t9, the voltage applied to the selection transistor falls, and the voltages applied to electrodes 711A, 711E, and 711B also fall. The period from the completion of charge transfer of photodiode 701-2 to time t9 is the D-phase period for reading the signal level of the pixel signal voltage VSL.

[0330] Figure 69 shows a seventh modified example of the configuration of pixel 2.

[0331] In the seventh modification, the pixel 2 is composed of two photodiodes 701 that share the same FD 704, similar to the pixel 2 in the seventh modification described with reference to Figure 67. On the other hand, in the pixel 2 in the seventh modification, a transfer transistor 702 is not formed, as shown in Figure 69.

[0332] In this case, during charge transfer of the photodiode 601-1, a positive bias is applied by electrodes 711A and 611B, and a negative bias is applied by the other electrodes 711.

[0333] As described above, by individually forming multiple electrodes, each capable of having an arbitrary voltage applied to them, within the inter-pixel isolation section that separates adjacent pixel regions 61 formed in the semiconductor layer 51, the electrodes can assist the transfer transistor 602 in transferring charge to the FD 604, or the electrodes themselves can transfer charge to the FD 604.

[0334] <6. Examples of application to electronic devices> The above-described photodetector 1 can be applied to various electronic devices, such as imaging devices like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0335] Figure 70 is a block diagram showing an example configuration of an imaging device as an electronic device to which the present disclosure is applied.

[0336] The imaging device 1001 shown in Figure 70 comprises an optical system 1002, a shutter device 1003, a solid-state imaging device 1004, a drive circuit 1005, a signal processing circuit 1006, a monitor 1007, and a memory 1008, and is capable of capturing both still and moving images.

[0337] The optical system 1002 is composed of one or more lenses and guides light from the subject (incident light) to the solid-state imaging device 1004, where it forms an image on the light-receiving surface of the solid-state imaging device 1004.

[0338] The shutter device 1003 is positioned between the optical system 1002 and the solid-state imaging device 1004, and controls the light irradiation period and light shielding period for the solid-state imaging device 1004 according to the control of the drive circuit 1005.

[0339] The solid-state imaging device 1004 is composed of the photodetector element 1 shown in Figure 1. The solid-state imaging device 1004 accumulates signal charge for a certain period of time in response to light that is imaged onto the light-receiving surface via the optical system 1002 and shutter device 1003. The signal charge accumulated in the solid-state imaging device 1004 is transferred according to the drive signal (timing signal) supplied from the drive circuit 1005.

[0340] The drive circuit 1005 drives the solid-state imager 1004 and the shutter device 1003 by outputting drive signals that control the transfer operation of the solid-state imager 1004 and the shutter operation of the shutter device 1003.

[0341] The signal processing circuit 1006 performs various signal processing operations on the signal charge output from the solid-state imaging device 1004. The image (image data) obtained by the signal processing circuit 1006 is supplied to the monitor 1007 for display or supplied to the memory 1008 for storage (recording).

[0342] Even in the imaging device 1001 configured in this way, by applying the photodetector element 1 shown in Figure 1 as the solid-state imaging device 1004, the degree of freedom in element placement is improved, making it possible to mount high-performance elements in the solid-state imaging device 1004, or to miniaturize the pixels 2 while maintaining the performance of the pixel transistors.

[0343] <7. Examples of Use of Photodetector> Figure 71 shows an example of use using the photodetector 1 described above.

[0344] The above-described photodetector 1 can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0345] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0346] <8. Examples of Application to Endoscopic Surgical Systems> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be applied to an endoscopic surgical system.

[0347] Figure 72 is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology described herein (the technology) may be applied.

[0348] Figure 72 illustrates a surgeon (physician) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 consists of an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment device 11112, a support arm device 11120 for supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0349] The endoscope 11100 consists of a barrel 11101, the tip of which is inserted into the body cavity of the patient 11132 for a predetermined length, and a camera head 11102 connected to the base end of the barrel 11101. In the illustrated example, the endoscope 11100 is shown as a so-called rigid endoscope having a rigid barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible endoscope having a flexible barrel.

[0350] An opening into which an objective lens is fitted is provided at the tip of the microscope tube 11101. A light source device 11203 is connected to the endoscope 11100, and the light generated by the light source device 11203 is guided to the tip of the microscope tube by a light guide extending inside the microscope tube 11101, and is irradiated through the objective lens towards the object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a straight-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0351] The camera head 11102 contains an optical system and an image sensor. Reflected light from the object being observed (observation light) is focused onto the image sensor by the optical system. The image sensor converts the observation light into electrical signals, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0352] The CCU 11201 is composed of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and other components, and comprehensively controls the operation of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing operations on that image signal, such as development processing (demosaic processing), to display an image based on that image signal.

[0353] The display device 11202 displays an image based on an image signal that has been processed by the CCU 11201, under control from the CCU 11201.

[0354] The light source device 11203 is composed of a light source such as an LED (light-emitting diode) and supplies illumination light to the endoscope 11100 when photographing the surgical area, etc.

[0355] The input device 11204 is an input interface for the endoscopic surgical system 11000. The user can input various types of information and instructions to the endoscopic surgical system 11000 via the input device 11204. For example, the user can input instructions to change the imaging conditions (type of light, magnification, focal length, etc.) of the endoscope 11100.

[0356] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for purposes such as tissue cauterization, incision, or blood vessel sealing. The insufflation device 11206 injects gas into the body cavity of the patient 11132 via the insufflation tube 11111 to inflate the body cavity for the purpose of securing a field of view by the endoscope 11100 and securing the operator's workspace. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various formats such as text, images, or graphs.

[0357] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical area can be configured as a white light source consisting of, for example, an LED, a laser light source, or a combination thereof. When the white light source is configured as a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, so the white balance of the captured image can be adjusted in the light source device 11203. In this case, it is also possible to capture images corresponding to each of the RGB colors in time-division by irradiating the observation target with laser light from each of the RGB laser light sources in time-division and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter on the image sensor.

[0358] Furthermore, the light source device 11203 may be controlled to change the intensity of the light it outputs at predetermined time intervals. By controlling the drive of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity, images can be acquired in time-division order, and these images can be combined to generate high dynamic range images without so-called black crushing and white clipping.

[0359] Furthermore, the light source device 11203 may be configured to supply light in a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue and irradiating with narrow-band light compared to the irradiation light used during normal observation (i.e., white light), so-called narrow-band imaging is performed to image predetermined tissues such as blood vessels on the surface of mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image from fluorescence generated by irradiation with excitation light. In fluorescence observation, excitation light is irradiated onto body tissue and fluorescence from the body tissue is observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) is injected into body tissue and excitation light corresponding to the fluorescence wavelength of the reagent is irradiated onto the body tissue to obtain a fluorescence image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0360] Figure 73 is a block diagram showing an example of the functional configuration of the camera head 11102 and CCU 11201 shown in Figure 72.

[0361] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0362] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and then incident on the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses, including a zoom lens and a focus lens.

[0363] The imaging unit 11402 may consist of one image sensor (a so-called single-chip type) or multiple image sensors (a so-called multi-chip type). If the imaging unit 11402 is configured as a multi-chip type, for example, each image sensor may generate image signals corresponding to RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 11402 may be configured to have a pair of image sensors for acquiring image signals for the right eye and left eye, respectively, corresponding to 3D (dimensional) display. By performing 3D display, the surgeon 11131 can more accurately grasp the depth of the biological tissue in the surgical area. In addition, if the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each image sensor.

[0364] Furthermore, the imaging unit 11402 does not necessarily have to be located on the camera head 11102. For example, the imaging unit 11402 may be located inside the lens barrel 11101, directly behind the objective lens.

[0365] The drive unit 11403 is composed of actuators and, under control from the camera head control unit 11405, moves the zoom lens and focus lens of the lens unit 11401 along the optical axis by a predetermined distance. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted as appropriate.

[0366] The communication unit 11404 is composed of communication devices for sending and receiving various types of information with the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0367] Furthermore, the communication unit 11404 receives a control signal from the CCU 11201 to control the drive of the camera head 11102 and supplies it to the camera head control unit 11405. The control signal includes information about imaging conditions, such as information to specify the frame rate of the captured image, information to specify the exposure value at the time of imaging, and / or information to specify the magnification and focus of the captured image.

[0368] The imaging conditions such as frame rate, exposure value, magnification, and focus may be specified by the user as appropriate, or they may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure), AF (Auto Focus), and AWB (Auto White Balance) functions.

[0369] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 via the communication unit 11404.

[0370] The communication unit 11411 is comprised of a communication device for sending and receiving various types of information with the camera head 11102. The communication unit 11411 receives image signals transmitted from the camera head 11102 via the transmission cable 11400.

[0371] Furthermore, the communication unit 11411 transmits control signals to the camera head 11102 to control the driving of the camera head 11102. Image signals and control signals can be transmitted by telecommunications, optical communications, etc.

[0372] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102.

[0373] The control unit 11413 performs various controls related to imaging the surgical area, etc., by the endoscope 11100, and the display of the images obtained from imaging the surgical area, etc. For example, the control unit 11413 generates a control signal to control the driving of the camera head 11102.

[0374] Furthermore, the control unit 11413 displays the captured image showing the surgical area, etc., on the display device 11202 based on the image signal processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, mist when using the energy treatment device 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When the control unit 11413 displays the captured image on the display device 11202, it may use the recognition results to superimpose various surgical support information onto the image of the surgical area. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can proceed with the surgery reliably.

[0375] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable compatible with electrical signal communication, an optical fiber compatible with optical communication, or a composite cable thereof.

[0376] In the illustrated example, communication was performed via a wired connection using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.

[0377] The above describes an example of an endoscopic surgical system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to, for example, the endoscope 11100, the camera head 11102 (imaging unit 11402), the CCU 11201 (image processing unit 11412), etc., among the configurations described above. Specifically, for example, the photodetector element 1 according to the above embodiment can be applied to the imaging unit 10402. By applying the technology of this disclosure to the imaging unit 10402, high-quality surgical images can be obtained using high-performance pixel transistors.

[0378] While an endoscopic surgical system has been described here as an example, the technology described herein may also be applied to other systems, such as microsurgical systems.

[0379] <9. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0380] Figure 74 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0381] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 74, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0382] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0383] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0384] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0385] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0386] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0387] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0388] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0389] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12030 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0390] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 74, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0391] Figure 75 shows an example of the installation position of the imaging unit 12031.

[0392] In Figure 75, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0393] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0394] Figure 75 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0395] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0396] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0397] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0398] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0399] The above describes an example of a vehicle control system to which the technology of this disclosure may be applied. The technology of this disclosure can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, for example, the photodetector element 1 according to the embodiment described above can be applied to the imaging unit 12031. By applying the technology of this disclosure to the imaging unit 12031, it is possible to provide high-quality images captured using high-performance pixel transistors. Furthermore, the obtained images can be used to reduce driver fatigue and improve the safety of the driver and the vehicle.

[0400] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0401] <Examples of configuration combinations> This technology can also be configured as follows:

[0402] (1) A photodetector comprising: a first semiconductor substrate on which a plurality of pixel regions are formed; an inter-pixel separation portion that separates adjacent pixel regions on the first semiconductor substrate; a first conductive portion formed within the inter-pixel separation portion; and a second conductive portion formed on the light-receiving surface of the first semiconductor substrate and connected to the first conductive portion. (2) The photodetector according to (1), wherein the first conductive portion is connected to an element formed on the side of the first semiconductor substrate opposite to the light-receiving surface. (3) The photodetector according to (2), wherein the first conductive portion is connected to an element to which a fixed potential is applied. (4) The photodetector according to (3), wherein the element is formed in the pixel region. (5) The photodetector according to (4), wherein the first conductive portion is connected to the element via a contact formed on the side of the first semiconductor substrate opposite to the light-receiving surface. (6) The photodetector according to (4), wherein the first conductive portion is connected to the element via a contact formed within the inter-pixel separation portion. (7) The photodetector element according to (4), wherein the first conductive portion is connected to the element formed to span adjacent pixel regions. (8) The photodetector element according to any one of (2) to (7), further comprising a second semiconductor substrate bonded to the surface of the first semiconductor substrate opposite to the light-receiving surface. (9) The photodetector element according to (8), wherein the element is formed on the second semiconductor substrate. (10) The photodetector element according to (8), comprising a plurality of first conductive portions, including conductive portions connected to the element formed in the pixel region and other conductive portions formed on the second semiconductor substrate and connected to the element. (11) The photodetector element according to (8), wherein the first conductive portion is connected to the element formed in the pixel region via a contact and is also directly connected to the element formed on the second semiconductor substrate. (12) The photodetector element according to (11), wherein a part of the first conductive portion penetrates the contact and is directly connected to the element formed on the second semiconductor substrate. (13) The photodetector element according to (11), wherein the first conductive portion extends in the substrate thickness direction so as to straddle the contact and is directly connected to the element formed on the second semiconductor substrate.(14) The photodetector element according to (1), wherein the first conductive portion is an electrode that applies a negative bias to the side surface of the pixel region. (15) The photodetector element according to any one of (1) to (14), wherein the second conductive portion is composed of a transparent oxide film. (16) The photodetector element according to any one of (1) to (15), wherein the first conductive portion is composed of a transparent oxide film. (17) The photodetector element according to (15), wherein the second conductive portion is formed to cover the light-receiving surface. (18) The photodetector element according to any one of (1) to (16), wherein the second conductive portion is formed to follow the inter-pixel separation portion in a plan view. (19) The photodetector element according to (2), further comprising a pixel transistor as the element having a gate region, a source-drain region, and a channel region, wherein the first conductive portion is connected to the gate region. (20) The photodetector element according to (19), wherein the gate region is formed within the inter-pixel separation portion. (21) The photodetector element according to (19) or (20), wherein the gate region is formed on the inter-pixel separation portion on the side opposite to the light-receiving surface. (22) The photodetector element according to any one of (19) to (21), wherein the inter-pixel separation portion is formed in a grid shape, and the gate region is formed within the intersection of the inter-pixel separation portion or on the intersection of the inter-pixel separation portion on the side opposite to the light-receiving surface. (23) The photodetector element according to any one of (19) to (22), wherein the gate region has a protrusion extending in the direction in which the channel is formed in the channel region. (24) The photodetector element according to (19), wherein the gate region and the first conductive portion are composed of a transparent oxide film. (25) The photodetector element according to (19), wherein the gate region has a shape that sandwiches the channel region or a shape that surrounds the channel region. (26) The photodetector element according to (2), further comprising a first well contact as an element, formed at a position deeper than the surface opposite to the light-receiving surface within the inter-pixel separation portion.(27) The photodetector according to (26), further comprising a floating diffusion region formed within the inter-pixel separation portion so as to overlap the first well contact with the substrate thickness direction, wherein the floating diffusion region is formed at a shallower position within the inter-pixel separation portion from the surface opposite to the light-receiving surface than the first well contact. (28) The photodetector according to (27), wherein an insulating film is formed between the first well contact and the floating diffusion region. (29) The photodetector according to (27), wherein a depletion layer is formed between the first well contact and the floating diffusion region. (30) The photodetector according to (26), further comprising a floating diffusion region formed in the pixel region, wherein the floating diffusion region is formed at a shallower position from the surface of the first semiconductor substrate opposite to the light-receiving surface than the first well contact, and is connected to a contact formed on the inter-pixel separation portion on the side of the first semiconductor substrate opposite to the light-receiving surface so as to overlap the first well contact with the substrate thickness direction. (31) The photodetector element according to any one of (26) to (30), further comprising a second semiconductor substrate bonded to the surface of the first semiconductor substrate opposite to the light-receiving surface. (32) An electronic device having a photodetector element comprising a first semiconductor substrate on which a plurality of pixel regions are formed, an inter-pixel isolation portion that separates adjacent pixel regions on the first semiconductor substrate, a first conductive portion formed within the inter-pixel isolation portion, and a second conductive portion formed on the light-receiving surface of the first semiconductor substrate and connected to the first conductive portion. (33) A photodetector element comprising a pixel region formed on a semiconductor substrate, a floating diffusion region to which charge accumulated in the pixel region is transferred, an inter-pixel isolation portion that separates the pixel region from other adjacent pixel regions on the semiconductor substrate, and a plurality of conductive portions individually formed within the inter-pixel isolation portion, each capable of applying an arbitrary voltage to the side surface of the pixel region. (34) The photodetector element according to (33), wherein the plurality of conductive portions are composed of a transparent oxide film. (35) The photodetector according to (33) or (34), wherein, during charge transfer of the pixel region, the conductive portion of the plurality of conductive portions formed on the side of the semiconductor substrate opposite to the light-receiving surface applies a positive bias to the side surface of the pixel region.(36) The photodetector according to any one of (33) to (35), wherein, during charge transfer in the pixel region, the conductive portion formed on the light-receiving surface side of the semiconductor substrate applies a negative bias to the side surface of the pixel region. (37) The photodetector according to any one of (33) to (36), wherein two conductive portions are formed on the inter-pixel separation portion defining the pixel region, and both of the two conductive portions are formed on the side of the semiconductor substrate opposite to the light-receiving surface. (38) The photodetector according to (33) to (36), wherein two conductive portions are formed on the inter-pixel separation portion defining the pixel region, and both of the two conductive portions are formed on the light-receiving surface side within the inter-pixel separation portion. (39) The photodetector element according to (33) to (36), wherein two conductive portions are formed on the inter-pixel separation portion defining the pixel region, one of the two conductive portions is formed on the light-receiving surface side of the semiconductor substrate, and the other is formed on the surface side of the semiconductor substrate opposite to the light-receiving surface. (40) The photodetector element according to (33), wherein four conductive portions are formed on the inter-pixel separation portion defining the pixel region. (41) The photodetector element according to (40), further comprising a transfer transistor for transferring charge accumulated in the pixel region to the floating diffusion region, wherein of the four conductive portions, the conductive portion closer to the floating diffusion region than the transfer transistor in a plan view is formed on the surface side of the semiconductor substrate opposite to the light-receiving surface, and the conductive portion further from the floating diffusion region than the transfer transistor in a plan view is formed on the light-receiving surface side of the semiconductor substrate. (42) The photodetector according to (33), wherein three conductive portions are formed on the inter-pixel separation portion that defines the pixel region. (43) The photodetector according to (42), further comprising a transfer transistor for transferring charge accumulated in the pixel region to the floating diffusion region, wherein, of the three conductive portions, the conductive portion closer to the transfer transistor in a plan view is formed on the side of the semiconductor substrate opposite to the light-receiving surface, and the conductive portion further from the floating diffusion region than the transfer transistor in a plan view is formed on the side of the semiconductor substrate that is the light-receiving surface.(44) The photodetector according to (42) or (43), wherein, of the three conductive portions, the conductive portion formed on the side of the semiconductor substrate opposite to the light-receiving surface is formed to a deeper position from the side opposite to the light-receiving surface as it moves away from the floating diffusion region.

[0403] 1 Photodetector, 2 Pixel, 3 Pixel array, 41 Pixel substrate, 42 Color filter, 43 Inter-pixel light-shielding film, 44 On-chip lens, 51 Semiconductor layer, 52 Wiring layer, 61 Pixel region, 62 Insulating film, 63 Inter-pixel isolation region, 101 Second conductive region, 102 First conductive region, 103 Insulating film, 121, 122 Transfer transistor, 123 p-well, 124, 125 Contact, 126 p-well, 201 Transistor substrate, 202 Logic substrate, 227 Semiconductor region, 281 p-well, 401 Pixel transistor, 421 Gate region, 422 Source-drain region, 423 Channel region, 431 Oxide film, 441 Fixed charge film, 501 p-well, 502 FD, 503 Insulating film, 505 Depletion layer, 511 FD, 512 Contact, 521 Well, 541 Dummy well, 601 Photodiode, 602 Transfer transistor, 603 p-well, 604 FD, 611 Electrode, 701-1 to 701-4 Photodiode, 702 Transfer transistor, 704 FD, 711 Electrode

Claims

1. A photodetector comprising: a first semiconductor substrate on which a plurality of pixel regions are formed; an inter-pixel separation portion that separates adjacent pixel regions on the first semiconductor substrate; a first conductive portion formed within the inter-pixel separation portion; and a second conductive portion formed on the light-receiving surface of the first semiconductor substrate and connected to the first conductive portion.

2. The photodetector according to claim 1, wherein the first conductive portion is connected to an element formed on the side of the first semiconductor substrate opposite to the light-receiving surface.

3. The photodetector element according to claim 2, wherein the first conductive portion is connected to the element to which a fixed potential is applied.

4. The element is a photodetector according to claim 3, formed in the pixel region.

5. The photodetector element according to claim 4, wherein the first conductive portion is connected to the element via a contact formed on the surface of the first semiconductor substrate opposite to the light-receiving surface.

6. The photodetector element according to claim 4, wherein the first conductive portion is connected to the element via a contact formed in the inter-pixel separation portion.

7. The photodetector element according to claim 4, wherein the first conductive portion is connected to the element formed to span adjacent pixel regions.

8. The photodetector element according to claim 2, further comprising a second semiconductor substrate bonded to the surface of the first semiconductor substrate opposite to the light-receiving surface.

9. The photodetector element according to claim 8, wherein the element is formed on the second semiconductor substrate.

10. The photodetector according to claim 8, comprising a plurality of first conductive portions, each including a conductive portion connected to the element formed in the pixel region and other conductive portions formed on the second semiconductor substrate and connected to the element.

11. The photodetector element according to claim 8, wherein the first conductive portion is connected to the element formed in the pixel region via a contact and is also directly connected to the element formed on the second semiconductor substrate.

12. The photodetector element according to claim 11, wherein a part of the first conductive portion penetrates the contact and is directly connected to the element formed on the second semiconductor substrate.

13. The photodetector element according to claim 11, wherein the first conductive portion extends in the substrate thickness direction so as to straddle the contact and is directly connected to the element formed on the second semiconductor substrate.

14. The photodetector element according to claim 1, wherein the first conductive portion is an electrode that applies a negative bias to the side surface of the pixel region.

15. The photodetector element according to claim 1, wherein the second conductive portion is composed of a transparent oxide film.

16. The photodetector element according to claim 15, wherein the first conductive portion is composed of a transparent oxide film.

17. The photodetector according to claim 15, wherein the second conductive portion is formed to cover the light-receiving surface.

18. The photodetector element according to claim 1, wherein the second conductive portion is formed to lie along the inter-pixel separation portion in a plan view.

19. The photodetector element according to claim 2, further comprising a pixel transistor as the element having a gate region, a source-drain region, and a channel region, wherein the first conductive portion is connected to the gate region.

20. The photodetector element according to claim 19, wherein the gate region is formed within the inter-pixel separation portion.

21. The photodetector according to claim 19, wherein the gate region is formed on the inter-pixel separation portion on the side opposite to the light-receiving surface.

22. The photodetector element according to claim 19, wherein the inter-pixel separation portion is formed in a grid shape, and the gate region is formed within the intersection of the inter-pixel separation portion or on the intersection of the inter-pixel separation portion on the side opposite to the light-receiving surface.

23. The photodetector according to claim 19, wherein the gate region has a protrusion that extends in the direction in which the channel is formed in the channel region.

24. The photodetector element according to claim 19, wherein the gate region and the first conductive portion are composed of a transparent oxide film.

25. The photodetector element according to claim 19, wherein the gate region has a shape that sandwiches the channel region or a shape that surrounds the channel region.

26. The photodetector element according to claim 2, further comprising a first well contact as an element, formed at a position deeper than the surface opposite to the light-receiving surface within the inter-pixel separation portion.

27. The photodetector according to claim 26, further comprising a floating diffusion region formed within the inter-pixel separation portion so as to overlap with the first well contact in the substrate thickness direction, wherein the floating diffusion region is formed at a shallower position within the inter-pixel separation portion from the surface opposite to the light-receiving surface than the first well contact.

28. The photodetector element according to claim 27, wherein an insulating film is formed between the first well contact and the floating diffusion region.

29. The photodetector according to claim 27, wherein a depletion layer is formed between the first well contact and the floating diffusion region.

30. The photodetector according to claim 26, further comprising a floating diffusion region formed in the pixel region, wherein the floating diffusion region is formed at a shallower position from the surface of the first semiconductor substrate opposite to the light-receiving surface than the first well contact, and is connected to a contact formed on the inter-pixel separation portion on the surface of the first semiconductor substrate opposite to the light-receiving surface so as to overlap with the first well contact in the substrate thickness direction.

31. The photodetector according to claim 26, further comprising a second semiconductor substrate bonded to the surface of the first semiconductor substrate opposite to the light-receiving surface.

32. An electronic device having a photodetector element comprising: a first semiconductor substrate on which a plurality of pixel regions are formed; an inter-pixel separation portion that separates adjacent pixel regions on the first semiconductor substrate; a first conductive portion formed within the inter-pixel separation portion; and a second conductive portion formed on the light-receiving surface of the first semiconductor substrate and connected to the first conductive portion.

33. A photodetector comprising: a pixel region formed on a semiconductor substrate; a floating diffusion region to which charge accumulated in the pixel region is transferred; an inter-pixel isolation section that separates the pixel region from other adjacent pixel regions on the semiconductor substrate; and a plurality of conductive sections individually formed within the inter-pixel isolation section, each capable of applying an arbitrary voltage to the side surface of the pixel region.

34. The photodetector element according to claim 33, wherein the plurality of conductive parts are composed of a transparent oxide film.

35. The photodetector according to claim 33, wherein, during charge transfer in the pixel region, the conductive portion of the plurality of conductive portions formed on the side of the semiconductor substrate opposite to the light-receiving surface applies a positive bias to the side surface of the pixel region.

36. The photodetector according to claim 33, wherein, during charge transfer in the pixel region, the conductive portion formed on the light-receiving surface side of the semiconductor substrate, among the plurality of conductive portions, applies a negative bias to the side surface of the pixel region.

37. The photodetector according to claim 33, wherein two conductive portions are formed on the inter-pixel separation portion that defines the pixel region, and both of the two conductive portions are formed on the side of the semiconductor substrate opposite to the light-receiving surface.

38. The photodetector according to claim 33, wherein two conductive portions are formed on the inter-pixel separation portion that defines the pixel region, and both of the two conductive portions are formed on the light-receiving surface side within the inter-pixel separation portion.

39. The photodetector according to claim 33, wherein two conductive portions are formed on the inter-pixel separation portion that defines the pixel region, one of the two conductive portions is formed on the light-receiving surface side of the semiconductor substrate, and the other is formed on the surface side of the semiconductor substrate opposite to the light-receiving surface.

40. The photodetector according to claim 33, wherein four conductive portions are formed on the inter-pixel separation portion that defines the pixel region.

41. The photodetector according to claim 40, further comprising a transfer transistor for transferring the charge accumulated in the pixel region to the floating diffusion region, wherein, of the four conductive portions, the conductive portion that is closer to the floating diffusion region than the transfer transistor in a plan view is formed on the side of the semiconductor substrate opposite to the light-receiving surface, and the conductive portion that is further from the floating diffusion region than the transfer transistor in a plan view is formed on the side of the semiconductor substrate toward the light-receiving surface.

42. The photodetector according to claim 33, wherein three conductive portions are formed on the inter-pixel separation portion that defines the pixel region.

43. The photodetector according to claim 42, further comprising a transfer transistor for transferring the charge accumulated in the pixel region to the floating diffusion region, wherein of the three conductive portions, the conductive portion closer to the transfer transistor in a plan view is formed on the side of the semiconductor substrate opposite to the light-receiving surface, and the conductive portion further from the floating diffusion region than the transfer transistor in a plan view is formed on the side of the semiconductor substrate toward the light-receiving surface.

44. The photodetector element according to claim 42, wherein, of the three conductive portions, the conductive portion formed on the side of the semiconductor substrate opposite to the light-receiving surface is formed to a deeper position from the side opposite to the light-receiving surface as it moves away from the floating diffusion region.

Images