Photodetection element

Abstract

The present disclosure relates to a photodetection element capable of accommodating pixel miniaturization and allowing for relaxation of the electric field between a gate electrode and a floating diffusion of a transfer transistor. This photodetection element comprises: a semiconductor substrate having a first surface in contact with an interconnect layer and a second surface that is a light-incident surface; a photoelectric conversion unit formed by an impurity region of a first conductivity type in the semiconductor substrate; a first transfer gate electrode and a second transfer gate electrode that transfer electric charges generated by the photoelectric conversion unit; and a floating diffusion that accumulates the electric charges transferred by the first transfer gate electrode and the second transfer gate electrode. The photoelectric conversion unit has a raised region on the interconnect layer side relative to the first surface. The first transfer gate electrode and the second transfer gate electrode are provided on a side wall of the raised region via an impurity region of a second conductivity type that is the opposite of the first conductivity type. The first transfer gate electrode and the second transfer gate electrode are provided, at least in part, at different heights in a cross-sectional view. The present disclosure can be applied to a photodetection element, for example.

Description

Photodetector element

[0001] The present disclosure relates to a photodetector element, and particularly to a photodetector element that can cope with miniaturization of pixels and can relax the electric field between the gate electrode and the floating diffusion of a transfer transistor.

[0002] Conventionally, as a transfer transistor of a pixel in a solid-state imaging device, a vertical transistor having a gate electrode structure in which a part of the gate electrode is embedded in a semiconductor substrate is known (see, for example, Patent Document 1). By using a vertical transistor as the transfer transistor of the pixel, it can be expected that signal charges can be easily transferred even when a photodiode is arranged at a position deep from the transistor formation surface of the semiconductor substrate.

[0003] Japanese Patent Application Laid-Open No. 2010-114273

[0004] When the distance between the gate electrode and the floating diffusion of the transfer transistor becomes short due to miniaturization of the pixel, a strong electric field is generated between the gate electrode and the floating diffusion. The strong electric field between the gate electrode and the floating diffusion may cause defect noise such as white dots.

[0005] The present disclosure has been made in view of such a situation, and enables coping with miniaturization of pixels and relaxes the electric field between the gate electrode and the floating diffusion of the transfer transistor.

[0006] A photodetector element in one aspect of the present disclosure comprises: a semiconductor substrate having a first surface in contact with a wiring layer and a second surface which is an incident light surface; a photoelectric conversion section formed on the semiconductor substrate in an impurity region of a first conductivity type; a first transfer gate electrode and a second transfer gate electrode for transferring charge generated in the photoelectric conversion section; and a floating diffusion for accumulating charge transferred by the first transfer gate electrode and the second transfer gate electrode, wherein the photoelectric conversion section has a convex region on the wiring layer side of the first surface, the first transfer gate electrode and the second transfer gate electrode are provided on the side wall of the convex region via an impurity region of a second conductivity type opposite to the first conductivity type, and at least a portion of the first transfer gate electrode and the second transfer gate electrode are provided at different heights in cross-sectional view.

[0007] In one aspect of this disclosure, a semiconductor substrate is provided having a first surface in contact with a wiring layer and a second surface which is an incident light surface; a photoelectric conversion section is formed on the semiconductor substrate in an impurity region of a first conductivity type; a first transfer gate electrode and a second transfer gate electrode transfer the charge generated in the photoelectric conversion section; and a floating diffusion is provided for accumulating the charge transferred by the first transfer gate electrode and the second transfer gate electrode. The photoelectric conversion section is provided with a convex region on the wiring layer side of the first surface; the first transfer gate electrode and the second transfer gate electrode are provided on the sidewall of the convex region via an impurity region of a second conductivity type opposite to the first conductivity type; and at least a portion of the first transfer gate electrode and the second transfer gate electrode are provided at different heights in cross-sectional view.

[0008] The photodetector and electronic equipment may be independent devices or modules incorporated into other devices.

[0009] This figure shows a schematic configuration of a photodetector element to which the technology of this disclosure is applied. This figure shows the equivalent circuit of a pixel of the photodetector element. This figure illustrates the charge readout operation. This figure shows a first example of pixel structure. This figure shows a second example of pixel structure. This figure shows a third example of pixel structure. This figure shows a fourth example of pixel structure. This is a cross-sectional view showing a modified example of the fourth example of pixel structure. This figure shows a fifth example of pixel structure. This is a top view showing the first and second modified examples of the fifth example of pixel structure. This figure shows a sixth example of pixel structure. This is a top view showing the first and second modified examples of the sixth example of pixel structure. This figure shows a seventh example of pixel structure. This is a block diagram showing an example of the configuration of an electronic device to which the technology of this disclosure is applied. This is a figure illustrating an example of the use of an image sensor.

[0010] The following describes embodiments for implementing the technology of this disclosure (hereinafter referred to as "embodiments") with reference to the attached drawings. The description will proceed in the following order: 1. Outline configuration example of a photodetector element 2. Equivalent circuit and operation of a pixel 3. First structure example of a pixel 4. Second structure example of a pixel 5. Third structure example of a pixel 6. Fourth structure example of a pixel 7. Fifth structure example of a pixel 8. Sixth structure example of a pixel 9. Seventh structure example of a pixel 10. Summary of pixel structures 11. Examples of applications to electronic devices

[0011] In the drawings referenced in the following explanation, identical or similar parts are denoted by the same or similar reference numerals, thereby omitting redundant explanations as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual figures. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0013] <1. Schematic Example of Photodetector Element> Figure 1 shows a schematic configuration of a photodetector element to which the technology of this disclosure is applied.

[0014] Figure 1 shows the configuration of a CMOS image sensor, which is a type of XY address type photodetector. A CMOS image sensor is an image sensor manufactured using or partially using the CMOS process.

[0015] The photodetector 1 comprises a pixel array section 11 and a peripheral circuit section. The peripheral circuit section includes, for example, a vertical drive section 12, a column processing section 13, a horizontal drive section 14, and a system control section 15.

[0016] The photodetector element 1 further includes a signal processing unit 16 and a data storage unit 17. The signal processing unit 16 and the data storage unit 17 may be mounted on the same substrate as the pixel array unit 11, the vertical drive unit 12, etc., or they may be placed on a separate substrate. Furthermore, the signal processing unit 16 and the data storage unit 17 may be provided on a semiconductor chip separate from the photodetector element 1, such as a DSP (Digital Signal Processor) chip.

[0017] The pixel array unit 11 has a configuration in which pixels 20, each having a photoelectric conversion unit that generates and stores an electric charge corresponding to the amount of light received, are arranged in a two-dimensional matrix in the row and column directions. Here, the row direction refers to the pixel rows of the pixel array unit 11, i.e., the horizontal arrangement direction, and the column direction refers to the pixel columns of the pixel array unit 11, i.e., the vertical arrangement direction. A specific example of the circuit configuration of the pixels 20 will be described later with reference to Figure 2, etc.

[0018] Furthermore, in the pixel array section 11, a pixel drive wiring 21 is routed along the row direction as a row signal line for each pixel row, and a vertical signal line 22 is routed along the column direction as a column signal line for each pixel column. The pixel drive wiring 21 transmits drive signals for driving when reading signals from the pixels 20. In Figure 1, the pixel drive wiring 21 is shown as a single wire, but it is not limited to one wire. One end of the pixel drive wiring 21 is connected to the output terminal corresponding to each row of the vertical drive section 12.

[0019] The vertical drive unit 12 is composed of a shift register, an address decoder, and the like, and drives each pixel 20 of the pixel array unit 11 simultaneously or row by row. Together with the system control unit 15, the vertical drive unit 12 constitutes a drive unit that controls the operation of each pixel 20 of the pixel array unit 11. The specific configuration of the vertical drive unit 12 is not shown in the diagram, but generally it has two scanning systems: a read scanning system and a sweep scanning system.

[0020] The readout scanning system sequentially selects and scans the pixels 20 of the pixel array 11 row by row in order to read signals from the pixels 20. The signals read from the pixels 20 are analog signals. The sweep scanning system performs a sweep scan ahead of the readout scan performed by the readout scanning system by the exposure time.

[0021] This sweep scanning system resets the photoelectric conversion unit of each pixel 20 by sweeping away unwanted charges from the photoelectric conversion unit of the pixels 20 in the readout row. This sweeping away (resetting) of unwanted charges by the sweep scanning system then performs what is known as an electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the charge in the photoelectric conversion unit and starting a new exposure (starting charge accumulation).

[0022] The signal read out by the readout scanning system corresponds to the amount of light received since the previous readout operation or electronic shutter operation. The period from the readout timing of the previous readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the exposure period for pixel 20.

[0023] The signals output from each pixel 20 of the pixel row selected and scanned by the vertical drive unit 12 are input to the column processing unit 13 through each of the vertical signal lines 22 for each pixel column. The column processing unit 13 performs predetermined signal processing on the signals output from each pixel 20 of the selected row through the vertical signal lines 22 for each pixel column of the pixel array unit 11, and temporarily holds the pixel signals after signal processing.

[0024] Specifically, the column processing unit 13 performs at least noise reduction processing as part of its signal processing, such as CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing. For example, CDS processing removes pixel-specific fixed pattern noise such as reset noise and threshold variations of amplification transistors within pixels. In addition to noise reduction processing, the column processing unit 13 can also be equipped with, for example, an AD (analog-to-digital) conversion function to convert analog pixel signals into digital signals and output them.

[0025] The horizontal drive unit 14 is composed of a shift register, an address decoder, and the like, and sequentially selects the unit circuits corresponding to the pixel rows of the column processing unit 13. Through this selective scanning by the horizontal drive unit 14, the pixel signals processed for each unit circuit in the column processing unit 13 are output sequentially.

[0026] The system control unit 15 is composed of a timing generator that generates various timing signals, and controls the vertical drive unit 12, column processing unit 13, and horizontal drive unit 14 based on the various timings generated by the timing generator.

[0027] The signal processing unit 16 has at least arithmetic processing capabilities and performs various signal processing, such as arithmetic processing, on the pixel signals output from the column processing unit 13. The data storage unit 17 temporarily stores the data necessary for the signal processing performed by the signal processing unit 16. The pixel signals processed by the signal processing unit 16 are converted to a predetermined format and output to the outside of the device from the output unit 18.

[0028] The photodetector element 1 configured as described above is a back-illuminated CMOS image sensor in which incident light is incident from the back surface of the semiconductor substrate on which the photoelectric conversion unit is formed.

[0029] <2. Equivalent Circuit and Operation of Pixels> Figure 2 shows the equivalent circuit of a pixel 20 of the photodetector 1.

[0030] Pixel 20 includes a photodiode PD, a first transfer transistor TG1, a second transfer transistor TG2, a floating diffusion transistor FD, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0031] The photodiode PD generates and stores an electric charge (signal charge) corresponding to the amount of incident light. The anode terminal of the photodiode PD is grounded, and the cathode terminal is connected to a floating diffusion FD via a first transfer transistor TG1 and a second transfer transistor TG2.

[0032] When the first transfer transistor TG1 and the second transfer transistor TG2 are turned on by a transfer control signal supplied to their gates, they read the charge generated by the photodiode PD and transfer it to the floating diffusion FD. The first transfer transistor TG1 is controlled to turn on and off by a first transfer control signal supplied to its gate, and the second transfer transistor TG2 is controlled to turn on and off by a second transfer control signal supplied to its gate. As will be described later with reference to Figure 3, after the first transfer transistor TG1 and the second transfer transistor TG2 are turned on simultaneously, when the charge transfer is to end, the first transfer transistor TG1 is turned off, and then the second transfer transistor TG2 is turned off.

[0033] The floating diffusion transistor FD stores the charge read from the photodiode PD by the first transfer transistor TG1 and the second transfer transistor TG2 in order to read it as a signal. The floating diffusion transistor FD converts the charge transferred from the first transfer transistor TG1 and the second transfer transistor TG2 into a voltage. When the reset transistor RST is turned on by the reset control signal supplied to its gate, the charge held in the floating diffusion transistor FD is discharged to the constant voltage source VDD, thereby resetting the potential of the floating diffusion transistor FD.

[0034] The amplification transistor AMP outputs a pixel signal corresponding to the potential of the floating diffusion FD. That is, the amplification transistor AMP forms a source follower circuit with a load MOS (not shown) as a constant current source, and a pixel signal indicating a level corresponding to the charge held in the floating diffusion FD is output from the amplification transistor AMP to the column processing unit 13 (Figure 1) via the selection transistor SEL. The load MOS is provided, for example, within the column processing unit 13.

[0035] The selection transistor SEL is turned on when pixel 20 is selected by the selection control signal supplied to its gate, and outputs the pixel signal of pixel 20 to the column processing unit 13 via the vertical signal line 22. The first transfer control signal, the second transfer control signal, the reset control signal, and the selection control signal are controlled by the vertical drive unit 12 and supplied to pixel 20 via the pixel drive wiring 21 (Figure 1).

[0036] As described above, the pixel 20 of the photodetector element 1 is characterized by having two transfer transistors TG, a first transfer transistor TG1 and a second transfer transistor TG2.

[0037] Referring to the potential diagram in Figure 3, the charge readout operation at pixel 20 will be briefly explained.

[0038] After the photodiode PD is reset, the exposure period begins. During the exposure period, as shown in Figure 3A, the first transfer transistor TG1 and the second transfer transistor TG2 are controlled to be off, and the charge generated in the photodiode PD according to the amount of light received is accumulated within the photodiode PD.

[0039] Once a predetermined exposure time has elapsed, the first transfer transistor TG1 and the second transfer transistor TG2 are controlled to be turned on simultaneously, as shown in Figure 3B. As a result, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.

[0040] When it comes to the timing when the charge transfer to the floating diffusion FD ends, first, as shown in C of FIG. 3, the first transfer transistor TG1 is controlled to be off, and then, as shown in D of FIG. 3, the second transfer transistor TG2 is controlled to be off.

[0041] As described above, when the pixel 20 finishes the charge transfer to the floating diffusion FD, first, the first transfer transistor TG1 is controlled to be off, and then, the second transfer transistor TG2 is controlled to be off. This prevents the reverse flow of charges from the floating diffusion FD to the photodiode PD.

[0042] <3. First Structural Example of Pixel> FIG. 4 is a diagram showing a first structural example of the pixel 20.

[0043] A in FIG. 4 is a cross-sectional view of the pixel 20 according to the first structural example, and B in FIG. 4 is a top view of the cross-sectional view of A in FIG. 4 as seen from the wiring layer side along the X-X' line.

[0044] In the cross-sectional view of A in FIG. 4, the photodiode PD, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g, and the floating diffusion FD are shown. The first transfer gate electrode TG1g is the gate electrode of the first transfer transistor TG1, and the second transfer gate electrode TG2g is the gate electrode of the second transfer transistor TG2.

[0045] In the cross-sectional view A of Figure 4, N-type semiconductor regions 61 and P-type semiconductor regions 62 constituting a photodiode PD are formed for each pixel on a semiconductor substrate 30 made of silicon (Si) or the like. The semiconductor substrate 30 has a first surface FA that is in contact with the wiring layer 31 and a second surface SA that is the light incident surface to which light is incident. The N-type semiconductor region 61 is an N-type impurity region, which is the first conductivity type, and is formed by ion implantation of N-type impurities such as phosphorus (P) and arsenic (As) into the substrate region of the semiconductor substrate 30. The P-type semiconductor region 62 is a P-type impurity region, which is the second conductivity type opposite to the first conductivity type, and is formed by ion implantation of P-type impurities such as boron (B) and gallium (Ga) into the substrate region of the semiconductor substrate 30. The N-type semiconductor region 61 is the photoelectric conversion part of the pixel 20 that converts incident light into signal charge and stores the signal charge generated by photoelectric conversion. The P-type semiconductor region 62 is provided near the pixel boundary with adjacent pixels so as to surround the inner N-type semiconductor region 61, which is the photoelectric conversion section, in a plan view, and near the interface between the first surface FA and the second surface SA in a cross-sectional view. In addition, an element isolation region 65 is formed at the pixel boundary of each pixel 50 to isolate it from the photodiode PD of other adjacent pixels 50. The element isolation region 65 can be made of an insulating film such as SiO2 or a P-type semiconductor region. Alternatively, the element isolation region 65 may be configured by further embedding a metallic material such as tungsten, aluminum, silver, and copper inside the insulating film.

[0046] In this specification, the direction parallel to the plane of the semiconductor substrate 30 (first surface FA, second surface SA) is referred to as the planar direction, and the direction perpendicular to the plane of the semiconductor substrate 30 is referred to as the depth direction or thickness direction. Furthermore, "top surface" and "upper side" refer to the surface and direction on the wiring layer 31 side of the semiconductor substrate 30 in the direction perpendicular to the plane, and "bottom surface" and "lower side" refer to the opposite surface and direction on the light incidence side.

[0047] The N-type semiconductor region 61 is also provided on the wiring layer 31 side of the first surface FA of the semiconductor substrate 30. This N-type semiconductor region 61 formed on the wiring layer 31 side of the first surface FA is called the convex region 71, and in Figure 4, the convex region 71 is simply shown with a dashed line. The N-type semiconductor region 61 of the convex region 71 is formed in a square (quadrilateral) shape in plan view, and the four side walls and the top surface of the square are covered with P-type semiconductor regions 63. Note that the P-type semiconductor region 63 on the top surface of the convex region 71 may be omitted, and it may be formed only on the side walls. As shown in the top view of B in Figure 4, the convex region 71 is provided in the center of the pixel area in plan view. The impurity concentration of the P-type semiconductor region 63 is formed at a lower concentration than that of the P-type semiconductor region 62 in the semiconductor substrate 30. For example, if the impurity concentration of the P-type semiconductor region 62 is "P++", then the impurity concentration of the P-type semiconductor region 63 is "P+". The P-type semiconductor region 63 is a region where a channel is formed that serves as a charge transfer path for transferring charge from the N-type semiconductor region 61 to the floating diffusion FD when the first transfer transistor TG1 and the second transfer transistor TG2 are turned on. The P-type semiconductor region 63 is provided in the vicinity of the interface between the outer periphery of the convex region 71 and the first surface FA of the semiconductor substrate 30 in a plan view.

[0048] On the sidewall of the convex portion region 71, a first transfer gate electrode TG1g and a second transfer gate electrode TG2g are provided via a P-type semiconductor region 63 and an insulating film 72. The insulating film 72 between the P-type semiconductor region 63 and the first transfer gate electrode TG1g and the second transfer gate electrode TG2g functions as a gate insulating film of the transfer transistor TG. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are formed of, for example, polysilicon. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are arranged at different positions (heights) in the depth direction. More specifically, the first transfer gate electrode TG1g is provided at a position closer to the semiconductor substrate 30 than the second transfer gate electrode TG2g. The first transfer gate electrode TG1g is provided so as to contact both the first surface FA of the semiconductor substrate 30 and the sidewall of the convex portion region 71 via the P-type semiconductor region 63 and the insulating film 72, and the second transfer gate electrode TG2g is provided at a position farther from the semiconductor substrate 30 than the first transfer gate electrode TG1g and contacts the sidewall of the convex portion region 71 via the P-type semiconductor region 63 and the insulating film 72.

[0049] In the following description, although the first transfer gate electrode TG1g and the second transfer gate electrode TG2g contact the P-type semiconductor region 63 formed on the sidewall of the convex portion region 71 via the insulating film 72 serving as a gate insulating film, for simplicity of explanation, "via the insulating film 72" may be omitted and described as "the first transfer gate electrode TG1g and the second transfer gate electrode TG2g contact the P-type semiconductor region 63 on the sidewall of the convex portion region 71".

[0050] Above the convex portion region 71, a floating diffusion FD is provided by an N-type impurity region 64. The N-type impurity region 64 is formed with an impurity concentration higher than that of the N-type semiconductor region 61. For example, if the impurity concentration of the N-type semiconductor region 61 is "N", the impurity concentration of the N-type impurity region 64 is "N+".

[0051] The first transfer gate electrode TG1g and the second transfer gate electrode TG2g transfer the charge accumulated in the N-type semiconductor region 61 to the N-type impurity region 64, which acts as a floating diffusion FD. The floating diffusion FD (N-type impurity region 64) accumulates the charge transferred by the first transfer gate electrode TG1g and the second transfer gate electrode TG2g. A contact wire 73 is connected to the upper surface of the first transfer gate electrode TG1g, and the first transfer transistor TG1 is turned on and off by a first drive control signal supplied by the contact wire 73. A contact wire 74 is connected to the upper surface of the second transfer gate electrode TG2g, and the second transfer transistor TG2 is turned on and off by a second drive control signal supplied by the contact wire 74. The charge accumulated in the floating diffusion FD (N-type impurity region 64) is transferred to an unillustrated transfer destination (e.g., the gate of an amplification transistor AMP) via a contact wire 75 connected to the upper surface of the N-type impurity region 64. For the contact wiring 73-75, materials such as copper (Cu), tungsten (W), aluminum (Al), and gold (Au) can be used.

[0052] The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are arranged to surround the outer periphery of the rectangular (square) convex region 71 in a plan view, as shown in Figure 4B. If we define the direction from the center to the outer periphery of the pixel region in a plan view as the radial direction, the radial width of the first transfer gate electrode TG1g is formed to be larger than that of the second transfer gate electrode TG2g, thereby securing a connection space for the contact wiring 73.

[0053] In the pixel 20 according to the first structural example configured as described above, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided on the side wall of the convex region 71 on the wiring layer 31 side of the first surface FA of the semiconductor substrate 30. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are arranged at different positions (heights) in the depth direction. The first transfer gate electrode TG1g is arranged to be in contact with both the first surface FA of the semiconductor substrate 30 and the side wall of the convex region 71 P-type semiconductor region 63, and the second transfer gate electrode TG2g is arranged to be in contact with the P-type semiconductor region 63 of the side wall of the convex region 71 at a position further from the semiconductor substrate 30 than the first transfer gate electrode TG1g. When the charge transfer is terminated, as explained with reference to Figure 3, the first transfer transistor TG1 is controlled to be turned off first, and then the second transfer transistor TG2 is controlled to be turned off. As a result, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD (the region close to the light incidence surface), and the second transfer transistor TG2 can assist the charge transfer of the first transfer transistor TG1.

[0054] The channel is formed in the P-type semiconductor region 63 on the side wall of the convex region 71, and the charge in the N-type semiconductor region 61 moves in the depth direction and is transferred to the floating diffusion FD. Some charge is also transferred via the N-type semiconductor region 61 within the convex region 71. By stacking the first transfer gate electrode TG1g and the second transfer gate electrode TG2g vertically in the depth direction, the channel can be extended in the depth direction, and the channel length can be secured even when the pixel size is reduced by miniaturization. Furthermore, even when the pixel size is reduced by miniaturization, a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD (N-type impurity region 64). This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress defect noise caused by the strong electric field between the gate electrode and the floating diffusion FD. In addition, it is possible to suppress the overlap capacitance (parasitic capacitance) between the gate electrode and the floating diffusion FD and improve the conversion efficiency. By extending the transfer gate length (L), a design that is robust to variations in the characteristics of the two transfer transistors TG can be achieved.

[0055] In the example described above, the planar shape of the convex region 71 above the first surface FA of the semiconductor substrate 30 was a square (quadrilateral), but it may also be a rectangle with different length and width, a circle, a rhombus, or any other shape.

[0056] <Modified Version of the First Structural Example> Figure 4C is a top view showing a modified version of the first structural example.

[0057] In the example described above, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g were formed to surround the four sides of the rectangular convex region 71 in a plan view. However, it is not necessary to surround all four sides; for example, as shown in Figure 4C, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g may be positioned on the outside of two opposing sides of the convex region 71, facing each other across the rectangular convex region 71.

[0058] <4. Example of a second pixel structure> Figure 5 shows an example of a second structure of pixel 20.

[0059] In the second to seventh structural examples described in Figure 5 and beyond, parts common to those described previously are given the same reference numerals and their explanations are omitted, while the explanation focuses on the parts that are different.

[0060] Figure 5A is a cross-sectional view of pixel 20 relating to the second structural example, and Figure 5B is a top view of the line X-X' in the cross-sectional view of Figure 5A, as seen from the wiring layer side.

[0061] The second structural examples in Figures 5A and 5B differ from the first structural example shown in Figure 4 in that the second transfer gate electrode TG2g, positioned above the first transfer gate electrode TG1g in a cross-sectional view, is otherwise common to the first structural example. Specifically, the second transfer gate electrode TG2g in the first structural example shown in Figure 4 was formed to surround the four sides of the rectangular convex region 71, as shown in Figure 4B. In contrast, the second transfer gate electrode TG2g in the second structural example is configured with the same shape as one of the regions obtained by dividing the second transfer gate electrode TG2g of the first structural example into left and right halves. In other words, it is formed to surround a part (one half) of the outer circumference of the rectangular convex region 71. The contact wiring 74 that supplies the second drive control signal to the second transfer gate electrode TG2g is connected to the upper surface of the second transfer gate electrode TG2g. The contact wiring 73 connected to the first transfer gate electrode TG1g is connected to the upper surface of the first transfer gate electrode TG1g in a region that does not overlap with the second transfer gate electrode TG2g in a plan view.

[0062] As shown in the pixel 20 of the second structural example above, the first transfer gate electrode TG1g is provided so as to surround the four sides of the rectangular convex region 71 in a plan view, and the second transfer gate electrode TG2g may be provided on a part of the four sides of the rectangular convex region 71, for example, outside one to three sides. When provided on the outside of three sides of the rectangular convex region 71, as shown in Figure 5B, one or two sides may be provided on a part of the side rather than the entire side.

[0063] Figure 5C is a top view showing a modified example of the second structural example, and shows an example of the arrangement of the second transfer gate electrode TG2g when the first transfer gate electrode TG1g is provided on the outside of two opposing sides of the rectangular convex region 71, as shown in Figure 4C, which is a modified example of the first structural example.

[0064] The second transfer gate electrode TG2g is located above one of the two regions where the first transfer gate electrode TG1g is provided. In other words, the second transfer gate electrode TG2g is located outside one of the four sides of the perimeter of the rectangular convex region 71.

[0065] In the pixel 20 according to the second structural example configured as described above, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress the overlap capacitance between the gate electrode and the floating diffusion FD. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG becomes possible.

[0066] <5. Example of the third structure of a pixel> Figure 6 shows an example of the third structure of pixel 20.

[0067] Figure 6A is a cross-sectional view of pixel 20 relating to the third structural example, and Figure 6B is a top view of the line X-X' in the cross-sectional view of Figure 6A, as seen from the wiring layer side.

[0068] In the second structural example shown in Figure 5, in a plan view, the first transfer gate electrode TG1g was configured to surround the entire perimeter of the rectangular convex region 71, while the second transfer gate electrode TG2g was configured to surround only a portion of the perimeter of the convex region 71. In contrast, in the third structural examples A and B of Figure 6, not only the second transfer gate electrode TG2g but also the first transfer gate electrode TG1g is configured to surround only a portion of the perimeter of the convex region 71. In a plan view, the region in which the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are in contact with the P-type semiconductor region 63 and the insulating film 72 is the same among the four sides of the perimeter of the rectangular convex region 71. In a plan view, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided so that at least a portion of them overlap. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g may be outside three sides, two sides, or one side of the rectangular convex region 71. Figure 6C shows an example in which a first transfer gate electrode TG1g and a second transfer gate electrode TG2g are provided outside one side of the rectangular convex region 71.

[0069] In the pixel 20 according to the third structural example configured as described above, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress the overlap capacitance between the gate electrode and the floating diffusion FD. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG becomes possible.

[0070] <6. Example of the fourth structure of a pixel> Figure 7 shows an example of the fourth structure of pixel 20.

[0071] Figure 7A is a cross-sectional view of pixel 20 relating to the fourth structural example, and Figure 7B is a top view of the line X-X' in the cross-sectional view of Figure 7A, as seen from the wiring layer side.

[0072] In the second and third structural examples described above, the second transfer gate electrode TG2g was positioned above the first transfer gate electrode TG1g so as to overlap with the first transfer gate electrode TG1g in a plan view. In contrast, the third structural example in Figure 7 shares with the second and third structural examples that the second transfer gate electrode TG2g is configured to surround only a part of the periphery of the convex region 71, but it differs from the second and third structural examples in that it is positioned so as not to overlap with the first transfer gate electrode TG1g in a plan view.

[0073] The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are arranged around the convex region 71 facing each other, as shown in Figure 7B. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided at different heights on the side walls of the convex region 71. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are arranged to divide the outer perimeter of the rectangular convex region 71 into left and right halves, and are arranged to be symmetrical (mirror symmetrical), and the planar sizes of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are the same. However, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g do not necessarily have to be arranged symmetrically; for example, they may be arranged so that the area occupied around the rectangular convex region 71 is larger for the first transfer gate electrode TG1g than for the second transfer gate electrode TG2g.

[0074] In the pixel 20 according to the fourth structural example configured as described above, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress the overlap capacitance between the gate electrode and the floating diffusion FD. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG becomes possible.

[0075] Figure 8 is a cross-sectional view showing a modified example of the fourth structure.

[0076] Figure 8A is a cross-sectional view showing the first modified example of the fourth structural example.

[0077] In the basic structure of the fourth structural example shown in Figure 7, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g, which are located on the side wall of the protruding region 71, are provided at different depths on the side wall of the protruding region 71 and have the same thickness.

[0078] In contrast, in the first modified example shown in Figure 8A, the thickness of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are different. Specifically, the upper surface positions of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are the same, but their bottom surface positions are different, with the bottom surface of the first transfer gate electrode TG1g connected to the first surface FA of the semiconductor substrate 30 via an insulating film 72. The gate insulating film of the first transfer transistor TG1 consists of an insulating film 72 between the side wall of the convex region 71 and the P-type semiconductor region 63, and an insulating film 72 on the first surface FA of the semiconductor substrate 30. The gate insulating film of the second transfer gate electrode TG2g consists only of an insulating film 72 between the side wall of the convex region 71 and the P-type semiconductor region 63.

[0079] Figure 8B is a cross-sectional view showing a second modified example of the fourth structural example.

[0080] In the second modification shown in Figure 8B, the thickness of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are different, which is similar to the first modification shown in Figure 8A, but the depth position of the second transfer gate electrode TG2g is different. Specifically, in the second modification shown in Figure 8B, the bottom positions of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are the same, but the top positions are different. The top position of the second transfer gate electrode TG2g is positioned lower than the top position of the first transfer gate electrode TG1g. The gate insulating films of both the first transfer transistor TG1 and the second transfer gate electrode TG2g are composed of an insulating film 72 between the side wall of the convex region 71 and the P-type semiconductor region 63, and an insulating film 72 on the first surface FA of the semiconductor substrate 30. However, the length of the gate insulating film in the channel length direction of the side wall of the convex region 71 is longer for the first transfer transistor TG1 than for the second transfer transistor TG2.

[0081] Figure 8C is a cross-sectional view showing a third modified example of the fourth structural example.

[0082] In the third modification shown in Figure 8C, the upper and lower positions of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are at different depths. The upper and lower positions of the first transfer gate electrode TG1g are lower than those of the second transfer gate electrode TG2g, and the length of the channel length direction of the side wall of the convex region 71 is longer for the first transfer gate electrode TG1g than for the second transfer gate electrode TG2g. Furthermore, the first transfer gate electrode TG1g has a recessed gate electrode TG1gv that is recessed to a predetermined depth within the semiconductor substrate 30.

[0083] In the first to third modifications of the fourth structural example described above, the same effects as the basic structure of the fourth structural example shown in Figure 7 can be achieved. Even when the bottom position of the second transfer gate electrode TG2g is not higher than the bottom position of the first transfer gate electrode TG1g, as in the second modification of the fourth structural example, the second transfer transistor TG2 can be made to function as a charge transfer assistant for the first transfer transistor TG1 by, for example, adjusting the voltage applied to the first transfer gate electrode TG1g and the second transfer gate electrode TG2g, or by adjusting the impurity concentration (potential) of the N-type semiconductor region 61.

[0084] <7. Example of the fifth structure of a pixel> Figure 9 shows an example of the fifth structure of pixel 20.

[0085] Figure 9A is a cross-sectional view of pixel 20 relating to the fifth structural example, and Figure 9B is a top view of the line X-X' in the cross-sectional view of Figure 9A, as seen from the wiring layer side.

[0086] In the first to fourth structural examples described above, the convex region 71 was located in the center of a rectangular pixel region in plan view. In contrast, in the fifth structural example, the convex region 71 is located close to a predetermined side of a rectangular pixel region in plan view, in other words, close to the pixel boundary with an adjacent pixel. Of the four sides surrounding the rectangular convex region 71 in plan view, a P-type semiconductor region 62, identical to the pixel boundary in the semiconductor substrate 30, is formed on the side wall of the side close to the pixel boundary. A first transfer gate electrode TG1g and a second transfer gate electrode TG2g are provided on the three side walls other than the side on which the P-type semiconductor region 62 is formed, via a P-type semiconductor region 63 and an insulating film 72. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are located at different positions in the depth direction.

[0087] Figures 10A and 10B are top views showing the first and second modified examples of the fifth structural example.

[0088] In the basic structure of the fifth structural example shown in Figure 9, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g were formed in a U-shape on the three surrounding side walls of the convex region 71. However, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g do not necessarily have to be formed in a U-shape.

[0089] In the first modified example shown in Figure 10A, the first transfer gate electrode TG1g is formed in a U-shape on the side walls of three sides surrounding the convex region 71, while the second transfer gate electrode TG2g is formed on a predetermined side of the rectangular convex region 71 in plan view, in other words, on the side wall opposite to the side adjacent to the pixel boundary. Conversely, the first transfer gate electrode TG1g may be formed on one side wall, and the second transfer gate electrode TG2g may be formed in a U-shape on the side walls of three sides surrounding the region. The arrangement of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g can be any combination of three sides of a U-shape, two sides of an L-shape, or one side. The second modified example shown in Figure 10B is an example in which the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are formed on the side wall of a predetermined side of the rectangular convex region 71, and the side on which they are formed is different for the first transfer gate electrode TG1g and the second transfer gate electrode TG2g. In this way, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g do not have to overlap in a plan view.

[0090] In the pixel 20 according to the fifth structural example, which includes the above modifications, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress the overlap capacitance between the gate electrode and the floating diffusion FD. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG becomes possible.

[0091] In the fifth structural example described above, the convex region 71 may be positioned at the corner of the pixel boundary so as to be close to two predetermined sides of the rectangular pixel region in a plan view, and the first transfer gate electrode TG1g and the second transfer gate electrode TG2g may be in contact with the two sides of the convex region 71 other than the pixel boundary.

[0092] <8. Example of the sixth structure of a pixel> Figure 11 shows an example of the sixth structure of pixel 20.

[0093] Figure 11A is a cross-sectional view of pixel 20 relating to the sixth structural example, and Figure 11B is a top view of the line X-X' in the cross-sectional view of Figure 11A, as seen from the wiring layer side.

[0094] In the first to fifth structural examples described above, the convex region 71 was formed in a rectangular parallelepiped shape with the same planar size at any position in the depth direction. In contrast, the convex region 71 of the sixth structural example in Figure 11 has a stepped shape in cross-section and has different planar sizes depending on the depth position. The first transfer gate electrode TG1g is provided on the side wall of the first stage, which is closer to the semiconductor substrate 30 than the second transfer gate electrode TG2g, and the second transfer gate electrode TG2g is provided on the side wall of the second stage, which is closer to the floating diffusion FD than the first transfer gate electrode TG1g. The planar size of the convex region 71 differs between the depth position where the first transfer gate electrode TG1g is located and the depth position where the second transfer gate electrode TG2g is located, with the planar size on the side of the first transfer gate electrode TG1g, which is located below the second transfer gate electrode TG2g, being larger than the side of the second transfer gate electrode TG2g. Because the convex region 71 is formed in a stepped shape in cross-section, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g can contact the P-type semiconductor region 63 in which the channel is formed on both the side and bottom surfaces, thereby enhancing the modulation force.

[0095] As shown in Figure 11B, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are formed in a U-shape on the three surrounding side walls of the convex region 71.

[0096] Figures 12A and 12B are top views showing the first and second modified examples of the sixth structural example.

[0097] In the basic structure of the sixth structural example shown in Figure 11, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g were formed in a U-shape on the three side walls surrounding the convex region 71. However, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g do not necessarily have to be formed in a U-shape.

[0098] As shown in the first modified example in Figure 12A, the first transfer gate electrode TG1g may be formed in a U-shape on the side walls of three surrounding sides of the convex region 71, and the second transfer gate electrode TG2g may be formed on the side wall of one predetermined side of the convex region 71, which is rectangular in plan view. Conversely, the first transfer gate electrode TG1g may be formed on one side wall, and the second transfer gate electrode TG2g may be formed in a U-shape on the side walls of three surrounding sides.

[0099] As shown in the second modified example in Figure 12B, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g may each be formed on a predetermined side wall of the rectangular protruding region 71. In the example in Figure 12B, the side on which the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are formed is the side in the same direction, but they may be different sides, as shown in the example in Figure 10B. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g do not have to overlap in a plan view. In Figures 12A and B, the first transfer gate electrode TG1g and the second transfer gate electrode TG2g may be arranged in a way that at least a part of them overlap, or they may not overlap.

[0100] In the pixel 20 according to the sixth structural example, which includes the above modifications, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to mitigate the electric field between the gate electrode and the floating diffusion FD, and to suppress the overlap capacitance between the gate electrode and the floating diffusion FD. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG becomes possible.

[0101] In the sixth structural example described above, the convex region 71 is positioned so as to be close to a predetermined side of a rectangular pixel region in plan view, in other words, close to the pixel boundary. However, as in the first to fourth structural examples described above, the convex region 71 may be positioned in the center of a rectangular pixel region in plan view. For example, a first transfer gate electrode TG1g and a second transfer gate electrode TG2g can be provided so as to surround all four sides of the stepped convex region 71. They may also be provided outside of a predetermined one to three sides of the stepped convex region 71.

[0102] Alternatively, the convex region 71 may be positioned in a plan view at a predetermined corner of a rectangular pixel region so as to be close to two sides of the pixel boundary, and a first transfer gate electrode TG1g and a second transfer gate electrode TG2g may be provided so as to be tangent to two sides of the stepped convex region 71 that are not pixel boundaries.

[0103] <9. Example of the seventh structure of a pixel> Figure 13 shows an example of the seventh structure of pixel 20.

[0104] Figure 13A is a cross-sectional view of pixel 20 relating to the seventh structural example, and Figure 13B is a top view of the line X-X' in the cross-sectional view of Figure 13A, viewed from the wiring layer side. Both Figures 13A and 13B show a 2x2 arrangement of four pixels.

[0105] The seventh structural example shown in Figure 13 illustrates a case where the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are shared by multiple pixels 20, rather than being provided for each pixel as shown in Figure 2. In other words, in the seventh structural example, the photodiode PD, the first transfer transistor TG1, and the second transfer transistor TG2 are provided for each pixel, while the floating diffusion transistor FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL are used in common by the four pixels that form the shared unit.

[0106] In the seventh structural example shown in Figure 13, the photodiode PD, first transfer transistor TG1, and second transfer transistor TG2 of each of the four pixels 20, which constitute a shared unit, are arranged to be symmetrical (mirror symmetrical) in the row and column directions of the pixel array 11. The convex region 71 of each pixel 20 is located in the central part of the 2x2 four pixels in a plan view. The four 2x2 convex regions 71 are arranged facing each other in the row and column directions, with the element isolation region 65 and the P-type semiconductor region 62 in between. The convex region 71 of each pixel 20 is located at a predetermined corner of the rectangular pixel region in a plan view (a corner close to the center of the four pixels), and the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided in an L-shape on the outside of the two sides of the convex region 71 that are farther from the center of the four pixels in a plan view.

[0107] As shown in the cross-sectional view A of Figure 13, the floating diffusion FD (N-type impurity region 64) located above the convex region 71 of each pixel 20 is electrically connected to the floating diffusion FD of other pixels 20 in the shared unit via contact wiring 75, so that substantially one floating diffusion FD is formed for the four pixels of the shared unit.

[0108] The pixel 20 according to the seventh structural example described above can achieve the same effects as the first to sixth structural examples described above. Furthermore, according to the seventh structural example, by using a shared pixel structure in which the floating diffusion transistor FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL are shared by multiple pixels, the area occupied by the elements can be reduced. The extra space can be used for the first transfer gate electrode TG1g and the second transfer gate electrode TG2g, and improvements in characteristics and suppression of variations due to increased transistor size can be expected.

[0109] Note that the shared unit is not limited to 2x2 (4 pixels), but may also consist of multiple pixels other than 4, such as 2x4 (8 pixels).

[0110] <10. Summary of Pixel Structure> The pixels 20 according to the first to seventh structural examples described above include a photoelectric conversion section (N-type semiconductor region 61) formed in an impurity region of a first conductivity type (e.g., N-type) on a semiconductor substrate 30 having a first surface FA in contact with the wiring layer 31 and a second surface SA which is a light incident surface, a first transfer gate electrode TG1g and a second transfer gate electrode TG2g that transfer the charge generated in the photoelectric conversion section, and a floating diffusion FD (N-type impurity region 64) that stores the charge transferred by the first transfer gate electrode TG1g and the second transfer gate electrode TG2g. The N-type semiconductor region 61, which serves as the photoelectric conversion section, has a convex region 71 on the wiring layer 31 side of the first surface FA. The first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided on the side wall of the convex region 71 via an impurity region (P-type semiconductor region 63) of a second conductivity type (e.g., P-type) opposite to the first conductivity type, and at least a portion of the first transfer gate electrode TG1g and the second transfer gate electrode TG2g are provided at different heights in cross-sectional view.

[0111] According to the pixel 20 of the first to seventh structural examples described above, the first transfer transistor TG1 can transfer charge from deep within the photodiode PD, and the second transfer transistor TG2 can assist in the charge transfer of the first transfer transistor TG1. Even when the pixel size is reduced by miniaturization, the channel length can be secured, and a predetermined distance can be secured between the first transfer gate electrode TG1g and the second transfer gate electrode TG2g and the floating diffusion FD. This makes it possible to accommodate pixel miniaturization and to mitigate the electric field between the gate electrode and the floating diffusion FD. In addition, the overlap capacitance between the gate electrode and the floating diffusion FD can also be suppressed. Since the transfer gate length (L) can be extended, a design that is robust to variations in the characteristics of the two transfer transistors TG can be achieved.

[0112] When the vertical drive unit 12 finishes transferring charge to the floating diffusion FD in the pixel 20, it controls the first transfer transistor TG1 (specifically its first transfer gate electrode TG1g) to be turned off, and then the second transfer transistor TG2 (specifically its second transfer gate electrode TG2g) to be turned off. This prevents reverse charge flow from the floating diffusion FD to the photodiode PD.

[0113] In the example described above, the planar shape of the convex region 71 was assumed to be a square (quadrilateral), but the planar shape of the convex region 71 may be a rectangle with different length and width, a circle, a rhombus, or any other shape other than a square.

[0114] <11. Examples of Application to Electronic Devices> The technology of this disclosure is not limited to application to photodetectors. That is, the technology of this disclosure is applicable to all electronic devices that use photodetectors in the image acquisition unit (photoelectric conversion unit), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use photodetectors in the image reading unit. The photodetector may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and the signal processing unit or optical system are packaged together.

[0115] Figure 14 is a block diagram showing an example configuration of an electronic device to which the technology of this disclosure is applied.

[0116] The electronic device 200 in Figure 14 is, for example, an imaging device capable of capturing still and moving images, such as a digital still camera or a digital video camera. The electronic device 200 may also be a mobile phone, smartphone, IoT (Internet of Things) camera, or in-vehicle camera equipped with imaging capabilities.

[0117] The electronic device 200 in Figure 14 includes an optical unit 201 consisting of a lens group, a photodetector (imaging device) 202 employing the configuration of the photodetector 1 in Figure 1, and a DSP (Digital Signal Processor) circuit 203 which is a camera signal processing circuit. The electronic device 200 also includes a frame memory 204, a display unit 205, a recording unit 206, an operation unit 207, and a power supply unit 208. The DSP circuit 203, frame memory 204, display unit 205, recording unit 206, operation unit 207, and power supply unit 208 are interconnected via a bus line 209.

[0118] The optical unit 201 captures incident light (image light) from the subject and forms an image on the imaging surface of the photodetector element 202. The photodetector element 202 converts the amount of incident light formed on the imaging surface by the optical unit 201 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal. As this photodetector element 202, the photodetector element 1 in Figure 1, that is, a photodetector element having a pixel structure in which the photoelectric conversion unit has a protruding region 71 on the wiring layer 31 side from the first surface FA of the semiconductor substrate 30, and a first transfer gate electrode TG1g and a second transfer gate electrode TG2g are provided on the side wall of the protruding region 71, can be used.

[0119] The display unit 205 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays a video or still image captured by the photodetector element 202. The recording unit 206 records the video or still image captured by the photodetector element 202 onto a recording medium such as a hard disk or semiconductor memory.

[0120] The operation unit 207 issues operation commands for various functions of the electronic device 200 under the user's input. The power supply unit 208 appropriately supplies various power sources to the DSP circuit 203, frame memory 204, display unit 205, recording unit 206, and operation unit 207.

[0121] As described above, by using a photodetector 1 having pixels 20 according to the first to seventh structural examples described above as the photodetector 202, it is possible to accommodate pixel miniaturization and to mitigate the electric field between the gate electrode and the floating diffusion FD of the transfer transistor. Therefore, even in electronic devices 200 such as video cameras, digital still cameras, and camera modules for mobile devices such as mobile phones, miniaturization and improved image quality of captured images can be achieved.

[0122] <Example of Image Sensor Usage> Figure 15 shows an example of using the image sensor with the above-described photodetector 1.

[0123] The above-described photodetector 1 can be used as an image sensor in various cases where light such as visible light, infrared light, ultraviolet light, and X-rays is sensed, for example, as follows.

[0124] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0125] In the example described above, a photodetector element using electrons as the signal charge was explained, with the first conductivity type being N-type and the second conductivity type being P-type. However, this disclosure can also be applied to a photodetector element using holes as the signal charge. In this case, the first conductivity type can be P-type and the second conductivity type can be N-type, and the aforementioned semiconductor regions can be composed of semiconductor regions of the opposite conductivity types.

[0126] Furthermore, this disclosure is not limited to photodetectors that detect the distribution of incident light intensity of visible light and capture it as an image, but is also applicable to photodetectors that capture the distribution of incident light intensity of infrared rays, X-rays, or particles as an image, and in a broader sense, to all photodetectors (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture it as an image.

[0127] Furthermore, the technology disclosed herein is applicable not only to photodetectors but also to semiconductor devices in general that have other semiconductor integrated circuits.

[0128] The embodiments of this disclosure are not limited to those described above, and various modifications are possible without departing from the gist of the technology of this disclosure.

[0129] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0130] The technology of this disclosure may adopt the following configurations: (1) A photodetector comprising: a semiconductor substrate having a first surface in contact with a wiring layer and a second surface which is an incident light surface; a photoelectric conversion section formed on the semiconductor substrate in an impurity region of a first conductivity type; a first transfer gate electrode and a second transfer gate electrode for transferring the charge generated in the photoelectric conversion section; and a floating diffusion for accumulating the charge transferred by the first transfer gate electrode and the second transfer gate electrode, wherein the photoelectric conversion section has a convex region on the wiring layer side of the first surface, the first transfer gate electrode and the second transfer gate electrode are provided on the sidewall of the convex region via an impurity region of a second conductivity type opposite to the first conductivity type, and at least a portion of the first transfer gate electrode and the second transfer gate electrode are provided at different heights in cross-sectional view. (2) The photodetector according to (1), wherein the first transfer gate electrode is provided on both the sidewall of the convex region and the first surface so as to be in contact with the impurity region of the second conductivity type via an insulating film. (3) The photodetector element according to (1) or (2) above, wherein the first transfer gate electrode and the second transfer gate electrode are provided so as to surround the outer periphery of the convex region in a plan view. (4) The photodetector element according to any one of (1) to (3) above, wherein the first transfer gate electrode and the second transfer gate electrode are provided so as to face each other across the convex region in a plan view. (5) The photodetector element according to (1) or (2) above, wherein the first transfer gate electrode is provided so as to surround the outer periphery of the convex region in a plan view, and the second transfer gate electrode is provided so as to surround a part of the outer periphery of the convex region in a plan view. (6) The photodetector element according to any one of (1) to (5) above, wherein the first transfer gate electrode and the second transfer gate electrode are provided so as to overlap at least a part of them in a plan view. (7) The photodetector element according to any one of (1) to (5) above, wherein the first transfer gate electrode and the second transfer gate electrode are provided in positions where they do not overlap in a plan view. (8) The photodetector according to any one of (1) to (7), wherein the first transfer gate electrode and the second transfer gate electrode are provided at different depth positions and with the same thickness.(9) The photodetector element according to any one of (1) to (7), wherein the first transfer gate electrode and the second transfer gate electrode are provided at the same upper surface position but at different lower surface positions. (10) The photodetector element according to any one of (1) to (7), wherein the first transfer gate electrode and the second transfer gate electrode are provided at the same lower surface position but at different upper surface positions. (11) The photodetector element according to any one of (1) to (10), wherein the first transfer gate electrode has a recessed gate electrode that is recessed to a predetermined depth in the semiconductor substrate. (12) The photodetector element according to any one of (1) to (11), wherein the convex region is provided so as to be close to a predetermined pixel boundary on one side of a rectangular pixel region in a plan view, and the first transfer gate electrode and the second transfer gate electrode are provided on the side wall of the convex region other than the pixel boundary. (13) The photodetector element according to any one of (1) to (12), wherein the convex region has a stepped shape in cross-sectional view, the first transfer gate electrode is provided on the side wall of the first stage closer to the semiconductor substrate than the second transfer gate electrode, and the second transfer gate electrode is provided on the side wall of the second stage closer to the floating diffusion than the first transfer gate electrode. (14) The photodetector element according to any one of (1) to (13), wherein the floating diffusion is electrically connected to the floating diffusion of other pixels via contact wiring and shared by multiple pixels. (15) The photodetector element according to (14), wherein the shared unit is 2x2 4 pixels, and the convex region is located at the corner near the center of the 4 pixels in plan view. (16) The photodetector element according to any one of (1) to (15), wherein when charge transfer to the floating diffusion is terminated, the second transfer gate electrode is controlled to be turned off after the first transfer gate electrode is turned off.

[0131] 1 Photodetector, 11 Pixel array section, 12 Vertical drive section, 20 Pixel, 30 Semiconductor substrate, 31 Wiring layer, 50 Pixel, 61 N-type semiconductor region, 62 P-type semiconductor region, 63 P-type semiconductor region, 64 N-type impurity region, 71 Convex region, 72 Insulating film, 73-75 Contact wiring, 600 Electronic device, 602 Photodetector, FA First surface, SA Second surface, PD Photodiode, TG1 First transfer transistor, TG1g First transfer gate electrode, TG1gv Recessed gate electrode, TG2 Second transfer transistor, TG2g Second transfer gate electrode, FD Floating diffusion, AMP Amplifier transistor, RST Reset transistor, SEL Selector transistor

Claims

1. A photodetector comprising: a semiconductor substrate having a first surface in contact with a wiring layer and a second surface which is a light incident surface; a photoelectric conversion section formed on the semiconductor substrate in an impurity region of a first conductivity type; a first transfer gate electrode and a second transfer gate electrode for transferring charge generated in the photoelectric conversion section; and a floating diffusion for accumulating charge transferred by the first transfer gate electrode and the second transfer gate electrode, wherein the photoelectric conversion section has a convex region on the wiring layer side of the first surface, the first transfer gate electrode and the second transfer gate electrode are provided on the side wall of the convex region via an impurity region of a second conductivity type opposite to the first conductivity type, and at least a portion of the first transfer gate electrode and the second transfer gate electrode are provided at different heights in cross-sectional view.

2. The photodetector element according to claim 1, wherein the first transfer gate electrode is provided so as to be in contact with the impurity region of the second conductivity type via an insulating film on both the side wall of the convex region and the first surface.

3. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are provided so as to surround the outer periphery of the convex region in a plan view.

4. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are arranged to face each other in a plan view, with the convex region in between.

5. The photodetector element according to claim 1, wherein the first transfer gate electrode is provided so as to surround the outer periphery of the convex region in a plan view, and the second transfer gate electrode is provided so as to surround a part of the outer periphery of the convex region in a plan view.

6. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are arranged so that at least a portion of them overlap in a plan view.

7. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are provided in positions that do not overlap in a plan view.

8. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are provided at different depth positions and with the same thickness.

9. The photodetector element according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are provided at the same upper surface position but at different lower surface positions.

10. The photodetector according to claim 1, wherein the first transfer gate electrode and the second transfer gate electrode are provided at the same bottom position but at different top positions.

11. The photodetector according to claim 1, wherein the first transfer gate electrode is a recessed gate electrode that is recessed to a predetermined depth in the semiconductor substrate.

12. The photodetector element according to claim 1, wherein the convex region is provided so as to be close to a predetermined pixel boundary on one side of a rectangular pixel region in a plan view, and the first transfer gate electrode and the second transfer gate electrode are provided on the side wall of the convex region other than the pixel boundary, via the impurity region of the second conductivity type and an insulating film.

13. The photodetector element according to claim 1, wherein the convex region has a stepped shape in cross-section, the first transfer gate electrode is provided on the side wall of the first stage which is closer to the semiconductor substrate than the second transfer gate electrode, and the second transfer gate electrode is provided on the side wall of the second stage which is closer to the floating diffusion than the first transfer gate electrode.

14. The photodetector element according to claim 1, wherein the floating diffusion is electrically connected to the floating diffusion of other pixels via contact wiring and shared by a plurality of pixels.

15. The photodetector element according to claim 14, wherein the shared unit is 2x2 4 pixels, and the convex region is located at the corners close to the center of the 4 pixels in a plan view.

16. The photodetector according to claim 1, wherein, when terminating the charge transfer to the floating diffusion, the second transfer gate electrode is controlled to be turned off after the first transfer gate electrode is turned off.

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