Communication control device, communication control method, and program
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2026-01-20
- Publication Date
- 2026-08-13
Smart Images
Figure JP2026001605_13082026_PF_FP_ABST
Abstract
Description
Communication control device, communication control method, and program
[0001] The present disclosure relates to a communication control device, a communication control method, and a program, and more particularly to a communication control device, a communication control method, and a program that can improve usability more.
[0002] Conventionally, I3C (Improved Inter Integrated Circuits) has been established as a communication standard that enables faster and more efficient communication between ICs (Integrated Circuits) by the MIPI (Mobile Industry Processor Interface) Alliance. In I3C, a communication system is configured by a host device having the function of a primary controller that mainly controls communication and a target device that communicates subordinate to the control by the host device.
[0003] Also, in I3C, a Multiple Controllers function is defined that enables the transfer of a controller right, which is the right to control communication as a controller device. Thereby, it is possible to provide a target device having the function of a secondary controller that normally operates as a target device and can control communication as a controller device when the controller right is transferred from the host device. For example, in a communication system configured with a plurality of sensor devices operating as target devices, a sensor device having the function of a secondary controller can be used as a sensor hub device that controls communication with a plurality of sensor devices other than that sensor device.
[0004] For example, Patent Document 1 discloses a communication system in which a master determines whether or not a secondary master that has made a request has group management ability when transferring the leadership of communication in response to a request from the secondary master.
[0005] Japanese Patent Application Laid-Open No. 2018-206267
[0006] Incidentally, when a CIS (CMOS (Complementary Metal Oxide Semiconductor) Image Sensor) device, which is a sensor device equipped with secondary controller functionality, has controller rights, it is necessary to prioritize the imaging control processing during image acquisition, which sometimes caused a delay in the timing of transmitting correction information to other sensor devices. As a result, if other sensor devices were unable to perform correction processing based on the correction information, synchronization discrepancies could accumulate between the CIS device and the other sensor devices.
[0007] Furthermore, in addition to timing control, I3C requires complex processing flows for device control, and error handling at each step of these processing flows is diverse. As a result, there are concerns that the processing flow executed by the host CPU (Central Processing Unit) of the CIS device to which controller rights have been transferred may become complicated or the processing load may increase, leading to a decrease in the availability of the communication system.
[0008] This disclosure is made in light of these circumstances and aims to improve availability.
[0009] A communication control device according to one aspect of this disclosure includes a host CPU that controls the entire device, including communication control of communication in accordance with a predetermined communication standard, and a secondary controller that normally operates as a target device in the communication standard according to instructions from the host CPU, and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, wherein the secondary controller has a system control unit that executes firmware layer processing, which is part of the communication control, according to instructions from the host CPU when it has controller rights, and a controller that executes hardware layer processing in the communication control when it has controller rights.
[0010] A communication control method according to one aspect of the present disclosure is a communication control method for a communication control device comprising: a host CPU that controls the entire device, including communication control of communication in accordance with a predetermined communication standard; and a secondary controller that normally operates as a target device in the communication standard and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, wherein the secondary controller, when it has controller rights, executes firmware layer processing which is part of the communication control according to instructions from the host CPU; and when it has controller rights, executes hardware layer processing in the communication control.
[0011] A program in one aspect of this disclosure causes a computer for a communication control device, which includes a host CPU that controls the entire device, including communication control of communication in accordance with a predetermined communication standard, and a secondary controller that normally operates as a target device in the communication standard and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, to execute a process in which, when the secondary controller has controller rights, it executes a process that includes executing firmware layer processing, which is part of the communication control, in accordance with instructions from the host CPU, and executing hardware layer processing in the communication control, when the secondary controller has controller rights.
[0012] In one aspect of this disclosure, the communication control device includes a host CPU that controls the entire device, including communication control of communications in accordance with a predetermined communication standard, and a secondary controller that normally operates as a target device in the communication standard according to instructions from the host CPU, and performs communication control as a controller device when controller rights are transferred from the host device in the communication standard. In the system control unit of the secondary controller, when it has controller rights, it executes firmware layer processing, which is part of the communication control, according to instructions from the host CPU, and in the controller of the secondary controller, when it has controller rights, it executes hardware layer processing in the communication control.
[0013] This is a block diagram illustrating an example configuration of a communication system to which this technology is applied. This is a diagram illustrating an example configuration of an I3C control model. This is a timing chart illustrating the timing at which synchronization correction processing is performed. This is a diagram illustrating an example sequence of I3C bus initialization processing in a conventional method. This is a diagram illustrating an example sequence of I3C bus initialization processing to which this technology is applied. This is a flowchart illustrating I3C bus initialization processing. This is a diagram illustrating an example sequence of timing control processing. This is a timing chart illustrating timing control processing. This is a diagram illustrating an example sequence of I3C role change processing. This is a flowchart illustrating I3C role change processing. This is a block diagram illustrating an example configuration of a computer to which this technology is applied.
[0014] The following describes in detail a specific embodiment of this technology, with reference to the drawings.
[0015] <Example of Communication System Configuration> Figure 1 is a block diagram showing an example configuration of one embodiment of a communication system to which this technology is applied.
[0016] As shown in Figure 1, the communication system 11 is configured such that a CIS device 21, an I3C sensor device 22, and a processor 23 are connected via an I3C bus, and they communicate with each other according to the I3C communication standard.
[0017] The CIS device 21 normally operates as a target device for communication via the I3C bus, and when controller rights are transferred from a host device (not shown), it can control communication via the I3C bus as a controller device. In addition, the CIS device 21 can transmit image data to the processor 23 using communication standards other than I3C, such as CIS-2 (Camera Serial Interface -2).
[0018] The I3C sensor device 22 operates as a target device that communicates via the I3C bus according to the control of the CIS device 21, which has controller rights. For example, the I3C sensor device 22 can output sensing data acquired by performing various sensing operations in synchronization with the CIS device 21.
[0019] The processor 23 operates as a target device that communicates via the I3C bus in accordance with the control of the CIS device 21, which has controller rights. The processor 23 also has a receiving unit 71 that receives data in accordance with the CIS-2 communication standard. For example, the processor 23 can acquire image data transmitted from the CIS device 21 and sensing data output from the I3C sensor device 22, and perform data processing on that data.
[0020] As shown in the figure, the CIS device 21 is configured by connecting a host CPU 41, memory 42, and I3C secondary controller 43 provided in the control unit 31, and an analog processing unit 61 and a digital processing unit 62 provided in the imaging processing unit 32, via a bus.
[0021] The host CPU 41 can perform various processes necessary for the overall control of the CIS device 21, including communication control in accordance with I3C, and can issue instructions to each block that constitutes the CIS device 21. In addition, the host CPU 41 can perform imaging control processing to control the imaging processing performed by the imaging processing unit 32 for each VSYNC, which is the vertical synchronization signal of the image frame captured by the CIS device 21.
[0022] Memory 42 stores various information necessary for the host CPU 41 to execute processing.
[0023] The I3C secondary controller 43 comprises an I3C system control unit 51, a memory 52, an I3C target 53, an I3C HCI (Host Controller Interface) 54, an I3C controller 55, and a multiplexer 56. The I3C secondary controller 43 normally operates as a target device in accordance with instructions from the host CPU 41, and when controller rights are transferred from a host device (not shown), it can control communication via the I3C bus as a controller device.
[0024] The I3C system control unit 51 is firmware (FW) that performs some control over communication via the I3C bus in the communication system 11 when the CIS device 21 has controller rights. For example, the CIS device 21 can implement firmware that performs some control over communication via the I3C bus from the host CPU 41 to the I3C secondary controller 43 using an API (Application Programming Interface).
[0025] Memory 52 stores various information necessary for the I3C system control unit 51 to execute control. For example, memory 52 stores information such as the presence or absence of various parameters and options supplied from the host CPU 41.
[0026] The I3C target 53 is hardware (HW) that becomes active when the CIS device 21 operates as a target device and communicates via the I3C bus according to the control of a host device (not shown) that has controller rights. The I3C target 53 is inactive when the CIS device 21 has controller rights.
[0027] The I3C HCI 54 is a standardized interface for controlling communication over the I3C bus, and provides the I3C controller 55 with a set of commands used for communication with, for example, the I3C sensor device 22 and the processor 23.
[0028] The I3C controller 55 is hardware (HW) that becomes active when the CIS device 21 has controller rights and controls communication via the I3C bus based on control by the I3C system control unit 51.
[0029] The multiplexer 56 can switch between inputting and outputting signals between the I3C target 53 and the I3C bus, and inputting and outputting signals between the I3C controller 55 and the I3C bus. For example, when the I3C controller 55 is active, the multiplexer 56 outputs signals supplied from the I3C controller 55 to the I3C bus and supplies signals input via the I3C bus to the I3C controller 55.
[0030] The analog processing unit 61 performs analog processing such as noise reduction on the pixel signals supplied from pixels (not shown), and also performs analog-to-digital (AD) conversion, and supplies the image data obtained by the AD conversion to the digital processing unit 62.
[0031] The digital processing unit 62 performs digital image processing on the image data supplied from the analog processing unit 61, and then transmits the image data to the processor 23 via the transmission unit 63, which transmits data according to the CIS-2 communication standard. The processor 23 receives the image data transmitted from the transmission unit 63 via the receiving unit 71.
[0032] In the communication system 11 configured as described above, the CIS device 21 can control communication via the I3C bus with the help of the hardware I3C controller 55 and the firmware I3C system control unit 51. For example, the I3C control model of the communication system 11 is configured such that some processing of the Device Driver layer and processing of the I3C HC (Host Controller) Driver layer are executed by the firmware I3C system control unit 51 as processing of the I3C system FW layer.
[0033] As a result, the communication system 11 can achieve improved availability compared to a communication system of the I3C control model (hereinafter referred to as a conventional communication system) which is configured to perform control related to I3C communication by an I3C controller and a host CPU, for example.
[0034] Referring to Figure 2, an example of the I3C control model configuration will be explained. In MIPI I3C, for example, a modeling approach aimed at standardizing the driver hierarchy has been proposed as an I3C Bus Controller control method.
[0035] Figure 2A shows an example configuration of an I3C control model in a conventional communication system, and Figure 2B shows an example configuration of an I3C control model in communication system 11.
[0036] In conventional communication systems, as shown in Figure 2A, the I3C control model was configured such that the host CPU performed processing at the System Agent layer, the Device Driver layer, and the I3C HC Driver layer, while the I3C controller performed processing at the I3C HW layer.
[0037] In contrast, in the communication system 11, as shown in Figure 2B, the I3C control model is configured such that some of the processing in the Device Driver layer is API-based and executed by the I3C system control unit 51. Therefore, the I3C control model is configured such that the host CPU 41 executes the processing in the System Agent layer and some of the processing in the Device Driver layer, the I3C system control unit 51 executes the processing in the I3C system FW layer, which includes some of the processing in the Device Driver layer, and the I3C controller 55 executes the processing in the I3C HW layer.
[0038] Thus, the communication system 11 can perform synchronization correction processing that enables more reliable synchronization with the I3C sensor device 22 by providing, for example, an I3C system control unit 51 equipped with an I3C timing control function that controls the timing of communication via the I3C bus, independently of the host CPU 41.
[0039] Referring to Figure 3, the timing of the synchronization correction process that corrects the synchronization with the I3C sensor device 22 will be explained.
[0040] For example, in I3C, the CIS device 21 equipped with an I3C secondary controller 43 can act as a VSYNC master itself, controlling the imaging process for each image frame, and using the I3C timing control function to perform synchronization control to the I3C sensor device 22 with a synchronization accuracy of several tens of nanoseconds. Furthermore, in the I3C timing control function, unless there is a special agreement between the devices, the VSYNC, which is the vertical synchronization signal of the image frame, coincides with the I3C synchronization correction reference time, which is the reference for correcting synchronization between the CIS device 21 and the I3C sensor device 22 at each synchronization correction interval (TPH).
[0041] Therefore, the CIS device 21 will perform imaging control processing and synchronization correction processing simultaneously. Further, in order to suppress the correction accuracy (synchronization accuracy) to several tens of nanoseconds, according to the I3C standard, the delay time DT from the I3C synchronization correction reference time until the correction information is transmitted must be within the correction possible period (within several microseconds from the I3C synchronization correction reference time) during which the I3C sensor device 22 can execute correction processing based on the correction information.
[0042] In FIG. 3A, a timing chart of the synchronization correction processing in the conventional communication system is shown, and in FIG. 3B, a timing chart of the synchronization correction processing in the communication system 11 is shown.
[0043] As shown in FIG. 3A, in the conventional communication system, the imaging control processing and the synchronization correction processing are performed by the host CPU. Therefore, as described above, when VSYNC and the I3C synchronization correction reference time coincide, the host CPU will perform the imaging control processing preferentially and then perform the synchronization correction processing. By the way, since the time required for the imaging control processing varies according to imaging conditions such as the shutter speed, for example, the timing at which the synchronization correction processing starts with respect to the I3C synchronization correction reference time will change. For this reason, the delay time DT from the I3C synchronization correction reference time until the I3C controller starts transmitting the correction information in the synchronization correction processing will also change according to the time required for the imaging control processing.
[0044] For example, at the I3C synchronization correction reference time of the timing t1 shown in FIG. 3A, since the time required for the imaging control processing is short, the I3C controller can transmit the correction information within the correction possible period of the I3C sensor device (delay time DT < correction possible period (several microseconds)). Therefore, in this case, the I3C sensor device can execute the correction processing based on the correction information.
[0045] On the other hand, at the I3C synchronization correction reference time of timing t2 shown in A of FIG. 3, since the time required for the imaging control process is long, the I3C controller cannot transmit correction information within the correction possible period of the I3C sensor device (delay time DT > correction possible period (several μs)). Therefore, in this case, the I3C sensor device cannot execute the correction process based on the correction information.
[0046] As described above, in the conventional communication system, as a result of the host CPU prioritizing the imaging control process, when the correction information is transmitted after the correction possible period has timed out, the I3C sensor device cannot execute the correction process based on the correction information.
[0047] On the other hand, as shown in B of FIG. 3, in the communication system 11, the synchronization correction process is performed by the I3C system control unit 51 independently of the imaging control process performed by the host CPU 41. Therefore, even if the time required for the imaging control process changes, the I3C system control unit 51 can start the synchronization correction process at a substantially constant timing from the I3C synchronization correction reference time. As a result, the delay time DT from the I3C synchronization correction reference time until the I3C controller 55 starts transmitting the correction information in the synchronization correction process can always be within the correction possible period of the I3C sensor device 22.
[0048] For example, even when the time required for the imaging control process is short, such as at the I3C synchronization correction reference time of timing t1 shown in B of FIG. 3, or when the time required for the imaging control process is long, such as at the I3C synchronization correction reference time of timing t2 shown in B of FIG. 3, the I3C controller 55 can transmit the correction information within the correction possible period of the I3C sensor device 22 (delay time DT < correction possible period (several μs)). Therefore, in this case, the I3C sensor device 22 can always execute the synchronization correction.
[0049] Therefore, since the communication system 11 can always perform synchronization correction on the I3C sensor device 22, the CIS device 21 can reliably synchronize the I3C sensor device 22. Furthermore, the communication system 11 can reduce the processing load on the host CPU 41 by having the I3C system control unit 51 perform the synchronization correction processing.
[0050] Furthermore, the communication system 11 is configured such that, in addition to the synchronization correction processing, some control in communication via I3C (for example, some processing in the Device Driver layer) is executed in the I3C system control unit 51. Therefore, the communication system 11 can reduce the processing load on the host CPU 41 and avoid the complexity of the processing flow in device control and error handling when errors occur in communication via the I3C bus. As a result, the communication system 11 can achieve improved availability compared to conventional communication systems.
[0051] <Example of I3C bus initialization process> The I3C bus initialization process will be explained with reference to Figures 4 to 6.
[0052] For example, during the I3C bus initialization process, commands such as SETDASA (SET Dynamic Address from Static Address), SETAASA (SET Assigned Address from Static Address), ENTDAA (Enter Dynamic Address Assignment), and DEFTGTS (DEFinition of Target Status) are sent from the CIS device 21 to the I3C sensor device 22 using CCC (Common Command Code). SETDASA is a command to assign a dynamic address to an I3C device that has a known static address; SETAASA is a command to set a static address for all devices on the I3C bus; ENTDAA is a command to assign a dynamic address to all devices on the bus; and DEFTGTS is a command to define a list of target devices on the I3C bus.
[0053] Figure 4 shows an example sequence of I3C bus initialization processing in a conventional communication system. As explained with reference to the example configuration of the I3C control model shown in Figure 2A above, in a conventional communication system, the host CPU executes the processing of the System Agent layer, the Device Driver layer, and the I3C HC Driver layer.
[0054] Therefore, as shown in Figure 4, in the conventional communication system, after the host CPU performs a device initialization entry, it is necessary to send SETDASA and SETAASA via the I3C controller, then confirm the assignment of the I3C device and obtain device information, send ENTDAA, then confirm the assignment of the I3C device and obtain device information again, and then send DEFTGTS.
[0055] Figure 5 shows an example sequence of the I3C bus initialization process in the communication system 11. As explained with reference to the example configuration of the I3C control model shown in Figure 2B above, in the communication system 11, the host CPU 41 executes the processing of the System Agent layer and some of the processing of the Device Driver layer, and the I3C system control unit 51 executes the processing of the I3C system FW layer (some other processing of the Device Driver layer and processing of the I3C HC Driver layer).
[0056] Therefore, as shown in Figure 5, in the communication system 11, the host CPU 41 only needs to perform a device initialization entry, which involves writing the parameters necessary for the I3C bus initialization process to the memory 52 of the I3C system control unit 51. After the device initialization entry is performed, when the host CPU 41 instructs the execution of the I3C bus initialization process, the I3C system control unit 51 starts the I3C bus initialization process, sends SETDASA and SETAASA via the I3C controller 55, then confirms the assignment of the I3C device and acquires device information, sends ENTDAA, then confirms the assignment of the I3C device and acquires device information again, and can send DEFTGTS.
[0057] In this way, the communication system 11 can reduce the processing load on the host CPU 41 compared to conventional communication systems. Furthermore, in the communication system 11, the interface with the host CPU 41 becomes more general-purpose during the I3C bus initialization process, which facilitates system switching and switching of communication means control.
[0058] Figure 6 is a flowchart illustrating the I3C bus initialization process.
[0059] In step S11, the I3C system control unit 51 determines whether or not the host CPU 41 has instructed it to execute the I3C bus initialization process, and waits until it determines that it has been instructed to execute the I3C bus initialization process. If the I3C system control unit 51 determines in step S11 that it has been instructed to execute the I3C bus initialization process, the process proceeds to step S12, and the I3C bus initialization process is started.
[0060] In step S12, the I3C system control unit 51 reads the parameters necessary for initialization from the memory 52. For example, the memory 52 has been pre-stored by the host CPU 41 with information indicating the presence or absence of various parameters and options.
[0061] In step S13, the I3C system control unit 51 sends SETDASA and SETAASA to the I3C sensor device 22 and assigns a dynamic address and a static address.
[0062] In step S14, the I3C system control unit 51 acquires device information (device attributes and device status) transmitted from the I3C sensor device 22.
[0063] In step S15, the I3C system control unit 51 transmits ENTDAA, DEFTGTS, etc., and manages the communication method so that communication via the I3C bus is optimized.
[0064] In step S16, the I3C system control unit 51 determines whether or not a processing error occurred during the processing in steps S12 to S15.
[0065] In step S16, if the I3C system control unit 51 determines that a processing error has occurred, the initialization of the I3C bus fails, and the I3C bus initialization process terminates with an error. On the other hand, in step S16, if the I3C system control unit 51 determines that no processing error has occurred, the initialization of the I3C bus succeeds, and the I3C bus initialization process terminates normally.
[0066] As described above, in the communication system 11, the I3C system control unit 51, which is instructed by the host CPU 41 to execute processing, performs I3C bus initialization processing, thereby reducing the processing load on the host CPU 41 compared to conventional communication systems. Furthermore, if a processing error occurs during the I3C bus initialization processing, the I3C system control unit 51 performs error handling, which simplifies the processing flow compared to, for example, a case where the host CPU 41 performs error handling.
[0067] <Example of Timing Control Processing> The timing control processing will be explained with reference to Figures 7 and 8.
[0068] Figure 7 shows an example sequence of timing control processing in the communication system 11.
[0069] As shown in Figure 7, in the communication system 11, the host CPU 41 performs a timing control information entry, writing the parameters necessary for timing control processing to the memory 52 of the system control unit 51. After the timing control information entry is made, when the host CPU 41 instructs the execution of timing control processing, the I3C system control unit 51 starts timing control processing.
[0070] First, in the timing control process, the I3C system control unit 51 performs a start process. For example, in the start process, the I3C system control unit 51 sets and activates the timing control counter to the I3C controller 55, and transmits the synchronization signal ST and delay time DT to the I3C sensor device 22 via the I3C controller 55.
[0071] Next, in the timing control process, the I3C system control unit 51 performs loop processing. For example, in the loop processing, the I3C system control unit 51 performs synchronization correction processing (Hander(TC Resync)) to maintain synchronization with the I3C sensor device 22 by sending a synchronization signal ST to the I3C sensor device 22 via the I3C controller 55, and after obtaining the delay time DT at the time the synchronization signal ST was sent from the I3C controller 55, it sends the delay time DT to the I3C sensor device 22 via the I3C controller 55. After that, the I3C system control unit 51 sends GETSTATUS Format2, which is a CCC command for obtaining the status of other I3C devices, to the I3C sensor device 22.
[0072] As described above, in the communication system 11, the I3C system control unit 51 performs timing control processing, which reduces the processing load on the host CPU 41 compared to conventional communication systems.
[0073] Figure 8 is a timing chart illustrating the timing control process.
[0074] For example, synchronization between the I3C controller 55 and the I3C sensor device 22 is defined in I3C as Timing Control, and the I3C controller 55 can notify the I3C bus of the start of a specific period (T_Ph) (SYNC Tick). The I3C controller 55 can then notify the I3C sensor device 22 of the delay time DT from the end of T_Ph until it outputs the SYNC Tick, but in I3C, the size of the delay time DT is limited to 1 byte.
[0075] Incidentally, the I3C controller 55 needs to determine the correction period by pre-setting a unit time with the I3C controller 55 so that the delay time DT fits within 1 byte, and the larger the delay time DT, the lower the synchronization accuracy becomes. Therefore, in the communication system 11, by providing an I3C system control unit 51, Timing Control can be performed regardless of the load status of the host CPU 41, so that the delay time DT can be shortened, and as a result, a decrease in synchronization accuracy can be avoided.
[0076] Furthermore, in the communication system 11, as shown in Figure 8, the I3C system control unit 51 performs synchronization correction processing, enabling the transmission of correction information via the I3C bus (SDA and SCL) within the correction period of the I3C sensor device 22.
[0077] <Example of I3C Role Change Processing> Referring to Figures 9 and 10, the I3C role change processing in which the CIS device 21 changes roles from a controller device to a target device (i.e., the CIS device 21 transfers controller rights to another I3C device (for example, a host device not shown)) will be described.
[0078] Figure 9 shows an example sequence of I3C role change processing in the communication system 11.
[0079] As shown in Figure 9, in the communication system 11, the host CPU 41 performs a role change information entry, writing the parameters necessary for the I3C role change process to the memory 52 of the I3C system control unit 51. After the role change information entry is made, when the host CPU 41 instructs the execution of the I3C role change process, the I3C system control unit 51 starts the I3C role change process from the controller device to the target device.
[0080] First, in the I3C role change process, the I3C system control unit 51 broadcasts a DISEC (Disable Target Events Command), which is a CCC command to disable the generation of specific events on the I3C bus.
[0081] The I3C system control unit 51 then performs a resynchronization (first option) to adjust the timing of operations with other I3C devices. First, the I3C system control unit 51 refers to the device information written to memory 52 and sends DEFTGTS, a CCC command to define a list of target devices on the I3C bus. Next, the I3C system control unit 51 refers to the device information written to memory 52 and sends GRPA (Get Role of Peripheral Address), a CCC command to check what role other I3C devices to which controller rights are to be transferred currently have (second option). Furthermore, the I3C system control unit 51 sends GETSTATUS Format2, a CCC command to obtain the status of other I3C devices.
[0082] Subsequently, the I3C system control unit 51 sends a GETACCCR (Get Accept Controller Role) command, which is a CCC command to check whether the host device accepts the role change, and then monitors the status of the role change process via the I3C controller 55.
[0083] As described above, in the communication system 11, the I3C system control unit 51 performs a Role Change process, which reduces the processing load on the host CPU 41 compared to conventional communication systems.
[0084] Figure 10 is a flowchart illustrating the I3C role change process.
[0085] In step S21, the I3C system control unit 51 determines whether or not the host CPU 41 has instructed it to execute the I3C role change process, and waits until it determines that it has been instructed to execute the I3C role change process. If the I3C system control unit 51 determines in step S21 that it has been instructed to execute the I3C role change process, the process proceeds to step S22, and the Handoff preparation process begins.
[0086] In step S22, the I3C system control unit 51 reads the parameters necessary to perform the role change from the memory 52. For example, the memory 52 has been pre-stored by the host CPU 41 with information indicating the presence or absence of various parameters and options.
[0087] In step S23, the I3C system control unit 51 sends CCC commands necessary to perform the role change (such as DISEC, DEFTGTS, GRPA, GETSTATUS Format2, etc., as described above in Figure 9).
[0088] In step S24, the I3C system control unit 51 determines whether or not an error occurred with respect to the CCC command sent in step S23.
[0089] In step S24, if the I3C system control unit 51 determines that an error has occurred with respect to the CCC command, the Handoff preparation process fails, and the I3C role change process terminates with an error. On the other hand, in step S24, if the I3C system control unit 51 determines that no error has occurred with respect to the CCC command, the Handoff preparation process succeeds, and the process proceeds to step S25.
[0090] In step S25, the I3C system control unit 51 sends GETACCCR, a CCC command, to check whether the host device accepts the role change. If an error occurs with GETACCCR, the role change fails, and the I3C role change process terminates with an error.
[0091] In step S26, the I3C system control unit 51 monitors the status of the host device in response to GETACCCR transmitted in step S25 and determines whether the host device was able to accept the role change.
[0092] In step S26, if the I3C system control unit 51 determines that the host device could not accept the role change, for example, if a controller error condition occurs in the host device, the role change fails and the I3C role change process terminates with an error. On the other hand, if the I3C system control unit 51 determines that the host device was able to accept the role change, the role change is successful and the I3C role change process terminates normally.
[0093] As described above, in the communication system 11, the I3C system control unit 51, which is instructed to execute processing by the host CPU 41, performs I3C role change processing, thereby reducing the processing load on the host CPU 41 compared to conventional communication systems. Furthermore, if a processing error occurs during I3C role change processing, the I3C system control unit 51 performs error handling, which simplifies the processing flow compared to, for example, if the host CPU 41 performs the error handling.
[0094] <Example of Computer Configuration> Next, the series of processes described above (communication control method) can be performed by hardware or by software. When the series of processes are performed by software, the programs that make up that software are installed on a general-purpose computer or the like.
[0095] Figure 8 is a block diagram showing an example configuration of one embodiment of a computer on which the program that performs the series of processes described above is installed.
[0096] In a computer, the CPU (Central Processing Unit) 101, ROM (Read Only Memory) 102, RAM (Random Access Memory) 103, and EEPROM (Electronically Erasable and Programmable Read Only Memory) 104 are interconnected by a bus 105. An input / output interface 106 is further connected to the bus 105, and the input / output interface 106 is connected to an external device.
[0097] In a computer configured as described above, the CPU 101 loads programs stored in ROM 102 and EEPROM 104 into RAM 103 via bus 105 and executes them, thereby performing the series of processes described above. In addition, programs executed by the computer (CPU 101) can be pre-written to ROM 102, or installed or updated from an external source via input / output interface 106 into EEPROM 104.
[0098] In this specification, the processes performed by a computer according to a program do not necessarily have to be performed chronologically in the order described in the flowchart. That is, the processes performed by a computer according to a program include processes that are executed in parallel or individually (e.g., parallel processing or object-based processing).
[0099] Furthermore, the program may be processed by a single computer (processor), or it may be processed in a distributed manner by multiple computers. Moreover, the program may be transferred to a remote computer for execution.
[0100] Furthermore, in this specification, a system means a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure or not. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device in which multiple modules are housed in one enclosure, are both considered systems.
[0101] Furthermore, for example, the configuration described as a single device (or processing unit) may be divided and configured as multiple devices (or processing units). Conversely, the configurations described above as multiple devices (or processing units) may be combined and configured as a single device (or processing unit). It is also possible to add configurations other than those described above to the configuration of each device (or each processing unit). Moreover, if the overall system configuration and operation are substantially the same, a part of the configuration of one device (or processing unit) may be included in the configuration of another device (or other processing unit).
[0102] Furthermore, for example, this technology can be configured as cloud computing, where a single function is shared and processed collaboratively by multiple devices via a network.
[0103] Furthermore, for example, the program described above can be executed on any device. In that case, the device should have the necessary functions (such as functional blocks) and be able to obtain the necessary information.
[0104] Furthermore, each step described in the flowchart above can be executed by a single device or shared among multiple devices. Additionally, if a single step includes multiple processes, these processes can be executed by a single device or shared among multiple devices. In other words, multiple processes within a single step can be executed as multiple steps. Conversely, processes described as multiple steps can be combined and executed as a single step.
[0105] Furthermore, the program executed by the computer may be executed in a chronological order according to the sequence of steps described herein, or it may be executed in parallel or individually at necessary times, such as when a call is made. In other words, as long as no inconsistencies arise, the processing of each step may be executed in an order different from the sequence described above. Moreover, the processing of the steps of this program may be executed in parallel with the processing of other programs, or it may be executed in combination with the processing of other programs.
[0106] Furthermore, the technologies described in this specification can be implemented independently, as long as they do not create a contradiction. Of course, any multiple technologies can also be implemented in combination. For example, some or all of the technologies described in one embodiment can be combined with some or all of the technologies described in another embodiment. In addition, some or all of the above-mentioned technologies can be implemented in combination with other technologies not mentioned above.
[0107] <Examples of Configuration Combinations> The technology can also take the following configurations: (1) A communication control device comprising: a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard; and a secondary controller that normally operates as a target device in the communication standard in accordance with instructions from the host CPU, and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, wherein the secondary controller has a system control unit that, when it has controller rights, executes firmware layer processing which is part of the communication control in accordance with instructions from the host CPU; and a controller that, when it has controller rights, executes hardware layer processing in the communication control. (2) The communication control device according to (1) above, wherein when the vertical synchronization signal of an image frame matches a reference time for each predetermined synchronization correction interval, the host CPU executes imaging control processing to control imaging for each image frame at timing in accordance with the vertical synchronization signal, and the system control unit executes synchronization correction processing to correct synchronization with other devices independently of the imaging control processing by the host CPU. (3) The communication control device according to (2) above, wherein the system control unit starts the synchronization correction process at approximately a constant timing from the reference time. (4) The communication control device according to any one of (1) to (3) above, wherein the communication standard is I3C (Improved Inter Integrated Circuits), and the I3C control model is configured such that the host CPU executes processing of the System Agent layer and a part of the processing of the Device Driver layer, and the system control unit executes processing of the I3C system FW layer, which includes processing of a part of the Device Driver layer and processing of the I3C HC (Host Controller) Driver layer.(5) The communication control device according to (4) above, wherein the host CPU performs a device initialization entry, writing parameters necessary for initializing the I3C bus to the memory of the system control unit, and the system control unit executes the I3C bus initialization process when instructed by the host CPU to do so. (6) The communication control device according to (4) or (5) above, wherein the host CPU performs a timing control information entry, writing parameters necessary for timing control with other I3C devices to the memory of the system control unit, and the system control unit executes the timing control process when instructed by the host CPU to do so. (7) The communication control device according to any one of (4) to (6) above, wherein the host CPU performs a role change information entry, writing parameters necessary for transferring controller rights to other I3C devices to the memory of the system control unit, and the system control unit executes the role change process when instructed by the host CPU to do so. (8) A communication control method for a communication control device comprising: a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard; and a secondary controller that normally operates as a target device in the communication standard in accordance with instructions from the host CPU, and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, the communication control method comprising: the secondary controller executing firmware layer processing which is part of the communication control in accordance with instructions from the host CPU when it has controller rights; and the hardware layer processing in the communication control when it has controller rights.(9) A computer for a communication control device comprising a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard, and a secondary controller that normally operates as a target device in the communication standard and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, a program for causing the secondary controller to execute processing that includes, when it has controller rights, executing firmware layer processing which is part of the communication control in accordance with instructions from the host CPU, and when it has controller rights, executing hardware layer processing in the communication control.
[0108] It should be noted that this embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.
[0109] 11 Communication system, 21 CIS device, 22 I3C sensor device, 23 Processor, 31 Control unit, 32 Imaging processing unit, 41 Host CPU, 42 Memory, 43 I3C secondary controller, 51 I3C system control unit, 52 Memory, 53 I3C target, 54 I3C HCI, 55 I3C controller, 56 Multiplexer, 61 Analog processing unit, 62 Digital processing unit, 63 Transmitter, 71 Receiver
Claims
1. A communication control device comprising: a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard; and a secondary controller that normally operates as a target device in the communication standard according to instructions from the host CPU, and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, wherein the secondary controller has a system control unit that executes firmware layer processing, which is part of the communication control, according to instructions from the host CPU when it has controller rights, and a controller that executes hardware layer processing in the communication control when it has controller rights.
2. The communication control device according to claim 1, wherein when the vertical synchronization signal of an image frame matches a reference time for each predetermined synchronization correction interval, the host CPU executes an imaging control process to control imaging for each image frame at a timing according to the vertical synchronization signal, and the system control unit executes a synchronization correction process to correct synchronization with other devices independently of the imaging control process by the host CPU.
3. The communication control device according to claim 2, wherein the system control unit starts the synchronization correction process at a substantially constant timing from the reference time.
4. The communication control device according to claim 1, wherein the communication standard is I3C (Improved Inter Integrated Circuits), and the I3C control model is configured such that the host CPU performs processing of the System Agent layer and a portion of the Device Driver layer, and the system control unit performs processing of the I3C system FW layer, which includes processing of a portion of the Device Driver layer and processing of the I3C HC (Host Controller) Driver layer.
5. The communication control device according to claim 4, wherein the host CPU performs a device initialization entry that writes the parameters necessary for initializing the I3C bus to the memory of the system control unit, and the system control unit performs the I3C bus initialization process when instructed by the host CPU to do so.
6. The communication control device according to claim 4, wherein the host CPU performs a timing control information entry, writing parameters necessary for timing control with other I3C devices to the memory of the system control unit, and the system control unit executes the timing control process when instructed by the host CPU to execute the timing control process for timing control with other I3C devices.
7. The communication control device according to claim 4, wherein the host CPU makes a role change information entry that writes the parameters necessary to transfer the controller rights to another I3C device to the memory of the system control unit, and the system control unit executes the role change process when instructed by the host CPU to execute the role change process to transfer the controller rights to the other I3C device.
8. A communication control method for a communication control device comprising: a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard; and a secondary controller that normally operates as a target device in the communication standard in accordance with instructions from the host CPU, and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, the communication control method comprising: the secondary controller executing firmware layer processing, which is part of the communication control, in accordance with instructions from the host CPU when it has controller rights; and the hardware layer processing in the communication control when it has controller rights.
9. A computer for a communication control device comprising a host CPU (Central Processing Unit) that controls the entire device, including communication control of communication in accordance with a predetermined communication standard, and a secondary controller that normally operates as a target device in the communication standard and performs the communication control as a controller device when controller rights are transferred from the host device in the communication standard, a program for causing the secondary controller to execute processing that includes, when it has controller rights, executing firmware layer processing which is part of the communication control in accordance with instructions from the host CPU, and when it has controller rights, executing hardware layer processing in the communication control.