Semiconductor element and semiconductor device

Abstract

Provided is a semiconductor element comprising: an oxide semiconductor layer which is provided in a wiring layer including an insulating film and wiring, and in which a channel region is positioned at the center and a source region and a drain region are respectively positioned at the ends; a gate insulating film which covers the entire surface of the channel region; and a gate electrode which covers the entire surface of the channel region with the gate insulating film interposed therebetween.

Description

Semiconductor devices and semiconductor devices

[0001] This disclosure relates to semiconductor devices and semiconductor devices.

[0002] In recent years, as an example of a semiconductor device, development has been progressing on a display device that uses electroluminescent (EL) elements as light-emitting elements. This display device has, for example, multiple light-emitting elements composed of a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer. Furthermore, in addition to the light-emitting elements described above, the display device has a drive circuit that includes multiple transistors (semiconductor elements) for driving the light-emitting elements.

[0003] In recent years, it has been proposed to form some of multiple transistors as thin-film transistors (TFTs). By making some of the multiple transistors thin-film transistors, it becomes possible to place these transistors, for example, within a wiring layer located above the semiconductor substrate. As a result, the layout size of the above-mentioned drive circuit can be reduced, and a display device, which is an example of a semiconductor device, can be miniaturized.

[0004] Japanese Patent Publication No. 2011-181913

[0005] However, since the oxide semiconductor layer on which the channel of a thin-film transistor (semiconductor device) is formed is susceptible to oxidation and reduction due to the influence of surrounding layers, in order to obtain a thin-film transistor with desired characteristics (e.g., threshold), it is necessary to suitably adjust and stabilize the characteristics of the oxide semiconductor layer.

[0006] Therefore, this disclosure proposes a semiconductor device and a semiconductor device that can adjust and stabilize the characteristics of the oxide semiconductor layer that serves as the channel.

[0007] The present disclosure provides a semiconductor device comprising: an oxide semiconductor layer provided within a wiring layer including an insulating film and wiring, having a channel region in the center and source and drain regions at each of its ends; a gate insulating film covering the entire surface of the channel region; and a gate electrode covering the entire surface of the channel region via the gate insulating film.

[0008] Furthermore, the present disclosure provides a semiconductor device comprising a wiring layer including an insulating film and wiring, and a semiconductor element provided within the wiring layer, wherein the semiconductor element includes an oxide semiconductor layer having a channel region in the center and a source region and a drain region at each of its ends, a gate insulating film covering the entire surface of the channel region, and a gate electrode covering the entire surface of the channel region via the gate insulating film.

[0009] This is a schematic diagram showing an example of the overall configuration of a display device according to an embodiment of this disclosure. This is a circuit diagram showing an example of a pixel of a display device according to an embodiment of this disclosure. This is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a comparative example. This is a schematic diagram showing an example of the main part of the cross-sectional configuration of a pixel according to a comparative example. This is a schematic diagram (1) showing an example of the detailed configuration of a thin-film transistor according to the first embodiment of this disclosure. This is a schematic diagram (2) showing an example of the detailed configuration of a thin-film transistor according to the first embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor of a display device according to modification 1 of the first embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 2 of the first embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 3 of the first embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to the second embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 1 of the second embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 2 of the second embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 3 of the second embodiment of this disclosure. This is a schematic diagram (1) showing an example of the detailed configuration of a thin-film transistor according to the third embodiment of this disclosure. This is a schematic diagram (2) showing an example of the detailed configuration of a thin-film transistor according to the third embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 1 of the third embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 2 of the third embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 3 of the third embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to the fourth embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 1 of the fourth embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 2 of the fourth embodiment of this disclosure. This is a schematic diagram showing an example of the detailed configuration of a thin-film transistor according to modification 3 of the fourth embodiment of this disclosure. This is a schematic diagram (1) showing an example of the planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure.This is a schematic diagram (part 2) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram (part 3) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram (part 4) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram (part 5) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram (part 6) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram (part 7) showing an example of a planar configuration of a thin-film transistor according to the fifth embodiment of this disclosure. This is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to the sixth embodiment of this disclosure. This is a schematic diagram showing an example of a main part of the cross-sectional configuration of a pixel according to the sixth embodiment of this disclosure. This is a cross-sectional diagram (part 1) for explaining the manufacturing method of the main part of a display device according to the seventh embodiment of this disclosure. This is a cross-sectional diagram (part 2) for explaining the manufacturing method of the main part of a display device according to the seventh embodiment of this disclosure. This is a cross-sectional diagram (part 3) for explaining the manufacturing method of the main part of a display device according to the seventh embodiment of this disclosure. This is a cross-sectional view (4) illustrating the manufacturing method of the main part of the display device according to the seventh embodiment of this disclosure. This is a cross-sectional view (5) illustrating the manufacturing method of the main part of the display device according to the seventh embodiment of this disclosure. This is a cross-sectional view (6) illustrating the manufacturing method of the main part of the display device according to the seventh embodiment of this disclosure. This is a front view showing an example of the appearance of a digital still camera. This is a rear view showing an example of the appearance of a digital still camera. This is an external view of a head-mounted display. This is an external view of a see-through head-mounted display. This is an external view of a television device. This is an external view of a smartphone. This is a diagram (1) showing the internal configuration of an automobile. This is a diagram (2) showing the internal configuration of an automobile.

[0010] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant descriptions are omitted. Also, in the present specification and drawings, a plurality of components having substantially the same or similar functional configurations may be distinguished by attaching different alphabets after the same reference numeral. However, when it is not necessary to particularly distinguish each of a plurality of components having substantially the same or similar functional configurations, only the same reference numeral is attached.

[0011] Also, the drawings referred to in the following description are for explaining one embodiment of the present disclosure and facilitating its understanding. For the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may be different from the actual ones. Furthermore, the devices shown in the drawings can be appropriately redesigned in consideration of the following description and known techniques.

[0012] The description of specific shapes in the following description does not mean only geometrically defined shapes. Specifically, the description of specific lengths and shapes in the following description includes cases where there are allowable differences (errors and distortions) in a display device (an example of a semiconductor device), its manufacturing processes, and its use and operation, as well as shapes similar to those shapes.

[0013] Also, in the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting such that electricity (signals) can conduct between a plurality of elements. In addition, "electrically connected" in the following description includes not only cases where a plurality of elements are directly and electrically connected, but also cases where they are indirectly and electrically connected via other elements.

[0014] The description shall be made in the following order: 1. Display device according to an embodiment of the present disclosure 1.1 Display device 1.2 Pixel 2. Background leading to the creation of an embodiment of the present disclosure 3. First embodiment 3.1 Detailed configuration 3.2 Variation 4. Second embodiment 4.1 Detailed configuration 4.2 Variation 5. Third embodiment 5.1 Detailed configuration 5.2 Variation 6. Fourth embodiment 6.1 Detailed configuration 6.2 Variation 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Summary 11. Application example 12. Supplementary remarks

[0015] <<1. Display device according to an embodiment of the present disclosure>> <1.1 Display device> First, referring to FIG. 1, an example of the overall configuration of a display device 10 according to an embodiment of the present disclosure, which is used as a display device or a lighting device as an example of a semiconductor device, will be described. FIG. 1 is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure.

[0016] The display device 10 is, for example, a device in which light-emitting elements such as OLED (Organic Light Emitting Diode) or Micro-OLED are formed in an array. Such a display device 10 can be applied to, for example, a display device for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), an electronic viewfinder (Electronic View Finder: EVF), or a small projector.

[0017] Furthermore, in the embodiments of this disclosure, the light-emitting element may be a self-emissive element as well as a current-driven electro-optic element. For example, in addition to OLEDs, current-driven electro-optic elements include inorganic EL elements, LED elements, semiconductor laser elements, etc. Furthermore, an organic EL display device using an OLED as the light-emitting element has the following features. Specifically, because the OLED is a self-emissive element, the organic EL display device has higher image visibility compared to liquid crystal display devices, which are also planar display devices, and is easy to make lighter and thinner because it does not require lighting members such as backlights. Moreover, because the response speed of OLED is very fast, on the order of a few microseconds, the organic EL display device does not produce afterimages when displaying moving images.

[0018] Here, as an example, we will explain using an active-matrix organic EL display device that uses a current-driven light-emitting element, such as an OLED, which changes its luminescence depending on the current flowing through the device, as the light-emitting element. Hereafter, "active-matrix organic EL display device" will simply be referred to as "display device".

[0019] As shown in Figure 1, the display device 10 has a configuration comprising a pixel array section 30 in which a plurality of pixels 20, including light-emitting elements, are arranged in a matrix-like (two-dimensional) arrangement on a semiconductor substrate (not shown), and a drive circuit section arranged around the pixel array section 30. The drive circuit section includes, for example, a write scanning section 40, a first drive scanning section 50, a second drive scanning section 60, and a signal output section 70 mounted on the same display panel 80 as the pixel array section 30, and drives each pixel 20 of the pixel array section 30.

[0020] Here, when the display device 10 supports color display, one pixel (unit pixel / pixel), which is the unit for forming a color image, is composed of a plurality of sub-pixels (sub-pixels / sub-pixels). At this time, each of the sub-pixels corresponds to the pixel 20 in FIG. 1. More specifically, in the display device 10 that supports color display, one pixel 20 may be composed of, for example, three sub-pixels: a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light. Alternatively, it may be composed of one, two, or more sub-pixels, and is not particularly limited. Also, one pixel 20 is not limited to, for example, a combination of sub-pixels of the three primary colors of red, green, and blue. One pixel 20 may be formed by adding one or more sub-pixels of one or more colors to the sub-pixels of the three primary colors. More specifically, the display device 10 can, for example, add a sub-pixel that emits white light to improve brightness to form one pixel 20, or add at least one sub-pixel that emits complementary color light to expand the color reproduction range to form one pixel 20.

[0021] In the pixel array unit 30, for the array of pixels 20 arranged in m rows and n columns, scanning lines 31 (31 ｎ , ~31 ｍ ) and drive lines 32 (32 １ ~32 ｍ ) are wired for each pixel row. Further, for the array of pixels 20 arranged in m rows and n columns, signal lines 34 (34 １ ~34 ｎ ) are wired for each pixel column.

[0022] The scanning lines 31 １ ~31 ｍ are electrically connected to the output ends of the corresponding rows of the writing scanning unit 40 respectively. The drive lines 32 １ ~32 ｍ are electrically connected to the output ends of the corresponding rows of the drive scanning unit 50 respectively. The signal lines 34 １ ~34 ｎ are electrically connected to the output ends of the corresponding columns of the signal output unit 70 respectively.

[0023] The write scanning unit 40 is composed of a shift register circuit and the like. When writing the signal voltage of the video signal to each pixel 20 of the pixel array unit 30, the write scanning unit 40 uses the scan line 31 (31 １ ~31 ｍ ) write scan signal WS (WS １ ~WS ｍ By sequentially supplying these, each pixel 20 of the pixel array unit 30 can be scanned row by row.

[0024] The first drive scanning unit 50 is configured with a shift register circuit and the like, similar to the write scanning unit 40. This drive scanning unit 50 synchronizes with the line sequential scanning by the write scanning unit 40 to drive the line 32 (32 １ ~32 ｍ ) in response to the light emission control signal DS (DS １ ~DS ｍ By supplying ( ), the light emission / non-light emission (extinction) of the pixel 20 can be controlled.

[0025] The signal output unit 70 outputs a signal voltage (hereinafter simply referred to as "signal voltage") V of the video signal corresponding to the brightness information supplied from the signal supply source (not shown). ｓｉｇ and reference voltage V ｏｆｓ It selectively outputs the following. Here, the reference voltage V ｏｆｓ The signal voltage V of the video signal ｓｉｇ This is a voltage equivalent to, or near, the reference voltage.

[0026] The signal voltage V is selectively output from the signal output unit 70. ｓｉｇ / Reference voltage V ｏｆｓ This is the signal line 34 (34 １ ~34 ｎ The data is written to each pixel 20 of the pixel array 30 via the write scanning unit 40 in units of pixel rows selected by line sequential scanning. That is, the signal output unit 70 outputs a signal voltage V ｓｉｇ It can be written in units of pixel rows (lines).

[0027] In the display device 10, by switching off the drive transistor Tr1 (see Figure 2) included in the pixel 20 (described later), the current supply to the light-emitting element EL (see Figure 2) included in the pixel 20 is cut off, and as a result the light emission of the light-emitting element EL is suppressed, so black gradation can be displayed. However, when the drive transistor Tr1 is switched off, current may leak between the source and drain of the drive transistor Tr1, which may reduce the contrast when displaying black gradation. Therefore, in order to avoid a decrease in contrast when displaying black gradation, the drive unit of the display device 10 has a second drive scanning unit 60, and further, a second drive line 33 (33) along the row direction. １ ~33 ｍ ) is wired for each pixel row. Second drive line 33 １ ~33 ｍ These are connected to the output terminals of the corresponding rows of the second drive scanning unit 60.

[0028] In detail, the second drive scanning unit 60 is configured with a shift register circuit and the like, similar to the write scanning unit 40. This second drive scanning unit 60 synchronizes with the line sequential scanning by the write scanning unit 40 to the second drive line 33 (33 １ ~33 ｍ ) drive signal AZ (AZ １ ~AZ ｍ By supplying (), control can be performed to prevent the pixel 20 from emitting light during the non-emitting period.

[0029] Note that the overall configuration example shown in Figure 1 is just one example of the configuration of the display device 10 according to the embodiment of this disclosure, and the circuit configuration of the display device 10 according to the embodiment of this disclosure is not limited to the configuration shown in Figure 1.

[0030] <1.2 Pixels> Next, the circuit configuration of the pixels (pixel circuits) 20 of the display device 10 according to the embodiment of the present disclosure shown in Figure 1 will be described. Figure 2 is a circuit diagram showing an example of the pixels 20 of the display device 10 according to the embodiment of the present disclosure.

[0031] In the embodiments of this disclosure, as shown in Figure 2, the pixel 20 is composed of a light-emitting element EL and a drive circuit that drives it. The light-emitting element EL is an example of a current-driven electro-optic element whose luminescence changes according to the current value flowing through the device, and is, for example, an OLED. The cathode of the light-emitting element EL is, for example, a node V for discharging current. ｓｓ It is electrically connected to it.

[0032] The drive circuit consists of multiple transistors electrically connected to the light-emitting element EL (drive transistor Tr1, writing transistor Tr2, light emission control transistor Tr3, switching transistor Tr4), and capacitance units C1 and C2. The anode of the light-emitting element EL is electrically connected to the drive transistor Tr1, and when current flows through the drive transistor Tr1, it can emit light.

[0033] Furthermore, the drive transistor (also called the light-emitting transistor) Tr1 and the write transistor (also called the data write control transistor) Tr2 are, for example, field-effect transistors (FETs). More specifically, the drive transistor Tr1 is a P-channel type transistor, and the write transistor Tr2 is an N-channel type transistor. Also, the light-emitting control transistor (also called the power supply control transistor) Tr3 and the switching transistor (also called the quenching control transistor) Tr4 are, for example, field-effect transistors. More specifically, the light-emitting control transistor Tr3 is a P-channel type transistor, and the switching transistor Tr4 is an N-channel type transistor.

[0034] More specifically, as shown in Figure 2, the source and drain of the drive transistor Tr1 are connected to the power supply voltage V via the drain of the light emission control transistor Tr3, which will be described later. ＤＤ The power supply node (current source) and the anode electrode of the light-emitting element EL are electrically connected, respectively. In addition, the source and drain of the writing transistor Tr2 are connected to the signal line (V ｓｉｇThe gate of the drive transistor Tr1 is electrically connected to the power supply voltage V, and the gate of the writing transistor Tr2 is electrically connected to the scan line (WS). In addition, the light emission control transistor Tr3 is electrically connected to the power supply voltage V ＤＤ The power supply node and the source of the drive transistor Tr1 are electrically connected. Additionally, the switching transistor Tr4 is electrically connected between the drain of the drive transistor Tr1 and the current discharge node Vss.

[0035] The drive transistor Tr1 can drive the light-emitting element EL by supplying a drive current to the light-emitting element EL that corresponds to the holding voltage (signal voltage) of the capacitance section C1, which will be described later.

[0036] The writing transistor Tr2 receives the signal voltage V supplied from the signal output unit 70. ｓｉｇ The signal can be sampled and written to the gate of the drive transistor Tr1. Here, "writing" means applying a signal voltage to the gate node, so that the potential of the gate node is maintained at a potential based on that signal voltage.

[0037] Furthermore, the light emission control transistor Tr3 controls the emission / non-emission of the light-emitting element EL under the drive of the light emission control signal DS.

[0038] The switching transistor Tr4 controls the light-emitting element EL to not emit light during its non-emitting period, under the drive signal AZ. In other words, by becoming conductive, the switching transistor Tr4 forms a bypass path around the light-emitting element EL, preventing current from being supplied to it. In this way, even if current leaks between the source and drain of the drive transistor Tr1 when it is switched to the off state, the switching transistor Tr4 becomes conductive, preventing current from being supplied to the light-emitting element EL. As a result, this configuration makes it possible to suppress the decrease in contrast during black gradation display.

[0039] Furthermore, the capacitance unit C1 is connected between the gate and source of the drive transistor Tr1 and holds the signal voltage Vsig written by sampling by the write transistor Tr2. The drive transistor Tr1 drives the light-emitting element EL by supplying a drive current to the light-emitting element EL corresponding to the holding voltage of the capacitance unit C1.

[0040] Furthermore, the capacitance section C2 connects the source of the drive transistor Tr1 to a node with a fixed potential (for example, the power supply voltage V). ＤＤ It is connected between the power node and the capacitor C2. The capacitance C2 is connected to the signal voltage V ｓｉｇ This suppresses fluctuations in the source voltage of the drive transistor Tr1 when data is written to it, and also has the effect of setting the gate-source voltage Vgs of the drive transistor Tr1 to the threshold voltage Vth of the drive transistor Tr1.

[0041] Note that the circuit configuration example shown in Figure 2 is just one example of the circuit configuration of the pixel 20 in this embodiment, and the circuit configuration of the pixel 20 in this embodiment is not limited to the circuit configuration shown in Figure 2.

[0042] <<2. Background to the Creation of the Embodiments of the Disclosure>> Next, before describing the details of the embodiments of the Disclosure, the background to the creation of the embodiments of the Disclosure will be explained with reference to Figures 3 and 4. Figure 3 is a schematic diagram showing an example of the cross-sectional configuration of a pixel 20a according to a comparative example, and Figure 4 is a schematic diagram showing an example of the main part of the cross-sectional configuration of a pixel 20a according to a comparative example. Here, the comparative example refers to a pixel 20a that the inventors had been studying before creating the embodiments of the Disclosure.

[0043] Up to this point, the inventors have been studying a pixel 20a related to a comparative example as shown in Figure 3. In the comparative example shown in Figure 3, a wiring layer 200 is provided on a semiconductor substrate 100, and a light-emitting part 300, which is a light-emitting element EL, is provided on the wiring layer 200. More specifically, the semiconductor substrate 100 is provided with, for example, a drive transistor Tr1 and a light-emitting control transistor Tr3, which are included in the drive circuit. Above the wiring layer 200, for example, a write transistor Tr2 and a switching transistor Tr4, which are included in the drive circuit, are provided. The write transistor Tr2 and the switching transistor Tr4 are configured as thin-film transistors.

[0044] More specifically, as can be seen from Figure 4, which illustrates the main part of the pixel 20a in Figure 3, among the multiple transistors, for example, the driving transistor Tr1 (labeled "Drv" in Figure 4) and the light emission control transistor Tr3 (labeled "DS" in Figure 4) are provided on the semiconductor substrate 100. Specifically, the driving transistor Tr1 and the light emission control transistor Tr3 have gate electrodes 102 provided via a gate insulating film on a region with an n-type conductivity that functions as a channel provided within the semiconductor substrate 100. Furthermore, these transistors Tr1 and Tr3 are provided within the semiconductor substrate 100 so as to sandwich the channel region and have a source / drain consisting of a diffusion region 104 containing impurities with a p-type conductivity. In addition, these transistors are isolated from other elements by an element isolation section (Shallow Trench Isolation: STI) 106 provided within the semiconductor substrate 100.

[0045] Furthermore, as shown in Figure 4, a wiring layer 200 is provided on the semiconductor substrate 100, and this wiring layer 200 includes an insulating film 202, wiring 204, and vias 206, etc. Although not shown in the figure, a barrier film is provided within the wiring layer 200 to prevent the diffusion of metal species from the wiring 204, etc.

[0046] Furthermore, as shown in Figure 4, among the multiple transistors, the writing transistor Tr2 (labeled "WS" in Figure 4) and the switching transistor Tr4 (labeled "AZ" in Figure 4) are thin-film transistors provided within the wiring layer 200. More specifically, the writing transistor Tr2 and the switching transistor Tr4 each have an oxide semiconductor layer 210 provided within the wiring layer 200 and a gate electrode 212 that contacts the oxide semiconductor layer 210 via a gate insulating film.

[0047] Furthermore, as shown in Figure 4, a light-emitting unit 300, which is a light-emitting element (EL), is provided on the wiring layer 200. The light-emitting element (EL) mainly comprises an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 stacked on the anode electrode 310 that emits light, and a cathode electrode 312 stacked on the light-emitting layer 314 that transmits light from the light-emitting layer 314. For example, the light-emitting element (EL) can be an OLED (Organic Light-Emitting Diode) having a light-emitting layer 314 made of an organic material.

[0048] In other words, in the comparative example, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100. Furthermore, in the comparative example, the writing transistor Tr2 and the switching transistor Tr4 are provided as thin-film transistors within the wiring layer 200 stacked on the semiconductor substrate 100. In this way, in the comparative example, thin-film transistors can be stacked while ensuring high breakdown voltage for the specified transistors, thereby reducing the size of the drive circuit. As a result, the display device 10 can be miniaturized according to the comparative example.

[0049] Furthermore, the writing transistor Tr2 and the switching transistor Tr4, which are provided as thin-film transistors, use the oxide semiconductor layer 210 as a channel. In the comparative example, by using such thin-film transistors, not only can the display device 10 be miniaturized, but low power consumption can also be achieved because the leakage current of Tr2 and Tr3 is small.

[0050] The oxide semiconductor layer 210, which forms the channel of the thin-film transistor, is made of, for example, indium-gallium-zinc oxide (IGZO) and has the property of being easily oxidized and reduced by the influence of surrounding layers. Specifically, when the oxide semiconductor layer 210 is reduced by electrons donated from surrounding layers, it becomes less resistive and becomes a conductor. On the other hand, when the oxide semiconductor layer 210 is oxidized by electrons taken from surrounding layers, it becomes more resistive and becomes a semiconductor, and further oxidation changes it into an insulator. Therefore, in the comparative example, in order to obtain a thin-film transistor with desired characteristics (e.g., threshold), it is required to suitably adjust and stabilize the characteristics of the oxide semiconductor layer 210.

[0051] Furthermore, in the comparative example, the barrier film provided within the wiring layer 200 has a reducing effect that reduces other materials. Consequently, the barrier film reduces the oxide semiconductor layer 210, which forms the channel of the thin-film transistor, and alters its properties.

[0052] Furthermore, in the comparative example, in order to prevent changes in characteristics due to heat applied during the manufacturing of the pixel 20a, it is preferable that the thin-film transistor be manufactured in a later process during the manufacturing of the pixel 20a. For this reason, the thin-film transistor is often provided in the upper layer of the stacked structure of the pixel 20a (specifically, the wiring layer 200). However, because the thin-film transistor is provided in the upper layer of the stacked structure of the pixel 20a, light may be incident on the oxide semiconductor layer 210 from above when the pixel 20a is in use. In the comparative example, this incident light can lead to photodegradation of the oxide semiconductor layer 210 and malfunction of the thin-film transistor.

[0053] Therefore, in light of these circumstances, the inventors have created the embodiments of the present disclosure described below, which are capable of adjusting and stabilizing the characteristics of the oxide semiconductor layer 210 that forms the channel of the thin-film transistor. The details of the embodiments of the present disclosure created by the inventors will be described in order below.

[0054] <<3. First Embodiment>> <3.1 Detailed Configuration> First, the detailed structure of the thin-film transistor (semiconductor element) Tr5 according to the first embodiment of the present disclosure will be described with reference to Figures 5A and 5B. In this embodiment, the gate region (labeled "G" in Figure 5A) of the thin-film transistor Tr5 has a via 206 above it, and the source / drain regions (labeled "S" and "D" respectively in Figure 5A) have a via 206 below them, thus having a "gate: top contact, source / drain: bottom contact" configuration. Figure 5A is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment. More specifically, the upper part of Figure 5A shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction (the channel region of the thin-film transistor Tr5 is cut along the channel length direction), and the lower part of Figure 5A shows a plan view of the thin-film transistor Tr5. Furthermore, Figure 5B is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment. More specifically, the upper part of Figure 5B shows a cross-sectional view obtained when the thin-film transistor Tr5 is cut along the line B-B' in the upper part of Figure 5A (the channel region of the thin-film transistor Tr5 is cut along the channel width direction), and the lower part of Figure 5B shows an enlarged view of region C in the upper part of Figure 5A.

[0055] As shown in the upper part of Figure 5A, the thin-film transistor Tr5 according to this embodiment is provided in a wiring layer 200 located on a semiconductor substrate, such as a silicon substrate. The wiring layer 200 has an insulating film 202 and a plurality of wirings 204, etc. In this embodiment, the insulating film 202 is, for example, silicon oxide (SiO₂), which is an oxygen-containing film. ｘ ) etc. In this embodiment, the wiring 204 can be formed from a metal film such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or a lamination thereof. In this embodiment, if the wiring 204 is formed from aluminum (Al), it is preferable to cover the wiring 204 with a barrier metal film of titanium (Ti) or titanium nitride (TiNx), and if it is formed from tungsten (W), it is preferable to cover it with a barrier metal film of titanium nitride (TiNx). ｘIt is preferable to cover it with a barrier metal film of ), and if it is formed of copper (Cu), tantalum (Ta), tantalum nitride (TaN ｘ It is preferable to cover them with a barrier metal film consisting of a laminate of these materials, or a barrier metal film made of these materials.

[0056] In this embodiment, the lower and upper surfaces of the wiring layer 200 (more specifically, the insulating film 202) may be covered with a barrier film 230 that prevents the diffusion of metal species from the wiring 204, as shown in Figure 5A. The barrier film 230 is silicon nitride (SiN ｘ ) or silicon carbonitride (SiCN), etc. In this embodiment, when the wiring 204 is made of copper (Cu), it is preferable to provide a barrier film 230. In this embodiment, the barrier film 230 has the effect of reducing others by diffusing hydrogen, for example.

[0057] Furthermore, in this embodiment, the thin-film transistor Tr5 has an oxide semiconductor layer 210 and a gate electrode 212 provided on the oxide semiconductor layer 210 via a gate insulating film 214. As shown in the upper part of Figure 5A, the channel of the thin-film transistor Tr5 is located in the center of the oxide semiconductor layer 210, and the source / drain regions of the thin-film transistor Tr5 are located at both ends of the oxide semiconductor layer 210.

[0058] The oxide semiconductor layer 210 can be formed from an oxide film containing, for example, at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), tin (Sn), silicon (Si), hafnium (Hf), and zinc (Zn). More specifically, the oxide semiconductor layer 210 may be, for example, indium oxide (In ２ O ３ ), tin-indium oxide (In ２ O ３ Sn is added as a dopant, for example, ITO), indium-gallium-zinc oxide (ZnO) ４ In and Ga are added as dopants, for example, IGZO), indium-gallium oxide (In ２ O ３ -Ga ２ O ３These can be formed from aluminum-zinc oxide (ZnO with Al added as a dopant, e.g., AZO), indium-zinc oxide (ZnO with In added as a dopant, e.g., IZO), indium-tin-zinc oxide (ZnO with In and Sn added as dopants, e.g., ITZO), indium-aluminum-zinc oxide (ZnO with In and Al added as dopants, e.g., IAZO), etc. In this embodiment, since these oxide semiconductors have extremely small leakage currents, leakage in the thin-film transistor Tr5 can be suppressed.

[0059] Furthermore, the gate insulating film 214 of the thin-film transistor Tr5 can be formed from, for example, an oxide film or nitride film containing silicon (Si), hafnium (Hf), or aluminum (Al). More specifically, the gate insulating film 214 may be, for example, silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum oxide (AlO ｘ ), aluminum oxynitride (AlON), hafnium oxide (HfO ｘ It can be formed from materials such as oxyhafnium nitride (HfON), etc.

[0060] Furthermore, the gate electrode 212 of the thin-film transistor Tr5 can be formed from a metal film, nitride film, or alloy thereof, which contains at least one element selected from the group consisting of silicon (Si), aluminum (Al), titanium (Ti), tungsten (W), niobium (Nb), and molybdenum (Mo). More specifically, the gate electrode 212 can be made from, for example, tungsten (W), titanium nitride (TiNb), or ｘ It can be formed from materials such as polysilicon (poly-Si).

[0061] Furthermore, in this embodiment, as shown in the upper and lower panels of Figure 5A and the upper panel of Figure 5B, the surface of the channel region located in the center of the oxide semiconductor layer 210 is covered by the gate insulating film 214 and is also covered by the gate electrode 212 via the gate insulating film 214. More specifically, as shown in the upper panel of Figure 5A, in the cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, the upper and lower surfaces of the channel region located in the center of the oxide semiconductor layer 210 are covered by the gate electrode 212 via the gate insulating film 214. Furthermore, as shown in the upper panel of Figure 5B, in the cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper panel of Figure 5A, the upper, lower, and side surfaces of the channel region are covered by the gate electrode 212 via the gate insulating film 214. Also, in this embodiment, in the cross-section shown in Figure 5A, the upper surface portion of the gate electrode 212 provided on the oxide semiconductor layer 210 and the lower surface portion of the gate electrode 212 provided on the oxide semiconductor layer 210 have substantially the same size and shape.

[0062] Furthermore, in this embodiment, as shown in the upper part of Figure 6, the gate electrode 212 is provided at a predetermined distance from the source / drain region of the thin-film transistor tr5 so as not to overlap with it. In this way, according to this embodiment, it is possible to suppress the increase in parasitic capacitance that may occur in the thin-film transistor Tr5. Moreover, as will be described later, in this embodiment, a protrusion 210a is provided at the edge of the oxide semiconductor layer 210 which becomes the source / drain region of the thin-film transistor Tr5, making it easy to define the range of the source / drain region by the protrusion 210a. Therefore, in this embodiment, it is also easy to provide the gate electrode 212 so as not to overlap with the source / drain region.

[0063] In this embodiment, by covering the central surface of the oxide semiconductor layer 210, which forms the channel region of the thin-film transistor Tr5, with the gate electrode 212 via the gate insulating film 214, it is possible to suppress oxidation and reduction of the channel region due to the diffusion of oxygen and hydrogen from the surroundings, thereby preventing changes in its characteristics. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to prevent light from being incident from above. As a result, according to this embodiment, photodegradation of the oxide semiconductor layer 210 can be suppressed, and malfunction of the thin-film transistor Tr can be prevented. Moreover, according to this embodiment, since no new light-shielding film is added, the manufacturing cost and manufacturing time of the pixel 20 are not significantly increased.

[0064] Furthermore, as shown in the upper part of Figures 5A and 5B, the thin-film transistor Tr5 has a via (second via) 206a that electrically connects the gate electrode 212 to the wiring 204. The via 206a can be formed from, for example, a metal film such as tungsten (W) or copper (Cu). In addition, in this embodiment, if the via 206a is formed from tungsten (W), titanium nitride (TiN) ｘ It is preferable to cover the via 206a with a barrier metal film of ), and if the via 206a is formed of copper (Cu), tantalum (Ta), tantalum nitride (TaN) ｘ It is preferable to cover the via 206a with a barrier metal film consisting of these layers.

[0065] Furthermore, in this embodiment, as shown in the lower part of Figure 5A and the upper part of Figure 5B, the via 206a is provided above the oxide semiconductor layer 210 and so as not to overlap with the oxide semiconductor layer 210. More specifically, in this embodiment, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, as shown in the lower part of Figure 5A, and the via 206a is located in this extended portion 212a. In this embodiment, by doing so, it is possible to avoid oxidation of the via 206a, which is made of a metal material or the like, by oxygen diffused from the oxide semiconductor layer 210, and thus prevent it from becoming highly resistive.

[0066] Furthermore, in this embodiment, as shown in the upper part of Figure 5A and the lower part of Figure 5B, the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, has two protrusions 210a at both ends that protrude downward along the thickness direction of the oxide semiconductor layer 210. In addition, vias (first vias) 206b are provided below the protrusions 210a so as to connect from below to the vertex region of each protrusion 210a. In detail, the vias 206b are in contact with the lower surface of the source / drain region of the oxide semiconductor layer 210. The vias 206b can be formed from, for example, a metal film such as tungsten (W) or copper (Cu). Furthermore, in this embodiment, if the vias 206b are formed from tungsten (W), titanium nitride (TiN) ｘ It is preferable to cover the via 206b with a barrier metal film of ), and if the via 206b is formed of copper (Cu), tantalum (Ta), tantalum nitride (TaN) ｘ It is preferable to cover the via 206b with a barrier metal film consisting of these layers, or a barrier metal film made of these layers.

[0067] In this embodiment, a protrusion 210a is provided at the edge of the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, projecting downward along the thickness direction of the oxide semiconductor layer 210. This brings the source / drain region opposite the barrier film 230 and closer to the barrier film 230. According to this embodiment, as the barrier film 230, which has a reducing effect, approaches, the source / drain region is reduced, making it possible to selectively reduce the resistance of the source / drain region.

[0068] As described above, in this embodiment, by covering the central surface of the oxide semiconductor layer 210, which forms the channel region of the thin-film transistor Tr5, with the gate electrode 212 via the gate insulating film 214, oxidation and reduction of the channel region, which can cause changes in its characteristics, can be suppressed. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, light incidence from above is avoided, and photodegradation of the oxide semiconductor layer 210 can be suppressed. Moreover, according to this embodiment, since no new light-shielding film is added, the manufacturing cost and time of the pixel 20 are not significantly increased. In addition, in this embodiment, by providing a protrusion 210a that protrudes downward along the film thickness direction of the oxide semiconductor layer 210 at the edge of the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, the barrier film 230 is brought closer to the source / drain region. In this way, according to this embodiment, the source / drain region is reduced, and thus the resistance can be reduced.

[0069] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figures 5A and 5B, but can take on various forms.

[0070] <3.2 Modified Examples> Next, the detailed structure of the thin-film transistor Tr5 according to the modified examples of this embodiment will be described with reference to Figures 6 to 8. Figure 6 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 1 of this embodiment, Figure 7 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 2 of this embodiment, and Figure 8 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 3 of this embodiment. More specifically, in these figures, the upper part of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower part of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper part of the figure.

[0071] (Modification 1) As shown in Figure 6, in Modification 1 of this embodiment, the thin-film transistor Tr5 may further have an oxygen supply layer 220 that is provided opposite the via 206a across the channel region and supplies oxygen to the channel region. The oxygen supply layer 220 is an oxidizing film that has the effect of oxidizing by taking electrons from the surrounding film. In detail, the oxygen supply layer 220 is located below the oxide semiconductor layer 210 and is provided so as to overlap with the channel region, and for example, the oxide semiconductor layer 210 can be oxidized by releasing oxygen to the oxide semiconductor layer 210. The oxygen supply layer 220 can also be formed from an oxide film or oxynitride film containing, for example, silicon (Si), hafnium (Hf), or aluminum (Al). In this Modification 1, by providing the oxygen supply layer 220 in this way, the channel region of the oxide semiconductor layer 210 can be oxidized and the characteristics of the channel region can be suitably adjusted.

[0072] (Modification 2) As shown in Figure 7, in Modification 2 of this embodiment, the thin-film transistor Tr5 may further have a hydrogen supply layer 222 that is provided opposite the via 206b with the source / drain region in between, and supplies hydrogen to the source / drain region. The hydrogen supply layer 222 is a reducing film that has a reducing effect by donating electrons from the surrounding film. In detail, the hydrogen supply layer 222 is located above the oxide semiconductor layer 210 and is provided so as to overlap the source / drain region, and can reduce the oxide semiconductor layer 210 by releasing hydrogen to the oxide semiconductor layer 210, for example. Specifically, the hydrogen supply layer 222 can be, for example, silicon nitride, silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxynitride (AlON), etc., which contain hydrogen. In addition, the hydrogen supply layer 222 may supply nitric oxide (NO), nitrogen dioxide (NO) to the oxide semiconductor layer 210. ２ It may be formed from a material that emits ) hydrogen. In this modified example 2, by providing the hydrogen supply layer 222 in this way, the source / drain region of the oxide semiconductor layer 210 can be reduced to lower its resistance.

[0073] Furthermore, in this modified example 2, by providing a protrusion 210a at the edge of the oxide semiconductor layer 210, the distance between the channel region and the source / drain region can be increased without increasing the area occupied by the thin-film transistor Tr5. Therefore, according to this modified example 2, the diffusion of hydrogen from the hydrogen supply layer 222 to the channel region can be suppressed, thereby avoiding changes in the channel characteristics and channel length.

[0074] (Modification 3) As shown in Figure 8, in Modification 3 of this embodiment, the thin-film transistor Tr5 may have an oxygen supply layer 220 and a hydrogen supply layer 222. In other words, Modification 3 is an embodiment that combines Modification 1 and Modification 2 described above.

[0075] Furthermore, in the embodiments of this disclosure, as described below, vias 206a and 206b may be provided above or below the oxide semiconductor layer 210, thereby increasing the degree of freedom in the arrangement of vias 206a and 206b. Therefore, according to the embodiments of this disclosure, it becomes easier to miniaturize the pixels 20 and the display device 10. The following describes variations in the arrangement of such vias 206a and 206b.

[0076] <<4. Second Embodiment>> <4.1 Detailed Configuration> Next, with reference to Figure 9, the detailed structure of the thin-film transistor Tr5 according to the second embodiment of the present disclosure will be described. In this embodiment, the gate / source / drain region of the thin-film transistor Tr5 has a "gate / source / drain: bottom contact" configuration, such that a via 206 is provided below it. Figure 9 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment. More specifically, the upper part of Figure 9 shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower part of Figure 9 shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper part of Figure 9. In this embodiment, the plan view of the thin-film transistor Tr5 corresponds to the plan view shown in the lower part of Figure 5A, and the enlarged view of region C in the upper part of Figure 9 corresponds to the enlarged view shown in the lower part of Figure 5B. Below, the explanation of points common to the first embodiment described above will be omitted, and the points that differ from the first embodiment will be explained.

[0077] In this embodiment, as shown in Figure 9, similar to the first embodiment, the surface of the channel region located in the center of the oxide semiconductor layer 210 is covered by the gate electrode 212 via the gate insulating film 214. In this embodiment as well, by covering the surface of the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to suppress oxidation and reduction of the channel region due to the diffusion of oxygen and hydrogen from the surroundings, which can change its characteristics. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to prevent light from being incident from above. As a result, according to this embodiment, photodegradation of the oxide semiconductor layer 210 can be suppressed and malfunction of the thin-film transistor Tr5 can be prevented. In addition, according to this embodiment, since no new light-shielding film is added, the manufacturing cost and manufacturing time of the pixel 20 are not significantly increased.

[0078] Furthermore, in this embodiment, as shown in Figure 9, the via 206a is provided below the oxide semiconductor layer 210 and so as not to overlap with the oxide semiconductor layer 210. More specifically, in this embodiment, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the via 206a is located in this extended portion 212a. In this embodiment as well, this prevents the via 206a, which is made of a metal material or the like, from being oxidized by oxygen diffused from the oxide semiconductor layer 210 and becoming highly resistive.

[0079] In this embodiment as well, as shown in the upper part of Figure 9, the oxide semiconductor layer 210 that forms the source / drain region of the thin-film transistor Tr5 has two protrusions 210a at both ends that protrude downward along the thickness direction of the oxide semiconductor layer 210. Furthermore, vias 206b are provided below the oxide semiconductor layer 210 so as to connect from below to the vertex region of each protrusion 210a. In this embodiment as well, by providing protrusions 210a at the ends of the oxide semiconductor layer 210 that forms the source / drain region of the thin-film transistor Tr5, the source / drain region is brought closer to the barrier film 230. According to this embodiment, by bringing the barrier film 230, which has a reducing effect, closer, the source / drain region can be reduced and its resistance reduced.

[0080] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figure 9, but can take on various forms.

[0081] <4.2 Modified Examples> Next, the detailed structure of the thin-film transistor Tr5 according to the modified examples of this embodiment will be described with reference to Figures 10 to 12. Figure 10 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 1 of this embodiment, Figure 11 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 2 of this embodiment, and Figure 12 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 3 of this embodiment. More specifically, in these figures, the upper section of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower section of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper section of the figure.

[0082] (Modification 1) As shown in Figure 10, in Modification 1 of this embodiment, the thin-film transistor Tr5 may further have an oxygen supply layer 220 that is provided opposite the via 206a across the channel region and supplies oxygen to the channel region. Specifically, the oxygen supply layer 220 is located above the oxide semiconductor layer 210 and is provided so as to overlap with the channel region. In this Modification 1, by providing the oxygen supply layer 220 in this way, the channel region of the oxide semiconductor layer 210 can be oxidized and the characteristics of the channel region can be suitably adjusted.

[0083] Furthermore, in this modified example 1, by providing a protrusion 210a at the edge of the oxide semiconductor layer 210, the distance between the channel region and the source / drain region can be increased without increasing the area occupied by the thin-film transistor Tr5. Therefore, according to this modified example 1, the diffusion of oxygen from the oxygen supply layer 220 to the source / drain region can be suppressed, thus avoiding increased resistance in the source / drain region.

[0084] (Modification 2) As shown in Figure 11, in Modification 2 of this embodiment, the thin-film transistor Tr5 may further have a hydrogen supply layer 222 that supplies hydrogen to the source / drain region, which is provided opposite the via 206b with the source / drain region in between. In detail, the hydrogen supply layer 222 is located above the oxide semiconductor layer 210 and is provided so as to overlap with the source / drain region. In this Modification 2, by providing the hydrogen supply layer 222 in this way, the source / drain region of the oxide semiconductor layer 210 can be reduced to lower its resistance.

[0085] (Modification 3) As shown in Figure 12, in Modification 3 of this embodiment, the thin-film transistor Tr5 may have an oxygen supply layer 220 and a hydrogen supply layer 222. In other words, Modification 3 is an embodiment that combines Modification 1 and Modification 2 described above.

[0086] <<5. Third Embodiment>> <5.1 Detailed Configuration> Next, the detailed structure of the thin-film transistor Tr5 according to the third embodiment of the present disclosure will be described with reference to Figures 13A and 13B. In this embodiment, the gate / source / drain region of the thin-film transistor Tr5 has a "gate / source / drain: top contact" configuration, such that a via 206 is provided above it. Figure 13A is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment, and in detail, it shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction. Furthermore, Figure 13B is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment, and in detail, the upper part of Figure 13B shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in Figure 13A, and the lower part of Figure 13B shows an enlarged view of region C in the upper part of Figure 13A. In this embodiment, the plan view of the thin-film transistor Tr5 corresponds to the plan view shown in the lower part of Figure 5A. In the following, we will omit explanations of points common to the embodiments described above and instead explain the points that differ from each embodiment.

[0087] In this embodiment as well, as shown in Figures 13A and 13B, the surface of the channel region located in the center of the oxide semiconductor layer 210 is covered by the gate electrode 212 via the gate insulating film 214, similar to the first and second embodiments. In this embodiment as well, by covering the surface of the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to suppress oxidation and reduction of the channel region due to the diffusion of oxygen and hydrogen from the surroundings, which can change its characteristics. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to prevent light from being incident from above. As a result, according to this embodiment, photodegradation of the oxide semiconductor layer 210 can be suppressed, and malfunction of the thin-film transistor Tr5 can be prevented. Furthermore, according to this embodiment, since no new light-shielding film is added, the manufacturing cost and manufacturing time of the pixel 20 are not significantly increased.

[0088] Furthermore, in this embodiment, as shown in the upper part of Figures 13A and 13B, the via 206a is provided above the oxide semiconductor layer 210 and so as not to overlap with the oxide semiconductor layer 210. More specifically, in this embodiment, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the via 206a is located in this extended portion 212a. In this embodiment as well, this makes it possible to avoid oxidation of the via 206a, which is made of a metal material or the like, by oxygen diffused from the oxide semiconductor layer 210, and thus prevent it from becoming highly resistive.

[0089] In this embodiment as well, as shown in the lower part of Figures 13A and 13B, the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, has two protrusions 210a at both ends that protrude downward along the thickness direction of the oxide semiconductor layer 210. Furthermore, vias 206b are provided above the oxide semiconductor layer 210 so as to connect from above to the vertex region of each protrusion 210a. In this embodiment as well, by providing protrusions 210a at the ends of the oxide semiconductor layer 210, which forms the source / drain region of the thin-film transistor Tr5, the source / drain region is brought closer to the barrier film 230. According to this embodiment, by bringing the barrier film 230, which has a reducing effect, closer, the source / drain region can be reduced and its resistance reduced.

[0090] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figures 13A and 13B, but can take on various forms.

[0091] <5.2 Modified Examples> Next, the detailed structure of the thin-film transistor Tr5 according to the modified examples of this embodiment will be described with reference to Figures 14 to 16. Figure 14 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 1 of this embodiment, Figure 15 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 2 of this embodiment, and Figure 16 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 3 of this embodiment. More specifically, in these figures, the upper part of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower part of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper part of the figure.

[0092] (Modification 1) As shown in Figure 14, in Modification 1 of this embodiment, the thin-film transistor Tr5 may further have an oxygen supply layer 220 that is provided opposite the via 206a across the channel region and supplies oxygen to the channel region. In this Modification 1, by providing the oxygen supply layer 220 in this way, the channel region of the oxide semiconductor layer 210 can be oxidized and the characteristics of the channel region can be suitably adjusted.

[0093] (Modification 2) As shown in Figure 15, in Modification 2 of this embodiment, the thin-film transistor Tr5 may further have a hydrogen supply layer 222 that supplies hydrogen to the source / drain region, which is provided opposite the via 206b with the source / drain region in between. In detail, the hydrogen supply layer 222 is located below the oxide semiconductor layer 210 and is provided so as to overlap with the source / drain region. In this Modification 2, by providing the hydrogen supply layer 222 in this way, the source / drain region of the oxide semiconductor layer 210 can be reduced to lower its resistance.

[0094] (Modification 3) As shown in Figure 16, in Modification 3 of this embodiment, the thin-film transistor Tr5 may have an oxygen supply layer 220 and a hydrogen supply layer 222. In other words, Modification 3 is an embodiment that combines Modification 1 and Modification 2 described above.

[0095] <<6. Fourth Embodiment>> <6.1 Detailed Configuration> Next, with reference to Figure 17, the detailed structure of the thin-film transistor Tr5 according to the fourth embodiment of the present disclosure will be described. In this embodiment, the gate region of the thin-film transistor Tr5 has a via 206 below it, and the source / drain region has a via 206 above it, so that it has a "gate: bottom contact, source / drain: top contact" configuration. Figure 17 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 according to this embodiment. More specifically, the upper part of Figure 17 shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower part of Figure 17 shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper part of Figure 17. In this embodiment, the plan view of the thin-film transistor Tr5 corresponds to the plan view shown in the lower part of Figure 5A, and the enlarged view of region C in the upper part of Figure 17 corresponds to the enlarged view shown in the lower part of Figure 13B. In the following, we will omit explanations of points common to the embodiments described above and instead explain the points that differ from each embodiment.

[0096] In this embodiment, as shown in Figure 17, similar to the first to third embodiments, the surface of the channel region located in the center of the oxide semiconductor layer 210 is covered by the gate electrode 212 via the gate insulating film 214. In this embodiment as well, by covering the surface of the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to suppress oxidation and reduction of the channel region due to the diffusion of oxygen and hydrogen from the surroundings, which can change its characteristics. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to prevent light from being incident from above. As a result, according to this embodiment, photodegradation of the oxide semiconductor layer 210 can be suppressed and malfunction of the thin-film transistor Tr5 can be prevented. Furthermore, according to this embodiment, since no new light-shielding film is added, the manufacturing cost and manufacturing time of the pixel 20 are not significantly increased.

[0097] Furthermore, in this embodiment, as shown in the lower part of Figure 17, the via 206a is provided below the oxide semiconductor layer 210 and so as not to overlap with the oxide semiconductor layer 210. More specifically, in this embodiment, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the via 206a is located in this extended portion 212a. In this embodiment as well, this makes it possible to avoid oxidation of the via 206a, which is made of a metal material or the like, by oxygen diffused from the oxide semiconductor layer 210, resulting in increased resistance.

[0098] In this embodiment as well, as shown in the upper part of Figure 17, the oxide semiconductor layer 210 that forms the source / drain region of the thin-film transistor Tr5 has two protrusions 210a that protrude downward along the thickness direction of the oxide semiconductor layer 210 at both ends. Furthermore, vias 206b are provided so as to connect from above to the vertex region of each protrusion 210a. In this embodiment as well, by providing protrusions 210a at the ends of the oxide semiconductor layer 210 that forms the source / drain region of the thin-film transistor Tr5, the source / drain region is brought closer to the barrier film 230. According to this embodiment, by bringing the barrier film 230, which has a reducing effect, closer, the source / drain region can be reduced and its resistance reduced.

[0099] In this embodiment, the thin-film transistor Tr5 is not limited to the form shown in Figure 17, but can take on various forms.

[0100] <6.2 Modified Examples> Next, the detailed structure of the thin-film transistor Tr5 according to the modified examples of this embodiment will be described with reference to Figures 18 to 19. Figure 18 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 1 of this embodiment, Figure 17 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 2 of this embodiment, and Figure 19 is a schematic diagram showing an example of the detailed configuration of the thin-film transistor Tr5 of a display device according to Modified Example 3 of this embodiment. More specifically, in these figures, the upper section of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the lower section of the figure shows a cross-sectional view when the thin-film transistor Tr5 is cut along the line B-B' in the upper section of the figure.

[0101] (Modification 1) As shown in Figure 18, in Modification 1 of this embodiment, the thin-film transistor Tr5 may further have an oxygen supply layer 220 that is provided opposite the via 206a across the channel region and supplies oxygen to the channel region. In this Modification 1, by providing the oxygen supply layer 220 in this way, the channel region of the oxide semiconductor layer 210 can be oxidized and the characteristics of the channel region can be suitably adjusted.

[0102] Furthermore, in this modified example 1, by providing a protrusion 210a at the edge of the oxide semiconductor layer 210, the distance between the channel region and the source / drain region can be increased without increasing the area occupied by the thin-film transistor Tr5. Therefore, according to this modified example 1, the diffusion of oxygen from the oxygen supply layer 220 to the source / drain region can be suppressed, thus avoiding increased resistance in the source / drain region.

[0103] (Modification 2) As shown in Figure 19, in Modification 2 of this embodiment, the thin-film transistor Tr5 may further have a hydrogen supply layer 222 that is provided opposite the via 206b with the source / drain region in between, and that supplies hydrogen to the source / drain region. In this Modification 2, by providing the hydrogen supply layer 222 in this way, the source / drain region of the oxide semiconductor layer 210 can be reduced to lower its resistance.

[0104] (Modification 3) As shown in Figure 20, in Modification 3 of this embodiment, the thin-film transistor Tr5 may have an oxygen supply layer 220 and a hydrogen supply layer 222. In other words, Modification 3 is an embodiment that combines Modification 1 and Modification 2 described above.

[0105] As described above, in the embodiments of this disclosure, the vias 206a and 206b of the thin-film transistor Tr5 can be provided at various positions. As a result, according to the embodiments of this disclosure, the pixels 20 can be miniaturized and the display device 10 can be made smaller.

[0106] <<7. Fifth Embodiment>> Next, with reference to Figures 21A to 21G, variations in the planar configuration of the thin-film transistor Tr5 according to the fifth embodiment of the present disclosure will be described. Figures 21A to 21G are schematic diagrams showing an example of the planar configuration of the thin-film transistor Tr5 according to the present embodiment. In the following, explanations of points common to each of the embodiments described above will be omitted, and points that differ from each embodiment will be explained.

[0107] In the example shown in Figure 21A, the thin-film transistor Tr5 has a gate electrode 212 provided on a strip-shaped oxide semiconductor layer 210 via a gate insulating film 214. In the example shown in Figure 21A, a pair of vias 206b, electrically connected to the source / drain region, are provided so as to sandwich the gate electrode 212. In other words, in the example shown in Figure 21A, the centers of the gate electrode 212 and the centers of the pair of vias 206b are aligned in a straight line in a plan view. Furthermore, in the example shown in Figure 21A, the via 206a connected to the gate electrode 212 is provided so as to overlap with the oxide semiconductor layer 210. By doing so, the area occupied by the thin-film transistor Tr5 can be reduced in the example shown in Figure 21A.

[0108] Furthermore, in the example shown in Figure 21B, the thin-film transistor Tr5 has an L-shaped oxide semiconductor layer 210 and a gate electrode 212 provided on the center of the oxide semiconductor layer 210 via a gate insulating film 214. In the example shown in Figure 21B, a pair of vias 206b are provided on the ends of the L-shaped oxide semiconductor layer 210, which are electrically connected to the source / drain region of the thin-film transistor Tr5. In other words, in the example shown in Figure 21B, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 206b are arranged in an L-shape. Moreover, in the example shown in Figure 21B, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the vias 206a are located on this extended portion 212a. In the example shown in Figure 21B, this configuration prevents the vias 206a, which are made of a metal material or the like, from being oxidized by oxygen diffused from the oxide semiconductor layer 210, resulting in increased resistance.

[0109] In the example shown in Figure 21C, the thin-film transistor Tr5 has an L-shaped oxide semiconductor layer 210 and a gate electrode 212 provided on the center of the oxide semiconductor layer 210 via a gate insulating film 214. In the example shown in Figure 21C, a pair of vias 206b are provided on the ends of the L-shaped oxide semiconductor layer 210, which are electrically connected to the source / drain region of the thin-film transistor Tr5. Furthermore, in the example shown in Figure 21C, the via 206a connected to the gate electrode 212 is provided so as to overlap with the oxide semiconductor layer 210.

[0110] Furthermore, in the example shown in Figure 21D, the thin-film transistor Tr5 has a U-shaped oxide semiconductor layer 210 and a gate electrode 212 provided on the center of the oxide semiconductor layer 210 via a gate insulating film 214. In the example shown in Figure 21D, a pair of vias 206b are provided on the ends of the U-shaped oxide semiconductor layer 210, which are electrically connected to the source / drain region of the thin-film transistor Tr5. In other words, in a plan view, the center of the gate electrode 212 and the centers of the pair of vias 206b are arranged in a U-shape. Moreover, in the example shown in Figure 21D, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the vias 206a are located on this extended portion 212a.

[0111] Furthermore, in the example shown in Figure 21E, the thin-film transistor Tr5 has a U-shaped oxide semiconductor layer 210 and a gate electrode 212 provided on the center of the oxide semiconductor layer 210 via a gate insulating film 214. In the example shown in Figure 21E, a pair of vias 206b are provided on the ends of the U-shaped oxide semiconductor layer 210, which are electrically connected to the source / drain region of the thin-film transistor Tr5. In addition, in the example shown in Figure 21E, the via 206a connected to the gate electrode 212 is provided so as to overlap with the oxide semiconductor layer 210.

[0112] Furthermore, as shown in the example in Figure 21F, a portion of the thin-film transistor Tr5 may share a portion of its region with an adjacent thin-film transistor Tr5. For example, as shown in Figure 21F, the gate electrode 212 of one thin-film transistor Tr5 is provided on the center of a Y-shaped oxide semiconductor layer 210. In addition, a pair of vias 206b electrically connected to the source / drain region of one thin-film transistor Tr5 and a via 206b electrically connected to the source or drain region of the other thin-film transistor Tr11 are provided on the three ends of the Y-shaped oxide semiconductor layer 210. In other words, in the example in Figure 21F, in a plan view, the center of the gate electrode 212 of one thin-film transistor Tr5, the center of the pair of vias 206b of one thin-film transistor Tr5, and the center of one of the pair of vias 206b of the other thin-film transistor Tr5 are arranged in a Y shape. In this way, the area occupied by the two thin-film transistors Tr5 can be reduced in the example in Figure 21F. Furthermore, in the example shown in Figure 21F, the gate electrode 212 has an extended portion 212a that does not overlap with the oxide semiconductor layer 210, and the via 206a is located in the extended portion 212a.

[0113] Furthermore, in the example shown in Figure 21G, the gate electrode 212 of one thin-film transistor Tr5 is provided on the center of the Y-shaped oxide semiconductor layer 210. In addition, a pair of vias 206b are provided on the three ends of the Y-shaped oxide semiconductor layer 210, which are electrically connected to the source / drain region of one thin-film transistor Tr5, and vias 206b are electrically connected to the source or drain region of the other thin-film transistor Tr11.

[0114] As described above, in this embodiment, the planar structure of the thin-film transistor Tr5 can be modified in various ways. As a result, in this embodiment, the area occupied by the thin-film transistor Tr5 can be reduced, and consequently, the display device 10 can be miniaturized.

[0115] <<8. Sixth Embodiment>> Next, the detailed structure of the pixel 20 according to the sixth embodiment of the present disclosure will be described with reference to Figures 22A and 22B. Figure 22A is a schematic diagram showing an example of the cross-sectional configuration of the pixel 20 according to this embodiment, and Figure 22B is a schematic diagram showing an example of the main part of the cross-sectional configuration of the pixel 20 according to this embodiment, and in detail is an enlarged view of region D shown in Figure 22A. In the following, the explanation of points common to each of the embodiments described above will be omitted, and the points that differ from each of the embodiments will be explained.

[0116] As shown in Figure 22A, in the pixel 20 according to this embodiment, a wiring layer 200 is stacked on a semiconductor substrate 100, and a light-emitting part 300, which is a light-emitting element (EL), is provided on the wiring layer 200. The light-emitting part 300 is electrically connected to a drive transistor Tr1, a light-emitting control transistor Tr3, a writing transistor Tr2, and a switching transistor Tr4, which are included in the drive circuit. In detail, for example, the semiconductor substrate 100 is provided with a drive transistor Tr1 and a light-emitting control transistor Tr3, which are included in the drive circuit. Furthermore, for example, a writing transistor Tr2 and a switching transistor Tr4, which are included in the drive circuit, are provided above the wiring layer 200. The writing transistor Tr2 and the switching transistor Tr4 are configured as thin-film transistors. In addition, in order to prevent changes in characteristics due to heat applied during the manufacturing of the pixel 20, it is preferable that the writing transistor Tr2 and the switching transistor Tr4, which are thin-film transistors, be provided in the upper layer of the wiring layer 200 so that they are created in the latter half of the manufacturing of the pixel 20.

[0117] In detail, in this embodiment, as shown in Figure 22B, the writing transistor Tr2 can have the configuration of the thin-film transistor Tr5 according to the first embodiment, for example, "gate: top contact, source / drain: bottom contact". Also, the switching transistor Tr4 can have the configuration of the thin-film transistor Tr5 according to the third embodiment, for example, "gate / source / drain: top contact".

[0118] As described above, in this embodiment, the vias 206a and 206b of each thin-film transistor Tr5 can be provided above or below the oxide semiconductor layer 210. As a result, in this embodiment, the pixel 20 can be miniaturized.

[0119] In this embodiment, the pixel 20 is not limited to the form shown in Figures 22A and 22B, but can take on various forms.

[0120] <<9. Seventh Embodiment>> Next, as a seventh embodiment of the present disclosure, an example of a method for manufacturing the main part of the display device 10 will be described with reference to Figures 23A to 23F. Figures 23A to 23F are cross-sectional views for illustrating the method for manufacturing the main part of the display device 10 according to this embodiment. More specifically, the left side of each figure shows a cross-sectional view when the thin-film transistor Tr5 is cut in a direction perpendicular to the stacking direction, and the right side of each figure shows a cross-sectional view corresponding to the cross-section shown in the upper part of Figure 5B.

[0121] First, as shown in the upper part of Figure 23A, an insulating film 202, a barrier film 230, etc. are deposited on top of the semiconductor substrate 100 (not shown). Then, a trench is created on the insulating film 202, and a gate electrode 212 is deposited so as to fill the trench. Next, as shown in the lower part of Figure 23A, a gate insulating film 214 is deposited on the insulating film 202 including the gate electrode 212. Furthermore, as shown in the upper part of Figure 23B, an opening is created in the gate insulating film 214 at the location that will become the source / drain region of the thin-film transistor Tr5. Next, as shown in the lower part of Figure 23B, an oxide semiconductor layer 210 is deposited on the gate insulating film 214 including the opening.

[0122] Then, as shown in the upper part of Figure 23C, a gate insulating film 214 is deposited so as to cover the oxide semiconductor layer 210. Next, as shown in the lower part of Figure 23C, the stacking of the gate insulating film 214 and the oxide semiconductor layer 210 is etched to match the shape of the thin-film transistor Tr5. Furthermore, as shown in the upper part of Figure 23D, a gate insulating film 214 is deposited so as to cover the sidewall of the thin-film transistor Tr5. Next, as shown in the lower part of Figure 23D, a gate electrode 212 is deposited so as to cover the gate insulating film 214.

[0123] Then, as shown in the upper part of Figure 23E, the gate electrode 212 is etched. Next, as shown in the lower part of Figure 23E, the stack of the gate insulating film 214 and the oxide semiconductor layer 210 is etched to form a trench along the side wall of the etched gate electrode 212. Furthermore, the gate electrode 212 is deposited so as to fill the trench.

[0124] Furthermore, by forming vias 206 and the like, the main parts of the display device 10 as shown in Figure 23F can be manufactured.

[0125] In this embodiment, the method for manufacturing the display device 10 is not limited to the method shown in Figures 23A to 23F.

[0126] Furthermore, the display device 10 according to the embodiment of this disclosure can be manufactured using methods, apparatus, and conditions commonly used in the manufacture of semiconductor devices. In other words, the display device 10 according to this embodiment can be manufactured using existing semiconductor device manufacturing methods.

[0127] Examples of the methods mentioned above include the PVD (Physical Vapor Deposition) method, the CVD (Chemical Vapor Deposition) method, and the ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) coupled bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, counter-target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and optical CVD. Furthermore, other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, as well as stamping, spraying, air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calender coater. In addition, patterning methods include chemical etching such as shadow masks, laser transfer, and photolithography, as well as physical etching using ultraviolet light or lasers. Furthermore, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0128] <<10. Summary>> As described above, in each embodiment of the present disclosure, by covering the central surface of the oxide semiconductor layer 210, which is the channel region of the thin-film transistor Tr5, with the gate electrode 212 via the gate insulating film 214, it is possible to suppress oxidation and reduction of the channel region and the resulting change in its characteristics. Furthermore, in this embodiment, by covering the channel region of the thin-film transistor Tr5 with the gate electrode 212 via the gate insulating film 214, it is possible to prevent light from being incident from above and suppress photodegradation of the oxide semiconductor layer 210. Moreover, according to this embodiment, there is no need to add a new light-shielding film, so the manufacturing cost and manufacturing time of the pixel 20 are not significantly increased. In addition, in each embodiment of the present disclosure, by providing a protrusion 210a at the end of the oxide semiconductor layer 210, which is the source / drain region of the thin-film transistor Tr5, the source / drain region is brought closer to the barrier film 230. In this way, according to this embodiment, the source / drain region can be reduced to lower resistance.

[0129] In other words, according to the embodiments of this disclosure, the properties of the oxide semiconductor layer that forms the channel can be adjusted and stabilized.

[0130] Furthermore, the technology disclosed herein may be applied not only to the display device 10, but also to various types of semiconductor devices.

[0131] Furthermore, each embodiment of this disclosure is not limited to the form shown in the figures, but can be modified in various ways and can also be combined with one another.

[0132] Furthermore, the display device 10 according to the embodiment of this disclosure can be applied to, for example, display devices for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), display devices for smartphones, television equipment, electronic viewfinders (EVF), or small projectors. The display device 10 can also be applied to various lighting devices.

[0133] <<11. Examples of Application>> For example, the technology relating to this disclosure may be applied to the display units of various electronic devices. Therefore, examples of electronic devices to which this technology can be applied will be described below.

[0134] (Specific Example 1) Figure 24A is a front view showing an example of the external appearance of the digital still camera 500, and Figure 24B is a rear view showing an example of the external appearance of the digital still camera 500. This digital still camera 500 is a single-lens reflex type with interchangeable lenses, and has an interchangeable shooting lens unit (interchangeable lens) 512 located approximately in the center of the front of the camera body 511, and a grip portion 513 for the photographer to hold on the left side of the front.

[0135] A monitor 514 is provided on the back of the camera body 511, slightly to the left of the center. An electronic viewfinder (eyepiece) 515 is provided above the monitor 514. The photographer can determine the composition by looking through the electronic viewfinder 515 and visually confirming the light image of the subject guided by the shooting lens unit 512. The display device 10 according to the embodiment of this disclosure can be used as the monitor 514 and the electronic viewfinder 515.

[0136] (Specific Example 2) Figure 25 is an external view of a head-mounted display 600. The head-mounted display 600 has, for example, an eyeglass-shaped display unit 611 and ear hooks 612 on both sides for attachment to the user's head. In this head-mounted display 600, the display device 10 according to the embodiment of this disclosure can be used as the display unit 611.

[0137] (Specific Example 3) Figure 26 is an external view of the see-through head-mounted display 634. The see-through head-mounted display 634 consists of a main body 632, an arm 633, and a lens barrel 631.

[0138] The main body 632 is connected to the arm 633 and the eyeglasses 630. Specifically, the long end of the main body 632 is connected to the arm 633, and one side of the main body 632 is connected to the eyeglasses 630 via a connecting member. The main body 632 may also be directly attached to the head of a person.

[0139] The main body 632 houses a control board for controlling the operation of the see-through head-mounted display 634 and a display unit. The arm 633 connects the main body 632 to the lens barrel 631 and supports the lens barrel 631. Specifically, the arm 633 is connected to the end of the main body 632 and the end of the lens barrel 631, respectively, and fixes the lens barrel 631 in place. The arm 633 also houses signal lines for communicating image-related data provided from the main body 632 to the lens barrel 631.

[0140] The lens barrel 631 projects image light, provided from the main body 632 via the arm 633, through the eyepiece lens towards the eyes of the user wearing the see-through head-mounted display 634. In this see-through head-mounted display 634, the display device 10 according to the embodiment of this disclosure can be used in the display section of the main body 632.

[0141] (Specific Example 4) Figure 27 shows an example of the appearance of a television device 710. This television device 710 has, for example, a video display screen section 711 including a front panel 712 and a filter glass 713, and this video display screen section 711 is configured by a display device 10 according to the embodiment of this disclosure.

[0142] (Specific Example 5) Figure 28 shows an example of the appearance of a smartphone 800. The smartphone 800 has a display unit 802 that displays various information, and an operation unit consisting of buttons, etc. that accept user input. The display unit 802 may be the display device 10 according to this embodiment.

[0143] (Specific Example 6) Figures 29A and 29B show the internal configuration of an automobile having a display device 10 according to the present disclosure as a display device. More specifically, Figure 29A shows the interior of the automobile from the rear to the front, and Figure 29B shows the interior of the automobile from the diagonally rear to the diagonally front.

[0144] The automobile shown in Figures 29A and 29B includes a center display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916. Some or all of these displays can be fitted with the display device 10 according to the embodiment of this disclosure.

[0145] The center display 911 is positioned on the center console 907, facing the driver's seat 901 and the passenger seat 902. Figures 29A and 29B show an example of a horizontally elongated center display 911 extending from the driver's seat 901 to the passenger seat 902, but the screen size and placement of the center display 911 are arbitrary. The center display 911 can display information detected by various sensors (not shown). As a specific example, the center display 911 can display images captured by an image sensor, distance images to obstacles in front of or to the side of the vehicle measured by a ToF (Time of Flight) sensor, and the body temperature of passengers detected by an infrared sensor. The center display 911 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0146] Safety-related information includes information such as drowsiness detection, distraction detection, detection of mischief by a passenger, seatbelt fastening status, and detection of an unattended occupant. This information is detected, for example, by a sensor (not shown) placed on top of the back of the center display 1911. Operation-related information is detected by sensing occupant gestures using sensors. The detected gestures may include the operation of various equipment in the vehicle. For example, the sensor detects the operation of air conditioning equipment, navigation systems, AV (Audio / Visual) systems, lighting systems, etc. Life logs include the life logs of all occupants. For example, life logs include records of each occupant's actions while riding in the vehicle. By acquiring and saving life logs, it is possible to confirm the state of the occupants at the time of an accident. Health-related information is detected by sensing the occupant's body temperature using a temperature sensor and inferring the occupant's health status based on the detected body temperature. Alternatively, the occupant's face may be captured using an image sensor, and the occupant's health status may be inferred from the facial expression captured. Furthermore, the system may engage in automated voice conversations with the occupants and infer their health status based on their responses. Authentication / identification-related information includes keyless entry functions that use sensors for facial recognition and functions that automatically adjust seat height and position based on facial recognition. Entertainment-related information includes functions that use sensors to detect information on how the occupants operate the AV equipment and functions that use sensors to recognize the occupants' faces and provide content suitable for the occupants through the AV equipment.

[0147] The console display 912 can be used, for example, to display life log information. The console display 912 is located near the shift lever 908 on the center console 907 between the driver's seat 901 and the passenger seat 902. The console display 912 can also display information detected by various sensors (not shown). In addition, the console display 912 may display an image of the area around the vehicle captured by an image sensor, or it may display an image showing the distance to obstacles around the vehicle.

[0148] The head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901. The head-up display 913 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 913 is often virtually positioned in front of the driver's seat 901, it is suitable for displaying information directly related to the operation of the vehicle, such as the vehicle's speed and fuel (battery) level.

[0149] The digital rearview mirror 914 can not only display what is behind the vehicle, but also what is happening to the passengers in the rear seat. By placing a sensor (not shown) on top of the back of the digital rearview mirror 914, it can be used, for example, to display life log information.

[0150] The steering wheel display 915 is positioned near the center of the steering wheel 906 of the automobile. The steering wheel display 915 can be used to display at least one of the following: safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 915 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0151] The rear entertainment display 916 is mounted on the back of the driver's seat 901 and the passenger seat 902, and is intended for viewing by rear-seat passengers. The rear entertainment display 916 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 916 is in front of the rear-seat passengers, it displays information relevant to the rear-seat passengers. For example, it may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of measurements of the rear-seat passengers' body temperature, etc., taken by a temperature sensor (not shown).

[0152] <<12. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these will naturally also be understood to fall within the technical scope of the present disclosure.

[0153] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that are obvious to those skilled in the art from the description herein, in addition to or in lieu of the effects described herein.

[0154] Furthermore, this technology can also take the following configurations: (1) A semiconductor element comprising: an oxide semiconductor layer provided in a wiring layer including an insulating film and wiring, having a channel region in the center and source and drain regions at each end; a gate insulating film covering the entire surface of the channel region; and a gate electrode covering the entire surface of the channel region via the gate insulating film. (2) The semiconductor element according to (1) above, wherein when the channel region is cut along the channel width direction, the gate electrode covers the upper surface, lower surface and side surface of the channel region. (3) The semiconductor element according to (1) above, wherein the gate electrode is formed from a metal film or a metal nitride film. (4) The semiconductor element according to any one of (1) to (3) above, wherein the source region and the drain region have protrusions that protrude downward along the film thickness direction of the oxide semiconductor layer. (5) The semiconductor element according to (4) above, further comprising two first vias electrically connected to each of the source region and the drain region, wherein the first vias are electrically connected to the apex regions of the protrusions. (6) The semiconductor element according to (5), wherein the apex region of the protrusion faces a barrier film that prevents the diffusion of a metal species. (7) The semiconductor element according to (6), wherein the barrier film is formed from a silicon carbonitride film. (8) The semiconductor element according to any one of (5) to (7), further comprising a hydrogen supply layer provided so as to face the first via, sandwiching the source region and the drain region, and supplying hydrogen to the source region and the drain region. (9) The semiconductor element according to any one of (1) to (8), further comprising a second via electrically connected to the gate electrode. (10) The semiconductor element according to (9), wherein when the semiconductor element is viewed from above, the second via is superimposed on the oxide semiconductor layer. (11) The semiconductor element according to (9), wherein when the semiconductor element is viewed from above, the gate electrode has an extended portion that does not superimpose on the oxide semiconductor layer, and the second via is located on the extended portion.(12) The semiconductor element according to any one of (9) to (11) above, wherein the second via is located above the oxide semiconductor layer. (13) The semiconductor element according to any one of (9) to (11) above, wherein the second via is located below the oxide semiconductor layer. (14) The semiconductor element according to any one of (9) to (13) above, further comprising an oxygen supply layer provided opposite to the second via across the channel region and supplying oxygen to the channel region. (15) The semiconductor element according to any one of (1) to (14) above, wherein the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, silicon, hafnium, and zinc. (16) The semiconductor element according to any one of (1) to (15) above, wherein the wiring layer is laminated on a semiconductor substrate. (17) The semiconductor element according to (16) above, wherein the semiconductor element is located in the upper part of the wiring layer. (18) A semiconductor element according to (16) or (17) above, which is electrically connected to a light-emitting element provided above the wiring layer. (19) A semiconductor element according to any one of (1) to (18) above, wherein the insulating film contains oxygen. (20) A semiconductor device comprising a wiring layer including an insulating film and wiring, and a semiconductor element provided within the wiring layer, wherein the semiconductor element includes: an oxide semiconductor layer having a channel region in the center and source regions and drain regions at each of its ends; a gate insulating film covering the entire surface of the channel region; and a gate electrode covering the entire surface of the channel region via the gate insulating film.

[0155] 10 Display device 20, 20a Pixels 30 Pixel array section 31 Scanning lines 32, 33 Drive lines 34 Signal lines 40, 50, 60 Scanning section 70 Signal output section 80 Display panel 100 Semiconductor substrate 102, 212 Gate electrode 104 Diffusion region 106 Element isolation section 200 Wiring layer 202 Insulating film 204 Wiring 206, 206a, 206b Via 210 Oxide semiconductor layer 210a Protruding section 212a Stretched section 214 Gate insulating film 220 Oxygen supply layer 222 Hydrogen supply layer 230 Barrier film 300 Light-emitting section 310 Anode electrode 312 Cathode electrode 314 Light-emitting layer

Claims

1. A semiconductor element comprising: an oxide semiconductor layer provided within a wiring layer including an insulating film and wiring, having a channel region in the center and source and drain regions at each of its ends; a gate insulating film covering the entire surface of the channel region; and a gate electrode covering the entire surface of the channel region via the gate insulating film.

2. When the channel region is cut along the channel width direction, the gate electrode covers the upper surface, lower surface and side surface of the channel region, as described in claim 1.

3. The semiconductor element according to claim 1, wherein the gate electrode is formed from a metal film or a metal nitride film.

4. The semiconductor element according to claim 1, wherein the source region and the drain region have protrusions that project downward along the film thickness direction of the oxide semiconductor layer.

5. The semiconductor element according to claim 4, further comprising two first vias electrically connected to the source region and the drain region, respectively, wherein the first vias are electrically connected to the apex region of the protrusion.

6. The semiconductor element according to claim 5, wherein the apex region of the protruding portion faces a barrier film that prevents the diffusion of a metal species.

7. The semiconductor device according to claim 6, wherein the barrier film is formed from a silicon carbonitride film.

8. The semiconductor element according to claim 5, further comprising a hydrogen supply layer provided opposite to the first via, with the source region and the drain region in between, for supplying hydrogen to the source region and the drain region.

9. The semiconductor element according to claim 1, further comprising a second via electrically connected to the gate electrode.

10. The semiconductor element according to claim 9, wherein, when the semiconductor element is viewed from above, the second via is superimposed on the oxide semiconductor layer.

11. The semiconductor element according to claim 9, wherein, when viewed from above, the gate electrode has an extended portion that does not overlap with the oxide semiconductor layer, and the second via is located in the extended portion.

12. The semiconductor device according to claim 9, wherein the second via is located above the oxide semiconductor layer.

13. The semiconductor device according to claim 9, wherein the second via is located below the oxide semiconductor layer.

14. The semiconductor element according to claim 9, further comprising an oxygen supply layer provided opposite to the second via, straddling the channel region, and supplying oxygen to the channel region.

15. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from the group consisting of aluminum, indium, gallium, tin, silicon, hafnium, and zinc.

16. The semiconductor element according to claim 1, wherein the wiring layer is laminated on a semiconductor substrate.

17. The semiconductor element according to claim 16, wherein the semiconductor element is located in the upper part of the wiring layer.

18. The semiconductor element according to claim 16, which is electrically connected to a light-emitting element provided above the wiring layer.

19. The semiconductor device according to claim 1, wherein the insulating film contains oxygen.

20. A semiconductor device comprising a wiring layer including an insulating film and wiring, and a semiconductor element provided within the wiring layer, wherein the semiconductor element includes: an oxide semiconductor layer having a channel region in the center and a source region and a drain region at each of its ends; a gate insulating film covering the entire surface of the channel region; and a gate electrode covering the entire surface of the channel region via the gate insulating film.

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