Display device and electronic apparatus

Abstract

The purpose of the present invention is to suppress noise generation in an image or the like. This display device comprises a pixel array, signal lines, and first and second drive circuits. In the pixel array, pixels each having a light-emitting element are provided in an array along a first direction and a second direction intersecting the first direction. The signal lines are connected to the pixels along the second direction. The first drive circuit brings the pixels arranged along the first direction into a drivable state. The second drive circuit outputs an offset signal and a pixel signal to the pixels belonging to the first direction and selected by the first drive circuit via the respective signal lines. The second drive circuit comprises a ramp signal output circuit that outputs a ramp signal, and a switch that acquires and holds the ramp signal output from the ramp signal output circuit at a timing corresponding to output intensity for each signal line. The ramp signal output circuit outputs a first ramp signal corresponding to the offset signal and a second ramp signal corresponding to the pixel signal, after varying the slopes thereof.

Description

Display device and electronic device

[0001] The present disclosure relates to a display device and an electronic device.

[0002] In a display device that outputs image and video information, each pixel emits light at an appropriate luminance by writing a luminance value via a signal line, thereby forming an image or the like. This luminance value is often transmitted as a digital signal. In this case, digital-to-analog conversion is performed on the luminance signal and the offset signal using a ramp signal, and a write signal converted into an analog signal is output to the light-emitting element of the pixel.

[0003] However, the slope of the ramp signal may vary due to power supply noise or the like, resulting in variation in the write signal. Due to this influence, there is a possibility that random or fixed streak-like noise may occur in the scanning direction in which the process of causing light emission at the same timing is executed.

[0004] International Publication No. 2021 / 124748

[0005] Therefore, one of the non-limiting problems to be solved by the embodiments of the present disclosure is to suppress the occurrence of noise in images and the like. The problems to be solved by the embodiments of the present disclosure can also be, as some further non-limiting examples, problems corresponding to the effects described in the embodiments. That is, the problems corresponding to any at least one of the effects described in the description of the embodiments of the present disclosure can be the problems to be solved in the present disclosure.

[0006] According to one embodiment, the display device comprises a pixel array, signal lines, a first drive circuit, and a second drive circuit. The pixel array is arranged in an array along a first direction and a second direction intersecting the first direction, with pixels having light-emitting elements. The signal lines are connected to the pixels along the second direction. The first drive circuit makes the pixels arranged along the first direction drivable. The second drive circuit outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit. The second drive circuit comprises a lamp signal output circuit that outputs a lamp signal, and a switch that acquires and holds the lamp signal output from the lamp signal output circuit at a timing corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal, with the slopes changed.

[0007] The lamp signal output circuit may output the first lamp signal such that its slope is gentler than the slope of the second lamp signal.

[0008] The lamp signal output circuit may include a first lamp signal output circuit that outputs the first lamp signal, and a second lamp signal output circuit that outputs the second lamp signal.

[0009] The lamp signal output circuit may include a capacitor whose first terminal is connected to the positive power supply voltage line and whose second terminal is connected to the output terminal of the lamp signal output circuit, and a transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line, and whose gate width can be changed, and the first lamp signal or the second lamp signal may be output depending on the gate width of the transistor.

[0010] The transistor may include a first transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line, and a second transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line.

[0011] The lamp signal output circuit may output the first lamp signal when the first transistor is on and the second transistor is off, or it may output the second lamp signal when the first transistor is off and the second transistor is on.

[0012] The lamp signal output circuit may output the first lamp signal when the first transistor is on and the second transistor is off, or it may output the second lamp signal when both the first and second transistors are on.

[0013] The lamp signal output circuit may include a capacitor whose first terminal is connected to the positive power supply voltage line and whose second terminal is connected to the output terminal of the lamp signal output circuit, and whose capacitance can be changed, and a transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line, and the first lamp signal or the second lamp signal may be output depending on the capacitance of the capacitor.

[0014] The capacitor may include a first capacitor, the first of which is connected to the positive power supply voltage line via a first switch and the second capacitor, the first of which is connected to the positive power supply voltage line via a second switch and the second capacitor, the second capacitor, the first of which is connected to the positive power supply voltage line via a second switch and the second capacitor, the second capacitor, the second capacitor,

[0015] The lamp signal output circuit may output the first lamp signal when the first switch is on and the second switch is off, or it may output the second lamp signal when the first switch is off and the second switch is on.

[0016] The lamp signal output circuit may output the first lamp signal when the first switch is on and the second switch is off, or it may output the second lamp signal when both the first switch and the second switch are on.

[0017] According to one embodiment, the electronic device comprises a pixel array, signal lines, a first drive circuit, and a second drive circuit. The pixel array is arranged in an array along a first direction and a second direction intersecting the first direction, with pixels having light-emitting elements. The signal lines are connected to the pixels along the second direction. The first drive circuit makes the pixels arranged along the first direction drivable. The second drive circuit outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit. The second drive circuit comprises a lamp signal output circuit that outputs a lamp signal, and a switch that acquires and holds the lamp signal output from the lamp signal output circuit at a timing corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal, with the slopes changed.

[0018] A block diagram schematically showing an example of a part of the display device according to one embodiment. A diagram showing an example of the timing chart of the pixel circuit according to one embodiment. A diagram showing an example of the lamp signal according to a comparative example. A diagram showing an example of the setting of the offset value and brightness value according to a comparative example. A diagram showing an example of the setting of the offset value and brightness value according to a comparative example. A diagram showing an example of the setting of the offset value and brightness value according to a comparative example. A diagram showing an example of the control of the lamp signal according to one embodiment. A diagram showing an example of the control of the lamp signal according to one embodiment. A diagram showing an example of the control of the lamp signal according to one embodiment. A diagram showing an example of a part of the second drive circuit according to one embodiment. A diagram showing an example of the lamp signal output circuit according to one embodiment. A diagram showing an example of the lamp signal output circuit according to one embodiment. A diagram showing an example of the lamp signal output circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. A circuit diagram showing an schematic example of the pixel circuit according to one embodiment. An external view of a head-mounted display, an electronic device as an example of its application. An external view of smart glasses, an electronic device as an example of its application. A front view of a digital camera, an electronic device as an example of its application. A rear view of a digital camera, an electronic device as an example of its application. An external view of a television system, an electronic device as an example of its application. An external view of a smartphone, an electronic device as an example of its application. A diagram showing the interior of a vehicle containing an electronic device, from the rear to the front, as an example of its application. A diagram showing the interior of a vehicle containing an electronic device, from the rear diagonal to the front diagonal, as an example of its application.

[0019] The embodiments of this disclosure will now be described with reference to the drawings. The drawings are for illustrative purposes only, and the shape, size, or size ratio of each component in the actual device does not need to be exactly as shown in the drawings. Furthermore, the drawings are simplified, so any other components necessary for implementation should be appropriately provided in addition to those shown in the drawings.

[0020] International Publication No. 2021 / 124748 may be incorporated by reference in part in this disclosure.

[0021] This disclosure will be described in the following order: 1. Outline of the display device 2. Example of lamp signal control 3. Example of lamp signal output circuit 4. Example of pixel circuit 5. Example of application to electronic equipment

[0022] <1. Display device>

[0023] The display element in this disclosure may be formed within a predetermined plane. This predetermined plane may be formed on a substrate.

[0024] The transistors used in display elements, such as those used to drive light-emitting elements, are not limited in their conductivity type. In embodiments, the conductivity type may be specified and described, but these may be n-type or p-type transistors.

[0025] Figure 1 is a schematic block diagram showing an example of a part of a display device according to one embodiment. The display device 1 comprises a pixel array 10, a control circuit 12, a first drive circuit 14, and a second drive circuit 16. The display device 1 is a device that displays images, videos, etc. (hereinafter referred to as "images, etc.") in at least a part of the area of ​​the pixel array 10. The display device 1 may be incorporated into a part of an electronic device.

[0026] The pixel array 10 is a region in which pixels 100 are arranged in a two-dimensional array along a first direction and a second direction intersecting the first direction. The first direction may be, for example, a line direction. The second direction may be, for example, a column direction.

[0027] Each pixel 100 comprises a light-emitting element and a pixel circuit. By emitting light from the light-emitting element in response to a signal supplied to the pixel circuit, it operates as a unit for displaying images and the like in the pixel array 10. Each pixel 100 emits light with a brightness based on the input image information, thereby enabling the display of images and the like in the pixel array 10.

[0028] The light-emitting element may be an organic light-emitting element (including OLED), an inorganic light-emitting element, other LED elements, an LD (laser diode) element, or other elements that emit light spontaneously.

[0029] The first and second directions are provided for illustrative purposes only, and the forms of this disclosure are not limited to these directions. For example, the first direction may be the line direction and the second direction may be the column direction.

[0030] Each individual pixel 100 can also emit light of the appropriate color. By combining the emission intensity of each color in each pixel 100 with the emission of the same or different colors from surrounding pixels 100, various colors of light can be emitted. As a result, the display device 1 can display a color image or the like in the pixel array 10.

[0031] Pixel 100 may be formed to emit light of one of the following colors, for example: blue, green, or red. Pixels 100 that emit light of each color may be arranged to emit light of various colors, for example, in a Bayer array. The selection of colors to emit light, the number of colors, and the arrangement of each color are not limited to those described above; other color combinations and arrangements are also possible. For example, the color combination may consist of other colors such as white, cyan, magenta, and yellow, or may include at least one of these colors.

[0032] Alternatively, each of the 100 pixels may be provided with a segmented pixel, and each pixel 100 itself may emit light of various colors and brightness levels. In this case, the color combinations and color arrangements in each individual pixel 100 are not limited, and any configuration that can appropriately emit various colors is acceptable.

[0033] The pixel array 10 may form a display area using all of the pixels 100 it has arranged, or it may form a display area using pixels 100 that belong to a predetermined area among the pixels 100 it has arranged. Pixels 100 located near the outer edge of the pixel array 10 may be, for example, dummy pixels. In this case, the display area where an image or the like is displayed in the pixel 100 can be formed using the pixels 100 excluding these dummy pixels.

[0034] The control circuit 12 is a circuit that appropriately processes the input image information, appropriately distributes it to the pixels 100 belonging to the pixel array 10, and controls the illumination and extinction of the light-emitting elements of these pixels 100. For example, the control circuit 12 can control illumination and extinction by outputting appropriate drive signals to the first drive circuit 14 and the second drive circuit 16. The control circuit 12 can also control the initialization of the pixels 100.

[0035] The first drive circuit 14 selects a line in the pixel array 10 and outputs a signal to drive a light-emitting element for each line. The first drive circuit 14 outputs a control signal to each pixel 100 belonging to each line of the pixel array 10 via the signal line 140.

[0036] The first drive circuit 14 outputs a control signal, for example, via the signal line 140, that enables the pixels 100 belonging to the selected line to be driven. The first drive circuit 14 can also output a control signal, for example, via the signal line 140, to initialize the pixels 100 belonging to the selected line.

[0037] The second drive circuit 16 selects a column in the pixel array 10 and outputs a signal for each column that includes information such as the light emission intensity of the light-emitting element for each pixel 100 in the line selected by the first drive circuit 14. The second drive circuit 16 outputs a control signal to each pixel 100 belonging to each column of the pixel array 10 via the signal line 160.

[0038] The second drive circuit 16 can output a signal indicating the brightness value for a pixel belonging to a line selected by the first drive circuit 14, for example, via the signal line 160.

[0039] In other words, based on image data or the like input to the control circuit 12 via an appropriate interface, the control circuit 12 controls the pixels 100 via the first drive circuit 14 and the second drive circuit 16 to emit and extinguish light at appropriate brightness and timing, thereby enabling the display of the input image or the like. Furthermore, the control circuit 12 can perform initialization control for each pixel 100 at appropriate timing.

[0040] The second drive circuit 16 receives, as an example without limitation, an image signal or video signal (hereinafter referred to as "image signal, etc.") indicating the gradation corresponding to the image or video to be displayed (hereinafter referred to as "image, etc."). This image signal, etc. may be a digital signal. The second drive circuit 16 may be equipped with switches for each signal line 160 that distributes the signal to the pixels belonging to each column (second direction).

[0041] The second drive circuit 16 may include, for example, a lamp signal output circuit (not shown) that generates a lamp signal. The lamp signal output circuit is a circuit that outputs a lamp signal. With the switch connected to the signal line 160 turned ON, the second drive circuit 16 applies the output from the lamp signal output circuit to the signal line 160, and turns off the switch of the corresponding signal line 160 at a time based on the pixel value of the pixel belonging to each column.

[0042] By this process, the respective signal lines 160 and the lamp signal output circuit are not electrically connected at the timing when the signal value output from the lamp signal output circuit indicates an appropriate value. As a result, the state where a signal indicating an appropriate luminance value is applied to each signal line 160 is maintained. By appropriately processing this signal value in the pixel 100, the light-emitting element emits light at an appropriate luminance value.

[0043] As will be described later, the lamp signal output circuit outputs a lamp signal so as to output appropriate values at the timing of the offset of each pixel 100 and at the timing of writing the luminance signal.

[0044] In FIG. 1, the first drive circuit 14 is provided on the left side facing the drawing, and the second drive circuit 16 is provided on the upper side facing the drawing, but it is not limited thereto. For example, the first drive circuit 14 may be provided on both the left and right sides of the drawing, or may be provided on the right side. For example, the second drive circuit 16 may be provided on both the upper and lower sides of the drawing, or may be provided on the lower side.

[0045] FIG. 15 is a diagram showing an example of the circuit configuration of the pixel 100 (pixel PIX) according to an embodiment. The operation of this circuit will be described in detail later. FIG. 2 is a timing chart showing an example of signal values in this circuit.

[0046] Vds indicates the gate potential of the transistor MP13 in FIG. 15, Vws indicates the gate potential of the transistor MP12, Vaz indicates the gate potential of the transistor MP15, Vs indicates the source potential of the transistor MP14, Vg indicates the gate potential of the transistor MP14, and Vanode indicates the potential of the anode of the light-emitting element EL.

[0047] In initialization, Vds and Vaz are turned on, and Vws is turned off. By this control, the potential of Vanode is appropriately reset.

[0048] When initialization is completed, the process proceeds to a Vth correction period for correcting the threshold voltage of the transistor MP14 for each pixel. First, Vws is set to the on potential. In this state, an offset signal is input to the signal line SGL. After setting Vws to the off potential, Vds is set to the off potential. In this state, due to the coupling between the capacitor C11 and the capacitor C12, after sufficient time has elapsed, the correction regarding the Vth of the transistor M14 is completed.

[0049] By setting Vaz to the on potential and then to the off potential, while initializing Vanode, at this time, by setting Vws to the on potential, a signal indicating the luminance value is written to Vg. At this timing, a signal indicating the luminance value is input to the signal line SGL. As a result, the gate potential Vg of the transistor M14 is pulled up based on the luminance signal. Due to the capacitor C12, the source potential Vs of the transistor M14 is also pulled up.

[0050] After the writing of the signal is completed, by setting Vaz to the off potential and Vds to the on potential, a current is passed through the anode of the light-emitting element EL. This current flows in an appropriate amount depending on Vg, Vs, and Vth, and the light-emitting element can be made to emit light at the intended intensity.

[0051] After light emission, by setting Vds to the off potential, the current flowing through the anode of the light-emitting element EL is stopped, and by setting Vws to the off potential and Vaz to the on potential, the potential of the anode of the light-emitting element EL is reset, and then the process proceeds to the initialization phase.

[0052] FIG. 3 is a diagram showing an example of a ramp signal according to a comparative example used at the timing of offset and the timing of writing the signal value. This ramp signal is, for example, a signal generated by a ramp signal output circuit provided in the second driving circuit 16. In the figure, the horizontal direction represents time, and the vertical direction indicates potential. The same applies to the diagrams showing the states of the following ramp signals.

[0053] The offset signal output circuit generates and outputs two lamp signals for each line in one light emission cycle: a lamp signal that sets the offset signal and a lamp signal that sets the light emission signal (a signal indicating the brightness value). The second drive circuit 16 applies the appropriate signal to each signal line 160 (i.e., signal line SGL) by switching the switch between this lamp signal output circuit and the signal line 160 from connected to disconnected at the appropriate timing.

[0054] Figure 4 shows an example of setting the offset signal value and luminance signal value using the lamp signal shown in Figure 3. The second drive circuit 16 can apply the appropriate signal value to the signal line 160 by switching the switch connecting the signal line 160 and the lamp signal output circuit from the ON state to the OFF state at the appropriate timing. For example, the second drive circuit 16 can apply the appropriate signal value to each signal line 160 by turning the switch OFF at the timing shown by the dashed line.

[0055] Figures 5 and 6 show comparative examples where the slope of the ramp signal deviates from the reference slope. Figure 5 shows an example where the absolute value of the ramp signal slope is small, and the dotted line shows the ramp signal whose slope deviates from the desired value. Figure 6 shows an example where the absolute value of the ramp signal slope is large, and the dotted line shows the ramp signal whose slope deviates from the desired value.

[0056] The second drive circuit 12, while the ramp signals for setting the offset signal and the ramp signals for setting the light emission signal are oscillating, turns off the switches that output to the signal lines 160 connected to each pixel at the appropriate time. Depending on the timing of this turning off, a signal with an appropriate value is output to and held on each signal line 160.

[0057] For example, by turning off the switch at the timing indicated by the dashed line in Figures 5 and 6, the offset signal and luminance value signal are applied to the pixel via their respective signal lines 160. Specifically, the signal value at the point where the solid ramp signal and the dashed line intersect indicates the desired offset value / desired luminance value, and the signal value at the point where the dotted ramp signal and the dashed line intersect indicates the actually output offset value / output luminance value.

[0058] When the slope of the lamp signal is misaligned, if the signal value is acquired at the same timing as when the lamp signal slope is not misaligned, then if the absolute value of the slope shown in Figure 5 becomes smaller, both the output offset value and the output brightness value will be higher than the desired offset value and brightness value, respectively. Conversely, if the absolute value of the slope shown in Figure 6 becomes larger, both the output offset value and the output brightness value will be lower than the desired offset value and brightness value, respectively.

[0059] On the other hand, if there is variation in the lamp signals, the deviation of the offset signal value from the reference lamp signal, which generally determines the signal value in a shorter time, becomes smaller than the deviation of the signal value indicating the brightness value from the reference lamp signal. As a result, the error between the signal value of the offset signal during the offset period and the signal value indicating the brightness value during the writing period are different in Figure 2.

[0060] Let's consider the case where only the offset signal is shifted. For example, in Figure 2, if the signal value of the offset signal shifts as shown in Figure 6, that is, if the absolute value of the slope of the ramp signal increases, then at the timing when Vws is set to ON during the Vth correction period in Figure 2, Vg will drop to a lower value. As a result, at the start of the writing period, both Vs and Vg will drop to low values. Due to the Vth correction, in this case, the potential difference between Vs and Vg becomes smaller than the ideal value. As a result, at the end of the writing period, the potential of Vg is raised to the signal value to be written, while Vs shows a potential lower than the ideal value. As a result, even during the light emission period, the gate-source voltage of the drive transistor becomes smaller, the drain current becomes smaller, and the brightness becomes lower than the written signal value.

[0061] Next, let's consider the case where only the signal indicating the brightness value is shifted. For example, in Figure 2, if the signal value of the brightness signal is shifted as shown in Figure 6, then during the writing period in Figure 2, Vg can only be raised to a potential lower than the ideal value. On the other hand, due to the effect of the coupled capacitor, the potential of Vs is raised to an appropriate potential, so the gate-source voltage of the drive transistor becomes larger than the ideal value. As a result, when the light emission period begins and Vs is raised to the power supply potential, this larger-than-ideal gate-source voltage causes a larger drain current, and the brightness value becomes higher than the signal value that was supposed to be written.

[0062] Combining the above, if the offset signal deviation and the luminance signal deviation are approximately the same, the potential fluctuations will cancel each other out, making it possible to emit light at an appropriate luminance value. However, as mentioned above, the luminance signal deviation is larger than the offset signal deviation. As a result, in the case of Figure 6, the emission intensity becomes higher than the input luminance value, and in the case of Figure 5, conversely, the emission intensity becomes lower than the input luminance value. Furthermore, even if the offset signal deviation and the luminance signal deviation are the same, the actual emission intensity is influenced more by the luminance value, so in any case, the emission intensity of lines controlled using the same lamp signal will deviate in the same direction.

[0063] <2. Examples of lamp signal control>

[0064] (First Embodiment)

[0065] An example of lamp signal generation by the lamp signal output circuit provided in the second drive circuit 16 will be described. Figure 7 is a diagram showing an example of lamp signal control according to one embodiment. As shown in this figure, the lamp signal output circuit outputs a first lamp signal for setting an offset signal and a second lamp signal for setting a signal indicating the luminance value to be emitted, with the slopes of the signals changed.

[0066] The ramp signal output circuit can, for example, output such that the slope of the first ramp signal is gentler (smaller in absolute value) than the slope of the second ramp signal. The dashed line indicates the reference ramp signal when the offset signal is set.

[0067] Figure 8 shows an example of control of a ramp signal according to one embodiment. The dashed line indicates the timing of offset signal setting in Figure 5, and the dashed line indicates the timing of offset signal setting in this embodiment. The second drive circuit 16 delays the timing of acquiring the set value for the offset signal applied to each signal line 160 in accordance with the slope of the ramp signal.

[0068] The offset value deviation in Figure 8 is larger than the offset value deviation in Figure 5, and as a result, the difference between the offset value deviation and the luminance value deviation can be reduced.

[0069] As described above, by controlling the lamp signal according to this embodiment, when variations occur in the slope of the lamp signal, the deviation of the offset signal and the deviation of the luminance signal transmitted to the pixel 100 can be reduced. As a result, the processing of the pixel circuit in the pixel 100 makes it possible to further cancel out the decrease in light emission intensity due to the deviation of the offset signal and the increase in light emission intensity due to the deviation of the luminance signal compared to when the slope of the lamp signal is not changed, and it becomes possible to suppress changes in luminance values ​​due to lines and timing. Such variations in the slope of the lamp signal may occur line by line depending on the timing, for example, but according to the configuration of this embodiment, it is possible to suppress the occurrence of horizontal stripes in the display caused by this variation occurring line by line.

[0070] (Second Embodiment)

[0071] As described in the first embodiment, by making the slope of the first lamp signal gentler than the slope of the second lamp signal, it is possible to reduce the effect of variations in the slope of the lamp signals. In other words, the same effect can be obtained by fixing the slope of the lamp signal on the offset signal side and making the slope of the lamp signal on the signal side indicating the brightness value steeper.

[0072] Figure 9 shows an example of lamp signal control according to one embodiment. As shown in Figure 9, the slope of the second lamp signal may be made stronger (the absolute value increased) than the slope of the reference lamp signal. In this case as well, the same effects as in the first embodiment can be achieved. In this case, the timing for acquiring the light emission signal indicating the brightness value is controlled to be earlier than that of the reference lamp signal.

[0073] These can be selected as appropriate depending on the clock frequency and circuit configuration.

[0074] <3. Example of a lamp signal output circuit>

[0075] (Third embodiment)

[0076] The above described the control of the lamp signal; below, we will describe some examples of lamp signal output circuits for controlling this lamp signal.

[0077] Figure 10 shows a part of the second drive circuit 16 according to one embodiment. The lamp signal output circuit 162 is connected to each signal line 160 via a switch. Based on the brightness value of the pixels 100 belonging to each column, the switch is transitioned from the on state to the off state at an appropriate timing to maintain an appropriate signal value in each signal line 160. Capacitors or the like may be connected to each signal line 160 as appropriate to maintain potential.

[0078] The output from the lamp signal output circuit 162 is distributed to each signal line 160 with an appropriate signal value depending on the timing at which the switches corresponding to each signal line 160 are turned off. The second drive circuit 16 turns off the switches for the first lamp signal and the second lamp signal, as described in the above embodiment, at the appropriate timing. In this embodiment, the generation of the first lamp signal and the second lamp signal with different slopes will be described.

[0079] Figure 11 is a diagram showing an unspecified example of the configuration of a lamp signal output circuit 162 according to one embodiment. As shown in Figure 11, the lamp signal output circuit 162 comprises a first lamp signal output circuit 164 and a second lamp signal output circuit 166. The first lamp signal output circuit 164 is a circuit that generates and outputs a first lamp signal, and the second lamp signal output circuit 166 is a circuit that generates and outputs a second lamp signal.

[0080] Of course, the first lamp signal output by the first lamp signal output circuit 164 has a gentler slope than the second lamp signal output by the second lamp signal output circuit 166.

[0081] Thus, the lamp signal output circuit 162 may be configured to include circuits that generate lamp signals with different slopes, and the signals output by these circuits may be switched using a switch.

[0082] (Fourth Embodiment)

[0083] Figure 12 shows an example, not limited to any part, of the configuration of a lamp signal output circuit 162 according to one embodiment. As shown in Figure 12, the lamp signal output circuit 162 may include a capacitor 168, a first transistor 170, and a second transistor 172. It is also possible to use a configuration in which the first transistor 170 and the second transistor 172 are combined to form a transistor with a variable gate width.

[0084] Capacitor 168 has its first terminal connected to the positive power supply voltage line VDD and its second terminal connected to the output terminal of the ramp signal output circuit 162. First transistor 170 has its first terminal connected to the second terminal of capacitor 168 and its second terminal connected to the negative power supply voltage line VSS. Second transistor 172 has its first terminal connected to the second terminal of capacitor 168 and its second terminal connected to the negative power supply voltage line VSS.

[0085] This configuration allows for switching between outputting a first lamp signal and a second lamp signal. As an example where the switching is not limited, the lamp signal output circuit 162 turns on the first transistor 170 and turns off the second transistor 172 while outputting the first lamp signal. The lamp signal output circuit 162 turns off the first transistor 170 and turns on the second transistor 172 while outputting the second lamp signal. When performing this control, for example, the gate width of the first transistor 170 is made smaller than the gate width of the second transistor 172.

[0086] Another example, not limited to switching, is that the lamp signal output circuit 162 turns on the first transistor 170 and turns off the second transistor 172 while outputting the first lamp signal. While outputting the second lamp signal, the lamp signal output circuit 162 turns on both the first transistor 170 and the second transistor 172. When this control is performed, for example, the gate width of the second transistor 172 is formed to an appropriate size based on the slopes of the first and second lamp signals.

[0087] As described above, the first ramp signal and the second ramp signal can be switched by changing the gate width (virtual gate width) of the transistor that gradually reduces the current flowing from capacitor 168.

[0088] (Fifth embodiment)

[0089] Figure 13 shows an example, not limited to any part, of the configuration of a lamp signal output circuit 162 according to one embodiment. As shown in Figure 13, the lamp signal output circuit 162 may include a first capacitor 174, a second capacitor 176, a first switch 178, a second switch 180, and a transistor 182. It is also possible to combine the first capacitor 174 and the second capacitor 176 to form a capacitor with variable capacitance.

[0090] The first capacitor 174 has its first terminal connected to the positive power supply voltage line VDD via the first switch 178, and its second terminal connected to the output terminal of the lamp signal output circuit 162. The second capacitor 176 has its first terminal connected to the positive power supply voltage line VDD via the second switch 180, and its second terminal connected to the output terminal of the lamp signal output circuit 162. The transistor 182 has its first terminal connected to the second terminals of the first switch 178 and the second switch 180, and its second terminal connected to the negative power supply voltage line VSS. The positive and negative power supply voltages are voltages that represent the drain voltage and source voltage, respectively, and for example, the negative power supply voltage may be the ground voltage. In other words, it can be a power supply equivalent to Vdd and Vss in the general sense.

[0091] This configuration allows for switching between outputting a first lamp signal and a second lamp signal. As an example where the switching is not limited, the lamp signal output circuit 162 turns on the first switch 178 and turns off the second switch 180 while outputting the first lamp signal. The lamp signal output circuit 162 turns off the first switch 178 and turns on the second switch 180 while outputting the second lamp signal. When performing this control, for example, the capacitance of the first capacitor 174 is made smaller than the capacitance of the second capacitor 176.

[0092] Another example, not limited to switching, is that the lamp signal output circuit 162 turns on the first switch 178 and off the second switch 180 while outputting the first lamp signal. While outputting the second lamp signal, the lamp signal output circuit 162 turns on both the first switch 178 and the second switch 180. When this control is performed, for example, the capacitance of the second switch 180 is formed to an appropriate size based on the slope of the first lamp signal and the second lamp signal.

[0093] As described above, the first lamp signal and the second lamp signal can be switched by changing the capacitance of the capacitor.

[0094] <4. Example of a pixel circuit>

[0095] In the following, the terms "first voltage" and "second voltage" are used, but in the embodiments described above, the first voltage and second voltage are not necessarily limited to being the same voltage. Pixel PIX can be a circuit corresponding to pixel 100 in each of the embodiments described above.

[0096] Furthermore, while the semiconductor type of transistor is provisionally shown in the pixel circuit of each pixel PIX, the applicable forms in this disclosure are not limited to these semiconductor types. When using transistors of different semiconductor types, it is possible to accommodate this by, for example, appropriately changing the signal applied to the gate or appropriately reinterpreting the source and drain.

[0097] Figure 14 shows an example configuration of a pixel PIX. The pixel PIX includes a capacitor C01, transistors MN02 to MN03, and a light-emitting element EL. Transistors MN02 to MN03 are, for example, N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0098] Transistor MN02 has its gate connected to the control line WSL, one of its source / drain connected to the gate of transistor MN03 and one end of capacitor C01, and the other of its source / drain connected to the signal line SGL.

[0099] Capacitor C01 has one end connected to either the source or drain of transistor MN02 and the gate of transistor MN03, and the other end connected to either the source or drain of transistor MN03 and the anode of light-emitting element EL.

[0100] Transistor MN03 has its gate connected to one of the source / drain of transistor MN02 and one end of capacitor C01, one of its source / drains connected to the other end of capacitor C01 and the anode of light-emitting element EL, and the other of its source / drains connected to the power line VCCP.

[0101] The light-emitting element EL has its anode connected to one of the source / drain terminals of transistor MN03 and the other end of capacitor C01, and its cathode connected to the power line VCATH.

[0102] The power line VCCP switches between a first voltage and a second voltage that is lower than the first voltage as needed.

[0103] In this configuration, at pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During the period when the voltage of power line VCCP is the first voltage, transistor MN03 supplies a current to light-emitting element EL corresponding to the voltage across capacitor C01. Light-emitting element EL emits light based on the current supplied by transistor MN03.

[0104] In this way, the pixel PIX emits light with a brightness corresponding to the pixel signal. Note that the light-emitting element EL is extinguished during the period when the voltage of the power line VCCP is the second voltage.

[0105] Figure 15 shows another example of a pixel PIX configuration. This pixel PIX includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are, for example, P-type MOSFETs.

[0106] Transistor MP12 has its gate connected to the control line WSL, one of its source / drain connected to the signal line SGL, and the other of its source / drain connected to the gate of transistor MP14 and the other end of capacitor C12.

[0107] Capacitor C11 has one end connected to the power line VCCP, and the other end connected to one end of capacitor C12, the other source / drain of transistor MP13, and one source / drain of transistor MP14.

[0108] Capacitor C12 has one end connected to the other end of capacitor C11, the other source / drain of transistor MP13, and one source / drain of transistor MP14, and the other end connected to the other source / drain of transistor MP12 and the gate of transistor MP14.

[0109] Transistor MP13 has its gate connected to the control line DSL, one of its source / drain connected to the power line VCCP, and the other of its source / drain connected to one of the source / drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12.

[0110] The gate of transistor MP14 is connected to the other source / drain of transistor MP12 and the other end of capacitor C12, one source / drain of transistor MP13 is connected to the other source / drain of transistor MP13, the other end of capacitor C11 and one end of capacitor C12, and the other source / drain of transistor MP14 is connected to the anode of light-emitting element EL and one source / drain of transistor MP15.

[0111] Transistor MP15 has its gate connected to the control line AZSL, one of its source / drain connected to the other source / drain of transistor MP14 and the anode of the light-emitting element EL, and the other source / drain connected to the power line VSS.

[0112] In this configuration, at pixel PIX, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL when transistor MP12 is turned on. Transistor MP13 is turned on / off based on the signal from control line DSL. Transistor MP14 supplies a current to light-emitting element EL corresponding to the voltage across capacitor C12 while transistor MP13 is on. Light-emitting element EL emits light based on the current supplied by transistor MP14.

[0113] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0114] Transistor MP15 is switched on / off based on the signal on control line AZSL. While transistor MP15 is on, the light-emitting element EL is initialized by setting the anode voltage to the voltage on power line VSS.

[0115] Transistors MP12 to MP15 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MP12 or MP15 may be a transistor made of oxide semiconductor.

[0116] Figure 16 shows another example of a pixel PIX configuration. This pixel PIX includes a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are, for example, N-type MOSFETs.

[0117] Transistor MN22 has its gate connected to the control line WSL, one of its source / drain is connected to the gate of transistor MN24 and one end of capacitor C21, and the other of its source / drain is connected to the signal line SGL.

[0118] Capacitor C21 has one end connected to one of the source / drain of transistor MN22 and the gate of transistor MN24, and the other end connected to one of the source / drain of transistor MN24, the other of the source / drain of transistor MN25 and the anode of light-emitting element EL.

[0119] The gate of transistor MN23 is connected to the control line DSL, one of its source / drain is connected to the other of the source / drain of transistor MN24, and the other of its source / drain is connected to the power line VCCP.

[0120] Transistor MN24 has its gate connected to one of the source / drain of transistor MN22 and one end of capacitor C21, one of its source / drains connected to the other end of capacitor C21, the other of the source / drain of transistor MN25 and the anode of light-emitting element EL, and the other of its source / drains connected to one of the source / drains of transistor MN23.

[0121] The gate of transistor MN25 is connected to the control line AZSL, one of its source / drain is connected to the power line VSS, and the other of its source / drain is connected to one of the source / drain of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL.

[0122] In this configuration, at pixel PIX, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL when transistor MN22 is turned on. Transistor MN23 is turned on / off based on the signal from control line DSL. Transistor MN24 supplies a current to light-emitting element EL corresponding to the voltage across capacitor C21 while transistor MN23 is on. Light-emitting element EL emits light based on the current supplied by transistor MN24.

[0123] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0124] Transistor MN25 is switched on / off based on the signal on control line AZSL. While transistor MN25 is on, light-emitting element EL is initialized by setting the anode voltage to the voltage on power line VSS.

[0125] Furthermore, transistors MN22 to MN25 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MN22 or MN25 may be a transistor using an oxide semiconductor.

[0126] Figure 17 shows another example of a pixel PIX configuration. This pixel PIX includes a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are, for example, P-type MOSFETs.

[0127] Transistor MP32 has its gate connected to the control line WSL, one of its source / drain connected to the signal line SGL, and the other of its source / drain connected to the gate of transistor MP33, the other of its source / drain of transistor MP34, and the other end of capacitor C31.

[0128] Capacitor C31 has one end connected to the power line VCCP, and the other end connected to the other source / drain of transistor MP32, the gate of transistor MP33, and the other source / drain of transistor MP34.

[0129] Transistor MP33 has its gate connected to the other source / drain of transistor MP32, the other end of capacitor C31, and the other source / drain of transistor MP34. One source / drain of transistor MP33 is connected to the power line VCCP, and the other source / drain of transistor MP34 is connected to one source / drain of transistor MP34 and one source / drain of transistor MP35.

[0130] Transistor MP34 has its gate connected to control line AZSL1, one of its source / drain is connected to the other source / drain of transistor MP33 and one of the source / drain of transistor MP35, and the other source / drain is connected to the other source / drain of transistor MP32, the gate of transistor MP33 and the other end of capacitor C31.

[0131] Transistor MP35 has its gate connected to the control line DSL, one of its source / drain is connected to the other source / drain of transistor MP33 and one of the source / drain of transistor MP34, and the other source / drain is connected to the other source / drain of transistor MP36 and the anode of light-emitting element EL.

[0132] The gate of transistor MP36 is connected to the control line AZSL2, one of its source / drain is connected to the other of the source / drain of transistor MP35 and the anode of the light-emitting element EL, and the other of its source / drain is connected to the power line VSS.

[0133] In this configuration, at pixel PIX, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL when transistor MP32 is turned on. Transistor MP35 is turned on / off based on the signal from control line DSL. Transistor MP33 supplies a current to light-emitting element EL corresponding to the voltage across capacitor C31 while transistor MP35 is on. Light-emitting element EL emits light based on the current supplied by transistor MP33.

[0134] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0135] Transistor MP34 is switched on / off based on the signal on control line AZSL1. While transistor MP34 is on, the source / drain and gate of transistor MP33 are connected to each other.

[0136] Transistor MP36 is switched on / off based on the signal on control line AZSL2. During the period when transistor MP36 is ON, the voltage at the anode of light-emitting element EL is initialized by setting it to the voltage on power line VSS.

[0137] Furthermore, transistors MP32 to MP36 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP32, MP34, and MP36 may be a transistor made of oxide semiconductor.

[0138] Figure 18 shows another example of a pixel PIX configuration.

[0139] Capacitor C48 has one end connected to the signal line SGL1 and the other end connected to the power line VSS.

[0140] Capacitor C49 has one end connected to signal line SGL1 and the other end connected to signal line SGL2.

[0141] The MP49 transistor is, for example, a P-type MOSFET, with its gate connected to the control line WSL2, one of its source / drain connected to the signal line SGL1, and the other of its source / drain connected to the signal line SGL2.

[0142] Each pixel PIX comprises a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are, for example, P-type MOSFETs.

[0143] Transistor MP42 has its gate connected to the control line WSL1, one of its source / drain connected to the signal line SGL2, and the other of its source / drain connected to the gate of transistor MP43 and the other end of capacitor C41.

[0144] Capacitor C41 has one end connected to the power line VCCP and the other end connected to the other of the source / drain of transistor MP42 and the gate of transistor MP43.

[0145] Transistor MP43 has its gate connected to the other source / drain of transistor MP42 and the other end of capacitor C41, one source / drain connected to the power line VCCP, and the other source / drain connected to one source / drain of transistor MP44 and one source / drain of transistor MP45.

[0146] Transistor MP44 has its gate connected to the control line AZSL1, one of its source / drain is connected to the other source / drain of transistor MP43 and one of the source / drain of transistor MP45, and the other source / drain is connected to the other end of capacitor C49 and the signal line SGL2.

[0147] Transistor MP45 has its gate connected to the control line DSL, one of its source / drain is connected to the other source / drain of transistor MP43 and one of its source / drains of transistor MP44, and the other source / drain is connected to the other source / drain of transistor MP46 and the anode of light-emitting element EL.

[0148] The transistor MP46 has its gate connected to the control line AZSL2, one of its source / drain is connected to the other source / drain of transistor MP45 and the anode of the light-emitting element EL, and the other source / drain is connected to the power line VSS.

[0149] In this configuration, at pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on / off based on the signal from control line DSL. Transistor MP43 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C41 while transistor MP45 is on. The light-emitting element EL emits light based on the current supplied by transistor MP43.

[0150] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0151] Transistor MP44 is switched on / off based on the signal on control line AZSL1. While transistor MP44 is on, the source / drain of transistor MP43 and the signal line SGL2 are connected to each other.

[0152] Transistor MP46 is switched on / off based on the signal on control line AZSL2. During the period when transistor MP46 is ON, the light-emitting element EL is initialized by setting the anode voltage to the voltage on power line VSS.

[0153] Furthermore, transistors MP42 to MP46 and MP49 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP42, MP46, and MP49 may be a transistor made of oxide semiconductor.

[0154] Figure 19 shows another example of a pixel PIX configuration. Multiple pixels PIX are arranged in a matrix within a display area 1000, which is located between the first control unit 40 and the second control unit 70.

[0155] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are, for example, P-type MOSFETs.

[0156] The transmission gate TG45 has a pixel signal supplied to one end and the other end connected to one end of the signal line 14a.

[0157] The transmission gate TG46 has one end connected to signal line 14b and the other end connected to power line VORST.

[0158] Capacitor C61 has one end connected to signal line 14a and the other end connected to power line VSS1.

[0159] The MP56 transistor has its gate connected to the control line INIL, one of its source / drain connected to the power line VINI, and the other of its source / drain connected to the signal line 14b.

[0160] The MP57 transistor has its gate connected to the control line ELL, one of its source / drain connected to the power line VEL, and the other of its source / drain connected to the signal line 14b.

[0161] The second control unit 70 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is, for example, a P-type MOSFET.

[0162] The transmission gate TG72 has one end connected to signal line 14a and the other end connected to the other source / drain of transistor MP73 and one end of capacitor C82.

[0163] The transistor MP73 has its gate connected to the control line REFL, one of its source / drain connected to the power line VREF, and the other of its source / drain connected to the other end of the transmission gate TG72 and one end of the capacitor C82.

[0164] Capacitor C82 has one end connected to the other end of the transmission gate TG72 and the other of the source / drain of transistor MP73, and the other end connected to one end of signal line 14b.

[0165] Each pixel PIX comprises a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are, for example, P-type MOSFETs.

[0166] The transistor MP122 has its gate connected to the control line WSL, one of its source / drain connected to the signal line 14b, and the other of its source / drain connected to the gate of transistor MP121 and the other end of capacitor C132.

[0167] Capacitor C132 has one end connected to the power line VEL, and the other end connected to the other source / drain of transistor MP122 and the gate of transistor MP121.

[0168] Transistor MP121 has its gate connected to the other source / drain of transistor MP122 and the other end of capacitor C132, one source / drain connected to power line VEL, and the other source / drain connected to one source / drain of transistor MP123 and one source / drain of transistor MP124.

[0169] Transistor MP123 has its gate connected to the control line AZSL, one of its source / drain is connected to the other source / drain of transistor MP121 and one of its source / drains of transistor MP124, and the other source / drain is connected to the signal line 14b.

[0170] Transistor MP124 has its gate connected to the control line DSL, one of its source / drain is connected to the other source / drain of transistor MP121 and one of its source / drains of transistor MP123, and the other source / drain is connected to the other source / drain of transistor MP125 and the anode of the light-emitting element EL.

[0171] The transistor MP125 has its gate connected to the control line AZSL, one of its source / drain connected to the power line VORST, and the other of its source / drain connected to the other of the source / drain of transistor MP124 and the anode of the light-emitting element EL.

[0172] In this configuration, at pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is turned on / off based on the signal on control line DSL. Transistor MP121 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C132 while transistor MP124 is on. The light-emitting element EL emits light based on the current supplied by transistor MP121.

[0173] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0174] Transistors MP123 and MP125 are switched on and off based on the signal on the control line AZSL. While transistor MP123 is ON, the other source / drain of transistor MP121 and one source / drain of transistor MP124 are connected to signal line 14b. While transistor MP125 is ON, the light-emitting element EL is initialized by setting the anode voltage to the voltage of the power line VORST.

[0175] Furthermore, transistor MP56 is switched on / off based on the signal on control line INIL, transistor MP57 is switched on / off based on the signal on control line ELL, and transistor MP73 is switched on / off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power line VINI, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power line VEL. When transistor MP73 is turned on, capacitor C82 is initialized by setting one end to the voltage of power line VREF.

[0176] Furthermore, transistors MP121 to MP125, MP56, and MP57 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP122 or MP125 may be a transistor made of oxide semiconductor.

[0177] Figure 20 shows another example of a pixel PIX configuration. This pixel PIX includes a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are, for example, P-type MOSFETs.

[0178] Transistor MP52 has its gate connected to the control line WSL, one of its source / drain connected to the signal line SGL, and the other of its source / drain connected to the other of transistor MP53 and one of transistor MP54.

[0179] Transistor MP53 has its gate connected to the control line DSL, one of its source / drain connected to the power line VCCP, and the other of its source / drain connected to the other source / drain of transistor MP52 and one of its source / drain of transistor MP54.

[0180] Transistor MP54 has its gate connected to one source / drain of transistor MP55, the other source / drain of transistor MP57, and the other end of capacitor C51; one source / drain of transistor MP52 is connected to the other source / drain of transistor MP52 and the other source / drain of transistor MP53; and the other source / drain of transistor MP58 is connected to one source / drain of transistor MP58 and one source / drain of transistor MP59.

[0181] Capacitor C51 has one end connected to the power line VCCP and the other end connected to the gate of transistor MP54, one of the source / drain of transistor MP55, and the other of the source / drain of transistor MP57. Capacitor C51 may include two or more capacitors connected in parallel with each other.

[0182] Transistor MP55 has its gate connected to the gate of transistor MP56 and control line AZSL1, one of its source / drains connected to the gate of transistor MP54, the other of its source / drains of transistor MP57 and the other end of capacitor C51, and the other of its source / drains connected to one of its source / drains of transistor MP56.

[0183] Transistor MP56 has its gate connected to the gate and control line AZSL1 of transistor MP55, one of its source / drains connected to the other of its source / drains of transistor MP55, and the other of its source / drains connected to the power line VSS.

[0184] Transistor MP57 has its gate connected to the gate and control line WSL of transistor MP58, and its other source / drain connected to the gate of transistor MP54, one of the source / drain of transistor MP55, and the other end of capacitor C51, and one of its source / drain connected to the other source / drain of transistor MP58.

[0185] Transistor MP58 has its gate connected to the gate and control line WSL of transistor MP57, its other source / drain connected to one source / drain of transistor MP57, and its other source / drain connected to the other source / drain of transistor MP54 and one source / drain of transistor MP59.

[0186] Transistor MP59 has its gate connected to the control line DSL, one of its source / drain is connected to the other source / drain of transistor MP54 and one of the source / drain of transistor MP58, and the other source / drain is connected to the other source / drain of transistor MP60 and the anode of light-emitting element EL.

[0187] The gate of transistor MP60 is connected to the control line AZSL2, one of its source / drain is connected to the other source / drain of transistor MP59 and the anode of the light-emitting element EL, and the other source / drain is connected to the power line VSS.

[0188] In this configuration, at pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, setting the voltage across capacitor C51 based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on / off based on the signal from control line DSL. Transistor MP54 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C51 while transistors MP53 and MP59 are on. The light-emitting element EL emits light based on the current supplied by transistor MP54.

[0189] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0190] Transistors MP55 and MP56 are switched on / off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, transistor MP54 is initialized by setting its gate voltage to the voltage on power line VSS.

[0191] Transistor MP60 is switched on / off based on the signal on control line AZSL2. While transistor MP60 is on, the light-emitting element EL is initialized by setting the anode voltage to the voltage on power line VSS.

[0192] Transistors MP52 to MP60 may be transistors made of low-temperature polycrystalline silicon (LTPS). Also, at least one of transistors MP55 to MP58 or MP60 may be a transistor made of oxide semiconductor.

[0193] Figure 21 shows another example of a pixel PIX configuration. The signals on control line WSNL and control line WSPL are inverted signals of each other.

[0194] Each pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65-MN67, and a light-emitting element EL. Transistors MN63 and MN65-MN67 are, for example, N-type MOSFETs, and transistor MP64 is, for example, a P-type MOSFET.

[0195] Transistor MN63 has its gate connected to the control line WSNL, one of its source / drain connected to the other source / drain of transistor MP64, one end of capacitor C61, one end of capacitor C62, and the gate of transistor MN65, and the other source / drain connected to the signal line SGL and one of the source / drain of transistor MP64.

[0196] Transistor MP64 has its gate connected to the control line WSPL, one of its source / drain connected to the signal line SGL and the other of the source / drain of transistor MN63, and the other of its source / drain connected to the other of the source / drain of transistor MN63, one end of capacitor C61, one end of capacitor C62, and the gate of transistor MN65.

[0197] Capacitor C61 is constructed using, for example, a MOM (Metal Oxide Metal) capacitor, with one end connected to one of the source / drain of transistor MN63, the other of the source / drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C61 may also be constructed using, for example, a MOS capacitor or a MIM (Metal Insulator Metal) capacitor.

[0198] Capacitor C62 is constructed using, for example, a MOS capacitor, with one end connected to one of the source / drain of transistor MN63, the other of the source / drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power line VSS2. Capacitor C62 may also be constructed using, for example, a MOM capacitor or a MIM capacitor. Furthermore, the other end of capacitor C62 may be connected to the power line VSS3 (not shown).

[0199] Transistor MN65 has its gate connected to one source / drain of transistor MN63, the other source / drain of transistor MP64, one end of capacitor C61, and one end of capacitor C62. One source / drain of transistor MN65 is connected to the other source / drain of transistor MN66 and the other source / drain of transistor MN67, and the other source / drain is connected to the power line VCCP.

[0200] Transistor MN66 has its gate connected to the control line AZL, one of its source / drain connected to the power line VSS1, and the other of its source / drain connected to one of the source / drains of transistor MN65 and the other of the source / drains of transistor MN67.

[0201] Transistor MN67 has its gate connected to the control line DSL, one of its source / drain connected to the anode of the light-emitting element EL, and the other of its source / drain connected to one of the source / drain of transistor MN65 and the other of the source / drain of transistor MN66. Alternatively, transistor MN67 and the control line DSL may be omitted, and one of the source / drain of transistor MN65 may be connected to the other of the source / drain of transistor MN66 and the anode of the light-emitting element EL.

[0202] In this configuration, at pixel PIX, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL when at least one of transistors MN63 and MP64 is turned on. Transistor MN67 is turned on / off based on the signal from control line DSL. Transistor MN65 supplies a current to the light-emitting element EL corresponding to the voltage across capacitors C61 and C62 while transistor MN67 is on. The light-emitting element EL emits light based on the current supplied by transistor MP65.

[0203] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0204] Transistor MN66 may be switched on or off based on the signal on control line AZL. Alternatively, transistor MN66 may function as a resistor with a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0205] Transistors MN63, MP64, and MN65-MN67 may be transistors made of low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of transistors MN63, MP64, and MN66 may be a transistor made of oxide semiconductor.

[0206] Figure 22 shows another example of a pixel PIX configuration. This pixel PIX includes a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are, for example, N-type MOSFETs.

[0207] Transistor MN72 has its gate connected to the control line WSL, one of its source / drain connected to one of the source / drain of transistor MN74 and the other of the source / drain of transistor MN75, and the other of its source / drain connected to the signal line SGL.

[0208] Capacitor C71 has one end connected to the gate of transistor MN74 and one of the source / drain of transistor MN76, and the other end connected to the other of the source / drain of transistor MN77, one of the source / drain of transistor MN75, and the anode of light-emitting element EL.

[0209] Transistor MN73 has its gate connected to control line DSL1, one of its source / drain is connected to the other source / drain of transistor MN74 and the other source / drain of transistor MN76, and the other source / drain is connected to power line VCCP.

[0210] Transistor MN74 has its gate connected to one of the source / drain of transistor MN76 and one end of capacitor C71, one of its source / drains connected to one of the source / drains of transistor MN72 and the other of the source / drains of transistor MN75, and the other of its source / drains connected to one of the source / drains of transistor MN73 and the other of the source / drains of transistor MN76.

[0211] Transistor MN75 has its gate connected to control line DSL2, one of its source / drain connected to the other end of capacitor C71, the other of the source / drain of transistor MN77, and the anode of light-emitting element EL, and the other of its source / drain connected to one of the source / drain of transistor MN72 and one of the source / drain of transistor MN74.

[0212] Transistor MN76 has its gate connected to the gate and control line AZSL of transistor MN77, one of its source / drains connected to the gate and one end of capacitor C71 of transistor MN74, and the other of its source / drains connected to one of the source / drains of transistor MN73 and the other of the source / drains of transistor MN74.

[0213] The gate of transistor MN77 is connected to the gate of transistor MN76 and the control line AZSL, one of its source / drain is connected to the power line VSS, and the other of its source / drain is connected to the other end of capacitor C71, one of the source / drain of transistor MN75, and the anode of light-emitting element EL.

[0214] In this configuration, at pixel PIX, transistors MN72, MN74, and MN76 are turned on, setting the voltage across capacitor C71 based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on / off based on the signal from control line DSL1, and transistor MN75 is turned on / off based on the signal from control line DSL2. Transistor MN74 supplies a current to the light-emitting element EL corresponding to the voltage across capacitor C71 while transistors MN73 and MN75 are turned on. The light-emitting element EL emits light based on the current supplied by transistor MN74.

[0215] In this way, each pixel (PIX) emits light with a brightness corresponding to the pixel signal.

[0216] Transistor MN77 is switched on / off based on the signal on control line AZSL. While transistor MN77 is on, light-emitting element EL is initialized by setting the anode voltage to the voltage on power line VSS.

[0217] Transistors MN72 to MN77 may be transistors using low-temperature polycrystalline silicon (LTPS). Also, transistor MN76 may be a transistor using an oxide semiconductor.

[0218] <5. Examples of applications for electronic equipment>

[0219] Next, we will describe some application examples of the display device / display system described in the above embodiments.

[0220] (First application example)

[0221] The display device 1 described herein is also applicable to head-mounted displays (HMDs). HMDs can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), etc.

[0222] Figure 23 is an external view of HMD 320, which is a first application example of the display device / system. The HMD 320 in Figure 23 has a mounting member 322 for wearing over a person's eyes. This mounting member 322 is secured, for example, by hooking onto a person's ears.

[0223] A display device 321 is located inside the HMD 320, allowing the wearer to view stereoscopic images and other content on this display device 321. The HMD 320 is equipped with features such as wireless communication and an accelerometer, and can switch the stereoscopic images and other content displayed on the display device 321 according to the wearer's posture and gestures.

[0224] Alternatively, the HMD 320 may be equipped with a camera to capture images of the wearer's surroundings, and the display device 321 may display a composite image of the camera's captured images and a computer-generated image.

[0225] For example, by placing a camera on the back side of the display device 321 that the wearer of the HMD 320 sees, and using this camera to capture images of the area around the wearer's eyes, and displaying these images on a separate display on the outer surface of the HMD 320, people around the wearer can understand the wearer's facial expressions and eye movements in real time.

[0226] (Second application example)

[0227] Various types of HMD 320 are possible. For example, as shown in Figure 24, the display device / display system according to this disclosure can also be applied to smart glasses 340 that project various information onto eyeglasses 344.

[0228] The smart glasses 340 in Figure 24 have a main body 341, an arm 342, and a lens barrel 343.

[0229] The main unit 341 is connected to the arm unit 342. The main unit 341 is detachable from the glasses 344. The main unit 341 contains a control board and display unit for controlling the operation of the smart glasses 340.

[0230] The main body 341 and the lens barrel are connected to each other via the arm 342. The lens barrel 343 emits the image light emitted from the main body 341 through the arm 342 towards the lens 345 of the glasses 344. This image light enters the human eye through the lens 345.

[0231] As shown in Figure 24, the wearer of the smart glasses 340 can see not only the surrounding environment but also various information emitted from the lens barrel 343, just like with regular glasses.

[0232] (Third application example)

[0233] The display device / display system described herein is applicable not only to various displays used in vehicles, but also to displays mounted on various electronic devices.

[0234] Figure 25A is a front view of a digital camera 310, which is a third application example of the display device / display system, and Figure 25B is a rear view of the digital camera 310. The digital camera 310 in Figures 25A and 25B shows an example of a single-lens reflex camera with an interchangeable lens 312, but it is also applicable to cameras in which the lens 312 cannot be changed.

[0235] In the cameras shown in Figures 25A and 25B, when the photographer holds the grip 313 of the camera body 311, looks through the electronic viewfinder 315 to determine the composition, adjusts the focus, and presses the shutter button, the shooting data is saved to the camera's memory.

[0236] As shown in Figure 25B, the rear of the camera is equipped with a monitor screen 314 that displays shooting data and live images, and an electronic viewfinder 315. Additionally, the top of the camera may have a sub-screen that displays setting information such as shutter speed and exposure value.

[0237] By placing the sensor on top of the back side of the monitor screen 314, electronic viewfinder 315, sub-screen, etc. used in the camera, it can be used as a display device / display system according to this disclosure.

[0238] (Fourth application example)

[0239] Figure 26 shows an example of the appearance of the television device 330. The television device 330 has a video display screen section 331 which includes a front panel 332 and a filter glass 333.

[0240] The technology described in the above embodiment can be applied to this video display screen unit 331.

[0241] (Fifth Application Example) Figure 27 shows an example of the appearance of a smartphone 350. The smartphone 350 has a display unit 351 that displays various information and an operation unit 352 that includes buttons and the like that accept user input.

[0242] The technology described in the above embodiment can be applied to this display unit 351.

[0243] (Sixth application example)

[0244] The display device / display system according to this disclosure can be used for various applications. Figures 28A and 28B show the internal configuration of a vehicle 360, which is a sixth application example of the display device / display system according to this disclosure. Figure 28A shows the interior of the vehicle 360 ​​from the rear to the front, and Figure 28B shows the interior of the vehicle 360 ​​from the diagonally rear to the diagonally front.

[0245] The vehicle 360 ​​in Figures 28A and 28B includes a center display 361, a console display 362, a head-up display 363, a digital rear mirror 364, a steering wheel display 365, and a rear entertainment display 366.

[0246] The center display 361 is located on the dashboard 367, facing the driver's seat 368 and the passenger seat 369. Figures 28A and 28B show an example of a horizontally elongated center display 361 extending from the driver's seat 368 to the passenger seat 369, but the screen size and placement of the center display 361 are arbitrary.

[0247] The center display 361 can display information detected by various sensors. Specifically, the center display 361 can display images captured by an image sensor, distance images to obstacles in front of and to the sides of the vehicle measured by a Time of Flight (ToF) sensor, and passenger body temperature detected by an infrared sensor. The center display 361 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0248] Safety-related information includes data such as drowsiness detection, distraction detection, detection of mischief by a passenger, seatbelt usage status, and detection of an unattended occupant. This information is detected, for example, by sensors positioned on the back of the center display 361.

[0249] Operation-related information is obtained by detecting occupant gestures using sensors. The detected gestures may include the operation of various equipment within the vehicle's 360-degree space. For example, the operation of air conditioning, navigation systems, AV equipment, lighting systems, etc., may be detected.

[0250] The life log includes the life logs of all occupants. For example, the life log includes a record of each occupant's actions while on board. By acquiring and saving life logs, it is possible to determine the state of the occupants at the time of an accident.

[0251] Health-related information is obtained by detecting the occupant's body temperature using a temperature sensor and inferring their health status based on the detected temperature. Alternatively, the occupant's face may be captured using an image sensor, and their health status may be inferred from the captured facial expression. Furthermore, the occupant may be spoken to using an automated voice system, and their health status may be inferred based on their responses.

[0252] Authentication / identification-related information includes features such as a keyless entry function that uses sensors for facial recognition, and an automatic seat height and position adjustment function based on facial recognition.

[0253] Entertainment-related information includes functions that use sensors to detect information on how occupants operate AV equipment, and functions that use sensors to recognize occupants' faces and provide content tailored to them through the AV equipment.

[0254] The console display 362 can be used, for example, to display life log information. The console display 362 is located near the shift lever 371 on the center console 370 between the driver's seat 368 and the passenger seat 369. The console display 362 can also display information detected by various sensors. In addition, the console display 362 may display images of the area around the vehicle captured by an image sensor, or distance images to obstacles around the vehicle.

[0255] The head-up display 363 is virtually displayed behind the windshield 372 in front of the driver's seat 368. The head-up display 363 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 363 is often virtually positioned in front of the driver's seat 368, it is suitable for displaying information directly related to the operation of the vehicle 360, such as the vehicle's speed and fuel (battery) level.

[0256] The digital rearview mirror 364 can not only display the area behind the vehicle 360, but also show the condition of the rear-seat occupants. By placing a sensor on top of the back of the digital rearview mirror 364, it can be used, for example, to display life log information.

[0257] The steering wheel display 365 is positioned near the center of the steering wheel 373 of the vehicle 360. The steering wheel display 365 can be used to display at least one of the following: safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 365 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0258] The rear entertainment display 366 is mounted on the back of the driver's seat 368 or passenger seat 369 and is intended for viewing by rear-seat passengers. The rear entertainment display 366 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 366 is in front of the rear-seat passengers, it displays information relevant to them. For example, it may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of temperature sensor measurements of rear-seat passengers' body temperature, etc.

[0259] As mentioned above, by placing sensors on the back side of a display device / display system, it is possible to measure the distance to surrounding objects. Optical distance measurement methods can be broadly divided into passive and active types.

[0260] Passive distance measurement methods do not project light onto an object from the sensor, but rather measure distance by receiving light from the object. Examples of passive methods include the lens focusing method, the stereo method, and the monocular method.

[0261] Active radar systems measure distance by projecting light onto an object and receiving the reflected light with a sensor. Examples of active radar systems include optical radar, active stereo, illuminance difference stereo, moiré topography, and interferometry.

[0262] The display device 1 according to this disclosure is applicable to any of these distance measurement methods. By using a sensor placed on top of the back side of the display device 1 according to this disclosure, the passive or active distance measurement described above can be performed.

[0263] The embodiments described above may also take the following forms.

[0264] (1) A display device comprising: a pixel array in which pixels having light-emitting elements are arranged in an array along a first direction and a second direction intersecting the first direction; signal lines connected to the pixels along the second direction; a first drive circuit that makes the pixels arranged along the first direction drivable; and a second drive circuit that outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit, wherein the second drive circuit comprises: a lamp signal output circuit that outputs a lamp signal; and a switch that acquires and holds the lamp signal output from the lamp signal output circuit at a timing corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal with their inclinations changed.

[0265] (2) The display device according to (1), wherein the lamp signal output circuit outputs such that the slope of the first lamp signal is gentler than the slope of the second lamp signal.

[0266] (3) The display device according to (2), wherein the lamp signal output circuit comprises a first lamp signal output circuit that outputs the first lamp signal and a second lamp signal output circuit that outputs the second lamp signal.

[0267] (4) The lamp signal output circuit comprises a capacitor whose first end is connected to the positive power supply voltage line and whose second end is connected to the output terminal of the lamp signal output circuit, and a transistor whose first end is connected to the second end of the capacitor and whose second end is connected to the negative power supply voltage line, and whose gate width can be changed, and which outputs the first lamp signal or the second lamp signal depending on the gate width of the transistor, as described in (2).

[0268] (5) The display device according to (4), wherein the transistors include: a first transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line; and a second transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line.

[0269] (6) The display device according to (5), wherein the lamp signal output circuit outputs the first lamp signal when the first transistor is on and the second transistor is off, and outputs the second lamp signal when the first transistor is off and the second transistor is on.

[0270] (7) The display device according to (5), wherein the lamp signal output circuit outputs the first lamp signal when the first transistor is on and the second transistor is off, and outputs the second lamp signal when both the first and second transistors are on.

[0271] (8) The lamp signal output circuit comprises a capacitor whose first end is connected to a positive power supply voltage line and whose second end is connected to the output terminal of the lamp signal output circuit and whose capacitance can be changed, and a transistor whose first end is connected to the second end of the capacitor and whose second end is connected to a negative power supply voltage line, and the display device according to (2) outputs the first lamp signal or the second lamp signal according to the capacitance of the capacitor.

[0272] (9) The display device according to (8), wherein the capacitor comprises: a first capacitor whose first end is connected to the positive power supply voltage line via a first switch and whose second end is connected to the output terminal of the lamp signal output circuit; and a second capacitor whose first end is connected to the positive power supply voltage line via a second switch and whose second end is connected to the output terminal of the lamp signal output circuit.

[0273] (10) The display device according to (9), wherein the lamp signal output circuit outputs the first lamp signal when the first switch is on and the second switch is off, and outputs the second lamp signal when the first switch is off and the second switch is on.

[0274] (11) The display device according to (9), wherein the lamp signal output circuit outputs the first lamp signal when the first switch is on and the second switch is off, and outputs the second lamp signal when both the first switch and the second switch are on.

[0275] (12) Electronic device comprising: a pixel array in which pixels having light-emitting elements are arranged in an array along a first direction and a second direction intersecting the first direction; signal lines connected to the pixels along the second direction; a first drive circuit that makes the pixels arranged along the first direction drivable; and a second drive circuit that outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit, wherein the second drive circuit comprises: a lamp signal output circuit that outputs a lamp signal; and a switch that acquires and holds the lamp signals output from the lamp signal output circuit at timings corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal with their inclinations changed.

[0276] The aspects of this disclosure are not limited to the embodiments described above, but include various conceivable variations, and the effects of this disclosure are not limited to those described above. The components in each embodiment may be appropriately combined and applied. That is, various additions, modifications, and partial deletions are possible, as long as they do not deviate from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0277] 1: Display device, 10: Pixel array, 100: Pixel, 12: Control circuit, 14: First drive circuit, 140: Signal line, 16: Second drive circuit, 160: Signal line, 162: Lamp signal output circuit, 164: First lamp signal output circuit, 166: Second lamp signal output circuit, VDD: Power supply voltage line, VSS: Power supply voltage line, 168: Capacitor, 170: First transistor, 172: Second transistor, 174: First capacitor, 176: Second capacitor, 178: First switch, 180: Second switch, 182: Transistor, 310: Digital camera, 311: Camera body, 312: Lens, 313: Grip, 314: Monitor screen, 315: Electronic viewfinder, 320: HMD, 321: Display device, 322: Mounting component, 330: Television device, 331: Video display screen, 332: Front panel, 333: Filter glass, 340: Smart glasses, 341: Main unit, 342: Arm unit, 343: Lens barrel, 344: Glasses, 345: Lens, 350: Smartphone, 351: Display unit, 352: Control unit, 360: Vehicle, 361: Center display, 362: Console display, 363: Head-up display, 364: Digital rear mirror, 365: Steering wheel display, 366: Rear entertainment display, 367: Dashboard, 368: Driver's seat, 369: Passenger seat, 370: Center console, 371: Shift lever, 372: Windshield, 373: Steering wheel

Claims

1. A display device comprising: a pixel array in which pixels having light-emitting elements are arranged in an array along a first direction and a second direction intersecting the first direction; signal lines connected to the pixels along the second direction; a first drive circuit that makes the pixels arranged along the first direction drivable; and a second drive circuit that outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit, wherein the second drive circuit comprises: a lamp signal output circuit that outputs a lamp signal; and a switch that acquires and holds the lamp signal output from the lamp signal output circuit at a timing corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal with their inclinations changed.

2. The display device according to claim 1, wherein the lamp signal output circuit outputs the first lamp signal such that the slope of the first lamp signal is gentler than the slope of the second lamp signal.

3. The display device according to claim 2, wherein the lamp signal output circuit comprises a first lamp signal output circuit that outputs the first lamp signal, and a second lamp signal output circuit that outputs the second lamp signal.

4. The lamp signal output circuit comprises a capacitor whose first end is connected to a positive power supply voltage line and whose second end is connected to the output terminal of the lamp signal output circuit, and a transistor whose first end is connected to the second end of the capacitor and whose second end is connected to a negative power supply voltage line, and whose gate width can be changed, and the first lamp signal or the second lamp signal is output depending on the gate width of the transistor, the display device according to claim 2.

5. The display device according to claim 4, comprising: a first transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line; and a second transistor whose first terminal is connected to the second terminal of the capacitor and whose second terminal is connected to the negative power supply voltage line.

6. The display device according to claim 5, wherein the lamp signal output circuit outputs the first lamp signal when the first transistor is on and the second transistor is off, and outputs the second lamp signal when the first transistor is off and the second transistor is on.

7. The display device according to claim 5, wherein the lamp signal output circuit outputs the first lamp signal when the first transistor is on and the second transistor is off, and outputs the second lamp signal when both the first transistor and the second transistor are on.

8. The lamp signal output circuit comprises a capacitor whose first end is connected to a positive power supply voltage line and whose second end is connected to the output terminal of the lamp signal output circuit, and whose capacitance can be changed; and a transistor whose first end is connected to the second end of the capacitor and whose second end is connected to a negative power supply voltage line, wherein the first lamp signal or the second lamp signal is output depending on the capacitance of the capacitor, as described in claim 2.

9. The display device according to claim 8, comprising: a first capacitor whose first end is connected to the positive power supply voltage line via a first switch and whose second end is connected to the output terminal of the lamp signal output circuit; and a second capacitor whose first end is connected to the positive power supply voltage line via a second switch and whose second end is connected to the output terminal of the lamp signal output circuit.

10. The display device according to claim 9, wherein the lamp signal output circuit outputs the first lamp signal when the first switch is on and the second switch is off, and outputs the second lamp signal when the first switch is off and the second switch is on.

11. The display device according to claim 9, wherein the lamp signal output circuit outputs the first lamp signal when the first switch is on and the second switch is off, and outputs the second lamp signal when both the first switch and the second switch are on.

12. Electronic device comprising: a pixel array in which pixels having light-emitting elements are arranged in an array along a first direction and a second direction intersecting the first direction; signal lines connected to the pixels along the second direction; a first drive circuit that makes the pixels arranged along the first direction drivable; and a second drive circuit that outputs an offset signal and a pixel signal via the respective signal lines to the pixels belonging to the first direction selected by the first drive circuit, wherein the second drive circuit comprises: a lamp signal output circuit that outputs a lamp signal; and a switch that acquires and holds the lamp signal output from the lamp signal output circuit at a timing corresponding to the intensity output for each signal line, wherein the lamp signal output circuit outputs a first lamp signal corresponding to the offset signal and a second lamp signal corresponding to the pixel signal with their inclinations changed.

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