Semiconductor device

Abstract

This semiconductor device comprises: a first conductivity-type semiconductor layer having a first principal surface and a second principal surface; a first pillar region of a first conductivity type extending in the depth direction of the semiconductor layer from the first principal surface toward the second principal surface in the semiconductor layer; and a second pillar region of a second conductivity type adjacent to the first pillar region in the semiconductor layer and extending in the depth direction, wherein the first width W1 of the first pillar region is greater than the second width W2 of the second pillar region.

Description

Semiconductor equipment Related applications

[0001] This application corresponds to Japanese Patent Application No. 2025-018599, filed with the Japan Patent Office on February 6, 2025, and Japanese Patent Application No. 2025-074519, filed with the Japan Patent Office on April 28, 2025, and the full disclosures of these applications are incorporated herein by reference.

[0002] This disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses an electronic device having an impurity region introduced into a silicon carbide layer by a channeling injection method.

[0004] U.S. Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; a first pillar region of the first conductivity type extending in the depth direction of the semiconductor layer from the first main surface toward the second main surface within the semiconductor layer; and a second pillar region of the second conductivity type adjacent to the first pillar region within the semiconductor layer and extending in the depth direction, wherein the first width W1 of the first pillar region is greater than the second width W2 of the second pillar region.

[0006] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of chip layout. Figure 4 is a perspective view showing an example of chip layout. Figure 5 is a cross-sectional perspective view showing a key part of the chip together with the basic form of the pillar region. Figure 6 is a diagram schematically showing the current path leading to dielectric breakdown in an asymmetric superjunction structure. Figure 7 is a grayscale color map showing the change in withstand voltage VB with respect to the rate of change of np doping concentration in a symmetric structure. Figure 8 is a grayscale color map showing the change in withstand voltage VB with respect to the rate of change of np doping concentration in an asymmetric structure. Figure 9 is a grayscale color map showing the change in withstand voltage VB with respect to the rate of change of np doping concentration in an asymmetric structure. Figure 10 is a grayscale color map showing the change in withstand voltage VB with respect to the rate of change of np doping concentration in an asymmetric structure. Figure 11 is a diagram showing the relationship between Δwn and Ron,sp for each pitch. Figure 12 shows the relationship between Δwn and Na and Nd for each pitch. Figure 13 shows the result of extracting the lowest Ron,sp dependent on wn for the breakdown voltage VB. Figure 14 shows the lateral electric field strength for each pillar width. Figure 15 shows the result of plotting the Δwn dependence of the peak electric field at the set point O together with the x and y components. Figure 16 shows the effect of predetermined physical properties on Ron,sp. Figure 17 shows the effect of the combination of physical properties in Figure 16 on Ron,sp. Figure 18 is a cross-sectional perspective view showing the pillar region according to the first embodiment. Figure 19 is a cross-sectional perspective view showing the pillar region according to the second embodiment. Figure 20 is a cross-sectional perspective view showing the pillar region according to the third embodiment. Figure 21 is a cross-sectional perspective view showing the pillar region according to the fourth embodiment. Figure 22 is a cross-sectional perspective view showing the pillar region according to the fifth embodiment. Figure 23 is a cross-sectional perspective view showing the pillar region according to the sixth embodiment. Figure 24 is a cross-sectional perspective view showing the pillar region according to the seventh embodiment. Figure 25 is a cross-sectional perspective view showing the pillar region according to the eighth embodiment. Figure 26 is a cross-sectional perspective view showing the pillar region according to the ninth embodiment. Figure 27 is a cross-sectional perspective view showing the pillar region according to the tenth embodiment.Figure 28 is a cross-sectional perspective view showing a pillar region according to the 11th embodiment. Figure 29 is a plan view showing a key part of the active region. Figure 30 is a cross-sectional perspective view showing a gate structure according to the first embodiment. Figure 31 is a cross-sectional view showing a key part of the outer peripheral region. Figure 32 is a schematic diagram showing a wafer used in the manufacture of a semiconductor device. Figure 33 is a flowchart showing an example of a semiconductor device manufacturing method. Figure 34A is a cross-sectional perspective view showing an example of a semiconductor device manufacturing method. Figure 34B is a cross-sectional perspective view showing a process after Figure 34A. Figure 34C is a cross-sectional perspective view showing a process after Figure 34B. Figure 35 is a plan view showing a semiconductor device according to the second embodiment. Figure 36 is a cross-sectional view along the line XXXVI-XXXVI shown in Figure 35. Figure 37 is a plan view showing an example of a chip layout. Figure 38 is a perspective view showing an example of a chip layout. Figure 39 is a plan view showing a key part of the active region. Figure 40 is a cross-sectional perspective view showing a gate structure according to the first embodiment. Figure 41 is a cross-sectional view showing a key part of the outer peripheral region. Figure 42 is a cross-sectional perspective view showing a gate structure according to the second embodiment. Figure 43 is a cross-sectional perspective view showing a gate structure according to the third embodiment. Figure 44 is a cross-sectional perspective view showing a gate structure according to the fourth embodiment. Figure 45 is a plan view showing a semiconductor device according to the third embodiment. Figure 46 is a cross-sectional view along the XLVI-XLVI line shown in Figure 45. Figure 47 is a plan view showing an example of a chip layout. Figure 48 is a perspective view showing an example of a chip layout. Figure 49 is a cross-sectional perspective view showing a diode structure according to the basic embodiment. Figure 50 is a cross-sectional perspective view showing a laminated portion according to the second embodiment. Figure 51 is a cross-sectional perspective view showing a laminated portion according to the third embodiment. Figure 52 is a cross-sectional perspective view showing a laminated portion according to the fourth embodiment. Figure 53 is a cross-sectional perspective view showing a laminated portion according to the fifth embodiment. Figure 54 is a cross-sectional perspective view showing a laminated portion according to the sixth embodiment. Figure 55 is a cross-sectional perspective view showing a laminated portion according to the seventh embodiment. Figure 56 is a diagram related to the manufacturing method of the laminated portion according to the seventh embodiment.

[0007] [Detailed Description] The following describes embodiments in detail with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not precisely illustrated. The scales, ratios, angles, etc. do not necessarily match. The same reference numerals are assigned to corresponding structures among the accompanying drawings, and duplicate descriptions are omitted or simplified. For structures with omitted or simplified descriptions, the descriptions made before the omission or simplification apply.

[0008] In this specification, when the term "substantially" is used, this term includes not only a numerical value (form) equal to the numerical value (form) of the comparison target, but also a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," "third," etc. are used, but these are symbols attached to the names of each structure to clarify the order of description and are not attached with the intention of limiting the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as "first conductivity type," and "n-type" may be referred to as "second conductivity type." Of course, "n-type" may be referred to as "first conductivity type," and "p-type" may be referred to as "second conductivity type." "p-type" is a conductivity type caused by a trivalent element, and "n-type" is a conductivity type caused by a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium unless otherwise specified. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth unless otherwise specified.

[0010] FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of the chip 2. FIG. 4 is a perspective view showing an example layout of the chip 2. FIG. 5 is a cross-sectional perspective view showing a main part of the chip 2 together with the basic form of the second pillar region 12.

[0011] Referring to FIGS. 1 to 5, in this embodiment, the semiconductor device 1A is a SiC semiconductor device. The semiconductor device 1A includes a chip 2 containing a SiC single crystal. The chip 2 may be referred to as a "SiC chip" or a "semiconductor chip". In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example where the chip 2 is made of a 4H-SiC single crystal is shown, but the chip 2 may be made of other polytypes.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from the vertical direction Z. The vertical direction Z is also the thickness direction of the chip 2 or the normal direction of the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square shape or a rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000 - 1) plane) of the SiC single crystal.

[0014] Regarding the circumferential direction (counterclockwise in FIG. 1) of the chip 2 starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face each other in a second direction Y intersecting (specifically, orthogonal) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X.

[0015] In this configuration, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0016] The XY plane, which includes the first direction X and the second direction Y, forms a horizontal plane perpendicular to the vertical direction Z. Hereafter, the axis extending along the vertical direction Z may be referred to as the "vertical axis." Also below, the first direction X and the second direction Y may be referred to as the "horizontal direction." The horizontal direction is also the direction extending along the first principal plane 3.

[0017] Referring to Figure 5, the chip 2 (first main surface 3 and second main surface 4) has an off-angle θoff, which is tilted at a predetermined angle in the off-direction Doff with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is tilted by an off-angle θoff from the vertical axis toward the off-direction Doff. Also, the c-plane of the SiC single crystal is tilted by an off-angle θoff with respect to the horizontal plane.

[0018] The off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X). The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0019] The off-angle θoff is preferably 5° or less. The off-angle θoff is particularly preferably 2° or more and 4.5° or less. The off-angle θoff is typically set in the range of 4° ± 0.1°. Of course, this specification does not exclude the form in which the off-angle θoff is 0° (i.e., the form in which the first principal surface 3 is a just plane with respect to the c-plane).

[0020] The chip 2 includes an n-type base layer 6 made of a SiC single crystal. The base layer 6 may also be referred to as the "base SiC layer," "base region," etc. The base layer 6 extends in layers horizontally and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a SiC single crystal substrate (i.e., a SiC substrate). The base layer 6 has the aforementioned off-direction Doff and off-angle θoff.

[0021] Base layer 6 is 1 x 10 １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values. It is preferable that the base layer 6 has a nearly constant n-type impurity concentration in the thickness direction. It is preferable that the n-type impurity concentration of the base layer 6 is adjusted by a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.

[0022] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value that falls within any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, and 250 μm or more and 300 μm or less. It is preferable that the base thickness TB is 50 μm or more and 250 μm or less.

[0023] Chip 2 includes a laminated portion 7 stacked on a base layer 6. The laminated portion 7 may be referred to as a "semiconductor layer," "SiC layer," "SiC laminated portion," or "semiconductor laminated portion." In this embodiment, the laminated portion 7 is provided as a forming layer for a superjunction structure SJ. In this embodiment, the laminated portion 7 is formed by a single semiconductor layer, but it may be formed by multiple semiconductor layers. If the laminated portion 7 consists of multiple semiconductor layers, the number of layers is arbitrary and is adjusted as appropriate according to the electrical characteristics to be achieved. Examples of electrical characteristics include breakdown voltage and resistance.

[0024] The laminated portion 7 extends horizontally in layers and forms part of the first to fourth sides 5A to 5D of the chip 2. The laminated portion 7 consists of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized starting from the base layer 6.

[0025] The laminated portion 7 has a lower end and an upper end. The lower end of the laminated portion 7 is the crystal growth starting point, and the upper end of the laminated portion 7 is the crystal growth ending point. Since the laminated portion 7 is grown continuously from the base layer 6, the lower end of the laminated portion 7 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the laminated portion 7 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The laminated portion 7 has an off-direction Doff and off-angle θoff that substantially coincide with the off-direction Doff and off-angle θoff of the base layer 6.

[0026] The laminated portion 7 may be referred to as the drift region 8. The drift region 8 is the base region for impurity regions (such as the first pillar region 13, second pillar region 12, body region 32, source region 33, and contact region 34, which will be described later) that are selectively formed by the implantation of impurity ions into the laminated portion 7. By implanting n-type or p-type impurity ions into the laminated portion 7 to a concentration exceeding that of the drift region 8, various n-type or p-type impurity regions with characteristics corresponding to their respective concentrations are formed.

[0027] The drift region 8 is replaced by various impurity regions in the target region of the laminated section 7 by ion implantation, but the n-type impurity ions added during the epitaxial growth of the laminated section 7 remain at the concentration at the time of growth. As a result, the drift region 8 provides an n-type background concentration within a range that does not impair the characteristics (electrical behavior) of the various impurity regions. On the other hand, even if n-type or p-type impurity ions are implanted into the laminated section 7, if the amount is small, the characteristics of the drift region 8 are maintained in that region, and the drift region 8 remains.

[0028] The n-type impurity concentration in the laminated portion 7 (drift region 8) is preferably less than the n-type impurity concentration in the base layer 6. The laminated portion 7 is 1 × 10１５ cm －３ The above 1 x 10 １６ cm －３ The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration in the laminated portion 7 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration in the laminated portion 7 may have a concentration gradient that gradually increases and / or decreases in the lamination direction (crystal growth direction).

[0029] The laminated portion 7 (drift region 8) has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the laminated portion 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the laminated portion 7 contains a pentavalent element other than phosphorus.

[0030] The concentration of n-type impurities in the laminated portion 7 (drift region 8) is preferably adjusted by at least nitrogen. If the laminated portion 7 contains two or more pentavalent elements, it is preferable that the laminated portion 7 contains nitrogen and a pentavalent element other than nitrogen. In this case, it is preferable that the laminated portion 7 contains either or both of arsenic and antimony as the pentavalent elements other than phosphorus and nitrogen. In this embodiment, the laminated portion 7 (drift region 8) does not contain phosphorus and contains nitrogen as the pentavalent element.

[0031] The laminated portion 7 has an epitaxial thickness TE. Preferably, the epitaxial thickness TE is less than the base thickness TB. Preferably, the epitaxial thickness TE is 1 μm or more. Preferably, the epitaxial thickness TE is 5 μm or less. The epitaxial thickness TE may have a value that falls within any one of the following ranges: 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0032] The semiconductor device 1A includes an active region 10 set on the chip 2. The active region 10 is set in the inner part of the chip 2, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. Preferably, the planar area of ​​the active region 10 is 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The semiconductor device 1A includes an outer peripheral region 11 set outside the active region 10 on the chip 2. The outer peripheral region 11 is located in the area between the periphery of the chip 2 and the active region 10 in a plan view. In a plan view, the outer peripheral region 11 extends in a band shape along the active region 10 and is set in a polygonal ring (a quadrilateral ring in this embodiment) surrounding the active region 10.

[0034] The semiconductor device 1A includes a plurality of p-type second pillar regions 12 formed in the laminated portion 7 in the active region 10. The second pillar regions 12 may also be referred to as "pillar layers," "column layers (regions)," "p-type layers (regions)," "p-type zones," etc. The plurality of second pillar regions 12 are formed horizontally spaced apart within the laminated portion 7 and demarcate a plurality of n-type first pillar regions 13, each consisting of a part of the laminated portion 7.

[0035] Multiple second pillar regions 12 are formed by a part of the laminated portion 7. Multiple second pillar regions 12, together with multiple first pillar regions 13, form multiple pn junctions that maintain charge balance. As a result, multiple second pillar regions 12, together with multiple first pillar regions 13, form a superjunction structure SJ within the laminated portion 7. Maintaining charge balance means that, with respect to multiple adjacent second pillar regions 12, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the multiple first pillar regions 13.

[0036] When the donor concentration Nd in the first pillar region 13 and the width of the first pillar region 13 are denoted as W1, and the acceptor concentration Na in the second pillar region 12 and the width of the second pillar region 12 are denoted as W2, the charge balance CB between the first pillar region 13 and the second pillar region 12 is given by the following formula (1).

[0037] CB = (Nd × W1) / (Na × W2) ... (1) The multiple second pillar regions 12 are arranged at intervals in the first direction X within the stacked portion 7 and are each formed in a strip shape extending in the second direction Y. In other words, the multiple second pillar regions 12 are formed in a stripe shape extending in the second direction Y, and the multiple first pillar regions 13 are formed in a stripe shape extending in the second direction Y. Furthermore, the multiple second pillar regions 12 are arranged at intervals in the a-axis direction of the SiC single crystal and extend in the m-axis direction of the SiC single crystal.

[0038] Referring to Figure 5, each of the multiple second pillar regions 12 has a second lower end portion 12a on the lower end side of the laminated portion 7 and a second upper end portion 12b on the upper end side of the laminated portion 7. The second lower end portion 12a is located in the region on the lower end side of the laminated portion 7 with respect to the middle part of the thickness range of the laminated portion 7, and the second upper end portion 12b is located in the region on the upper end side of the laminated portion 7 with respect to the middle part of the thickness range of the laminated portion 7.

[0039] The second lower end portion 12a is formed with a gap between the lower end and upper end of the laminated portion 7, and may face the base layer 6 with a part (lower end portion) of the laminated portion 7 in between. The second lower end portion 12a may substantially coincide with the lower end of the laminated portion 7 and be connected to the base layer 6.

[0040] The distance between the lower end of the laminated portion 7 and the second lower end portion 12a may be 0 μm or more and 2 μm or less. The distance between the lower end of the laminated portion 7 and the second lower end portion 12a may have a value that falls within any one of the following ranges: 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0041] The second lower end portion 12a may cross the boundary between the base layer 6 and the stacked portion 7 and have an extension portion located within the base layer 6. In this case, the thickness of the extension portion of the second lower end portion 12a with reference to the upper end of the base layer 6 may exceed 0 μm and be 2 μm or less. The thickness of the extension portion of the second lower end portion 12a may have a value belonging to any one of the ranges of more than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0042] The second upper end portion 12b may be formed at an interval from the upper end of the stacked portion 7 toward the lower end side and may face the upper end of the stacked portion 7 with a part (upper end portion) of the stacked portion 7 interposed therebetween. The second upper end portion 12b may substantially coincide with the upper end of the stacked portion 7.

[0043] The distance between the upper end of the stacked portion 7 and the second upper end portion 12b may be 0 μm or more and 1 μm or less. The distance between the upper end of the stacked portion 7 and the second upper end portion 12b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0044] The plurality of second pillar regions 12 may have a p-type impurity concentration with a peak value of 1 × 10 １５ cm －３ or more and 1 × 10 １８ cm －３ or less. The p-type impurity concentration of the second pillar region 12 is preferably adjusted by at least one trivalent element. In this form, the p-type impurity concentration of the second pillar region 12 is adjusted by aluminum.

[0045] The plurality of second pillar regions 12 each have a second width W2. The second width W2 is the width in a direction orthogonal to the extending direction of the second pillar region 12. The second width W2 is preferably less than the epi thickness TE of the stacked portion 7. Of course, the second width W2 may be equal to or greater than the epi thickness TE.

[0046] The second width W2 may be 0.1 μm or more and 10 μm or less. The second width W2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less. The second width W2 may have a value that falls within any one of the following ranges: above 5 μm or less, 5 μm to 5.5 μm, 5.5 μm to 6 μm, 6 μm to 6.5 μm, 6.5 μm to 7 μm, 7 μm to 7.5 μm, 7.5 μm to 8 μm, 8 μm to 8.5 μm, 8.5 μm to 9 μm, 9 μm to 9.5 μm, and 9.5 μm to 10 μm. The second width W2 is preferably 0.4 μm to 1.5 μm.

[0047] Each of the multiple second pillar regions 12 has a second thickness T2. The second thickness T2 may also be referred to as the depth of the multiple second pillar regions 12. The second thickness T2 may be less than the epitaxial thickness TE of the laminated portion 7. The second thickness T2 may be greater than the epitaxial thickness TE. The second thickness T2 may be approximately equal to the epitaxial thickness TE.

[0048] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 30 μm or less. The second thickness T2 may have a value that falls within any one of the following ranges: 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, and 25 μm or more and 30 μm or less.

[0049] It is preferable that the second width W2 is less than the epitaxial thickness TE of the laminated portion 7, and the second thickness T2 is greater than the second width W2. In other words, it is preferable that each of the multiple second pillar regions 12 has a second aspect ratio T2 / W2 that extends in a vertical columnar shape along the thickness direction of the laminated portion 7. The second aspect ratio T2 / W2 is the ratio of the second thickness T2 to the second width W2. In this case, it is particularly preferable that the second thickness T2 is greater than the epitaxial thickness TE. For example, the second aspect ratio T2 / W2 may be 2 or more and 30 or less.

[0050] Multiple second pillar regions 12 are formed with a second pitch P2 spacing in the first direction X. Preferably, the second pitch P2 is less than the epitaxial thickness TE of the laminated portion 7. Of course, the second pitch P2 may be greater than or equal to the epitaxial thickness TE.

[0051] The second pitch P2 may be 0.1 μm or more and 10 μm or less. The second pitch P2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm The second pitch P2 may have a value that falls within any one of the following ranges: 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or less, and 9.5 μm or more and 10 μm or less. The second pitch P2 is preferably 0.5 μm or more and 1.5 μm or less.

[0052] Referring to Figure 5, each of the multiple first pillar regions 13 has a first lower end portion 13a on the lower end side of the laminated portion 7 and a first upper end portion 13b on the upper end side of the laminated portion 7. The first lower end portion 13a is located in the region on the lower end side of the laminated portion 7 with respect to the middle part of the thickness range of the laminated portion 7, and the first upper end portion 13b is located in the region on the upper end side of the laminated portion 7 with respect to the middle part of the thickness range of the laminated portion 7.

[0053] The first lower end portion 13a is formed with a gap between the lower end and upper end of the laminated portion 7, and may face the base layer 6 with a part (lower end) of the laminated portion 7 in between. The first lower end portion 13a may substantially coincide with the lower end of the laminated portion 7 and be connected to the base layer 6.

[0054] The distance between the lower end of the laminated portion 7 and the first lower end portion 13a may be 0 μm or more and 2 μm or less. The distance between the lower end of the laminated portion 7 and the first lower end portion 13a may have a value that falls within any one of the following ranges: 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0055] The first lower end portion 13a may have an extension that crosses the boundary between the base layer 6 and the laminated portion 7 and is located within the base layer 6. In this case, the thickness of the extension portion of the first lower end portion 13a, with respect to the upper end of the base layer 6, may be greater than 0 μm and less than or equal to 2 μm. The thickness of the extension portion of the first lower end portion 13a may have a value that falls within any one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.5 μm, and 1.5 μm or more and less than or equal to 2 μm.

[0056] The first upper end portion 13b is formed with a gap between the upper end and lower end of the laminated portion 7, and may face the upper end of the laminated portion 7 with a part of the laminated portion 7 (upper end portion) in between. The first upper end portion 13b may substantially coincide with the upper end of the laminated portion 7.

[0057] The distance between the upper end of the laminated portion 7 and the first upper end portion 13b may be 0 μm or more and 1 μm or less. The distance between the upper end of the laminated portion 7 and the first upper end portion 13b may have a value that falls within any one of the following ranges: 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0058] Multiple first pillar regions 13 are 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３The following n-type impurity concentrations may be present as peak values. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration in the first pillar region 13 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this embodiment, the n-type impurity concentration in the first pillar region 13 is adjusted by phosphorus.

[0059] Each of the multiple first pillar regions 13 has a first width W1. The first width W1 is the width in a direction perpendicular to the extending direction of the first pillar region 13. Preferably, the first width W1 is wider than the second width W2. Preferably, the first width W1 is less than the epitaxial thickness TE of the laminated portion 7. Of course, the first width W1 may be greater than or equal to the epitaxial thickness TE.

[0060] The first width W1 may be 0.1 μm or more and 10 μm or less. The first width W1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less. The first width W1 may have a value that falls within any one of the following ranges: above 5 μm or less, 5 μm to 5.5 μm, 5.5 μm to 6 μm, 6 μm to 6.5 μm, 6.5 μm to 7 μm, 7 μm to 7.5 μm, 7.5 μm to 8 μm, 8 μm to 8.5 μm, 8.5 μm to 9 μm, 9 μm to 9.5 μm, and 9.5 μm to 10 μm. The first width W1 is preferably 0.5 μm to 1.6 μm.

[0061] Each of the multiple first pillar regions 13 has a first thickness T1. The first thickness T1 may also be referred to as the depth of the multiple first pillar regions 13. The first thickness T1 may be less than the epitaxial thickness TE of the laminated portion 7. The first thickness T1 may be greater than the epitaxial thickness TE. The first thickness T1 may be approximately equal to the epitaxial thickness TE.

[0062] The first thickness T1 is preferably 1 μm or more. The first thickness T1 is preferably 30 μm or less. The first thickness T1 may have a value that falls within any one of the following ranges: 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, and 25 μm or more and 30 μm or less.

[0063] It is preferable that the first width W1 is less than the epitaxial thickness TE of the laminated portion 7, and the first thickness T1 is greater than the first width W1. In other words, it is preferable that each of the multiple first pillar regions 13 has a first aspect ratio T1 / W1 that extends in a vertical columnar shape along the thickness direction of the laminated portion 7. The first aspect ratio T1 / W1 is the ratio of the first thickness T1 to the first width W1. In this case, it is particularly preferable that the first thickness T1 is greater than the epitaxial thickness TE. For example, the first aspect ratio T1 / W1 may be greater than 1 and less than or equal to 100.

[0064] Multiple first pillar regions 13 are formed with a first pitch P1 spacing in the first direction X. Preferably, the first pitch P1 is less than the epitaxial thickness TE of the laminated portion 7. Of course, the first pitch P1 may be greater than or equal to the epitaxial thickness TE.

[0065] The first pitch P1 may be 0.1 μm or more and 10 μm or less. The first pitch P1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm The first pitch P1 may have a value that falls within any one of the following ranges: 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or less, and 9.5 μm or more and 10 μm or less. The first pitch P1 is preferably 0.5 μm or more and 1.5 μm or less.

[0066] In this configuration, the drift region 8 of the active region 10 is replaced entirely or partially by the first pillar region 13 and the second pillar region 12. The drift region 8 may be formed (remaining) outside the formation area of ​​the first pillar region 13 and the second pillar region 12 in the active region 10. Figure 5 shows a configuration in which the drift region 8 is not formed in the active region 10, and is formed only in the outer peripheral region 11, in order to clarify the basic configuration of the first pillar region 13 and the second pillar region 12. Although not shown in Figure 5, the drift region 8 may remain in the active region 10.

[0067] Furthermore, the first pillar region 13 is an impurity region where the conductivity type of the drift region 8 is maintained, and therefore may simply be referred to as the drift region. Considering the concentration difference between the first pillar region 13 and the drift region 8 (concentration of the first pillar region 13 > concentration of the drift region 8), the first pillar region 13 may be referred to as the "high-concentration drift region" and the drift region 8 as the "low-concentration drift region". Also, considering that the first pillar region 13 is formed in the drift region 8 after its formation, the drift region 8 may be referred to as the "base drift region" and the first pillar region 13 as the "second drift region".

[0068] Furthermore, in this configuration, the concentration of the first pillar region 13 / concentration of the second pillar region 12 (N1 / N2) may be within the range of -10% to +10% of the standard second width / first width (W2 / W1).

[0069] The following describes in detail a structure that can maintain the voltage rating of the superjunction structure (SJ) while further reducing the on-resistance.

[0070] 1. Issues to be considered A superjunction structure SJ having a repeating structure of n-type pillars (corresponding to the first pillar region 13 mentioned above) and p-type pillars (corresponding to the second pillar region 12 mentioned above) is attracting attention as a structure that can reduce on-resistance in addition to maintaining high breakdown voltage. The breakdown voltage and on-resistance of a superjunction structure SJ are determined by parameters such as the pillar width of the superjunction structure SJ, the doping concentration (impurity concentration) to the pillars, and the depth of the pillars. To date, much research has been conducted on improving the characteristics of superjunction structures SJ by optimizing these parameters.

[0071] Many previous studies have focused on optimizing symmetric superjunction structures where the width and density of both n-type and p-type pillars are equal (hereinafter sometimes referred to as "symmetric configuration"). On the other hand, it is also necessary to consider asymmetric superjunction structures with n-type and p-type pillars having different widths and densities (hereinafter sometimes referred to as "asymmetric configuration").

[0072] In superjunction structures (SJs) fabricated from SiC, unlike superjunction structures (SJs) made from Si, the current path leading to dielectric breakdown may cross the boundary between n-type and p-type pillars due to the crystal orientation anisotropy of collisional ionization. Therefore, in SiC superjunction structures (SJs), it is preferable to design the device breakdown voltage appropriately, taking this physical phenomenon into consideration.

[0073] In the following, referring to Figures 6 to 17, we perform a breakdown voltage analysis considering the crystal orientation anisotropy of collisional ionization and propose a structure that can reduce on-resistance while maintaining excellent breakdown voltage.

[0074] 2. Method for Calculating Static Characteristics The method for calculating the static characteristics of a device that solves the above problems is shown below. (1) Characteristic On-Resistance Ron,sp The characteristic on-resistance Ron,sp is obtained by the following formula (1).

[0075] The definitions of the letters and symbols used in the formulas are as follows. The same definitions apply when the same letters and symbols appear in other formulas.

[0076] wn = width of n-type pillar, wp = width of p-type pillar, Nd = concentration of n-type impurities in n-type pillar, Na = concentration of p-type impurities in p-type pillar, dsj = depth of superjunction structure SJ, μ = mobility, pitch W = wn + wp. Note that Nd and Na may be the average impurity concentrations in the n-type and p-type pillars, respectively. The average impurity concentration may be obtained, for example, by creating impurity concentration profiles in the depth direction of the n-type and p-type pillars and averaging those profiles.

[0077] Furthermore, the calculation of Ron,sp assumes that the n-type pillar is doped with nitrogen, and takes into account the resulting incomplete ionization ration ξ and the np depletion layer width asj under zero bias. The depletion layer width asj and the incomplete ionization ration ξ are given by equations (2) and (3) below, respectively.

[0078]

[0079] (2) Withstand Voltage (VB) Figure 6 schematically shows the current path leading to dielectric breakdown in an asymmetric SJ structure. In Figure 6, the strength of the electric field strength is indicated by the shades of gray. The areas of relatively dark gray have a high electric field strength, and the areas of relatively light gray have a low electric field strength.

[0080] The blocking voltage (VB) is calculated from Poisson's equation. The electric field strength distribution in Figure 6 is the result of a simulation based on the x-component (εx) and y-component (εy) of the electric field strength calculated using equations (4) and (5) below.

[0081]

[0082] In the formula, Θ≡q(Na+Nd)(wn+wp) / (επ ２ )

[0083] Referring to Figure 6, the four vertices of the quadrilateral are defined as points A, B, C, and D. It is understood that strong electric fields (local maximum) are applied at point A near the upper end of the n-type pillar and at point D near the lower end of the p-type pillar. Therefore, possible current paths leading to dielectric breakdown include path BA from point B to point A, and path DC from point D to point C. In addition, a strong electric field (local maximum) is also applied at point O at the boundary between the n-type and p-type pillars. Therefore, path BOC from point B through point O to point C can also be considered a current path leading to dielectric breakdown.

[0084] The path BOC was calculated sequentially using Δx = Δy(εx / εy) as the starting point, with point O being the point of maximum electric field. The breakdown voltage VB is defined as the magnitude of the reverse bias at the moment when the ionization integral I equals 1 (One). The ionization integral I is given by equation (6) below.

[0085] When all of the drift region 8 shown in Figure 5 is a superjunction structure SJ, path BOC exhibits the largest ionization integral value. Therefore, among paths BA, DC, and BOC, path BOC is considered to preferentially cause dielectric breakdown.

[0086] 3. Detailed Description of Preferred Forms of Asymmetric SJ Structures (1) Optimal Characteristics of Symmetric SJ Structures Prior to a detailed description of asymmetric SJ structures, as a reference example, the optimal characteristics of symmetric SJ structures are derived and a benchmark is established. In symmetric SJ structures, the pillar width w, doping concentration N*d, and pillar depth d*sj are adjustable parameters.

[0087] In deriving the optimal properties of a symmetric SJ structure, Ron,sp is first calculated as a function of N*d, and d*sj is adjusted to maintain a predetermined VB under a fixed w. The minimum Ron,sp obtained in this process represents the optimal Ron,sp (equation (7) below) under a predetermined w and VB, i.e., the optimal conditions shown in equations (8) and (9) below. The units of Ron,sp, N*d, and d*sj are Ron,sp (mΩ・cm), respectively. ２ ), N*d(cm －３ ) and d*sj (μm). The above analysis may be valid in the range w = 0.5 μm to 10.0 μm.

[0088]

[0089]

[0090] (2) Performance of the asymmetric SJ structure Next, preferred forms of the asymmetric SJ structure were evaluated by modifying the preferred form of the symmetric SJ structure (reference example) described above. As provisional conditions for the symmetric SJ structure, a pillar width w = 3 μm and a withstand voltage VB = 2200 V were set.

[0091] Figure 7 shows the rate of change of withstand voltage VB with respect to the rate of change of np doping concentration (ΔNd, ΔNa) for a symmetric SJ structure. More specifically, the rate of change of withstand voltage VB is shown in grayscale as a color map against the rate of change of np doping concentration. In Figure 7, the white area represents the region where the set withstand voltage VB (2200V in this configuration) can be maintained.

[0092] In Figure 7, the coordinates of the star, indicated by the rate of change of n-type doping concentration ΔNd = 0% on the horizontal scale and the rate of change of p-type doping concentration ΔNa = 0% on the vertical scale, represent the conditions for optimal performance in a symmetric SJ structure. Even if ΔNd and ΔNa are changed from these star marks, if the resulting coordinates remain within the white area, the set withstand voltage of 2200V can be achieved. Furthermore, the contour lines extending along the vertical direction in Figure 7 represent the rate of change (%) from Ron,sp of the optimal performance of the symmetric SJ structure.

[0093] Figures 8 to 10 show a grayscale color map of the rate of change in pressure resistance VB from a symmetric SJ structure against the rate of change in np doping concentration. Δwn, shown at the top of each figure in Figures 8 to 10, represents the rate of change from the width of the n-type pillar in a symmetric SJ structure (= 3 μm). Figure 8 shows an asymmetric SJ structure with a narrower n-type pillar width than a symmetric SJ structure (Δwn = -15%), while Figures 9 and 10 show asymmetric SJ structures with a wider n-type pillar width than a symmetric SJ structure (Δwn = 21% and Δwn = 42%, respectively). Note that Figure 7 corresponds to a symmetric SJ structure, so Δwn = 0%.

[0094] In Figures 7 to 10, the pitch W = wn + wp = 6 μm is fixed, so as the width wn of the n-type pillar increases, the width wp of the p-type pillar decreases. In other words, in the asymmetric SJ structure of Figure 8, wn < wp, and in the asymmetric SJ structures of Figures 9 and 10, wn > wp.

[0095] In Figures 8 to 10, the white areas represent the regions where the set withstand voltage VB (2200V in this configuration) of the symmetric SJ structure can be maintained. The contour lines extending vertically in Figures 8 to 10 represent the percentage change (%) from the optimal characteristics of Ron,sp of the symmetric SJ structure. Furthermore, in Figures 7 to 10, the plots indicated by circles represent the conditions where the reduction in Ron,sp is greatest among the conditions where the rate of change of the set withstand voltage VB is approximately zero.

[0096] Referring to Figures 9 and 10, and comparing the coordinates of the circled plots with the contour lines, it can be seen that in both cases, Ron,sp is reduced compared to the optimal characteristic of the symmetric SJ structure. In Figure 9, at Δwn = 21%, Ron,sp is reduced by -6%, and in Figure 10, at Δwn = 42%, Ron,sp is reduced by approximately -8%. On the other hand, referring to Figure 8, at Δwn = -15%, Ron,sp increased by more than 4%. From these results, it was found that by making the width of the n-type pillar larger than the width of the p-type pillar, Ron,sp can be reduced while maintaining VB.

[0097] In this way, Figure 11 summarizes the results of extracting the condition that yielded the largest reduction in Ron and sp under multiple pitch W values ​​when the withstand voltage was set to 2200V.

[0098] The multiple plots in Figure 11 show the relationship between the rate of change of the n-type pillar (Δwn) and the characteristic on-resistance Ron,sp in superjunction structures (SJs) where W / 2 is 1.5 μm, 2 μm, 3 μm, and 4 μm, assuming that half of the pitch W = wn + wp is W = (wn + wp) / 2. In Figure 11, the plots corresponding to the intersections of the line representing the symmetric SJ structure extending along the vertical direction and each plot represent the optimal characteristic Ron,sp for the symmetric SJ structure. For the symmetric SJ structure, when W / 2 = 1.5 μm, Ron,sp = 0.26 mΩ·cm ２ Therefore, when W / 2 = 2 μm, Ron, sp = 0.32 mΩ·cm ２ Therefore, when W / 2 = 3 μm, Ron, sp = 0.44 mΩ·cm ２ Therefore, when W / 2 = 4 μm, Ron, sp = 0.56 mΩ·cm ２ That is the case.

[0099] Furthermore, the area to the left of the line of the symmetric SJ structure shows Ron,sp for the asymmetric SJ structure where Δwn < 0% and wn < wp. On the other hand, the area to the right of the line of the symmetric SJ structure shows Ron,sp for the asymmetric SJ structure where Δwn > 0% and wn > wp. From Figure 11, it can be seen that if Δwn = 60%, Ron,sp is sufficiently reduced in all W / 2. The condition that the width wn of the n-type pillar is 160% of that of the symmetric SJ structure and the width wp of the p-type pillar is 40%, that is, if the width of the n-type pillar is 4 times or more the width of the p-type pillar, Ron,sp can be sufficiently reduced. On the other hand, if the width wn of the n-type pillar is too wide, it may affect depletion inside the n-type pillar. Therefore, it is preferable that the width wn of the n-type pillar is about 12 times or less the width wp of the p-type pillar.

[0100] Figure 12 shows the donor concentration Nd and acceptor concentration Na in the condition that yielded the greatest reduction in Ron,sp under multiple pitch W / 2 conditions with a breakdown voltage of 2200V. Referring to Figure 12, it can be seen that at Δwn > 0% to the right of the straight line of the symmetric SJ structure, the white-filled donor concentration Nd is smaller than the black-filled acceptor concentration Na. In other words, for the greatest reduction in Ron,sp, it is preferable that Nd < Na.

[0101] Figure 13 shows the results of extracting the lowest Ron,sp depending on the width wn of the n-type pillar for each voltage VB. More specifically, for each of the voltage VBs of 1600V, 2200V, 3300V, 4400V, and 5500V, the results shown in Figure 11 were extracted within the range of -20% ≤ Δwn < 60%. From these results, the Ron,sp that could be reduced the most was plotted as a percentage of the Ron,sp of the symmetric SJ structure. Referring to Figure 13, it was found that for various voltages, the Ron,sp could be reduced by about 6% to 15% compared to the Ron,sp of the symmetric SJ structure.

[0102] 4. Physical Concept of Improved Characteristics Next, we will explain, for reference, that the above-mentioned reduction in on-resistance is due to the balance of various geometric parameters.

[0103] From the perspective of breakdown voltage VB, dielectric breakdown along path BOC is caused by the interaction between the electric field strength (εO) at point O and a high collision ionization coefficient along the x-axis direction (the direction crossing the boundary between the n-type pillar and the p-type pillar), via the crystal orientation anisotropy of collision ionization. Therefore, it is necessary to adjust the parameters to ensure breakdown voltage VB while preventing an increase in εO. As shown in equation (10) below, the peak of the electric field strength εO appears at x = wn / 2, and the second term of equation (10) becomes significantly smaller near the peak.

[0104] Under these conditions, the charge imbalance is very small (the charge balance is almost maintained), so wnNd ≈ wpNa. From this equation, there are two options for adjusting the parameters to maintain the desired withstand voltage VB. The first option (i) is to increase Nd and decrease wn, and the second option (ii) is to decrease Nd and increase wn.

[0105] Figure 14 shows the electric field along the path BOC at Δwn = 18%, 21%, and 54%. The pitch condition is W / 2 = 3.0 μm, as shown in Figure 11. As shown in Figure 15, as Δwn increases (Nd decreases based on Figure 12), εx decreases and εy increases, and as a whole, ε0 decreases slightly. This corresponds to case (ii) of option above.

[0106] Furthermore, we will explain the effects of changes in Δwn and Nd on Ron and sp. Changes in wn modulate Ron and sp through changes in conduction, while changes in Nd simultaneously modulate mobility μ, incomplete ionization rate ξ, and depletion layer width asj.

[0107] Figure 16 shows the influence of mobility μ, incomplete ionization rate ξ, and depletion layer width asj on the rate of change of Δwn and ΔNd. Figure 16 shows the results under the condition W / 2 = 2.0 μm at a breakdown voltage VB = 2200 V as shown in Figure 11. Referring to Figure 16, increasing ΔNd increases the denominator of equation (1) above, so Ron,sp decreases. However, at the same time, it causes an increase in the incomplete ionization rate ξ and a decrease in mobility μ. Furthermore, increasing ΔNd is accompanied by a narrowing of Δwn, so as a result Ron,sp becomes larger.

[0108] Therefore, as shown in Figure 17, a net reduction of Ron and sp is difficult to achieve with option (i). In contrast, with option (ii), as shown in Figure 17, Ron and sp can be reduced without impairing the breakdown voltage VB by combining an increase in the incomplete ionization rate ξ, suppression of the decrease in mobility μ, and widening of wn. In option (ii), the mobility μ is thought to increase due to the suppression of impurity scattering by the decrease in Nd (decrease in concentration), and the incomplete ionization rate ξ is suppressed because it approaches 100% at low concentrations. As a result, an asymmetric SJ structure superior to a symmetric SJ structure can be provided. In other words, by widening wn (decrease in Nd), a combined effect of mitigating current constriction, improving mobility, and suppressing incomplete ionization can be enjoyed.

[0109] Furthermore, the aforementioned charge balance CB may be maintained or disrupted by adjusting Nd and Na. When the charge balance CB is maintained, the charge balance CB may be within the range of 0.9 to 1.1 in the section from the top to the bottom in the depth direction of the n-type pillar and the p-type pillar. On the other hand, when the charge balance CB is disrupted, the charge balance CB may be less than 0.9 or greater than 1.1 in the section from the top to the bottom in the depth direction of the n-type pillar and the p-type pillar.

[0110] The first to eleventh embodiments of the second pillar region 12 are shown below with reference to Figures 18 to 28. Multiple second pillar regions 12 may have at least one of the features shown in the first to eleventh embodiments. Multiple second pillar regions 12 may have features that are a combination of multiple (two or more) features shown in the first to eleventh embodiments.

[0111] Figure 18 is a cross-sectional perspective view showing the second pillar region 12 according to the first embodiment. Referring to Figure 18, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the laminated portion 7 and is formed within the laminated portion 7 (drift region 8) at a distance from the upper end of the laminated portion 7. Specifically, the second upper end portion 12b of the second pillar region 12 is formed at a distance from the upper end (first main surface 3) of the laminated portion 7 toward the lower end and faces the first main surface 3 with a part of the laminated portion 7 (upper end portion) in between.

[0112] Figure 19 is a cross-sectional perspective view showing the second pillar region 12 according to the second embodiment. Referring to Figure 19, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the laminated portion 7 and is formed within the laminated portion 7 (drift region 8) at a distance from the lower end of the laminated portion 7. Specifically, the second lower end portion 12a of the second pillar region 12 is formed at a distance from the lower end (base layer 6) of the laminated portion 7 toward the upper end, and faces the base layer 6 with a part of the laminated portion 7 (lower end portion) in between.

[0113] Figure 20 is a cross-sectional perspective view showing the second pillar region 12 according to the third embodiment. Referring to Figure 20, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the laminated portion 7 and is formed within the laminated portion 7 (drift region 8) with a gap between it and both the lower and upper ends of the laminated portion 7. Specifically, the second upper end portion 12b of the second pillar region 12 is formed with a gap between it and the lower end of the laminated portion 7 (first main surface 3), and faces the first main surface 3 with a part of the laminated portion 7 (upper end portion) in between. On the other hand, the second lower end portion 12a of the second pillar region 12 is formed with a gap between it and the upper end of the laminated portion 7 (base layer 6), and faces the base layer 6 with a part of the laminated portion 7 (lower end portion) in between.

[0114] Figure 21 is a cross-sectional perspective view showing a second pillar region 12 according to the fourth embodiment. Referring to Figure 21, the multiple second pillar regions 12 each have a laminated structure in the thickness direction of the laminated portion 7 that includes a first region 18 and a second region 19. In this embodiment, the first region 18 and the second region 19 are spaced apart from each other in the thickness direction of the laminated portion 7.

[0115] The first region 18 and the second region 19 may each have a second width W2 set independently. For example, the second width W2 of the first region 18 may be greater than the W2 of the second region 19, or the second width W2 of the first region 18 may be smaller than the W2 of the second region 19. The second widths W2 of the first region 18 and the second region 19 may be equal to each other.

[0116] A portion of the laminated portion 7 (drift region 8) is interposed between the first region 18 and the second region 19. This portion of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located in the center of the thickness direction of the laminated portion 7, or it may be located on the upper or lower end side relative to the central position.

[0117] Figure 22 is a cross-sectional perspective view showing a second pillar region 12 according to the fifth embodiment. Referring to Figure 22, the multiple second pillar regions 12 each have a laminated structure including a first region 18 and a second region 19 in the thickness direction of the laminated portion 7. In this embodiment, the first region 18 and the second region 19 are connected to each other in the thickness direction of the laminated portion 7.

[0118] The first region 18 and the second region 19 may each have a second width W2 set independently. For example, the second width W2 of the first region 18 may be greater than the W2 of the second region 19, or the second width W2 of the first region 18 may be smaller than the W2 of the second region 19. The second widths W2 of the first region 18 and the second region 19 may be equal to each other.

[0119] The boundary portion 26 of the first region 18 and the second region 19 may be located in the center in the thickness direction of the laminated portion 7, or it may be located on the upper or lower end side with respect to the central position.

[0120] Figure 23 is a cross-sectional perspective view showing the second pillar region 12 according to the sixth embodiment. Figure 24 is a cross-sectional perspective view showing the second pillar region 12 according to the seventh embodiment. Referring to Figures 23 and 24, the second pillar region 12, which has a second upper end portion 12b at a position spaced apart from the upper end of the laminated portion 7, may have a laminated structure including the first region 18 and the second region 19.

[0121] Figure 25 is a cross-sectional perspective view showing the second pillar region 12 according to the eighth embodiment. Figure 26 is a cross-sectional perspective view showing the second pillar region 12 according to the ninth embodiment. Referring to Figures 25 and 26, the second pillar region 12, which has a second lower end portion 12a at a position spaced apart from the lower end of the laminated portion 7, may have a laminated structure including the first region 18 and the second region 19.

[0122] Figure 27 is a cross-sectional perspective view showing the second pillar region 12 according to the tenth embodiment. Figure 28 is a cross-sectional perspective view showing the second pillar region 12 according to the eleventh embodiment. Referring to Figures 27 and 28, the second pillar region 12, which has a second upper end portion 12b and a second lower end portion 12a, respectively, at positions spaced apart from the upper and lower ends of the laminated portion 7, may have a laminated structure including the first region 18 and the second region 19.

[0123] The following shows examples of the configuration of the device structure formed within the active region 10. Figure 29 is a plan view showing a key part of the active region 10. Figure 30 is a cross-sectional perspective view showing the gate structure 35 according to the first embodiment. In Figure 30, the second pillar region 12 according to the third embodiment is illustrated. Of course, in Figure 30, a configuration may be applied in which one or more of the second pillar regions 12 according to the basic embodiment and the first to eleventh embodiments are applied.

[0124] Referring to Figures 29 and 30, in this embodiment, the semiconductor device 1A includes an MIS structure 31 (Metal Insulator Semiconductor structure) as an example of a device structure formed in the active region 10. The MIS structure 31 may also be referred to as a "field-effect transistor structure".

[0125] The semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. In this configuration, the plurality of body regions 32 are arranged at intervals in the first direction X and each is formed in a strip shape extending in the second direction Y. That is, the plurality of body regions 32 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. Furthermore, the direction of extension of the plurality of body regions 32 coincides with the direction of extension of the plurality of second pillar regions 12.

[0126] Multiple body regions 32 are formed on the surface layer of the first main surface 3 so as to overlap with the second pillar regions 12 corresponding to the stacking direction. Specifically, the multiple body regions 32 overlap with the multiple second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0127] When multiple second pillar regions 12 are formed at intervals from the first main surface 3, multiple body regions 32 are formed in the region between the first main surface 3 and the second upper end portions 12b (see Figure 20) of the multiple second pillar regions 12. Preferably, the multiple body regions 32 are formed on the first main surface 3 side with respect to the intermediate portion of the thickness range of the laminated portion 7 and are exposed from the first main surface 3. Preferably, the multiple body regions 32 are connected to the corresponding second pillar regions 12 (second upper end portions 12b).

[0128] Each of the multiple body regions 32 is formed wider than the second pillar region 12 directly below it, and is formed with a gap between adjacent second pillar regions 12 and the second pillar region 12 directly below it. The multiple body regions 32 expose a portion of the first pillar region 13 from the area between adjacent second pillar regions 12 on the first main surface 3.

[0129] The multiple body regions 32 are, for example, 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0130] The p-type impurity concentrations in the multiple body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element in the body region 32 may be the same type as the trivalent element in the second pillar region 12, or it may be a different type. The trivalent element in the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0131] The semiconductor device 1A includes one or more n-type source regions 33 formed on the surface of each of the multiple body regions 32 in the active region 10. In this embodiment, multiple (two in this embodiment) source regions 33 are formed at intervals on the surface of each body region 32. The multiple source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the first pillar region 13 and the drift region 8 of the laminated portion 7. The multiple source regions 33 have a density of 1 × 10⁻¹⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0132] The multiple source regions 33 may each extend in a strip-like shape along the extending direction of the corresponding body region 32. Of course, the multiple source regions 33 may be formed at intervals along the extending direction of the corresponding body region 32. The multiple source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and at intervals from the periphery of the corresponding body region 32 toward the inward side. The multiple source regions 33, together with the multiple first pillar regions 13, define channels (current paths) along the first main surface 3 at the periphery of the body region 32.

[0133] The semiconductor device 1A includes one or more p-type contact regions 34 formed on the surface of each of the multiple body regions 32 in the active region 10. The contact regions 34 may also be referred to as "back gate regions". In this configuration, one contact region 34 is formed in the region between multiple adjacent source regions 33 on the surface of each body region 32.

[0134] Multiple contact regions 34 have a higher p-type impurity concentration (peak value) than the p-type impurity concentration (peak value) of multiple body regions 32. The p-type impurity concentration (peak value) of multiple contact regions 34 is higher than the p-type impurity concentration (peak value) of multiple second pillar regions 12. Multiple contact regions 34 have a p-type impurity concentration of 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0135] The multiple contact regions 34 may each extend in a strip-like manner along the extending direction of the corresponding body region 32. Of course, the multiple contact regions 34 may be formed at intervals along the extending direction of the corresponding body region 32. The multiple contact regions 34 may be formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and at intervals from the peripheral edge of the corresponding body region 32 toward the inward side.

[0136] The semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures". The plurality of gate structures 35 are spaced apart on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction. The plurality of gate structures 35 are assigned a gate potential as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of channels (current paths) within the body region 32 in response to the gate potential.

[0137] In this configuration, the multiple gate structures 35 are arranged at intervals in the first direction X and each is formed in a strip shape extending in the second direction Y. In other words, the multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. The direction of extension of the multiple gate structures 35 coincides with the direction of extension of the multiple second pillar regions 12.

[0138] The multiple gate structures 35 are positioned offset from the multiple second pillar regions 12 toward the multiple first pillar regions 13, and overlap the multiple first pillar regions 13 in a one-to-one correspondence in the stacking direction. In this configuration, the multiple gate structures 35 are each positioned to span two adjacent body regions 32, and each covers the multiple source regions 33 located within one and the other body region 32, respectively.

[0139] Each of the multiple gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may contain a silicon oxide film. The gate electrode 37 may contain conductive polysilicon.

[0140] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second pillar region 12 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second pillar region 12 in the stacking direction.

[0141] The configuration of the outer peripheral region 11 is shown below. Figure 31 is a cross-sectional view showing a key part of the outer peripheral region 11. The semiconductor device 1A includes at least one (preferably two to twenty) p-type field regions 38 formed on the surface layer of the first main surface 3 in the outer peripheral region 11.

[0142] The number of field regions 38 is typically between four and eight. The field regions 38 are formed in an electrically floating state and relax the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, and p-type impurity concentration of the field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relaxed.

[0143] Multiple field regions 38 are formed at intervals in the region between the periphery of the chip 2 and the active region 10. In a plan view, the multiple field regions 38 are formed in a strip shape extending along the active region 10. Each of the multiple field regions 38 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, in a plan view, the multiple field regions 38 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active region 10 (i.e., the multiple second pillar regions 12).

[0144] Multiple field regions 38 are formed within the laminated portion 7 (drift region 8) at intervals from the lower end of the laminated portion 7 toward the first main surface 3, and each field region 38 forms a pn joint with the drift region 8. Preferably, the multiple field regions 38 have a bottom portion located toward the first main surface 3 with respect to the middle portion of the thickness range of the laminated portion 7. In this embodiment, the multiple field regions 38 are formed at intervals from the multiple second pillar regions 12 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the multiple second pillar regions 12 in the lamination direction.

[0145] The bottoms of the multiple field regions 38 may be located on the first main surface 3 side of the depth position of the second upper end portion 12b of the second pillar region 12. Of course, the bottoms of the multiple field regions 38 may also be located on the second lower end portion 12a side of the second pillar region 12, rather than on the depth position of the second upper end portion 12b of the second pillar region 12. In this case, it is preferable that the bottoms of the multiple field regions 38 are located on the first main surface 3 side of the intermediate portion of the thickness range of the second pillar region 12.

[0146] The multiple field regions 38 may have a thickness approximately equal to the thickness of the multiple body regions 32. In this case, the multiple field regions 38 can be formed simultaneously with the multiple body regions 32. Of course, the thickness of the multiple field regions 38 may be greater than the thickness of the multiple body regions 32. Also, the thickness of the multiple field regions 38 may be less than the thickness of the multiple body regions 32.

[0147] Multiple field regions 38 are 1 × 10 １５cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0148] The p-type impurity concentration in the field region 38 may be approximately equal to the p-type impurity concentration in the body region 32. Of course, the p-type impurity concentrations in multiple field regions 38 may also be high in the multiple body regions 32. Furthermore, the p-type impurity concentrations in multiple field regions 38 may be lower than the p-type impurity concentrations in multiple body regions 32.

[0149] It is preferable that the p-type impurity concentrations in multiple field regions 38 are adjusted by at least one trivalent element. The trivalent element in the field region 38 may be the same type as the trivalent element in the second pillar region 12, or it may be a different type. The trivalent element in the field region 38 may be at least one of boron, aluminum, gallium, and indium.

[0150] It is preferable that the multiple field regions 38 have widths different from the second width W2 of the second pillar region 12. In other words, it is preferable that the electric field relaxation effect of the multiple field regions 38 be adjusted independently of the multiple second pillar regions 12.

[0151] It is particularly preferable that the widths of the multiple field regions 38 are greater than the second width W2 of the second pillar region 12. Of course, the widths of the multiple field regions 38 may also be smaller than the second width W2. Furthermore, the widths of the multiple field regions 38 may also be approximately equal to the second width W2.

[0152] It is preferable that the multiple field regions 38 are formed with a pitch different from the second pitch P2 of the second pillar region 12. It is particularly preferable that the pitch of the multiple field regions 38 is greater than the second pitch P2. Of course, the pitch of the multiple field regions 38 may be smaller than the second pitch P2. Also, the pitch of the multiple field regions 38 may be approximately equal to the second pitch P2.

[0153] The semiconductor device 1A includes an interlayer insulating film 40 that covers the first main surface 3. The interlayer insulating film 40 may also be referred to as an "insulating film," "interlayer film," or "intermediate insulating film." In this embodiment, the interlayer insulating film 40 has a laminated structure including a first insulating film 41 and a second insulating film 42 (see Figure 31). The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 includes a silicon oxide film made of the oxide of the chip 2 (laminated portion 7).

[0154] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11. In this embodiment, the first insulating film 41 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the first insulating film 41 may be formed with a gap inward from the periphery of the first main surface 3, and the laminated portion 7 may be exposed from the periphery of the first main surface 3.

[0155] The second insulating film 42 is laminated on the first insulating film 41. The second insulating film 42 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably contains a silicon oxide film. The second insulating film 42 covers the first main surface 3 with the first insulating film 41 sandwiched between it in the active region 10 and the peripheral region 11.

[0156] The second insulating film 42 covers a plurality of gate structures 35 in the active region 10. The second insulating film 42 covers a plurality of field regions 38 in the outer peripheral region 11, sandwiching the first insulating film 41. In this embodiment, the second insulating film 42 is connected to the periphery of the first main surface 3. Of course, the second insulating film 42 may be formed with a gap inward from the periphery of the first main surface 3, exposing the periphery of the first main surface 3 together with the first insulating film 41.

[0157] The semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37), and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in the region between adjacent gate structures 35, exposing a plurality of source regions 33 and a plurality of contact regions 34.

[0158] Referring to Figure 1, the semiconductor device 1A includes a gate pad 45 disposed on an interlayer insulating film 40. The gate pad 45 is an electrode to which a gate potential is applied from the outside. The gate pad 45 may also be called a "gate pad electrode," "first pad electrode," etc. The gate pad 45 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side.

[0159] In this embodiment, the gate pad 45 is positioned on the portion of the interlayer insulating film 40 that covers the active region 10. The gate pad 45 may be positioned at a distance from the outer peripheral region 11 toward the active region 10. In this embodiment, the gate pad 45 is positioned on the periphery of the active region 10 in a plan view.

[0160] Figure 1 shows an example in which the gate pad 45 is positioned in a region along the center of the second side surface 5B at the periphery of the active region 10. Of course, the gate pad 45 may also be positioned in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be positioned at any corner of the active region 10 in a plan view. Furthermore, the gate pad 45 may also be positioned in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a rectangular shape in a plan view.

[0161] The semiconductor device 1A includes at least one (or more in this embodiment) gate wiring 46 drawn from a gate pad 45 onto an interlayer insulating film 40. The gate wiring 46 may be referred to as "wiring," "wiring electrode," etc. The plurality of gate wirings 46 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side. In this embodiment, the plurality of gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0162] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically perpendicular to) a portion (specifically one end) of the plurality of gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to one end of the plurality of gate structures 35.

[0163] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically perpendicular to) a portion (specifically the other end) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35.

[0164] The semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and gate wiring 46. The source pad 47 is an electrode to which a source potential is applied from the outside. The source pad 47 may also be called a "source pad electrode," "second pad electrode," etc. The source pad 47 may have a laminated structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side.

[0165] The source pad 47 is positioned on the portion of the interlayer insulating film 40 that covers the active region 10. The source pad 47 may be positioned at a distance from the outer peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape with a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may be formed in a rectangular shape in a plan view.

[0166] The source pad 47 penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to a plurality of body regions 32, a plurality of source regions 33, and a plurality of contact regions 34. In other words, the source pad 47 is electrically connected to a plurality of second pillar regions 12 via a plurality of body regions 32.

[0167] Referring to Figure 2, the semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be called a "drain pad electrode," "third pad electrode," etc. The drain pad 48 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the drain pad 48 is electrically connected to the laminated portion 7 (drift region 8 and a plurality of first pillar regions 13) via the base layer 6.

[0168] The drain pad 48 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Alternatively, the drain pad 48 may cover the second main surface 4 with a gap inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0169] The breakdown voltage that can be applied between the source pad 47 and the drain pad 48 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within any one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0170] Figure 32 is a schematic diagram showing a wafer 50 used in the manufacture of a semiconductor device 1A. The wafer 50 is the substrate for the base layer 6 and contains a SiC single crystal. The wafer 50 is formed in the shape of a flat disc. Of course, the wafer 50 may also be formed in the shape of a flat rectangular parallelepiped. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0171] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of a SiC single crystal. The first wafer main surface 51 is formed by the silicon plane of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon plane of the SiC single crystal. The wafer 50 (first wafer main surface 51 and second wafer main surface 52) has the aforementioned off-direction Doff and off-angle θoff.

[0172] The wafer 50 has markings 54 on the wafer side surface 53 that indicate the crystal orientation of the SiC single crystal. The markings 54 may include either an orientation flat or an orientation notch, or both. An orientation flat consists of a notch that is cut out in a straight line in a plan view. An orientation notch consists of a notch that is cut out in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 51 in a plan view.

[0173] The marker 54 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 54 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. In Figure 32, the orientation flat extending in the m-axis direction is shown in plan view.

[0174] For example, the wafer 50 has multiple device regions 55 and multiple cutting lines 56 marked by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1A. The multiple device regions 55 are each set in a rectangular shape when viewed from above.

[0175] In this configuration, the multiple device regions 55 are arranged in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 55 are each spaced inward from the periphery of the first wafer main surface 51 in a plan view. The multiple cutting lines 56 are arranged in a grid pattern extending along the first direction X and the second direction Y to demarcate the multiple device regions 55.

[0176] Figure 33 is a flowchart showing an example of a manufacturing method for semiconductor device 1A. Figures 34A to 34C are cross-sectional perspective views showing an example of a manufacturing method for semiconductor device 1A. Figures 34A to 34C show a cross-sectional perspective view of a part of the active region 10 of one device region 55.

[0177] First, referring to Figure 34A, the wafer preparation process described above is carried out (step S1 in Figure 33).

[0178] Next, referring to Figure 34B, the process of forming the n-type laminated portion 7 is carried out (step S2 in Figure 33). The laminated portion 7 is formed by epitaxial growth, starting from the first wafer main surface 51 (wafer 50), while adding n-type impurity ions. The impurity ions used are at least one pentavalent element, preferably nitrogen. At this point, the entire laminated portion 7 (active region 10 and outer peripheral region 11) is formed as a drift region 8.

[0179] Next, referring to Figure 34C, a process for forming a mask 62 having a predetermined pattern is carried out (step SS in Figure 33). The mask 62 is preferably an organic mask (resist mask). The mask 62 is placed on the first main surface 3 of the laminated portion 7 and has a plurality of openings 63 that expose areas in the laminated portion 7 where a plurality of second pillar regions 12 are to be formed. The plurality of openings 63 are formed at intervals in the first direction X and each is divided into a strip shape extending in the second direction Y.

[0180] Next, referring to Figure 34C, a process for forming multiple second pillar regions 12 is carried out (step S4 in Figure 33). The process for forming multiple second pillar regions 12 includes an ion implantation process of a trivalent element (p-type impurity) into the laminated portion 7. The impurity ions used are at least one trivalent element, preferably aluminum. As the ion implantation process, for example, a random implantation method or a channeling implantation method can be applied. As a result, second pillar regions 12 are formed in the drift region 8 that was exposed from the opening 63. Furthermore, by forming multiple second pillar regions 12, the portion of the drift region 8 sandwiched between the multiple second pillar regions 12 is formed as multiple first pillar regions 13.

[0181] Subsequently, the MIS structure 31, multiple field regions 38, interlayer insulating film 40, gate pad 45, gate wiring 46, source pad 47, drain pad 48, etc. are formed (step S5 in Figure 33). Then, the wafer 50 is cut along multiple planned cutting lines 56. In this way, multiple semiconductor devices 1A are manufactured from a single wafer 50.

[0182] Figure 35 is a plan view showing a semiconductor device 1B according to the second embodiment. Figure 36 is a cross-sectional view along the line XXXVI-XXXVI shown in Figure 35. Figure 37 is a plan view showing an example of the layout of the chip 2. Figure 38 is a perspective view showing an example of the layout of the chip 2.

[0183] Referring to Figures 35 to 38, semiconductor device 1B includes a chip 2, a base layer 6, a stacked portion 7, an active region 10, and an outer peripheral region 11, similar to semiconductor device 1A.

[0184] In this embodiment, the semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3. The active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.

[0185] The active surface 71 may be referred to as the "first surface portion," the outer peripheral surface 72 as the "second surface portion," the first to fourth connecting surfaces 73A to 73D as the "connecting surface portion," and the active base 74 as the "mesa portion." The active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D (i.e., the active base 74) may be considered components of the chip 2 (first main surface 3).

[0186] The active surface 71 is formed in the active region 10. That is, the active surface 71 is formed with a gap inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 71 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 71 is formed by a c-plane (Si plane). In this embodiment, the active surface 71 is formed in a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0187] The outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71. The outer peripheral surface 72 is recessed in the thickness direction of the tip 2 (towards the second main surface 4) relative to the active surface 71. In a plan view, the outer peripheral surface 72 extends in a band shape along the active surface 71 and is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 71.

[0188] The outer circumferential surface 72 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 71. In this embodiment, the outer circumferential surface 72 is formed by a c-plane (Si plane). The outer circumferential surface 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer circumferential surface 72 has an outer circumferential depth DO.

[0189] The outer perimeter depth DO may be 0.1 μm or more and 2 μm or less. The outer perimeter depth DO may have a value that falls within any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. It is preferable that the outer perimeter depth DO is 0.1 μm or more and 1.5 μm or less.

[0190] The first to fourth connecting surfaces 73A to 73D extend in the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72. The first connecting surface 73A is located on the first side surface 5A side, the second connecting surface 73B is located on the second side surface 5B side, the third connecting surface 73C is located on the third side surface 5C side, and the fourth connecting surface 73D is located on the fourth side surface 5D side. The first connecting surface 73A and the third connecting surface 73C extend in the first direction X and face the second direction Y. The second connecting surface 73B and the fourth connecting surface 73D extend in the second direction Y and face the first direction X.

[0191] The first to fourth connecting surfaces 73A to 73D may extend substantially vertically between the active surface 71 and the outer peripheral surface 72 so as to define the rectangular prism-shaped active plateau 74. The first to fourth connecting surfaces 73A to 73D may also be inclined diagonally downward from the active surface 71 toward the outer peripheral surface 72 so as to define the pyramidal-shaped active plateau 74. In this way, the active plateau 74 is defined in a protruding manner in the stacked portion 7 on the first main surface 3.

[0192] The semiconductor device 1B includes a plurality of p-type second pillar regions 12 formed in the laminated portion 7 in the active region 10. The plurality of second pillar regions 12 are formed in the same layout as in the semiconductor device 1A.

[0193] The multiple second pillar regions 12 may have at least one feature from the multiple features shown in the basic form and the first to eleventh embodiment examples. The multiple second pillar regions 12 may have features that are a combination of the multiple (two or more) features shown in the basic form and the first to eleventh embodiment examples.

[0194] Figure 39 is a plan view showing a key part of the active region 10. Figure 40 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment. Referring to Figures 39 and 40, the semiconductor device 1B includes an MIS structure 31 formed in the active region 10. The following components will be described as elements of the semiconductor device 1B, but they are also elements of the MIS structure 31.

[0195] The semiconductor device 1B includes a p-shaped body region 32 formed on the surface layer of the first main surface 3 (active surface 71). In this embodiment, the body region 32 is formed in layers extending along the active surface 71. The body region 32 may be formed over the entire area of ​​the active surface 71 and may be exposed from the first to fourth connecting surfaces 73A to 73D.

[0196] The body region 32 is formed with a gap from the lower end of the laminated portion 7 toward the active surface 71 and overlaps with a plurality of second pillar regions 12 in the laminated direction. Preferably, the body region 32 overlaps with all of the second pillar regions 12 in the laminated direction. Preferably, the body region 32 is formed with a gap from the depth position of the outer peripheral surface 72 toward the active surface 71 and is exposed from the first main surface 3.

[0197] When multiple second pillar regions 12 are formed at intervals from the first main surface 3, the body region 32 is formed in the region between the active surface 71 and the second upper end portions 12b (see Figure 20) of the multiple second pillar regions 12. Preferably, the body region 32 is connected to the multiple second pillar regions 12 (second upper end portions 12b).

[0198] The body region 32 is 1 x 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0199] The p-type impurity concentration in the body region 32 is preferably adjusted by at least one trivalent element. The trivalent element in the body region 32 may be the same as the trivalent element in the second pillar region 12, or it may be a different trivalent element from the trivalent element in the second pillar region 12. The trivalent element in the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0200] The semiconductor device 1B includes a plurality of trench electrode type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10. The gate structures 35 may also be referred to as "trench gate structures". A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of channels (current paths) within the body region 32 in response to the gate potential.

[0201] The multiple gate structures 35 are arranged in the active region 10 at intervals extending inward from the periphery (first to fourth connecting surfaces 73A to 73D) of the active surface 71. In this embodiment, the multiple gate structures 35 are arranged in a stripe-like pattern extending in the direction of extension of the multiple second pillar regions 12. Specifically, in this embodiment, the multiple gate structures 35 are arranged at intervals in the first direction X and each is formed in a strip-like pattern extending in the second direction Y.

[0202] In other words, the multiple gate structures 35 are arranged at intervals in the a-axis direction of the SiC single crystal and extend in the m-axis direction of the SiC single crystal. The extension direction of the multiple gate structures 35 coincides with the extension direction of the multiple second pillar regions 12.

[0203] In this configuration, the multiple gate structures 35 are positioned offset from the multiple second pillar regions 12 toward the multiple first pillar regions 13. Specifically, the multiple gate structures 35 penetrate the body region 32 with a gap between them from the multiple second pillar regions 12 and are positioned within the multiple first pillar regions 13 in a one-to-one correspondence. In other words, the multiple gate structures 35 face the multiple second pillar regions 12 in the horizontal direction.

[0204] The multiple gate structures 35 are formed at intervals from the lower ends of the multiple first pillar regions 13 toward the active surface 71, and face the multiple base layers 6 with a portion of the multiple first pillar regions 13 in between. Preferably, the multiple gate structures 35 are formed at intervals from the middle of the thickness range of the multiple second pillar regions 12 toward the active surface 71. Of course, the multiple gate structures 35 may also be formed at depth positions that cross the middle of the thickness range of the multiple second pillar regions 12.

[0205] Each gate structure 35 has a trench width WT in the first direction X and a trench depth DT in the vertical direction Z. The trench width WT is less than the second pitch P2. The trench depth DT is less than the second thickness T2 of the second pillar region 12. It is preferable that the trench depth DT is approximately equal to the outer circumference depth DO mentioned above. Of course, the trench depth DT may be greater than or less than the outer circumference depth DO.

[0206] The trench width WT may be 0.1 μm or more and 5 μm or less. The trench width WT may have a value that falls within any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0207] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value that falls within any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. It is preferable that the trench depth DT is 0.1 μm or more and 1.5 μm or less.

[0208] Each gate structure 35 includes a trench 75, an insulating film 76, and an embedded electrode 77. The trench 75 is formed on the active surface 71 and partitions the wall surface of the gate structure 35. The insulating film 76 covers the wall surface of the trench 75. The insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0209] In this embodiment, the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of the oxide of the chip 2. The embedded electrode 77 is embedded in the trench 75 with the insulating film 76 in between, and faces the channel with the insulating film 76 in between. The embedded electrode 77 may contain p-type or n-type conductive polysilicon.

[0210] The semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in the surface layer of the first main surface 3 (active surface 71). The plurality of source regions 33 are formed in the surface layer of the body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than that of the first pillar region 13 and drift region 8 of the laminated portion 7. The plurality of source regions 33 have a density of 1 × 10⁻¹⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following n-type impurity concentrations may be present as peak values.

[0211] The multiple source regions 33 extend in a strip-like manner along the corresponding gate structure 35 in a plan view. The multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the first pillar region 13 in the stacking direction, with a portion of the body region 32 in between. Together with the multiple first pillar regions 13 located directly below them, the multiple source regions 33 define channels (current paths) that extend along the wall surface of the corresponding gate structure 35.

[0212] Multiple source regions 33 may face the second pillar region 12 with a portion of the body region 32 in between in the stacking direction. Of course, multiple source regions 33 may be formed with a gap between them and the second pillar region 12 on the first pillar region 13 side (gate structure 35 side) so as not to face the second pillar region 12 in the stacking direction.

[0213] The semiconductor device 1B includes a plurality of contact regions 34 formed in the region between a plurality of gate structures 35 on the surface layer of the first main surface 3 (active surface 71). The plurality of contact regions 34 are formed on the surface layer of the body region 32.

[0214] Multiple contact regions 34 have a higher p-type impurity concentration (peak value) than the p-type impurity concentration (peak value) of multiple body regions 32. The p-type impurity concentration (peak value) of multiple contact regions 34 is higher than the p-type impurity concentration (peak value) of multiple second pillar regions 12. Multiple contact regions 34 have a p-type impurity concentration of 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following p-type impurity concentrations may be present as peak values.

[0215] Multiple contact regions 34 are interposed in the regions between multiple adjacent source regions 33 and extend in a strip shape along multiple gate structures 35. Multiple contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71 and face multiple second pillar regions 12 in the stacking direction, with a portion of the body region 32 in between.

[0216] Multiple contact regions 34 may face the first pillar region 13 with a portion of the body region 32 in between in the stacking direction. Of course, multiple contact regions 34 may be formed with a gap between them and the second pillar region 12 so as not to face the first pillar region 13 in the stacking direction.

[0217] The configuration of the outer peripheral region 11 is shown below. Figure 41 is a cross-sectional view showing a key part of the outer peripheral region 11. Referring to Figure 41, the semiconductor device 1B includes a p-type well region 78 formed on the surface layer of the outer peripheral surface 72. In a plan view, the well region 78 is formed with a gap from the periphery (first to fourth side surfaces 5A to 5D) of the outer peripheral surface 72 toward the active surface 71, and extends in a band shape along the active surface 71.

[0218] In this configuration, the well region 78 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 71 in a plan view. The well region 78 is drawn out from the surface layer of the outer peripheral surface 72 toward the first to fourth connecting surfaces 73A to 73D and extends along the surface layer of the first to fourth connecting surfaces 73A to 73D. The well region 78 is electrically connected to the body region 32 at the surface layer of the active surface 71. The well region 78 is formed with a gap from the lower end of the laminated portion 7 toward the outer peripheral surface 72 and faces the base layer 6 with a part of the drift region 8 in between.

[0219] The bottom of the well region 78 is located on the lower end side of the laminated portion 7, relative to the bottom wall of the gate structure 35. Preferably, the bottom of the well region 78 is located on the outer peripheral surface 72 side with respect to the second lower end portion 12a of the plurality of second pillar regions 12. Particularly preferable is that the bottom of the well region 78 is located on the outer peripheral surface 72 side with respect to the intermediate portion of the thickness range of the plurality of second pillar regions 12.

[0220] The well area 78 is 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following p-type impurity concentrations may be present as peak values.

[0221] The well region 78 has a lower p-type impurity concentration than the contact region 34. The p-type impurity concentration in the well region 78 is higher than the p-type impurity concentration in the body region 32. Of course, the p-type impurity concentration in the well region 78 may be lower than that in the body region 32. The well region 78 forms a pn junction with the drift region 8.

[0222] The p-type impurity concentration in the well region 78 is preferably adjusted by at least one trivalent element. The trivalent element in the well region 78 may be the same as the trivalent element in the second pillar region 12, or it may be a different trivalent element from the trivalent element in the second pillar region 12. The trivalent element in the well region 78 may be at least one of boron, aluminum, gallium, and indium.

[0223] The semiconductor device 1B includes at least one (preferably two to twenty) p-type field regions 38 formed on the surface layer of the outer peripheral surface 72 in the outer peripheral region 11. The multiple field regions 38 are formed on the surface layer of the outer peripheral surface 72 in the same manner as in the case of semiconductor device 1A.

[0224] In this configuration, the multiple field regions 38 are arranged with a gap between them and the periphery of the active surface 71 (first to fourth connecting surfaces 73A to 73D) and the periphery of the tip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 38 are arranged with a gap between them and the periphery of the outer surface 72 from the well region 78.

[0225] The multiple field regions 38 extend in a band shape along the active surface 71 in a plan view and are formed in an annular shape (specifically, a square annular shape) surrounding the active surface 71. The multiple field regions 38 are formed at intervals from the bottom of the laminated portion 7 (drift region 8) toward the outer peripheral surface 72, and face the base layer 6 with a portion of the drift region 8 in between. The multiple field regions 38 are located on the lower end side of the drift region 8, below the bottom of the gate structure 35.

[0226] The semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3. The interlayer insulating film 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. In this embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D. The first insulating film 41 is connected to the insulating film 76 on the active surface 71, exposing the embedded electrode 77.

[0227] The first insulating film 41 covers the well region 78 and a plurality of field regions 38 on the outer peripheral surface 72. In this embodiment, the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 41 may be formed with a gap inward from the periphery of the outer peripheral surface 72, and the second layer 9 may be exposed from the periphery of the outer peripheral surface 72. The first insulating film 41 covers the well region 78 on the first to fourth connecting surfaces 73A to 73D.

[0228] In this embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D, sandwiching the first insulating film 41. The second insulating film 42 covers a plurality of gate structures 35 in the active region 10. The second insulating film 42 covers a plurality of field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41. In this embodiment, the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 42 may be formed with a gap inward from the periphery of the outer peripheral surface 72, and the laminated portion 7 may be exposed from the periphery of the outer peripheral surface 72 together with the first insulating film 41.

[0229] The semiconductor device 1B includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (embedded electrodes 77), and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in the region between adjacent gate structures 35, exposing a plurality of source regions 33 and a plurality of contact regions 34.

[0230] The semiconductor device 1B includes a sidewall structure 79 disposed within the interlayer insulating film 40 so as to cover at least one of the first to fourth connecting surfaces 73A to 73D. The sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42. The sidewall structure 79 mitigates the step formed between the active surface 71 and the outer peripheral surface 72.

[0231] The sidewall structure 79 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed in an annular shape (specifically, a rectangular annular shape) extending along the first to fourth connecting surfaces 73A to 73D so as to surround the active surface 71 in a plan view.

[0232] The sidewall structure 79 may have a portion that extends in a film-like manner along the outer peripheral surface 72, and a portion that extends in a film-like manner along the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed with a gap from the innermost field region 38 toward the active surface 71, and faces the well region 78 across the first insulating film 41 in the horizontal and stacking directions. The sidewall structure 79 may also face the body region 32 across the first insulating film 41.

[0233] The semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48, similar to the semiconductor device 1A. The drain pad 48 is formed in the same manner as in the first embodiment.

[0234] In this embodiment, the gate pad 45 is positioned on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The gate pad 45 is positioned in a region close to the center of one side of the active surface 71 (the second connecting surface 73B in this embodiment) in a plan view. Of course, the gate pad 45 may also be positioned at the corners or the center of the active surface 71 in a plan view.

[0235] In this configuration, the multiple gate wirings 46 are arranged on the active surface 71 at a distance from the outer surface 72 in a plan view. The multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0236] The first gate wiring 46A is drawn out from the gate pad 45 toward the first connection surface 73A and extends in a line along the periphery of the active surface 71 so as to intersect (specifically perpendicular to) a portion (specifically one end) of the plurality of gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to one end of the plurality of gate structures 35 (embedded electrodes 77).

[0237] The second gate wiring 46B is drawn out from the gate pad 45 toward the third connection surface 73C and extends in a line along the periphery of the active surface 71 so as to intersect (specifically perpendicular to) a portion (specifically the other end) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 through multiple contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35 (embedded electrodes 77).

[0238] In this embodiment, the source pad 47 is positioned on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The source pad 47 penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to the body region 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the plurality of second pillar regions 12 via the body region 32.

[0239] Figure 42 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. In the first embodiment described above, the multiple gate structures 35 were arranged offset from the multiple second pillar regions 12 toward the multiple first pillar regions 13. In contrast, referring to Figure 42, the multiple gate structures 35 according to the second embodiment are arranged so as to overlap the multiple second pillar regions 12 in the stacking direction. The multiple gate structures 35 overlap the multiple second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0240] Each of the multiple gate structures 35 has a bottom wall connected to the corresponding second pillar region 12. Specifically, each of the multiple gate structures 35 is formed to be wider than the corresponding second pillar region 12 and has a bottom wall connected to the corresponding second pillar region 12, and side walls connected to the corresponding first pillar region 13.

[0241] In other words, the embedded electrode 77 faces the corresponding second pillar region 12 across the insulating film 76 in the stacking direction, and faces the corresponding first pillar region 13 across the insulating film 76 in the horizontal direction. The aforementioned multiple source regions 33 and multiple contact regions 34 each face the corresponding first pillar region 13 across a part of the body region 32 in the stacking direction.

[0242] Figure 43 is a cross-sectional perspective view showing a gate structure 35 according to the third embodiment. Referring to Figure 43, each of the multiple gate structures 35 according to the third embodiment has a configuration that contributes to narrowing the pitch. The multiple gate structures 35 according to the third embodiment are particularly effective in achieving a narrow pitch in the second pillar region 12. Figure 43 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the third embodiment, but the configuration of the gate structure 35 according to the third embodiment is also applicable to the configuration of the gate structure 35 according to the second embodiment.

[0243] The multiple gate structures 35 each include a trench 75, an insulating film 76, an embedded electrode 77, and an embedded insulator 80. The trench 75 has the same configuration as in the first embodiment. In this embodiment, the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) towards the bottom wall of the trench 75, and the surface layer of the first main surface 3 (active surface 71) is exposed at the opening end of the trench 75. Preferably, the upper end of the insulating film 76 is located on the side of the first main surface 3 relative to the middle of the depth range of the trench 75.

[0244] In this configuration, the embedded electrode 77 is embedded in the trench 75 with a gap between the first main surface 3 (active surface 71) and the bottom wall side of the trench 75, defining an open recess that is recessed toward the bottom wall of the trench 75 at the open end of the trench 75. The embedded electrode 77 exposes the surface layer of the first main surface 3 (active surface 71) and the upper end of the insulating film 76 at the open end of the trench 75. Preferably, the upper end of the embedded electrode 77 is located on the first main surface 3 side with respect to the middle of the depth range of the trench 75.

[0245] The embedded insulator 80 is embedded in the trench 75 (opening recess) such that its first main surface 3 (active surface 71) is exposed, and covers the insulating film 76 and the embedded electrode 77 within the trench 75. The embedded insulator 80 is embedded in the trench 75 with a gap between the first main surface 3 (active surface 71) and the embedded electrode 77, and the surface layer of the first main surface 3 (active surface 71) is exposed at the opening end of the trench 75.

[0246] The upper end of the buried insulator 80 is preferably located on the first main surface 3 side with respect to the middle of the depth range of the trench 75. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the buried insulator 80 includes a silicon oxide film.

[0247] In this configuration, the aforementioned multiple source regions 33 are each formed in the regions between adjacent gate structures 35 on the surface of the first main surface 3 (active surface 71). The multiple source regions 33 are arranged at intervals along the multiple gate structures 35 so as to connect to the multiple gate structures 35 located on both sides.

[0248] Specifically, the multiple source regions 33 arranged along one side wall of the gate structure 35 are in a one-to-one correspondence with the multiple source regions 33 arranged along the other side wall of the gate structure 35. In other words, the multiple source regions 33 are arranged in a matrix in a plan view.

[0249] Of course, the multiple source regions 33 on one side may face each other in a one-to-one correspondence with the region between the multiple source regions 33 on the other side. In other words, the multiple source regions 33 may be arranged in a staggered pattern in a plan view. The multiple source regions 33 have portions exposed from the side walls of the trench 75 at the opening end of the trench 75 and face the embedded electrode 77 and the embedded insulator 80 across the insulating film 76.

[0250] In this configuration, the aforementioned multiple contact regions 34 are each formed in the regions between adjacent gate structures 35 on the surface of the first main surface 3 (active surface 71). The multiple contact regions 34 are spaced apart along the multiple gate structures 35 so as to connect to the multiple gate structures 35 located on both sides.

[0251] Specifically, the multiple contact regions 34 are arranged alternately with the multiple source regions 33 along the multiple gate structures 35. More specifically, the multiple contact regions 34 arranged along one side wall of the gate structure 35 are in a one-to-one correspondence with the multiple contact regions 34 arranged along the other side wall of the gate structure 35. In addition, the multiple source regions 33 are arranged in a matrix in a plan view.

[0252] Of course, the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence. In other words, the multiple contact regions 34 may be arranged in a staggered pattern in a plan view. The multiple contact regions 34 have portions exposed from the side walls of the trench 75 at the opening end of the trench 75 and face the embedded electrode 77 and the embedded insulator 80 across the insulating film 76.

[0253] Although specific illustrations are omitted, the aforementioned interlayer insulating film 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. The first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D, similar to the first embodiment.

[0254] In this embodiment, the first insulating film 41 covers the peripheral edge of the active surface 71, exposing multiple gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the multiple gate structures 35, exposing the embedded electrodes 77. Furthermore, the first insulating film 41 covers the outer peripheral surface 72 and the first to fourth connecting surfaces 73A to 73D in the same manner as in the first embodiment.

[0255] Similar to the first embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D with the first insulating film 41 in between. In this embodiment, the second insulating film 42 covers the peripheral edge of the active surface 71, exposing multiple gate structures 35 collectively in the inner part of the active surface 71. Specifically, the second insulating film 42 enters the trench 75 from above the first main surface 3 (active surface 71) at both ends of the multiple gate structures 35, and is connected to the embedded insulator 80 within the trench 75.

[0256] In this embodiment, the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (embedded electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that exposes the inner portions (embedded insulators 80) of the plurality of gate structures 35, a plurality of source regions 33, and a plurality of contact regions 34 together.

[0257] The aforementioned gate pad 45, the aforementioned multiple gate wirings 46, and the aforementioned drain pad 48 have the same configuration as in the first embodiment. The aforementioned source pad 47 enters a single contact opening 43 from above the interlayer insulating film 40 and covers the inner portions (embedded insulators 80) of the multiple gate structures 35, the multiple source regions 33, and the multiple contact regions 34 together within the single contact opening 43.

[0258] The source pad 47 is electrically insulated from the multiple gate structures 35 (embedded electrodes 77) by the embedded insulator 80 and is electrically connected to the multiple source regions 33 and the multiple contact regions 34 on the first main surface 3 (active surface 71). The source pad 47 has an embedded portion embedded in the trench 75. The embedded portion of the source pad 47 faces the embedded electrodes 77 within the trench 75, with the embedded insulator 80 in between, and is electrically connected to the multiple source regions 33 and the multiple contact regions 34 at the open end of the trench 75.

[0259] Figure 44 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment. Referring to Figure 44, each of the multiple gate structures 35 according to the fourth embodiment has a configuration that is a modification of the multiple gate structures 35 according to the third embodiment. The configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configuration of the gate structures 35 according to the first to third embodiments.

[0260] The multiple gate structures 35 each include a trench 75, an insulating film 76, an embedded electrode 77, and an embedded insulator 80. The trench 75 has the same configuration as in the first embodiment. In this embodiment, the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.

[0261] The upper insulating film 81 is formed as an insulating film for channel control and covers the wall surface on the opening side of the trench 75 with respect to the bottom of the body region 32. The upper insulating film 81 has a portion that crosses the boundary between the first pillar region 13 and the body region 32 and covers the first pillar region 13. In this case, it is preferable that the covering area of ​​the upper insulating film 81 with respect to the body region 32 is larger than the covering area of ​​the upper insulating film 81 with respect to the first pillar region 13.

[0262] The upper insulating film 81 may contain a silicon oxide film. Preferably, the upper insulating film 81 contains a silicon oxide film made of the oxide of the chip 2. The upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that falls within any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0263] The lower insulating film 82 covers the bottom wall surface of the trench 75 relative to the bottom of the body region 32. The lower insulating film 82 also covers the first pillar region 13. The covering area of ​​the lower insulating film 82 over the first pillar region 13 is larger than the covering area of ​​the upper insulating film 81 over the body region 32.

[0264] The lower insulating film 82 may contain a silicon oxide film. The lower insulating film 82 may contain a silicon oxide film made of the oxide of the chip 2, or it may contain a silicon oxide film formed by the CVD method. The lower insulating film 82 has a thickness greater than the thickness of the upper insulating film 81. Preferably, the thickness of the lower insulating film 82 is 10 to 50 times the thickness of the upper insulating film 81.

[0265] The lower insulating film 82 may have a thickness of 100 nm or more and 500 nm or less. The thickness of the lower insulating film 82 may have a value that falls within any one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or more and 400 nm or more and 450 nm or more and 500 nm or less.

[0266] In this configuration, the embedded electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is embedded on the opening side of the trench 75, with the insulating film 76 in between. Specifically, the upper electrode 83 is embedded on the opening side of the trench 75, with the upper insulating film 81 in between, and faces the body region 32, with the upper insulating film 81 in between.

[0267] The area of ​​the upper electrode 83 facing the body region 32 is larger than the area of ​​the upper electrode 83 facing the first pillar region 13. In this embodiment, the upper electrode 83 is embedded in the trench 75 with a gap between the first main surface 3 (active surface 71) and the bottom wall side of the trench 75, and defines an opening recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75. At the opening end of the trench 75, the upper electrode 83 exposes the surface layer of the first main surface 3 (active surface 71) and the upper end of the upper insulating film 81.

[0268] A gate potential is applied to the upper electrode 83 as a control potential. The upper electrode 83 controls the inversion and non-inversion of the channel (current path) within the body region 32 in response to the gate potential. The upper electrode 83 may contain p-type or n-type conductive polysilicon.

[0269] The lower electrode 84 is embedded on the bottom wall side of the trench 75, with the insulating film 76 in between. Specifically, the lower electrode 84 is embedded on the bottom wall side of the trench 75, with the lower insulating film 82 in between, and faces the first pillar region 13, with the lower insulating film 82 in between. In other words, the lower electrode 84 is embedded on the bottom wall side of the trench 75 relative to the bottom of the body region 32. Although not shown in detail, the lower electrode 84 is pulled out towards the opening side of the trench 75 in part of the trench 75 (both ends in this configuration).

[0270] The area of ​​the lower electrode 84 facing the first pillar region 13 is larger than the area of ​​the upper electrode 83 facing the body region 32. The lower electrode 84 extends in a wall-like manner along the depth direction of the trench 75. The lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83 and engages with the lower end of the upper electrode 83. The upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) horizontally, sandwiching the lower end of the upper electrode 83.

[0271] A gate potential or source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 becomes at the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.

[0272] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the first pillar region 13 is reduced. This suppresses the decrease in switching speed caused by parasitic capacitance. The lower electrode 84 may contain p-type or n-type conductive polysilicon.

[0273] The intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, electrically insulating the upper electrode 83 and the lower electrode 84 within the trench 75. The intermediate insulating film 85 is connected to the upper insulating film 81 and the lower insulating film 82. The intermediate insulating film 85 has a thickness less than the thickness of the lower insulating film 82. Preferably, the thickness of the intermediate insulating film 85 is greater than the thickness of the upper insulating film 81. The intermediate insulating film 85 may contain a silicon oxide film. Preferably, the intermediate insulating film 85 contains a silicon oxide film made of the oxide of the lower electrode 84.

[0274] The embedded insulator 80 is embedded in the trench 75 (opening recess) such that its first main surface 3 (active surface 71) is exposed, and covers the upper insulating film 81 and the upper electrode 83 within the recess. The embedded insulator 80 is embedded in the trench 75 with a gap between the first main surface 3 (active surface 71) and the upper electrode 83, and the surface layer of the first main surface 3 (active surface 71) is exposed at the opening end of the trench 75.

[0275] In this configuration, the aforementioned multiple source regions 33 have portions exposed from the side wall of the trench 75 at the open end of the trench 75 and face the upper electrode 83 and the embedded insulator 80 with the upper insulating film 81 in between. In this configuration, the aforementioned multiple contact regions 34 have portions exposed from the side wall of the trench 75 at the open end of the trench 75 and face the upper electrode 83 and the embedded insulator 80 with the upper insulating film 81 in between.

[0276] The aforementioned multiple field regions 38, interlayer insulating film 40, gate pad 45, the aforementioned multiple gate wirings 46, the aforementioned source pad 47, and the aforementioned drain pad 48 have the same configuration as in the second embodiment. In this embodiment, the multiple gate wirings 46 penetrate the interlayer insulating film 40 through the multiple contact openings 43 and are electrically connected to the multiple upper electrodes 83. When a gate potential is applied to the lower electrode 84, the multiple gate wirings 46 penetrate the interlayer insulating film 40 through the multiple contact openings 43 and are electrically connected to the multiple upper electrodes 83 and the multiple lower electrodes 84.

[0277] When a source potential is applied to the lower electrode 84, the source pad 47 is electrically connected to the plurality of lower electrodes 84. In this case, the semiconductor device 1B may include source wiring drawn out from the source pad 47 onto the interlayer insulating film 40. In this case, the source wiring is formed in a line shape extending along the periphery of the active surface 71 so as to intersect (specifically orthogonally) with a portion (one end or both ends) of the plurality of gate structures 35 in a region outside the plurality of gate wirings 46. The source wiring penetrates the interlayer insulating film 40 through a plurality of contact openings 43 and is electrically connected to the plurality of lower electrodes 84.

[0278] Figure 45 is a plan view showing a semiconductor device 1C according to the third embodiment. Figure 46 is a cross-sectional view along the line XLVI-XLVI shown in Figure 45. Figure 47 is a plan view showing an example of the layout of the chip 2. Figure 48 is a perspective view showing an example of the layout of the chip 2.

[0279] Referring to Figures 45 to 48, the semiconductor device 1C, like the semiconductor device 1A, includes a chip 2, a base layer 6, a laminated portion 7, an active region 10, an outer peripheral region 11, a plurality of second pillar regions 12, a plurality of first pillar regions 13, and a plurality of field regions 38. The plurality of second pillar regions 12 may have at least one of the plurality of features shown in the basic embodiment and the first to eleventh embodiment examples described above. The plurality of second pillar regions 12 may have features that are a combination of a plurality (two or more) of the features shown in the basic embodiment and the first to eleventh embodiment examples described above.

[0280] The semiconductor device 1C includes an interlayer insulating film 90 that selectively covers the first main surface 3. The interlayer insulating film 90 may have a single-layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 90 has a single-layer structure that includes a silicon oxide film.

[0281] The interlayer insulating film 90 covers a plurality of field regions 38 in the outer peripheral region 11. In this embodiment, the interlayer insulating film 90 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating film 90 may be formed with a gap inward from the periphery of the first main surface 3, and the laminated portion 7 may be exposed from the periphery of the first main surface 3.

[0282] The interlayer insulating film 90 has a contact opening 91 that exposes the active region 10. In this configuration, the contact opening 91 has an opening wall surface located above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.

[0283] The semiconductor device 1C includes a first pad electrode 92 that covers the first main surface 3 in the active region 10. The first pad electrode 92 is formed as an anode pad. The first pad electrode 92 is positioned at a distance from the periphery of the chip 2 inward. In a plan view, the first pad electrode 92 is formed in a polygonal shape (a quadrilateral shape in this embodiment) along the periphery of the chip 2.

[0284] The first pad electrode 92 enters the contact opening 91 from above the interlayer insulating film 90 and is electrically connected to the first main surface 3 and the innermost field region 38 within the contact opening 91. The first pad electrode 92 forms a Schottky junction with the first main surface 3 (first pillar region 13). As a result, a Schottky Barrier Diode structure 93 (SBD structure) as a diode structure (device structure) is formed in the active region 10.

[0285] The semiconductor device 1C includes a second pad electrode 94 that covers the second main surface 4. The second pad electrode 94 is formed as a cathode pad. The second pad electrode 94 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the second pad electrode 94 is electrically connected to the first pillar region 13 via the base layer 6.

[0286] The second pad electrode 94 may cover the entire area of ​​the second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the tip 2. Alternatively, the second pad electrode 94 may cover the second main surface 4 with a gap inward from the periphery of the tip 2 so as to expose the periphery of the tip 2.

[0287] The breakdown voltage that can be applied between the first pad electrode 92 and the second pad electrode 94 (between the first main surface 3 and the second main surface 4) may be 500V or less and 3000V or less. The breakdown voltage may have a value that falls within any one of the following ranges: 500V or less and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or more and 3000V or less.

[0288] The basic form of the SBD structure 93 is shown below with reference to Figure 49. Figure 49 is a cross-sectional perspective view showing the SBD structure 93 according to the basic form. Referring to Figure 49, when a plurality of second pillar regions 12 and a plurality of first pillar regions 13 are exposed from the first main surface 3, the first pad electrode 92 is mechanically and electrically connected to the plurality of second pillar regions 12 and a plurality of first pillar regions 13 on the first main surface 3. In this case, the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the plurality of second pillar regions 12 and forms a Schottky junction with the plurality of first pillar regions 13.

[0289] The second to seventh embodiments of the laminated portion 7 are shown below with reference to Figures 50 to 56. The laminated portion 7 may have at least one of the features shown in the second to seventh embodiments. Furthermore, the laminated portion 7 according to the second to seventh embodiments may have features that combine multiple (two or more) features of the second pillar region 12 according to the first to eleventh embodiments described above.

[0290] Referring to Figures 50 to 55, the common features of the laminated portion 7 according to the second to seventh embodiments will first be described. The laminated portion 7 may be formed from a plurality of semiconductor layers. In this embodiment, the laminated portion 7 includes a first semiconductor layer 14 and a second semiconductor layer 15. The laminated portion 7 has a laminated structure in which the first semiconductor layer 14 and the second semiconductor layer 15 are stacked in this order.

[0291] The epitaxial thickness TE of the laminated portion 7 having the laminated structure is preferably 1 μm or more and 70 μm or less. The epitaxial thickness TE may have a value that falls within any one of the following ranges: 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, and 60 μm or more and 70 μm or less.

[0292] The first semiconductor layer 14 is interposed between the base layer 6 and the second semiconductor layer 15. The first semiconductor layer 14 may be in contact with the base layer 6 and the second semiconductor layer 15. The first semiconductor layer 14 extends horizontally in layers so as to cross the boundaries of a plurality of first pillar regions 13 and a plurality of second pillar regions 12 formed on the second semiconductor layer 15, and forms part of the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor layer 14 consists of an epitaxial layer (i.e., a SiC epitaxial layer) that has been crystallized starting from the base layer 6.

[0293] The first semiconductor layer 14 has a lower end and an upper end. Since the first semiconductor layer 14 is grown continuously from the base layer 6, the lower end of the first semiconductor layer 14 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the first semiconductor layer 14 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The first semiconductor layer 14 has an off-direction Doff and an off-angle θoff that substantially coincide with the off-direction Doff and off-angle θoff of the base layer 6.

[0294] The first semiconductor layer 14 has an epitaxial thickness TE1. Preferably, the epitaxial thickness TE1 is 20% or more of the total epitaxial thickness TE of the laminated portion 7 (in this embodiment, TE1 + TE2). Preferably, the epitaxial thickness TE1 is 20% or more and 80% or less of the epitaxial thickness TE. The epitaxial thickness TE1 may have a value that falls within any one of the following ranges of epitaxial thickness TE: 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, and 70% to 80%.

[0295] More specifically, the epitaxial thickness TE1 is preferably 1 μm or more. The epitaxial thickness TE is preferably 55 μm or less. The epitaxial thickness TE1 may have a value that falls within any one of the following ranges: 1 μm or more and 15 μm or less, 15 μm or more and 25 μm or less, 25 μm or more and 35 μm or less, 35 μm or more and 45 μm or less, and 45 μm or more and 55 μm or less.

[0296] In this configuration, the second semiconductor layer 15 is provided as a superjunction structure SJ formation layer. The second semiconductor layer 15 extends in layers horizontally and forms part of the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor layer 15 consists of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystallized continuously from the first semiconductor layer 14 which is crystallized starting from the base layer 6.

[0297] The second semiconductor layer 15 has a lower end and an upper end. Since the second semiconductor layer 15 is grown continuously from the first semiconductor layer 14, the lower end of the second semiconductor layer 15 coincides with the upper end of the first semiconductor layer 14. The boundary between the first semiconductor layer 14 and the second semiconductor layer 15 is not necessarily visible and can be indirectly evaluated and / or determined from other components and elements. The second semiconductor layer 15 has an off-direction Doff and off-angle θoff that substantially coincide with the off-direction Doff and off-angle θoff of the base layer 6. The entirety of the second semiconductor layer 15 may be referred to as the drift region 8.

[0298] The second semiconductor layer 15 has an epitaxial thickness TE2. Preferably, the epitaxial thickness TE2 is 20% or more of the total epitaxial thickness TE of the laminated portion 7 (in this embodiment, TE1 + TE2). Preferably, the epitaxial thickness TE2 is 10% or more and 80% or less of the epitaxial thickness TE. The epitaxial thickness TE2 may have a value that falls within any one of the following ranges of epitaxial thickness TE: 10% to 20%, 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, and 70% to 80%.

[0299] More specifically, the epitaxial thickness TE2 is preferably 1 μm or more. The epitaxial thickness TE is preferably 50 μm or less. The epitaxial thickness TE2 may have a value that falls within any one of the following ranges: 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, 25 μm to 30 μm, 30 μm to 35 μm, 35 μm to 40 μm, 40 μm to 45 μm, and 45 μm to 50 μm.

[0300] Next, the individual characteristics of the laminated portion 7 according to the second to seventh embodiments will be described. Referring to Figure 50, the n-type impurity concentration of the first semiconductor layer 14 may be the same as the n-type impurity concentration of the first pillar region 13. The first semiconductor layer 14 is 1 × 10 １５ cm －３ The above 1 x 10 １８ cm －３ The following n-type impurity concentrations may be present as peak values.

[0301] The structure shown in Figure 50 may be formed through the following steps. For example, the n-type portions of the first semiconductor layer 14 and the second semiconductor layer 15 are formed continuously by epitaxial growth. Next, a trench is formed in the region of the second semiconductor layer 15 where the second pillar region 12 is to be formed. Then, the trench is filled with p-type semiconductor by epitaxial growth of p-type semiconductor within the trench. The structure shown in Figure 50 is obtained through these steps.

[0302] Referring to Figure 51, the n-type impurity concentration of the first semiconductor layer 14 may be less than the n-type impurity concentration of the first pillar region 13. The first semiconductor layer 14 is 1 × 10 １５ cm －３ The above 1 x 10 １７ cm －３ The following n-type impurity concentrations may be present as peak values. In this case, the first pillar region 13 and the first semiconductor layer 14 are defined as an n-type region and an n-type region, respectively, in order to clearly distinguish the difference in their impurity concentrations. － It may also be referred to as a type region. Also, the base layer 6 is n ＋ It may also be referred to as a type region.

[0303] Referring to Figure 52, the n-type impurity concentration of the first semiconductor layer 14 may exceed the n-type impurity concentration of the first pillar region 13. In this case, the n-type impurity concentration of the first semiconductor layer 14 may be less than the n-type impurity concentration of the base layer 6. The first semiconductor layer 14 is 1 × 10⁻¹⁶ １５ cm －３ The above 1 x 10 １７ cm －３ The following n-type impurity concentrations may be present as peak values. In this case, the first pillar region 13 and the first semiconductor layer 14 are each n-type in order to clearly distinguish the difference in their impurity concentrations. － These may be referred to as the type region and the n-type region.

[0304] Referring to Figure 53, the second pillar region 12 has a thickness T2 that exceeds the epitaxial thickness TE2 of the second semiconductor layer 15, and a portion of it may penetrate the first semiconductor layer 14. Specifically, the second lower end portion 12a of the second pillar region 12 is located in the middle of the thickness direction of the first semiconductor layer 14.

[0305] The structure in Figure 53 may be formed through the following steps. For example, after forming the first semiconductor layer 14, the same n-type impurity concentration (n －The second semiconductor layer 15 is epitaxially grown at a concentration corresponding to the type. Next, n-type impurity ions and p-type impurity ions are selectively implanted into the regions of the second semiconductor layer 15 where the first pillar region 13 and the second pillar region 12 are to be formed, respectively. As a result, the first pillar region 13 and the second pillar region 12 are formed in the second semiconductor layer 15, and the structure shown in Figure 53 is obtained. Note that the above process can be repeated multiple times to increase the number of superjunctions.

[0306] Alternatively, the structure shown in Figure 53 may be obtained by epitaxially growing the second semiconductor layer 15 with the same n-type impurity concentration (a concentration equivalent to n-type) as the first pillar region 13, and selectively implanting p-type impurity ions into the second semiconductor layer 15.

[0307] Referring to Figure 54, the second pillar region 12 may have a thickness T2 less than the epitaxial thickness TE2 of the second semiconductor layer 15 and may be formed within the second semiconductor layer 15 at a distance from the lower end of the second semiconductor layer 15. Specifically, the second lower end portion 12a of the second pillar region 12 is formed at a distance from the lower end (first semiconductor layer 14) of the second semiconductor layer 15 toward the upper end, and faces the first semiconductor layer 14 with a part (lower end portion) of the second semiconductor layer 15 in between.

[0308] Referring to Figure 55, the second semiconductor layer 15 may include a plurality of selectively formed trenches 16 and embedded insulators 17 embedded in the trenches 16.

[0309] Multiple trenches 16 are formed in a pillar-like manner in the second semiconductor layer 15. The trenches 16 may also be called "pillar trenches," "column trenches," etc. The trenches 16 may or may not penetrate the second semiconductor layer 15 in the thickness direction. If the trenches 16 penetrate the second semiconductor layer 15, the bottom wall of the trenches 16 is the first semiconductor layer 14; if they do not penetrate, the bottom wall of the trenches 16 is the second semiconductor layer 15.

[0310] The buried insulator 17 is an insulating film that backfills the trench 16. The buried insulator 17 may include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 17 may also be referred to as a "pillar insulating film," "column insulating film," etc.

[0311] The second pillar region 12 is formed in the inner wall of the trench 16. More specifically, it is formed in the side wall and bottom wall of the trench 16. The second pillar region 12, together with the first pillar region 13, forms a pn joint in the side wall of the trench 16.

[0312] The structure shown in Figure 55 may be formed through the following steps. For example, the n-type portions of the first semiconductor layer 14 and the second semiconductor layer 15 are formed continuously by epitaxial growth. Next, referring to Figure 56, a trench 16 is formed in the region of the second semiconductor layer 15 where the second pillar region 12 is to be formed. Next, p-type impurity ions are implanted into the side walls and bottom walls of the trench 16 to form the second pillar region 12. Next, the inside of the trench 16 is backfilled with insulating material by, for example, CVD to form an embedded insulator 17. The structure shown in Figure 55 is obtained through the above steps.

[0313] The embodiments described above can be implemented in other forms. For example, in each of the embodiments described above, a base layer 6 and a laminated portion 7 containing a SiC single crystal were employed. However, at least one or all of the base layer 6 and the laminated portion 7 may contain a single crystal of a wide-bandgap semiconductor other than a SiC single crystal.

[0314] Wide-bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Examples of wide-bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga). ２ O ３ Examples include the following. The base layer 6 and the laminated portion 7 may be made of the same type of single crystal, or they may be made of different types of single crystal.

[0315] In the embodiments described above, examples were shown in which the MIS structure 31 and the SBD structure 93 were formed individually on different chips 2. However, the MIS structure 31 and the SBD structure 93 may be formed on a single chip 2. In this case, the SBD structure 93 may be electrically interposed between the source pad 47 (anode pad) and the drain pad 48 (cathode pad) as a freewheeling diode for the MIS structure 31.

[0316] In the embodiments described above, an n-type base layer 6 was shown. However, a p-type base layer 6 may also be used. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of a MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure. The p-type base layer 6 may also be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0317] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components in each of the embodiments described above, but this is not intended to limit the scope of each Clause to the embodiments. The term "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," "MISFET device," "IGBT device," "diode device," etc., as needed.

[0318] [Note 1-1] A semiconductor device (1A, 1B, 1C) comprising: a semiconductor layer (6, 7) of a first conductivity type having a first main surface (3) and a second main surface (4); a first pillar region (13) of a first conductivity type extending in the depth direction of the semiconductor layer (6, 7) from the first main surface (3) to the second main surface (4) within the semiconductor layer (6, 7); and a second pillar region (12) of a second conductivity type adjacent to the first pillar region (13) within the semiconductor layer (6, 7) and extending in the depth direction, wherein the first width W1 of the first pillar region (13) is greater than the second width W2 of the second pillar region (12).

[0319] [Note 1-2] The semiconductor device (1A, 1B, 1C) described in Note 1-1, wherein the first width W1 of the first pillar region (13) is 4 times or more and 12 times or less of the second width W2 of the second pillar region (12).

[0320] [Note 1-3] The semiconductor device (1A, 1B, 1C) described in Note 1-1 or Note 1-2, wherein the first average impurity concentration N1, which is the average of the impurity concentrations of the first conductivity type in the first pillar region (13), is smaller than the second average impurity concentration N2, which is the average of the impurity concentrations of the second conductivity type in the second pillar region (12).

[0321] [Note 1-4] The semiconductor device (1A, 1B, 1C) described in Note 1-3, wherein the first average impurity concentration / second average impurity concentration (N1 / N2) is within the range of -10% or more and +10% or less with respect to the second width / first width (W2 / W1).

[0322] [Appendix 1-5] The semiconductor device (1A, 1B, 1C) described in Appendix 1-3, wherein the charge balance CB between the first pillar region (13) and the second pillar region (12), as shown by the following formula (1), is maintained by the first average impurity concentration N1, the first width W1, the second average impurity concentration N2, and the second width W2.

[0323] CB = (N1 × W1) / (N2 × W2) ... (1) [Note 1-6] The charge balance CB is in the range of 0.9 or more and 1.1 or less in the section from the top to the bottom in the depth direction of the first pillar region (13) and the second pillar region (12), as described in Note 1-5 (1A, 1B, 1C).

[0324] [Note 1-7] The semiconductor device (1A, 1B, 1C) described in Note 1-3, wherein the charge balance CB between the first pillar region (13) and the second pillar region (12), as shown by formula (1) below, is disrupted due to the first average impurity concentration N1, the first width W1, the second average impurity concentration N2, and the second width W2.

[0325] CB = (N1 × W1) / (N2 × W2) ... (1) [Note 1-8] The charge balance CB is less than 0.9 or greater than 1.1 in the section from the top to the bottom in the depth direction of the first pillar region (13) and the second pillar region (12), according to the semiconductor device (1A, 1B, 1C) described in Note 1-7.

[0326] [Appendix 1-9] The aspect ratio of the second pillar region (12) is 2 or more and 30 or less, according to any one of the appendices 1-1 to 1-8, semiconductor device (1A, 1B, 1C).

[0327] [Appendix 1-10] A semiconductor device (1A, 1B, 1C) according to any one of Appendix 1-1 to 1-9, comprising an element structure formed on the surface layer of the first main surface (3), wherein the superjunction structure provided by the pn junctions of the first pillar region (13) and the second pillar region (12) extends downward toward the element structure.

[0328] [Appendix 1-11] The semiconductor device (1A) according to Appendix 1-10, wherein the element structure includes a second conductivity type body region formed on the surface layer of the first main surface (3) and a planar gate structure formed on the first main surface (3) so as to be located on the body region.

[0329] [Appendix 1-12] The semiconductor device (1B) according to Appendix 1-10, wherein the element structure includes a second conductivity type body region formed on the surface layer of the first main surface (3) and a trench gate structure formed on the first main surface (3) so as to penetrate the body region.

[0330] [Appendix 1-13] The semiconductor device (1C) according to Appendix 1-10, wherein the element structure includes a diode structure formed by an electrode formed on the first main surface (3) and electrically connected to the first pillar region (13), and the first pillar region (13).

[0331] [Appendix 1-14] The semiconductor device (1A, 1B, 1C) described in any one of the appendices 1-1 to 1-13, wherein the first pillar region (13) is an n-type pillar region and the second pillar region (12) is a p-type pillar region.

[0332] [Appendix 1-15] The semiconductor device (1A, 1B, 1C) according to any one of the appendices 1-1 to 1-14, wherein the semiconductor layer (6, 7) is a SiC semiconductor layer (6, 7).

[0333] [Appendix 2-1] A semiconductor device (1A, 1B, 1C) comprising: a SiC chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (7) of a first conductivity type located on the surface of the first main surface (3); an element structure formed within the first impurity region (7); a plurality of first pillar regions (13) of a first conductivity type formed by a part of the first impurity region (7); and a plurality of second pillar regions (12) extending downward toward the element structure within the first impurity region (7) and providing a superjunction structure (SJ) by a pn junction between them and the first pillar regions (13), wherein the first width W1 of the first pillar region (13) is greater than the second width W2 of the second pillar region (12).

[0334] [Appendix 2-2] The semiconductor device (1A) according to Appendix 2-1, wherein the element structure includes a second conductivity type body region formed on the surface layer of the first main surface (3) and a planar gate structure formed on the first main surface (3) so as to be located on the body region.

[0335] [Note 2-3] The semiconductor device (1B) according to Note 2-1, wherein the element structure includes a second conductivity type body region formed on the surface layer of the first main surface (3) and a trench gate structure formed on the first main surface (3) so as to penetrate the body region.

[0336] [Note 2-4] The semiconductor device (1C) according to Note 2-1, wherein the element structure includes a diode structure formed by an electrode formed on the first main surface (3) and electrically connected to the first pillar region (13), and the first pillar region (13).

[0337] [Appendix 2-5] The semiconductor device (1A, 1B, 1C) described in any one of Appendix 2-1 to 2-4, wherein the first pillar region (13) is an n-type pillar region and the second pillar region (12) is a p-type pillar region.

[0338] [Note 3-1] A semiconductor layer (6, 7) of a first conductivity type having a first main surface (3) and a second main surface (4); a first pillar region (13) of a first conductivity type extending in the depth direction of the semiconductor layer (6, 7) from the first main surface (3) toward the second main surface (4) within the semiconductor layer (6, 7); a second pillar region (12) of a second conductivity type adjacent to the first pillar region (13) within the semiconductor layer (6, 7) and extending in the depth direction; and a first semiconductor layer (14) of a first conductivity type extending horizontally in layers below the first pillar region (13) and the second pillar region (12), crossing the boundaries of a plurality of the first pillar regions (13) and a plurality of the second pillar regions (12), and in contact with the lower end (13a) of the first pillar region (13) and the lower end (12a) of the second pillar region (12), respectively. A semiconductor device wherein the first width W1 of the first pillar region (13) is greater than the second width W2 of the second pillar region (12).

[0339] 1A...Semiconductor device, 1B...Semiconductor device, 1C...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...Base layer, 7...Laminated portion, 8...Drift region, 9...Second layer, 10...Active region, 11...Peripheral region, 12...Second pillar region, 12a...Second lower end, 12b...Second upper end, 13...First pillar region, 13a...First lower end, 13b ...First upper end, 14...First semiconductor layer, 15...Second semiconductor layer, 16...Trench, 17...Buried insulator, 18...First region, 19...Second region, 25...Intermediate region, 26...Boundary, 31...MIS structure, 32...Body region, 33...Source region, 34...Contact region, 35...Gate structure, 36...Gate insulating film, 37...Gate electrode, 38...Field region, 40...Interlayer insulating film, 41...First insulating film, 42...Second insulating film, 43...Contact opening, 45...Gate pad, 46...Gate wiring, 46A...First gate wiring, 46B...Second gate wiring, 47...Source pad, 48...Drain pad, 50...Wafer, 51...First wafer main surface, 52...Second wafer main surface, 53...Wafer side, 54...Marker, 55...Device region, 56...Cutting line, 62...Mask, 63...Opening, 71...Active surface, 72...Outer peripheral surface, 73A...First connection surface, 73 B...Second connection surface, 73C...Third connection surface, 73D...Fourth connection surface, 74...Active plateau, 75...Trench, 76...Insulating film, 77...Buried electrode, 78...Well region, 79...Sidewall structure, 80...Buried insulator, 81...Upper insulating film, 82...Lower insulating film, 83...Upper electrode, 84...Lower electrode, 85...Intermediate insulating film, 90...Interlayer insulating film, 91...Contact opening, 92...First pad electrode, 93...SBD structure, 94...Second pad electrode

Claims

1. A semiconductor device comprising: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; a first pillar region of the first conductivity type extending in the depth direction of the semiconductor layer from the first main surface toward the second main surface within the semiconductor layer; and a second pillar region of the second conductivity type adjacent to the first pillar region within the semiconductor layer and extending in the depth direction, wherein the first width W1 of the first pillar region is greater than the second width W2 of the second pillar region.

2. The semiconductor device according to claim 1, wherein the first width W1 of the first pillar region is 4 times or more and 12 times or less of the second width W2 of the second pillar region.

3. The semiconductor device according to claim 1 or 2, wherein the first average impurity concentration N1, which is the average of the impurity concentrations of the first conductivity type in the first pillar region, is smaller than the second average impurity concentration N2, which is the average of the impurity concentrations of the second conductivity type in the second pillar region.

4. The semiconductor device according to claim 3, wherein the first average impurity concentration / second average impurity concentration (N1 / N2) is within the range of -10% or more and +10% or less with respect to the second width / first width (W2 / W1).

5. The semiconductor device according to claim 3, wherein the charge balance CB between the first pillar region and the second pillar region, represented by the following formula (1), is maintained by the first average impurity concentration N1, the first width W1, the second average impurity concentration N2, and the second width W2. CB = (N1 × W1) / (N2 × W2) ... (1) 6. The semiconductor device according to claim 5, wherein the charge balance CB is within the range of 0.9 or more and 1.1 or less in the section from the top to the bottom in the depth direction of the first pillar region and the second pillar region.

7. The semiconductor device according to claim 3, wherein the charge balance CB between the first pillar region and the second pillar region, as shown by the following formula (1), is disrupted due to the first average impurity concentration N1, the first width W1, the second average impurity concentration N2, and the second width W2. CB = (N1 × W1) / (N2 × W2) ... (1) 8. The semiconductor device according to claim 7, wherein the charge balance CB is less than 0.9 or greater than 1.1 in the section from the top to the bottom in the depth direction of the first pillar region and the second pillar region.

9. The semiconductor device according to any one of claims 1 to 8, wherein the aspect ratio of the second pillar region is 2 or more and 30 or less.

10. A semiconductor device according to any one of claims 1 to 9, comprising an element structure formed on the surface layer of the first main surface, wherein the superjunction structure provided by the pn junctions of the first pillar region and the second pillar region extends downward toward the element structure.

11. The semiconductor device according to claim 10, wherein the element structure includes a second conductivity type body region formed on the surface layer of the first main surface and a planar gate structure formed on the first main surface so as to be located on the body region.

12. The semiconductor device according to claim 10, wherein the element structure includes a second conductive body region formed on the surface layer of the first main surface and a trench gate structure formed on the first main surface so as to penetrate the body region.

13. The semiconductor device according to claim 10, wherein the element structure includes a diode structure formed by an electrode formed on the first main surface and electrically connected to the first pillar region and the first pillar region.

14. The semiconductor device according to any one of claims 1 to 13, wherein the first pillar region is an n-type pillar region and the second pillar region is a p-type pillar region.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor layer is a SiC semiconductor layer.

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