Semiconductor device

Abstract

This semiconductor device includes: a semiconductor layer that contains SiC and has a main surface having a first barrier height; a trench that is formed in the main surface, has a side wall having a second barrier height lower than the first barrier height, and has an inclined side wall having a third barrier height higher than the second barrier height and lower than the first barrier height and inclined downward from the main surface to the side wall; and an electrode that covers the main surface and the inclined side wall and forms a Schottky junction with both the main surface and the inclined side wall.

Description

Semiconductor device

[0001] This application claims priority based on Patent Application No. 2025-017024 filed with the Japan Patent Office on February 4, 2025, and the entire contents of this application are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0012050A1) discloses a semiconductor device having a trench gate type transistor and a Schottky barrier diode formed on a semiconductor substrate.

[0003] U.S. Patent Application Publication No. 2008 / 0012050

[0004] [Summary] The present disclosure provides a semiconductor device that contributes to improving electrical characteristics.

[0005] The present disclosure includes a semiconductor layer containing SiC and having a main surface with a first barrier height, a side wall having a second barrier height lower than the first barrier height, and a third barrier height higher than the second barrier height and lower than the first barrier height, having an inclined side wall sloping downward from the main surface to the side wall, a trench formed on the main surface, and an electrode covering the main surface and the inclined side wall and forming a Schottky junction with both the main surface and the inclined side wall, and provides a semiconductor device.

[0006] The present disclosure includes a semiconductor layer having a main surface, a gate structure of a trench electrode type formed on the main surface, a main surface portion formed of a part of the main surface and an inclined portion sloping downward from the main surface portion toward the plurality of gate structures, a mesa portion partitioned by the gate structure in the semiconductor layer, and an electrode forming a Schottky junction with both the main surface portion and the inclined portion of the mesa portion, and provides a semiconductor device.

[0007] The above or further other objects, features, and effects will be clarified by a detailed description with reference to the accompanying drawings.

[0008] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view showing the inner part of the active region according to the first layout example. Figure 5 is an enlarged plan view showing the end of the active region according to the first layout example. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 5. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional perspective view showing the configuration of a trench. Figure 10 is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the first example. Figure 11 is a further enlarged cross-sectional view showing the inclined side wall. Figure 12 is a cross-sectional view showing the outer region. Figure 13A is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the second example. Figure 13B is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the third example. Figure 13C is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the fourth example. Figure 13D is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the fifth example. Figure 13E is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the sixth example. Figure 13F is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the seventh example. Figure 13G is an enlarged cross-sectional view showing the gate structure (mesa portion) according to the eighth example. Figure 14A is an enlarged plan view showing the active region according to the second layout example. Figure 14B is an enlarged plan view showing the active region according to the third layout example. Figure 14C is an enlarged plan view showing the active region according to the fourth layout example. Figure 15 is a circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 1. Figure 16 is a graph showing the electrical behavior of the semiconductor device shown in Figure 1. Figure 17 is an enlarged plan view showing the active region of the semiconductor device according to the second embodiment. Figure 18 is a cross-sectional view along the line XVIII-XVIII shown in Figure 17. Figure 19 is a cross-sectional view along the line XIX-XIX shown in Figure 17. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 17. Figure 21 is an enlarged plan view showing the active region of the semiconductor device according to the third embodiment. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 21. Figure 23 is a cross-sectional view along the line XXIII-XXIII shown in Figure 21. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 21.Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 21. Figure 26 is an enlarged plan view showing the active region of the semiconductor device according to the fourth embodiment. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 26. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 26. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 26. Figure 30 is a cross-sectional perspective view showing the well region according to a modified example. Figure 31 is an enlarged cross-sectional view showing the mesa portion of the semiconductor device according to a modified example.

[0009] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0010] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0011] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0012] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0013] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0014] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3. Figure 4 is an enlarged plan view showing the inner part of the active region 8 according to the first layout example. Figure 5 is an enlarged plan view showing the end of the active region 8 according to the first layout example.

[0015] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 5. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 5. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 9 is a cross-sectional perspective view showing the configuration of the trench 15. Figure 10 is an enlarged cross-sectional view showing a first example of the gate structure 10 (mesa section 20). Figure 11 is a further enlarged cross-sectional view showing the inclined side wall 14. Figure 12 is a cross-sectional view showing the outer region 9.

[0016] Referring to Figures 1 to 12, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate type vertical structure.

[0017] The semiconductor device 1A includes a chip 2 formed in a hexahedral (cuboidal) shape. In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0018] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0019] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Chip 2 may also contain cubic or polycrystalline materials. Chip 2 may also contain 3C (Cubic)-SiC single crystals or 3C-SiC polycrystalline materials.

[0020] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed from the thickness direction Z of the chip 2 (hereinafter referred to as "plan view"). The thickness direction Z is also the vertical direction of the first main surface 3 and the second main surface 4.

[0021] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0022] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0023] In this configuration, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Hereafter, the direction extending along the first principal surface 3 may be referred to as the "horizontal direction". The horizontal direction is the direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the thickness direction Z.

[0024] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0025] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0026] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0027] SiC single crystals have barrier heights corresponding to their crystal planes (plane polarity). The c-plane (Si plane) of a SiC single crystal is relatively stable and has a relatively high barrier height. The m-plane ((1-100) plane) of a SiC single crystal has a lower barrier height than the c-plane. The a-plane ((11-20) plane) of a SiC single crystal has a lower barrier height than the c-plane.

[0028] The barrier height of surface a tends to be higher than that of surface m, but this may vary depending on experimental conditions and surface state. Therefore, in this disclosure, the barrier height of surface a may be lower or higher than that of surface m.

[0029] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0030] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a SiC substrate containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. The first semiconductor layer 6 may consist of other polytypes. The first semiconductor layer 6 may consist of a 3C-SiC polycrystal.

[0031] The first semiconductor layer 6 may have a substantially constant n-type impurity concentration in the thickness direction Z. The n-type impurity concentration of the first semiconductor layer 6 may be adjusted by a single pentavalent element. Preferably, the first semiconductor layer 6 contains a pentavalent element other than phosphorus. In this embodiment, the concentration of the first semiconductor layer 6 is adjusted by nitrogen as the pentavalent element.

[0032] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0033] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)," "drain layer (region)," "drift layer (region)," etc. The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6 and forms the upper part of the chip 2. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6) and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0034] The second semiconductor layer 7 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a SiC layer containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. The second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0035] The second semiconductor layer 7 has a lower n-type impurity concentration than the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z. The n-type impurity concentration of the second semiconductor layer 7 may have a concentration gradient that gradually increases and / or decreases in the stacking direction (crystal growth direction).

[0036] The n-type impurity concentration of the second semiconductor layer 7 is preferably adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the second semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0037] The second semiconductor layer 7 preferably contains a pentavalent element other than phosphorus. If the second semiconductor layer 7 contains two or more pentavalent elements, it is preferable that the second semiconductor layer 7 contains at least two of nitrogen, arsenic, and antimony. The second semiconductor layer 7 preferably contains at least nitrogen as a pentavalent element.

[0038] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, 17.5 μm or more and 20 μm or less, 20 μm or more and 22.5 μm or less, and 22.5 μm or more and 25 μm or less.

[0039] The semiconductor device 1A includes an active region 8 provided on the first main surface 3. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is set as a polygonal shape with four sides parallel to the periphery of the first main surface 3 (in this form, a rectangular shape with a concave recess on the side of the first side surface 5A).

[0040] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, 0.9 or more and 0.95 or less, and 0.95 or more and less than 1.

[0041] The semiconductor device 1A includes an outer region 9 located outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include the device structure (transistor structure Tr). The outer region 9 is set at the periphery of the first main surface 3. The outer region 9 is provided in the region between the periphery of the first main surface 3 and the active region 8. In a plan view, the outer region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this embodiment) that surrounds the active region 8.

[0042] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 10 formed in the inner part (active region 8) of the second semiconductor layer 7. The gate structure 10 may be referred to as a "trench structure", a "trench gate structure", or the like. A gate potential (gate signal) as a control potential is applied to the plurality of gate structures 10.

[0043] The plurality of gate structures 10 are formed in the active region 8 at an interval from the periphery of the first main surface 3 and are not formed in the outer region 9. The plurality of gate structures 10 are formed at an interval from the bottom of the second semiconductor layer 7 toward the first main surface 3 side and face the first semiconductor layer 6 through a part of the second semiconductor layer 7.

[0044] The plurality of gate structures 10 are arranged at an interval in the first direction X in a plan view and extend in a strip shape in the second direction Y, respectively. The plurality of gate structures 10 are arranged in a stripe shape extending in the second direction Y (= a-axis direction) in a plan view. The extending direction of the plurality of gate structures 10 coincides with the off-direction of the SiC single crystal.

[0045] The plurality of gate structures 10 may be arranged at an interval greater than 0 μm and not more than 2 μm. The interval between the gate structures 10 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The interval between the gate structures 10 is preferably 1 μm or less.

[0046] The plurality of gate structures 10 each have a pair of first side walls 11 extending in the longitudinal direction (second direction Y), a pair of second side walls 12 extending in the short direction (first direction X), and a bottom wall 13 connecting the pair of first side walls 11 and the pair of second side walls 12.

[0047] A pair of first sidewalls 11 form the long sides of the gate structure 10 and are formed by the m-plane of a single-crystalline SiC. The pair of first sidewalls 11 are formed substantially perpendicular to the first main surface 3 in a cross-sectional view along the first direction X. The pair of first sidewalls 11 may be obliquely inclined with respect to the first main surface 3. That is, the gate structure 10 may be formed in a tapered shape that tapers toward the second main surface 4 in a cross-sectional view.

[0048] The inclination angle (absolute value) of the first sidewall 11 with respect to the horizontal plane may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95°. The inclination angle is preferably 87° or more and 93° or less.

[0049] A pair of second sidewalls 12 form the short sides of the gate structure 10 and are formed by the a-plane of a single-crystalline SiC. The pair of second sidewalls 12 are formed substantially perpendicular to the first main surface 3 in a cross-sectional view. The pair of second sidewalls 12 may be obliquely inclined with respect to the first main surface 3. That is, the gate structure 10 may be formed in a tapered shape that tapers toward the second main surface 4 in a cross-sectional view along the second direction Y.

[0050] The inclination angle (absolute value) of the second sidewall 12 with respect to the horizontal plane may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95°. The inclination angle is preferably 87° or more and 93° or less.

[0051] The bottom wall 13 is formed by the c-plane of a single-crystalline SiC. In this form, the bottom wall 13 extends substantially flat along the horizontal direction. The bottom wall 13 may be curved in an arc shape toward the second main surface 4.

[0052] In this embodiment, the gate structure 10 has a width greater than the spacing between the gate structures 10. The width of the gate structure 10 is defined by the distance in the first direction X between the pair of first side walls 11. The width of the gate structure 10 may be less than the spacing between the gate structures 10. The width of the gate structure 10 may be between 0.1 μm and 2 μm.

[0053] The width of the gate structure 10 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. Preferably, the width of the gate structure 10 is 1 μm or less.

[0054] The gate structure 10 has a depth less than the thickness of the second semiconductor layer 7. The depth of the gate structure 10 may be greater than 0 μm and 3 μm or less. The depth of the gate structure 10 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less.

[0055] The gate structure 10 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 10 is the ratio of the depth of the gate structure 10 to the width of the gate structure 10. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0056] Each of the multiple gate structures 10 has one or more (in this embodiment, a pair) inclined side walls 14 formed at the open ends of either one or both (in this embodiment, both) of the pair of first side walls 11. The open ends of the first side walls 11 are the connection corners between the first main surface 3 and the first side walls 11.

[0057] In this configuration, the inclined side wall 14 has a different inclination angle θ than the first main surface 3 and the first side wall 11, and in cross-sectional view, it slopes diagonally downward in a straight line from the first main surface 3 to the first side wall 11. The inclination angle θ is defined by the angle that a straight line connecting the upper end (starting point of inclination) on the first main surface 3 side and the lower end (ending point of inclination) on the first side wall 11 side makes with respect to the horizontal plane (first main surface 3) (see also Figure 10). The inclination angle θ may also be called the "miscut angle".

[0058] The inclination angle θ may be greater than 0° and 60° or less. The inclination angle θ may have a value that falls within at least one of the following ranges: greater than 0° and 10° or less, 10° or more and 20° or less, 20° or more and 30° or less, 30° or more and 40° or less, 40° or more and 50° or less, and 50° or more and 60° or less.

[0059] The inclination angle θ is preferably an acute angle of 45° or less. The inclination angle θ may be 40° or less. The inclination angle θ may be 35° or less. The inclination angle θ may be 30° or less. The inclination angle θ is preferably 10° or more. The inclination angle θ may be 20° or more. The inclination angle θ may be 30° or more.

[0060] The inclined sidewall 14 is formed by a plurality of step surfaces S formed by the c-plane and m-plane of the SiC single crystal (see Figure 11). Here, the barrier height of the first main surface 3 is defined as the first barrier height BH1, the barrier height of the first sidewall 11 is defined as the second barrier height BH2, and the barrier height of the inclined sidewall 14 is defined as the third barrier height BH3 (see Figure 10).

[0061] The first barrier height BH1 is due to the c-plane of the SiC single crystal. The second barrier height BH2 is due to the m-plane of the SiC single crystal and is lower than the first barrier height BH1. The third barrier height BH3 is due to both the c-plane and m-plane of the SiC single crystal and is higher than the second barrier height BH2 and lower than the first barrier height BH1. In other words, the inclined sidewall 14 is formed as a relaxation section for the barrier height difference between the first main surface 3 and the first sidewall 11.

[0062] The inclined sidewall 14 may have a width greater than 0 μm and less than or equal to 1 μm. The width of the inclined sidewall 14 is defined by the horizontal distance (length) between the upper end and lower end of the inclined sidewall 14 in a cross-sectional view.

[0063] The width of the inclined sidewall 14 may be greater than 0 μm and less than or equal to 0.1 μm, 0.1 μm or more and less than or equal to 0.2 μm, 0.2 μm or more and less than or equal to 0.3 μm, 0.3 μm or more and less than or equal to 0.4 μm, 0.4 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.6 μm, 0.6 μm or more and less than or equal to 0.7 μm, 0.7 μm or more and less than or equal to 0.8 μm, 0.8 μm or more and less than or equal to 0.9 μm, and 0.9 μm or more and less than or equal to 1 μm. The width of the inclined sidewall 14 may be between 0.1 μm and 0.5 μm. The width of the inclined sidewall 14 may be 0.25 μm or less.

[0064] The ratio of the width of the inclined side wall 14 to the spacing of the gate structure 10 may be greater than 0 and 0.5 or less. The ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, and 0.4 or more and 0.5 or less. Preferably, the ratio is between 0.1 (= 1 / 10) and 0.33 (= 1 / 3).

[0065] The inclined sidewall 14 is formed at a distance from the depth position of the intermediate part of the gate structure 10 toward the first main surface 3. The inclined sidewall 14 may have a depth greater than 0 μm and less than or equal to 0.5 μm. The depth of the inclined sidewall 14 is defined by the distance in the thickness direction Z between the height position of the first main surface 3 and the lower end of the inclined sidewall 14 in a cross-sectional view.

[0066] The depth of the inclined sidewall 14 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, and 0.4 μm or more and 0.5 μm or less. The depth of the inclined sidewall 14 may be 0.25 μm or less.

[0067] The ratio of the depth of the inclined side wall 14 to the depth of the gate structure 10 may be greater than 0 μm and 0.25 or less. The ratio may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, and 0.2 or more and 0.25 or less.

[0068] Each of the gate structures 10 includes a trench 15, an insulating film 16, an embedded electrode 17, and an embedded insulator 18. The insulating film 16 may be referred to as the "gate insulating film," and the embedded electrode 17 may be referred to as the "embedded electrode" or "gate embedded electrode."

[0069] The trench 15 is formed in the first main surface 3 and partitions the wall surface of the gate structure 10. In other words, the trench 15 partitions a pair of first side walls 11, a pair of second side walls 12, a bottom wall 13, and a pair of inclined side walls 14.

[0070] The insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 16 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 16 may also include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0071] The insulating film 16 covers the walls of the trench 15 in a film-like manner. In this embodiment, the insulating film 16 covers the walls of the trench 15 below the inclined side walls 14. Specifically, the insulating film 16 has an upper end located on the bottom wall 13 side relative to the inclined side walls 14, and covers the first side wall 11, the second side wall 12, and the bottom wall 13. In this embodiment, the insulating film 16 exposes the entire area of ​​the inclined side walls 14.

[0072] The upper end of the insulating film 16 is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 15. In this embodiment, the upper end of the insulating film 16 is formed with a gap from the lower end of the inclined side wall 14 toward the bottom wall 13, exposing the upper end of the first side wall 11. The thickness of the portion of the insulating film 16 that covers the bottom wall 13 may be greater than the thickness of the portion of the insulating film 16 that covers the first side wall 11 (second side wall 12).

[0073] The thickness of the insulating film 16 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 16 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 250 nm or less.

[0074] The embedded electrode 17 includes either a metallic conductor or a non-metallic conductor, or both. The embedded electrode 17 may also include conductive polysilicon. In this case, the embedded electrode 17 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. It is preferable that the embedded electrode 17 is made of n-type conductive polysilicon.

[0075] The embedded electrode 17 is embedded in the trench 15 via an insulating film 16. The embedded electrode 17 is embedded in the trench 15 below the inclined side wall 14. The embedded electrode 17 has an electrode surface located on the bottom wall 13 side relative to the inclined side wall 14. The embedded electrode 17 exposes the entire area of ​​the inclined side wall 14.

[0076] In this configuration, the electrode surface is formed with a gap from the lower end of the inclined side wall 14 toward the bottom wall 13, exposing the upper end of the first side wall 11 and the entire area of ​​the inclined side wall 14. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 15. The electrode surface may also be located on the bottom wall 13 side with respect to the depth position of the middle part of the trench 15.

[0077] The electrode surface may have a recess that extends inward from the first side wall 11 into the trench 15. The electrode surface may also have a raised portion that extends inward from the first side wall 11 into the trench 15.

[0078] The embedded insulator 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The embedded insulator 18 may include an insulating material that is different from or the same type as the insulating material of the insulating film 16. In this embodiment, the embedded insulator 18 includes a silicon oxide film having properties different from those of the insulating film 16.

[0079] The embedded insulator 18 may have a single-layer or multi-layer structure containing at least one of the following: NSG film (Nondoped Silicate Glass film), PSG film (Phosphorus Silicon Glass film), BSG film (Boron Silicon Glass film), BPSG film (Boron Phosphorus Silicon Glass film), and TEOS film (tetraethyl orthosilicate film).

[0080] NSG film is a silicon oxide film without impurities, PSG film is a silicon oxide film containing phosphorus, BSG film is a silicon oxide film containing boron, and BPSG film is a silicon oxide film containing both phosphorus and boron.

[0081] The embedded insulator 18 preferably has a single-layer or multilayer structure including at least an NSG film. The embedded insulator 18 may have a multilayer structure including an NSG film and a PSG film (or BPSG film) stacked in this order from the embedded electrode 17 side. The embedded insulator 18 may have a multilayer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the embedded electrode 17 side. The embedded insulator 18 may have a single-layer or multilayer structure including a silicon oxide film containing the oxide of the embedded electrode 17.

[0082] The embedded insulator 18 covers the embedded electrode 17 within the trench 15. In this configuration, the embedded insulator 18 is embedded in the trench 15 via the insulating film 16 and is in contact with the insulating film 16 and the embedded electrode 17 within the trench 15. In other words, the embedded insulator 18 has a portion that faces the chip 2 in the horizontal direction via the insulating film 16.

[0083] In this configuration, the buried insulator 18 is embedded in the trench 15 below the inclined side wall 14. Specifically, the buried insulator 18 has an insulating surface located on the bottom wall 13 side relative to the lower end of the inclined side wall 14. In this configuration, the insulating surface is formed with a gap from the lower end of the inclined side wall 14 toward the bottom wall 13, exposing the upper end of the first side wall 11 and the entire area of ​​the inclined side wall 14.

[0084] The insulating surface is located on the first main surface 3 side of the trench 15 with respect to the depth position of the middle part of the trench 15. The insulating surface may also be located on the bottom wall 13 side with respect to the depth position of the middle part of the trench 15. The insulating surface exposes the upper end of the insulating film 16. In this embodiment, the insulating surface is flush with the upper end of the insulating film 16. That is, the insulating surface is formed flush with the upper end of the insulating film 16.

[0085] The insulating surface may be located on the side of the first main surface 3 or the bottom wall 13, relative to the upper end of the insulating film 16. The insulating surface may have a recess that extends inward from the first side wall 11 into the trench 15. The insulating surface may have a raised portion that extends inward from the first side wall 11 into the trench 15.

[0086] In this embodiment, the buried insulator 18 has a thickness greater than the thickness of the insulating film 16. Preferably, the thickness of the buried insulator 18 is less than the thickness of the buried electrode 17. The ratio of the thickness of the buried insulator 18 to the depth of the trench 15 may be greater than 0 and 0.5 or less. The thickness ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, and 0.4 or more and 0.5 or less. The thickness ratio may be 0.25 or less.

[0087] The semiconductor device 1A includes a plurality of mesa portions 20 demarcated on the first main surface 3 in an active region 8. Each of the plurality of mesa portions 20 is demarcated in regions between adjacent gate structures 10. The plurality of mesa portions 20 are demarcated with spacing in the first direction X and extend in a strip-like manner in the second direction Y. In other words, the plurality of mesa portions 20 extend in a stripe-like manner in the second direction Y. The width of the plurality of mesa portions 20 corresponds to the spacing of the gate structures 10.

[0088] Each of the multiple mesa sections 20 has a main surface section 21 which is part of the first main surface 3 in cross-sectional view, and a pair of inclined sections 22 which are a pair of inclined side walls 14. In other words, the main surface section 21 has a first barrier height BH1. The inclined sections 22 have a third barrier height BH3 which is lower than the first barrier height BH1, and are inclined diagonally downward from the main surface section 21 toward the gate structure 10.

[0089] In this embodiment, the multiple mesa sections 20 have a first layout example in which multiple first mesa units MU1 for transistors and multiple second mesa units MU2 for diodes are arranged alternately in a first direction X.

[0090] Each of the multiple first mesa units MU1 includes either a single first mesa portion 20A or multiple first mesa portions 20A adjacent to each other in a first direction X. The first mesa portion 20A may also be referred to as a "first area". The number of first mesa portions 20A contained within each of the multiple first mesa units MU1 (first mesa number) may be equal to each other or may be different. In this embodiment, each first mesa number is 2.

[0091] The first mesa number may be between 1 and 50. The first mesa number may have a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, and 45 to 50.

[0092] Each of the multiple second mesa units MU2 includes either a single second mesa section 20B or multiple second mesa sections 20B adjacent to each other in a first direction X. The second mesa sections 20B may also be referred to as "second areas". The number of second mesa sections 20B contained within each of the multiple second mesa units MU2 (number of second mesas) may be equal to each other or may be different.

[0093] The number of second mesas may be equal to the number of first mesas. The number of second mesas may be greater than the number of first mesas. The number of second mesas may be less than the number of first mesas. In this form, each second mesa is 1.

[0094] The number of second mesas may be between 1 and 50. The number of second mesas may have a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 15, 15 to 20, 20 to 25, 25 to 30, 30 to 35, 35 to 40, 40 to 45, and 45 to 50.

[0095] The total planar area of ​​the multiple second mesa portions 20B per unit area is less than the total planar area of ​​the multiple first mesa portions 20A per unit area. The total planar area of ​​the multiple second mesa portions 20B in the active region 8 is less than the total planar area of ​​the multiple first mesa portions 20A in the active region 8.

[0096] In this configuration, the first gate structure 10 (trench 15) demarcates first mesa portions 20A for transistors on both sides in the first direction X. The second gate structure 10 (trench 15) demarcates a first mesa portion 20A for transistors on one side in the first direction X, and a second mesa portion 20B for diodes on the other side in the first direction X.

[0097] The third gate structure 10 (trench 15) demarcates a second mesa portion 20B for a diode on one side in the first direction X, and a first mesa portion 20A for a transistor on the other side in the first direction X.

[0098] The semiconductor device 1A includes a plurality of FET structures 25 (Field Effect Transistor structures) formed in the inner portion (active region 8) of the second semiconductor layer 7. The plurality of FET structures 25 are formed in each of the plurality of first mesa portions 20A, but not in the second mesa portion 20B. In this embodiment, the plurality of FET structures 25 are formed in a one-to-one correspondence relationship with each of the plurality of first mesa portions 20A. The configuration of the FET structures 25 will be described below.

[0099] Each of the multiple FET structures 25 includes a p-type body region 26. The body region 26 may also be called an "impurity region". The body region 26 forms a bipolar diode DB with the second semiconductor layer 7. A source potential may be applied to the body region 26. The source potential may be a reference potential (for example, ground potential) that serves as the reference for circuit operation.

[0100] The body region 26 is formed in the first mesa portion 20A on the surface of the second semiconductor layer 7, and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The body region 26 is formed on the surface of the first main surface 3 and extends in the second direction Y, following the extension direction of the plurality of gate structures 10. The body region 26 is adjacent to two gate structures 10 corresponding to the first direction X.

[0101] The body region 26 is formed with a gap between the depth position of the bottom wall 13 of the multiple gate structures 10 and the first main surface 3 side. The body region 26 may have a portion located on the bottom wall 13 side with respect to the depth position of the intermediate part of the multiple gate structures 10. The body region 26 may be formed with a gap between the depth position of the intermediate part of the multiple gate structures 10 and the first main surface 3 side.

[0102] The body region 26 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 17, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the electrode surface of the embedded electrode 17. The body region 26 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 18, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the insulating surface of the embedded insulator 18.

[0103] The body region 26 has a portion facing the embedded electrode 17 in the horizontal direction and a portion facing the embedded insulator 18 in the horizontal direction. The body region 26 has portions that are along the first main surface 3, the first side wall 11 of the gate structure 10, and the inclined side wall 14 of the gate structure 10. The body region 26 has portions that are along the main surface portion 21 and the inclined portion 22 of the first mesa portion 20A.

[0104] The body region 26 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the body region 26 as the anode region.

[0105] Each of the multiple FET structures 25 contains multiple n-type source regions 27. The source regions 27 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The n-type impurity concentration of the multiple source regions 27 is higher than the p-type impurity concentration of the body region 26.

[0106] In this configuration, the multiple source regions 27 are formed at intervals on the surface of the body region 26, corresponding to the multiple first mesa portions 20A in a one-to-many correspondence, thereby changing the conductivity type of the body region 26 from p-type to n-type.

[0107] Multiple source regions 27 are formed at intervals in the second direction Y, following the direction of extension of the multiple gate structures 10. In this embodiment, the multiple source regions 27 extend in a strip shape in the second direction Y and are adjacent to two gate structures 10 in the first direction X. In this embodiment, the multiple source regions 27 have a length greater than the spacing between the gate structures 10 with respect to the second direction Y. The length of the multiple source regions 27 is greater than the width of the gate structures 10.

[0108] With respect to one and the other FET structure 25, the plurality of source regions 27 of the other structure face the plurality of source regions 27 of the one structure in the first direction X via one or more gate structures 10. The plurality of source regions 27 of the other structure may face the region between the plurality of source regions 27 of the one structure in the first direction X.

[0109] Multiple source regions 27 are formed at intervals from the bottom of the body region 26 toward the first main surface 3, and face the second semiconductor layer 7 via a part of the body region 26. Multiple source regions 27 may have portions located toward the bottom wall 13 of the multiple gate structures 10 with respect to the depth position of the intermediate part of the multiple gate structures 10. Multiple source regions 27 may be formed at intervals from the depth position of the intermediate part of the multiple gate structures 10 toward the first main surface 3.

[0110] The multiple source regions 27 have a depth greater than the thickness between the bottom of the body region 26 and the bottoms of the multiple source regions 27. The depth of the multiple source regions 27 may be less than the thickness between the bottom of the body region 26 and the bottoms of the multiple source regions 27.

[0111] Each of the multiple source regions 27 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 17, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the electrode surface of the embedded electrode 17. Each of the multiple source regions 27 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 18, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the insulating surface of the embedded insulator 18.

[0112] Each of the multiple source regions 27 has a portion facing the embedded electrode 17 in the horizontal direction and a portion facing the embedded insulator 18 in the horizontal direction. The multiple source regions 27 face the embedded electrode 17 and the embedded insulator 18 via the insulating film 16.

[0113] Each of the multiple source regions 27 has a portion that follows the first main surface 3, the first side wall 11 of the gate structure 10, and the inclined side wall 14 of the gate structure 10. Each of the multiple source regions 27 has a portion that follows the main surface portion 21 and the inclined portion 22 of the first mesa portion 20A.

[0114] Each of the multiple FET structures 25 includes multiple p-type contact regions 28. The contact regions 28 have a higher p-type impurity concentration than the body region 26. In this configuration, the multiple contact regions 28 are formed at intervals on the surface of the body region 26 corresponding to the multiple first mesa portions 20A in a one-to-many correspondence, thereby increasing the p-type impurity concentration of the corresponding body region 26.

[0115] Multiple contact regions 28 are formed at intervals in the second direction Y, following the extension direction of the multiple gate structures 10, and are adjacent to two gate structures 10 corresponding to the first direction X. Each of the multiple contact regions 28 is interposed between the multiple source regions 27 with respect to the second direction Y.

[0116] Multiple contact regions 28 may be connected to multiple source regions 27 in the second direction Y. Multiple contact regions 28 may be formed at intervals from the multiple source regions 27 in the second direction Y and may face the multiple source regions 27 via a part of the body region 26.

[0117] With respect to one and the other FET structure 25, the plurality of contact regions 28 of the other structure face the plurality of contact regions 28 of the one structure via one or more gate structures 10 in the first direction X. The plurality of contact regions 28 of the other structure may face the region between the plurality of contact regions 28 of the one structure (a plurality of source regions 27) in the first direction X.

[0118] In this embodiment, each of the multiple contact regions 28 has a length less than the length of the multiple source regions 27 with respect to the second direction Y. The length of the multiple contact regions 28 may be greater than the length of the multiple source regions 27. The length of the multiple contact regions 28 may be greater than or less than the spacing between the gate structures 10. The length of the multiple contact regions 28 may be greater than or less than the width of the gate structures 10.

[0119] In each FET structure 25, the total area of ​​the multiple contact regions 28 may be less than the total area of ​​the multiple source regions 27. The total area of ​​the multiple source regions 27 is also the channel area. The channel areas of the multiple FET structures 25 may be equal to each other or may be different. The channel area of ​​each FET structure 25 is adjusted by adjusting the area of ​​the multiple source regions 27 and the multiple contact regions 28.

[0120] Multiple contact regions 28 are formed at intervals from the bottom of the body region 26 toward the first main surface 3, and face the second semiconductor layer 7 via a part of the body region 26. Multiple contact regions 28 may have portions located toward the bottom wall 13 of the multiple gate structures 10 with respect to the depth position of the intermediate part of the multiple gate structures 10. Multiple contact regions 28 may be formed at intervals from the depth position of the intermediate part of the multiple gate structures 10 toward the first main surface 3.

[0121] The contact area 28 may have a depth greater than the depth of the source area 27. The depth of the contact area 28 may be less than the depth of the source area 27. The depth of the contact area 28 may be greater than the thickness between the bottom of the body area 26 and the bottom of the contact area 28. The depth of the contact area 28 may be less than the thickness between the bottom of the body area 26 and the bottom of the contact area 28.

[0122] Each of the multiple contact regions 28 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 17, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the electrode surface of the embedded electrode 17. Each of the multiple contact regions 28 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 18, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the insulating surface of the embedded insulator 18.

[0123] Each of the multiple contact regions 28 has a portion facing the embedded electrode 17 in the horizontal direction and a portion facing the embedded insulator 18 in the horizontal direction. The multiple contact regions 28 face the embedded electrode 17 and the embedded insulator 18 via the insulating film 16.

[0124] Each of the multiple contact areas 28 has portions that are aligned with the first main surface 3, the first side wall 11 of the gate structure 10, and the inclined side wall 14 of the gate structure 10. Each of the multiple contact areas 28 has portions that are aligned with the main surface portion 21 and the inclined portion 22 of the first mesa portion 20A.

[0125] The semiconductor device 1A includes a plurality of n-type diode regions 30 formed in the inner portion (active region 8) of the second semiconductor layer 7. The plurality of diode regions 30 are formed in each of the plurality of second mesa portions 20B, but not in the first mesa portion 20A. In this configuration, the plurality of diode regions 30 are formed in a one-to-one correspondence with the plurality of second mesa portions 20B.

[0126] In this embodiment, the diode region 30 is formed using a portion of the second semiconductor layer 7 and has an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode region 30 may be higher or lower than that of the second semiconductor layer 7.

[0127] A different potential is applied to the diode region 30 than to the gate structure 10. The diode region 30 is electrically connected to the FET structure 25, and the same potential applied to the diode region 30 as the potential applied to the FET structure 25 is applied to the diode region 30. In other words, the source potential (reference potential) is applied to the diode region 30.

[0128] The diode region 30 extends in the second direction Y, following the direction of extension of the plurality of gate structures 10, and is adjacent to two gate structures 10 corresponding to the first direction X. The diode region 30 faces a plurality of body regions 26, a plurality of source regions 27, and a plurality of contact regions 28 in the first direction X via one or more gate structures 10.

[0129] The diode region 30 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 17, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the electrode surface of the embedded electrode 17. The diode region 30 has a portion located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 18, and a portion located on the bottom wall 13 side of the gate structure 10 with respect to the insulating surface of the embedded insulator 18.

[0130] The diode region 30 has a portion facing the embedded electrode 17 in the horizontal direction and a portion facing the embedded insulator 18 in the horizontal direction. The diode region 30 faces the embedded electrode 17 and the embedded insulator 18 via the insulating film 16.

[0131] The diode region 30 has portions that follow the first main surface 3, the first side wall 11 of the gate structure 10, and the inclined side wall 14 of the gate structure 10. The diode region 30 also has portions that follow the main surface portion 21 and the inclined portion 22 of the second mesa portion 20B. The diode region 30 forms a first barrier height BH1 on the first main surface 3 (main surface portion 21), a second barrier height BH2 on the first side wall 11, and a third barrier height BH3 on the inclined side wall 14 (inclined portion 22).

[0132] The semiconductor device 1A includes a plurality of p-type well regions 35 formed in the inner portion (active region 8) of the second semiconductor layer 7. The well regions 35 may also be referred to as "gate well regions". The p-type impurity concentration in the well regions 35 may be higher or lower than the p-type impurity concentration in the body region 26. The p-type impurity concentration in the well regions 35 is lower than the p-type impurity concentration in the contact region 28. Source potentials are applied to the plurality of well regions 35.

[0133] Multiple well regions 35 are formed within the second semiconductor layer 7, spaced apart from each other in the horizontal direction (first direction X), and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Each of the multiple well regions 35 is formed in the regions below (specifically directly below) the multiple gate structures 10, and they overlap with the multiple gate structures 10 in a one-to-one correspondence in the thickness direction Z.

[0134] The multiple well regions 35 each extend in a strip-like manner in the second direction Y, following the extension direction of the corresponding gate structure 10 in a plan view. The multiple well regions 35 are arranged in a stripe-like pattern extending in the second direction Y in a plan view. The extension direction of the multiple well regions 35 coincides with the off-direction of the SiC single crystal.

[0135] With respect to the second direction Y, the ends of the multiple well regions 35 may be located inward or outward from the ends of the multiple gate structures 10. The multiple well regions 35 may be formed at intervals in the second direction Y in a one-to-many correspondence with respect to the corresponding gate structures 10. In this case, the multiple well regions 35 may extend in a strip-like manner in the second direction Y along the corresponding gate structures 10.

[0136] Multiple well regions 35 are formed in the thickness range between the bottom of the second semiconductor layer 7 and the bottom walls 13 of the multiple gate structures 10, and extend vertically in the thickness direction Z. The multiple well regions 35 are formed at intervals from the bottom of the second semiconductor layer 7 towards the bottom walls 13 of the multiple gate structures 10, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0137] Each of the multiple well regions 35 has an upper end located on the bottom wall 13 side of the corresponding gate structure 10, and a bottom located on the bottom side of the second semiconductor layer 7. The upper ends of the multiple well regions 35 are formed with a gap between the bottom of the body region 26 and the bottom wall 13 side of the corresponding gate structure 10. The upper ends of the multiple well regions 35 are connected to the bottom wall 13 of the corresponding gate structure 10 and face the embedded electrode 17 via the insulating film 16.

[0138] The upper ends of the multiple well regions 35 may have portions that follow the first sidewall 11 of the corresponding gate structure 10. That is, the multiple well regions 35 may face the embedded electrode 17 via the insulating film 16 at the first sidewall 11 of the corresponding gate structure 10. Similarly, the upper ends of the multiple well regions 35 may have portions that follow the second sidewall 12 of the corresponding gate structure 10.

[0139] The upper ends of the multiple well regions 35 may bulge out on both sides of the corresponding gate structure 10. The bottoms of the multiple well regions 35 may be located on the bottom wall 13 side of the multiple gate structures 10 or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the intermediate part of the second semiconductor layer 7. The upper ends of the multiple well regions 35 may be formed with a gap between the bottom wall 13 of the corresponding gate structure 10 and the bottom side of the second semiconductor layer 7.

[0140] In this embodiment, the depth of the well region 35 relative to the bottom wall 13 of the gate structure 10 is greater than the depth of the gate structure 10 relative to the first main surface 3. The depth of the well region 35 may also be less than the depth of the gate structure 10 relative to the first main surface 3.

[0141] The depth of the well region 35 may be greater than 0 μm and 5 μm or less. The depth of the well region 35 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0142] Multiple well regions 35 form a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the multiple well regions 35 as the anode region. The multiple well regions 35 together with the body region 26 form the bipolar diode DB.

[0143] The multiple well regions 35 may form a superjunction structure with charge balance with the second semiconductor layer 7. In this case, the depletion layer extending from the multiple well regions 35 becomes integrated in the region between the multiple well regions 35.

[0144] Each of the multiple well regions 35 may be formed by a single p-type impurity region extending in the thickness direction Z. Each of the multiple well regions 35 may be formed by a plurality of p-type impurity regions connected to each other in the thickness direction Z.

[0145] The semiconductor device 1A includes a plurality of p-type well high-concentration regions 36 formed within a plurality of well regions 35. The well high-concentration regions 36 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 26. The p-type impurity concentration of the well high-concentration regions 36 is higher than the p-type impurity concentration of the well regions 35.

[0146] The p-type impurity concentration in the high-concentration well region 36 may be approximately equal to the p-type impurity concentration in the contact region 28. The p-type impurity concentration in the high-concentration well region 36 may be higher or lower than the p-type impurity concentration in the contact region 28.

[0147] Multiple well-high-concentration regions 36 each extend in a strip-like manner in the second direction Y, following the direction of extension of the corresponding gate structure 10 (well region 35) within the multiple well regions 35. The multiple well-high-concentration regions 36 are arranged in a stripe-like pattern extending in the second direction Y when viewed from above.

[0148] With respect to the second direction Y, the ends of the multiple well high-concentration regions 36 may be located inward or outward from the ends of the multiple gate structures 10. The multiple well high-concentration regions 36 may be formed at intervals in the second direction Y in a one-to-many correspondence with respect to the corresponding gate structures 10. In this case, the multiple well high-concentration regions 36 may extend in a strip-like manner in the second direction Y along the corresponding gate structures 10.

[0149] Multiple well high-concentration regions 36 are formed in the thickness range between the bottom walls 13 of the multiple gate structures 10 and the bottoms of the multiple well regions 35. The multiple well high-concentration regions 36 are formed at the upper ends of the corresponding well regions 35, increasing the p-type impurity concentration in the well regions 35.

[0150] Multiple well-high-concentration regions 36 are formed at intervals from the bottom of the multiple well regions 35 toward the bottom wall 13 of the multiple gate structures 10, and face the second semiconductor layer 7 via a portion of the multiple well regions 35. The multiple well-high-concentration regions 36 may be located toward the bottom wall 13 of the multiple gate structures 10 or toward the bottom of the well region 35 with respect to the depth position of the intermediate portion of the corresponding well region 35.

[0151] Multiple well-high-concentration regions 36 are connected to the bottom wall 13 of the corresponding gate structure 10 and face the embedded electrode 17 via an insulating film 16. The multiple well-high-concentration regions 36 may have portions along the first side wall 11 of the corresponding gate structure 10. Similarly, the upper ends of the multiple well-high-concentration regions 36 may have portions along the second side wall 12 of the corresponding gate structure 10.

[0152] Multiple well-high-concentration regions 36 may bulge outwards from the first sidewall 11 of the corresponding gate structure 10 toward the first mesa portion 20A. Multiple well-high-concentration regions 36 may bulge outwards from the first sidewall 11 of the corresponding gate structure 10 toward the second mesa portion 20B. The depth of the well-high-concentration region 36 relative to the bottom wall 13 of the gate structure 10 is smaller than the depth of the gate structure 10 relative to the first main surface 3.

[0153] The semiconductor device 1A includes a plurality of p-type well contact regions 37 formed in the inner portion (active region 8) of the second semiconductor layer 7. The well contact regions 37 have a higher p-type impurity concentration than the body region 26. The p-type impurity concentration in the well contact regions 37 is higher than the p-type impurity concentration in the well region 35.

[0154] The p-type impurity concentration in the well contact region 37 may be approximately equal to the p-type impurity concentration in the contact region 28. The p-type impurity concentration in the well contact region 37 may be higher or lower than the p-type impurity concentration in the contact region 28.

[0155] Multiple well contact regions 37 are formed in regions along multiple gate structures 10, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. The multiple well contact regions 37 are formed at intervals in the second direction Y in a one-to-many correspondence with respect to one corresponding gate structure 10.

[0156] Multiple well contact regions 37 are formed in regions adjacent to multiple contact regions 28 in the first direction X, and are interposed in regions between multiple source regions 27 in the second direction Y. Multiple well contact regions 37 extend along the first side walls 11 and bottom walls 13 of the corresponding gate structure 10, electrically connecting the corresponding well regions 35 and well high-concentration regions 36 to the body region 26.

[0157] Each of the multiple well contact regions 37 has one or more sidewalls and a bottom wall. One or more sidewalls extend along one or both of a pair of first sidewalls 11 of the corresponding gate structure 10 and face the embedded electrode 17 via an insulating film 16.

[0158] In this configuration, the sidewall portion is formed along the first sidewall 11 on the first mesa portion 20A side, but not along the first sidewall 11 on the second mesa portion 20B side. The sidewall portion is connected to the body region 26 and increases the p-type impurity concentration of the body region 26. In this configuration, the sidewall portion is connected to one or more adjacent contact regions 28 in the first direction X.

[0159] The bottom wall portion is formed along the bottom wall 13 of the corresponding gate structure 10 and faces the embedded electrode 17 via an insulating film 16. The bottom wall portion is connected to the well region 35 and the well high-concentration region 36, increasing the p-type impurity concentration in the well region 35. The bottom wall portion extends from one or both sides of the corresponding gate structure 10 and is connected to one or more corresponding side walls.

[0160] As a result, the well contact region 37 electrically connects the corresponding well region 35 to the body region 26. The bottom wall protrudes toward the first mesa region 20A and does not protrude toward the second mesa region 20B. The bottom wall may be formed with a gap between the second mesa region 20B and the first mesa region 20A. The bottom wall may protrude toward the second mesa region 20B.

[0161] The bottom wall may have a width greater than the width of the gate structure 10. The width of the bottom wall may be less than the width of the gate structure 10. The bottom wall may have a thickness greater than the width of the side wall. The width of the side wall is the horizontal width based on the first side wall 11 of the gate structure 10, and the thickness of the bottom wall is the thickness based on the bottom wall 13 of the gate structure 10.

[0162] The semiconductor device 1A includes a p-type outer well region 40 formed in the peripheral region (outer region 9) of the second semiconductor layer 7. The p-type impurity concentration in the outer well region 40 may be higher or lower than the p-type impurity concentration in the body region 26. The p-type impurity concentration in the outer well region 40 is lower than the p-type impurity concentration in the contact region 28. A source potential is applied to the outer well region 40.

[0163] The outer well region 40 is formed on the surface of the first main surface 3 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The outer well region 40 is formed at intervals from the periphery of the first main surface 3 to the inward side of the first main surface 3 (towards the active region 8) and extends in layers along the first main surface 3.

[0164] The outer well region 40 extends in a band shape along the active region 8 in a plan view. In this configuration, the outer well region 40 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 10).

[0165] The outer well region 40 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The outer well region 40 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer well region 40 demarcates the boundary between the active region 8 and the outer region 9.

[0166] The inner edge of the outer well region 40 may be connected to either or both of the body region 26 and the well region 35. The inner edge of the outer well region 40 may also be connected to the ends (a pair of second side walls 12) of the multiple gate structures 10. The outer edge of the outer well region 40 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 40.

[0167] The outer well region 40 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The outer well region 40 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0168] In this embodiment, the outer well region 40 has a depth less than the depth of the multiple gate structures 10. The depth of the outer well region 40 may be greater than the depth of the multiple gate structures 10. The depth of the outer well region 40 may be approximately equal to the depth of the body region 26.

[0169] The depth of the outer well region 40 may be greater than or less than the depth of the body region 26. In this configuration, the depth of the outer well region 40 is less than the depth of the well region 35. The depth of the outer well region 40 may be approximately equal to the depth of the well region 35, or it may be greater than the depth of the well region 35.

[0170] The outer well region 40 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the outer well region 40 as the anode region. The outer well region 40 together with the body region 26 forms the bipolar diode DB.

[0171] When a reverse bias voltage is applied, the depletion layer extends from the outer well region 40 to the second semiconductor layer 7. The depletion layer extending from the outer well region 40 extends the depletion layer extending from the body region 26 (active region 8) to the peripheral edge of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the peripheral edge of the active region 8.

[0172] The semiconductor device 1A includes a p-type outer contact region 41 formed on the surface of the outer well region 40. The outer contact region 41 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 40.

[0173] The p-type impurity concentration in the outer contact region 41 is higher than that in the body region 26. The p-type impurity concentration in the outer contact region 41 may be approximately equal to that in the contact region 28. The p-type impurity concentration in the outer contact region 41 may be greater or less than that in the contact region 28.

[0174] The outer contact region 41 extends in a band shape along the outer well region 40 in a plan view. In this configuration, the outer contact region 41 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 10).

[0175] The outer contact region 41 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape). The semiconductor device 1A may include a plurality of outer contact regions 41. In this case, the plurality of outer contact regions 41 may be formed with spacing between them following the extending direction of the outer well region 40.

[0176] The outer contact region 41 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. In this embodiment, the inner edge of the outer contact region 41 is formed at intervals from the plurality of gate structures 10 on the peripheral side of the first main surface 3. The inner edge of the outer contact region 41 may be connected to the plurality of gate structures 10. In this case, the inner edge of the outer contact region 41 may be connected to the body region 26.

[0177] The outer edge of the outer contact region 41 is formed with a gap between it and the periphery of the first main surface 3, on the inward side of the first main surface 3. In this configuration, the outer edge of the outer contact region 41 is formed with a gap between it and the outer edge of the outer well region 40, on the inward side of the first main surface 3, and extends substantially parallel to the inner edge of the outer contact region 41.

[0178] The outer contact region 41 is formed at a distance from the bottom of the outer well region 40 toward the first main surface 3, and faces the second semiconductor layer 7 via a portion of the outer well region 40. The outer contact region 41 has a depth less than the depth of the multiple gate structures 10. The depth of the outer contact region 41 is less than the depth of the body region 26. The depth of the outer contact region 41 may be greater than the depth of the body region 26.

[0179] The semiconductor device 1A includes at least one (or more in this embodiment) p-type field region 42 formed on the surface of the first main surface 3 at the peripheral edge (outer region 9) of the second semiconductor layer 7. The multiple field regions 42 may be formed in an electrically floating state. The multiple field regions 42 may be fixed to the source potential.

[0180] The number of field regions 42 may be between 1 and 20. The number of field regions 42 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 42 is between 1 and 8. In this embodiment, the semiconductor device 1A includes 6 field regions 42.

[0181] Multiple field regions 42 have a p-type impurity concentration lower than that of the outer contact region 41. The p-type impurity concentration of the multiple field regions 42 may be approximately equal to that of the outer well region 40. The p-type impurity concentration of the multiple field regions 42 may be higher or lower than that of the outer well region 40.

[0182] The p-type impurity concentrations in the multiple field regions 42 are lower than the p-type impurity concentrations in the contact region 28. The p-type impurity concentrations in the multiple field regions 42 may be higher or lower than the p-type impurity concentrations in the body region 26. The p-type impurity concentrations in the multiple field regions 42 may be approximately equal to the p-type impurity concentrations in the well region 35. The p-type impurity concentrations in the multiple field regions 42 may be higher or lower than the p-type impurity concentrations in the well region 35.

[0183] Multiple field regions 42 are formed at intervals from each other on the surface of the second semiconductor layer 7 at the periphery of the first main surface 3, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Multiple field regions 42 are formed at intervals from the periphery of the first main surface 3 and the active region 8, in the region between the periphery of the first main surface 3 and the active region 8. Multiple field regions 42 are formed at intervals from the outer well region 40 toward the periphery of the first main surface 3.

[0184] The multiple field regions 42 extend in a band shape along the outer well region 40 in a plan view. In this embodiment, the multiple field regions 42 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 10). The multiple field regions 42 may have edge portions that connect the portion extending in a band shape in the first direction X and the portion extending in a band shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0185] Multiple field regions 42 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 through a portion of the second semiconductor layer 7. The multiple field regions 42 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0186] In this embodiment, the multiple field regions 42 have a depth greater than the depth of the body region 26. The depth of the multiple field regions 42 may be approximately equal to the depth of the body region 26. In this embodiment, the depth of the multiple field regions 42 is greater than the depth of the multiple gate structures 10. The depth of the multiple field regions 42 may be less than the depth of the multiple gate structures 10.

[0187] The depth of the multiple field regions 42 is greater than the depth of the outer contact region 41. The depth of the multiple field regions 42 is greater than the depth of the outer well region 40. The depth of the multiple field regions 42 may be approximately equal to the depth of the outer well region 40. The depth of the multiple field regions 42 may be less than the depth of the outer well region 40.

[0188] Multiple field regions 42 form a pn junction with the second semiconductor layer 7. When a reverse bias voltage is applied, multiple depletion layers spread from the multiple field regions 42 to the second semiconductor layer 7. The depletion layers spreading from the multiple field regions 42 extend the depletion layer spreading from the outer well region 40 (active region 8) toward the periphery of the first main surface 3, thereby mitigating the electric field strength (electric field concentration) at the periphery of the first main surface 3.

[0189] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 42 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 42 may be approximately constant or non-uniform. The width of the multiple field regions 42 may gradually increase or decrease toward the periphery of the first main surface 3.

[0190] The depths of the multiple field regions 42 may be approximately constant or non-uniform. The depths of the multiple field regions 42 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 42 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0191] The spacing between the multiple field regions 42 may be approximately constant or non-uniform. The spacing between the multiple field regions 42 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 42 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 42 may gradually increase or decrease toward the periphery of the first main surface 3.

[0192] The semiconductor device 1A includes an insulating interlayer film 45 that selectively covers the first main surface 3. In this embodiment, the interlayer film 45 has a laminated structure including a first interlayer film 46 and a second interlayer film 47. The first interlayer film 46 may be referred to as the "main surface insulating film" or "lower insulating film," and the second interlayer film 47 may be referred to as the "upper insulating film."

[0193] The first interlayer film 46 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 46 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The first interlayer film 46 may include a silicon oxide film containing oxides other than the oxide of the chip 2. The first interlayer film 46 may include an insulator of the same type as the insulating film 16.

[0194] The first interlayer film 46 selectively covers the first main surface 3 in a film-like manner in the active region 8 and the outer region 9. The first interlayer film 46 covers the first main surface 3 at the periphery of the active region 8, exposing a plurality of gate structures 10. Specifically, the first interlayer film 46 is connected to a plurality of insulating films 16, exposing a plurality of embedded insulators 18.

[0195] The first interlayer film 46 forms a single insulating film integral with the plurality of insulating films 16. The first interlayer film 46 has portions that cover the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) in the regions between the plurality of gate structures 10 (plural mesa portions 20).

[0196] The first interlayer membrane 46 covers the outer well region 40, the outer contact region 41, and multiple field regions 42 in the outer region 9. The first interlayer membrane 46 is continuous with the first to fourth side surfaces 5A to 5D. The first interlayer membrane 46 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0197] The first interlayer film 46 may have a thickness approximately equal to the thickness of the plurality of insulating films 16. The thickness of the first interlayer film 46 may be greater than 0 nm and 250 nm or less. The thickness of the first interlayer film 46 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0198] The second interlayer film 47 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 47 may have a single-layer structure or a multilayer structure containing at least one of an NSG film, a PSG film, a BSG film, a BPSG film, and a TEOS film. It is preferable that the second interlayer film 47 has a single-layer structure or a multilayer structure containing at least an NSG film.

[0199] The second interlayer film 47 may have a laminated structure including an NSG film and a PSG film (or BPSG film) stacked in this order from the chip 2 side. The second interlayer film 47 may have a laminated structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. The second interlayer film 47 may contain an insulator of the same type as the embedded insulator 18. The second interlayer film 47 may contain an insulator of the same type as the first interlayer film 46.

[0200] The second interlayer membrane 47 covers the first interlayer membrane 46 in a film-like manner in the active region 8 and the outer region 9. The second interlayer membrane 47 covers a plurality of gate structures 10 at the periphery of the active region 8. Specifically, the second interlayer membrane 47 penetrates a plurality of trenches 15 from above the first interlayer membrane 46 and covers a plurality of embedded electrodes 17 within the plurality of trenches 15.

[0201] The second interlayer membrane 47 is connected to a plurality of buried insulators 18 within the trench 15. In this embodiment, the second interlayer membrane 47 is integrally formed with the plurality of buried insulators 18. The connection portion of the second interlayer membrane 47 to the plurality of buried insulators 18 may be considered as part of the plurality of buried insulators 18, or as part of the second interlayer membrane 47.

[0202] The second interlayer membrane 47 has a portion that covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the first interlayer membrane 46 in the region between the multiple gate structures 10 (multiple mesa portions 20).

[0203] The second interlayer membrane 47 covers the first main surface 3 via the first interlayer membrane 46 in the outer region 9. Specifically, the second interlayer membrane 47 covers the outer well region 40, the outer contact region 41, and a plurality of field regions 42 via the first interlayer membrane 46. The second interlayer membrane 47 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the second interlayer membrane 47 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the first interlayer membrane 46.

[0204] The second interlayer membrane 47 has a thickness greater than the thickness of the first interlayer membrane 46. The thickness of the second interlayer membrane 47 may be greater than 0 μm and 5 μm or less. The thickness of the second interlayer membrane 47 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0205] The semiconductor device 1A includes one or more (one in this embodiment) gate wiring 50 selectively routed to the outer region 9. The gate wiring 50 is electrically connected to the plurality of gate structures 10 and provides gate potentials to the plurality of gate structures 10.

[0206] The gate wiring 50 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 50 contains the same conductive material as the conductive material of the embedded electrode 17.

[0207] The gate wiring 50 is located within the interlayer film 45. Specifically, the gate wiring 50 is located on the first interlayer film 46 and covered by the second interlayer film 47. The gate wiring 50 is spaced apart from the periphery of the first main surface 3 towards the active region 8. The gate wiring 50 is formed spaced apart from multiple field regions 42 (the innermost field region 42).

[0208] The gate wiring 50 is positioned at a distance from the outer edge of the outer well region 40. The gate wiring 50 is positioned at a distance from the outer edge of the outer contact region 41. In a plan view, the gate wiring 50 extends in a strip shape along the active region 8.

[0209] In this embodiment, the gate wiring 50 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 10). The gate wiring 50 may also be formed in the shape of an ended strip. The gate wiring 50 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0210] The gate wiring 50 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the gate wiring 50 is mechanically and electrically connected to the ends (a pair of second side walls 12) of the multiple gate structures 10. Specifically, the inner edge of the gate wiring 50 enters into the multiple trenches 15 from above the first interlayer membrane 46 and is mechanically and electrically connected to the multiple embedded electrodes 17 within the multiple trenches 15.

[0211] In this configuration, the gate wiring 50 is integrally formed with the multiple buried electrodes 17 as the lead-out portion of the multiple buried electrodes 17. The connection portion of the gate wiring 50 to the multiple buried electrodes 17 may be considered as part of the multiple buried electrodes 17, or as part of the gate wiring 50.

[0212] The inner edge of the gate wiring 50 has a portion that covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the first interlayer film 46 in the region between the multiple gate structures 10 (multiple mesa portions 20).

[0213] The semiconductor device 1A includes one or more (one in this embodiment) source openings 51 formed in the interlayer film 45 in the active region 8. The source openings 51 penetrate the interlayer film 45 and expose together a plurality of gate structures 10 and a plurality of mesa portions 20 (a plurality of first mesa portions 20A and a plurality of second mesa portions 20B). Specifically, the source openings 51 expose a plurality of embedded insulators 18, a body region 26, a plurality of source regions 27, a plurality of contact regions 28, and a plurality of diode regions 30.

[0214] The semiconductor device 1A includes one or more (in this embodiment, more than one) gate openings 52 formed in the interlayer film 45 in the outer region 9. The multiple gate openings 52 penetrate the interlayer film 45 and selectively expose the gate wiring 50.

[0215] In this configuration, the multiple gate openings 52 extend in a strip-like shape following the direction of extension of the gate wiring 50. The multiple gate openings 52 may be formed at intervals in the direction of extension of the gate wiring 50. The multiple gate openings 52 may be formed in a polygonal or circular shape in plan view. The multiple gate structures 10 may be formed in a square or hexagonal shape in plan view.

[0216] The multiple gate openings 52 may have portions that extend in a strip shape in a first direction X and portions that extend in a strip shape in a second direction Y when viewed from above. The multiple gate openings 52 may have edge portions that connect the portions that extend in the first direction X and the portions that extend in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above. The semiconductor device 1A may include one gate opening 52 that extends in a strip shape along the gate wiring 50.

[0217] The semiconductor device 1A includes one or more (one in this embodiment) outer openings 53 formed in the interlayer film 45. The outer openings 53 are formed with a gap from the gate wiring 50 toward the periphery of the first main surface 3 and with a gap from the periphery of the first main surface 3 toward the inward side of the first main surface 3. The outer openings 53 are formed with a gap from a plurality of field regions 42 (the innermost field region 42) toward the inward side of the first main surface 3.

[0218] The outer opening 53 penetrates the first interlayer membrane 46 and exposes the outer contact region 41. In this embodiment, the outer opening 53 has a width less than the width of the outer contact region 41 and exposes the inner portion of the outer contact region 41 at a distance from its inner and outer edges. The outer opening 53 may also expose the outer well region 40.

[0219] The outer opening 53 extends in a strip shape following the direction of extension of the outer well region 40. The outer opening 53 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the outer opening 53 is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 10).

[0220] The outer opening 53 may be formed in the shape of a strip with ends. The outer opening 53 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed in plan.

[0221] The semiconductor device 1A may include a plurality of outer openings 53. In this case, the plurality of outer openings 53 may be formed at intervals in the extending direction of the outer well region 40. The plurality of outer openings 53 may be formed in a polygonal or circular shape in plan view. The plurality of outer openings 53 may be formed in a square or hexagonal shape in plan view.

[0222] The semiconductor device 1A includes a source electrode 55 positioned in the inner portion (active region 8) of the first main surface 3. The source electrode 55 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source pad electrode," etc. The source electrode 55 is made of metal and is positioned on the interlayer film 45.

[0223] In this configuration, the source electrode 55 has a first pad portion 55a, a second pad portion 55b, and a third pad portion 55c. The first pad portion 55a has a relatively large surface area and forms the main body of the source electrode 55. In this configuration, the first pad portion 55a is formed in a polygonal shape (a quadrilateral shape in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the second side surface 5B with respect to the central part of the first main surface 3.

[0224] The second pad portion 55b has a flat area less than that of the first pad portion 55a and extends in a strip-like (square-shaped) manner from one end of the first pad portion 55a in the first direction X (the end on the first side surface 5A side) toward the fourth side surface 5D. The third pad portion 55c has a flat area less than that of the first pad portion 55a and extends in a strip-like (square-shaped) manner from the other end of the first pad portion 55a in the second direction Y (the end on the third side surface 5C side) toward the fourth side surface 5D, and faces the second pad portion 55b in the second direction Y.

[0225] The flat area of ​​the third pad portion 55c may be approximately equal to the flat area of ​​the second pad portion 55b. The flat area of ​​the third pad portion 55c may be larger or smaller than the flat area of ​​the second pad portion 55b. Either or both of the second pad portion 55b and the third pad portion 55c may be used as terminal portions for current monitoring.

[0226] The source electrode 55 may have only one of the second pad portion 55b and the third pad portion 55c. The source electrode 55 may consist only of the first pad portion 55a and may not have both the second pad portion 55b and the third pad portion 55c.

[0227] The source electrode 55 enters the source opening 51 from above the interlayer film 45 and collectively covers the multiple gate structures 10 and the multiple mesa portions 20 in a film-like manner. The source electrode 55 is electrically insulated from the multiple gate structures 10 and is mechanically and electrically connected to the multiple mesa portions 20. The source electrode 55 is formed as a first planar electrode for the first mesa portion 20A and as a second planar electrode for the second mesa portion 20B.

[0228] The source electrode 55 is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via a plurality of first mesa portions 20A. In this configuration, the source electrode 55 is mechanically and electrically connected to the c-face and m-face of a plurality of step surfaces S via the inclined side wall 14 (inclined portion 22) on the first mesa portion 20A side.

[0229] The source electrode 55 is mechanically and electrically connected to a plurality of body regions 26, a plurality of source regions 27, and a plurality of contact regions 28 by its first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22). The source electrode 55 forms ohmic contact with the plurality of source regions 27 and the plurality of contact regions 28.

[0230] The source electrode 55 enters into the trenches 15 via the inclined side walls 14 and covers the insulating surfaces of the embedded insulators 18. In this configuration, the source electrode 55 has a portion that covers the first side wall 11 within the trenches 15, and is mechanically and electrically connected to the body regions 26, source regions 27, and contact regions 28 at the first side wall 11. The source electrode 55 forms ohmic contact with the source regions 27 and contact regions 28 at the first side wall 11.

[0231] The source electrode 55 is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via a plurality of second mesa portions 20B. In this configuration, the source electrode 55 is mechanically and electrically connected to the c-face and m-face of a plurality of step surfaces S via the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B.

[0232] The source electrode 55 forms Schottky junctions with the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) at multiple second mesa portions 20B. In other words, in this embodiment, the source electrode 55 forms Schottky junctions with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0233] Specifically, the source electrode 55 covers the c-plane and m-plane of the multiple step surfaces S with its inclined sidewall 14 (inclined portion 22), forming a Schottky junction with the c-plane and m-plane of the multiple step surfaces S (see also Figure 11). In this configuration, the source electrode 55 forms a Schottky junction with the multiple diode regions 30.

[0234] The source electrode 55 enters into the trenches 15 via the inclined side walls 14 and covers the insulating surfaces of the embedded insulators 18. In this configuration, the source electrode 55 is mechanically and electrically connected to the first side wall 11 within the trenches 15.

[0235] In this embodiment, the source electrode 55 has a portion that forms a Schottky junction with the first sidewall 11 having a second barrier height BH2. In this embodiment, the source electrode 55 forms a Schottky junction with the diode region 30 at the first sidewall 11. This forms a unipolar diode DU including a plurality of second mesa portions 20B (diode regions 30) as cathode regions and the source electrode 55 as an anode region.

[0236] In other words, in this configuration, a bipolar diode DB is formed in the first mesa portion 20A, and a unipolar diode DU is formed in the second mesa portion 20B. The unipolar diode DU is connected in parallel to the bipolar diode DB and, together with the bipolar diode DB, constitutes a freewheeling diode for multiple FET structures 25.

[0237] With respect to each second mesa portion 20B, the Schottky junction area of ​​the source electrode 55 with respect to one inclined side wall 14 (inclined portion 22) is smaller than the Schottky junction area of ​​the source electrode 55 with respect to the first main surface 3 (main surface portion 21). The Schottky junction area with respect to one inclined side wall 14 (inclined portion 22) may be larger than the Schottky junction area with respect to the first main surface 3 (main surface portion 21).

[0238] With respect to each second mesa portion 20B, it is preferable that the Schottky bonding area of ​​the source electrode 55 with respect to the pair of inclined side walls 14 (inclined portion 22) is smaller than the Schottky bonding area of ​​the source electrode 55 with respect to the first main surface 3 (main surface portion 21). The Schottky bonding area with respect to the pair of inclined side walls 14 (inclined portion 22) may be larger than the Schottky bonding area with respect to the first main surface 3 (main surface portion 21).

[0239] The Schottky bonding area with respect to the first side wall 11 is preferably smaller than the Schottky bonding area with respect to the inclined side wall 14 (inclined portion 22). Of course, the Schottky bonding area with respect to the first side wall 11 may be larger than the Schottky bonding area with respect to the inclined side wall 14 (inclined portion 22).

[0240] In this case, it is preferable that the Schottky bonding area with respect to the first side wall 11 is smaller than the total Schottky bonding area with respect to the first main surface 3 (main surface portion 21) and one inclined side wall 14 (inclined portion 22). The area ratio of the Schottky bonding area with respect to the one inclined side wall 14 (inclined portion 22) to the Schottky bonding area with respect to the first side wall 11 may be greater than 1 and less than or equal to 2.

[0241] The area ratio may be greater than 1 and fall within at least one of the following ranges: 1.1 or less, 1.1 or more and 1.2 or less, 1.2 or more and 1.3 or less, 1.3 or more and 1.4 or less, 1.4 or more and 1.5 or less, 1.5 or more and 1.6 or less, 1.6 or more and 1.7 or less, 1.7 or more and 1.8 or less, 1.8 or more and 1.9 or less, and 1.9 or more and 2 or less. Preferably, the area ratio is 1.25 or less.

[0242] The source electrode 55 has a peripheral portion that faces the ends (a pair of second side walls 12) of the multiple gate structures 10 via the interlayer film 45. The peripheral portion of the source electrode 55 is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 45 and gate wiring 50. The peripheral portion of the source electrode 55 faces the outer well region 40 in the stacking direction.

[0243] The peripheral edge of the source electrode 55 is formed with a gap between it and the active region 8 from the multiple field regions 42. The peripheral edge of the source electrode 55 is formed with a gap between it and the active region 8 from the outer edge of the outer well region 40. The peripheral edge of the source electrode 55 is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 41.

[0244] The peripheral edge of the source electrode 55 may be formed with a gap between it and the inner edge of the outer contact region 41 toward the active region 8. The peripheral edge of the source electrode 55 is formed with a gap between it and the outer edge of the gate wiring 50 toward the active region 8. The peripheral edge of the source electrode 55 may be located on top of the outer contact region 41.

[0245] The source electrode 55 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source electrode 55 may contain a metal film comprising at least one of the following: magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0246] The source electrode 55 may include an alloy film containing at least one of the following: magnesium alloy, aluminum alloy, titanium alloy, vanadium alloy, chromium alloy, manganese alloy, cobalt alloy, nickel alloy, copper alloy, zirconium alloy, niobium alloy, molybdenum alloy, palladium alloy, silver alloy, indium alloy, tin alloy, tantalum alloy, tungsten alloy, platinum alloy, and gold alloy.

[0247] In this embodiment, the source electrode 55 has a laminated structure including a base electrode 56 and a main electrode 57 stacked in this order from the first main surface 3 side. The base electrode 56 is formed as a barrier electrode for the second semiconductor layer 7 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0248] In this embodiment, the base electrode 56 has a laminated structure including a first electrode 56a and a second electrode 56b. The first electrode 56a consists of a metal film containing any one of the aforementioned metals or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 56a consists of a titanium film.

[0249] The first electrode 56a penetrates the source opening 51 from above the interlayer film 45. The first electrode 56a has a portion that covers the interlayer film 45 in a film-like manner, a portion that covers the wall surface of the source opening 51 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner.

[0250] The first electrode 56a collectively covers the multiple gate structures 10 and the multiple mesa portions 20 (multiple first mesa portions 20A and multiple second mesa portions 20B) within the source opening 51 in a film-like manner. The first electrode 56a is electrically insulated from the multiple gate structures 10 and is mechanically and electrically connected to the multiple mesa portions 20.

[0251] The first electrode 56a is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 by a plurality of first mesa portions 20A. In this configuration, the first electrode 56a is mechanically and electrically connected to the c-face and m-face of a plurality of step surfaces S by the inclined side wall 14 (inclined portion 22).

[0252] The first electrode 56a is mechanically and electrically connected to a plurality of body regions 26, a plurality of source regions 27, and a plurality of contact regions 28 by its first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22). The first electrode 56a forms ohmic contact with the plurality of source regions 27 and the plurality of contact regions 28.

[0253] The first electrode 56a enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18. In this configuration, the first electrode 56a has a portion that covers the multiple first side walls 11 and is mechanically and electrically connected to the multiple body regions 26, the multiple source regions 27, and the multiple contact regions 28 at the multiple first side walls 11. The first electrode 56a forms ohmic contact with the multiple source regions 27 and the multiple contact regions 28 at the first side walls 11.

[0254] The first electrode 56a is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 by a plurality of second mesa portions 20B. The first electrode 56a forms Schottky junctions with both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) by a plurality of second mesa portions 20B.

[0255] In other words, in this configuration, the first electrode 56a forms a Schottky junction with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0256] In this configuration, the first electrode 56a is mechanically and electrically connected to the c-plane and m-plane of the multiple step surfaces S at the inclined side wall 14 (inclined portion 22) (see also Figure 11). Specifically, the first electrode 56a forms a Schottky junction with the c-plane and m-plane of the multiple step surfaces S. In this configuration, the first electrode 56a also forms a Schottky junction with the multiple diode regions 30.

[0257] With respect to each second mesa portion 20B, the Schottky junction area of ​​the first electrode 56a with respect to one inclined side wall 14 (inclined portion 22) is smaller than the Schottky junction area of ​​the first electrode 56a with respect to the first main surface 3 (main surface portion 21). The Schottky junction area with respect to one inclined side wall 14 (inclined portion 22) may be larger than the Schottky junction area with respect to the first main surface 3 (main surface portion 21).

[0258] With respect to each second mesa portion 20B, it is preferable that the Schottky bonding area of ​​the first electrode 56a with respect to the pair of inclined side walls 14 (inclined portion 22) is smaller than the Schottky bonding area of ​​the first electrode 56a with respect to the first main surface 3 (main surface portion 21). The Schottky bonding area with respect to the pair of inclined side walls 14 (inclined portion 22) may be larger than the Schottky bonding area with respect to the first main surface 3 (main surface portion 21).

[0259] The Schottky bonding area with respect to the first side wall 11 is preferably smaller than the Schottky bonding area with respect to the inclined side wall 14 (inclined portion 22). Of course, the Schottky bonding area with respect to the first side wall 11 may be larger than the Schottky bonding area with respect to the inclined side wall 14 (inclined portion 22).

[0260] In this case, it is preferable that the Schottky bonding area with respect to the first side wall 11 is smaller than the total Schottky bonding area with respect to the first main surface 3 (main surface portion 21) and one inclined side wall 14 (inclined portion 22). The area ratio of the Schottky bonding area with respect to the one inclined side wall 14 (inclined portion 22) to the Schottky bonding area with respect to the first side wall 11 may be greater than 1 and 2 or less.

[0261] The area ratio may be greater than 1 and fall within at least one of the following ranges: 1.1 or less, 1.1 or more and 1.2 or less, 1.2 or more and 1.3 or less, 1.3 or more and 1.4 or less, 1.4 or more and 1.5 or less, 1.5 or more and 1.6 or less, 1.6 or more and 1.7 or less, 1.7 or more and 1.8 or less, 1.8 or more and 1.9 or less, and 1.9 or more and 2 or less. Preferably, the area ratio is 1.25 or less.

[0262] The first electrode 56a has a peripheral edge that faces the ends (a pair of second side walls 12) of the multiple gate structures 10 via the interlayer film 45. The peripheral edge of the first electrode 56a is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 45 and gate wiring 50. The peripheral edge of the first electrode 56a faces the outer well region 40 in the stacking direction.

[0263] The peripheral edge of the first electrode 56a is formed with a gap between it and the active region 8 from the multiple field regions 42. The peripheral edge of the first electrode 56a is formed with a gap between it and the active region 8 from the outer edge of the outer well region 40. The peripheral edge of the first electrode 56a is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 41.

[0264] The peripheral edge of the first electrode 56a may be formed with a gap between it and the inner edge of the outer contact region 41 toward the active region 8. The peripheral edge of the first electrode 56a is formed with a gap between it and the outer edge of the gate wiring 50 toward the active region 8. The peripheral edge of the first electrode 56a may be located on the outer contact region 41.

[0265] The first electrode 56a has a thickness less than the thickness of the interlayer film 45. The thickness of the first electrode 56a may be greater than 0 nm and 100 nm or less. The thickness of the first electrode 56a may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0266] The second electrode 56b consists of a metal film containing one of the aforementioned metals or an alloy film containing one of the aforementioned alloys. The second electrode 56b consists of a different metal film or alloy film than the first electrode 56a. In this embodiment, the second electrode 56b consists of a titanium nitride film (titanium alloy film).

[0267] The second electrode 56b covers the first electrode 56a in a film-like manner and penetrates the source opening 51 from above the interlayer film 45. The second electrode 56b has a portion that covers the interlayer film 45 in a film-like manner via the first electrode 56a, a portion that covers the wall surface of the source opening 51 in a film-like manner via the first electrode 56a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 56a. The second electrode 56b covers multiple gate structures 10 and multiple mesa portions 20 collectively in a film-like manner via the first electrode 56a and is electrically connected to the multiple mesa portions 20.

[0268] The second electrode 56b covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the first electrode 56a with multiple first mesa portions 20A, and is electrically connected to multiple body regions 26, multiple source regions 27, and multiple contact regions 28. In this configuration, the second electrode 56b covers the c-face and m-face of multiple step surfaces S via the first electrode 56a with the inclined side wall 14 (inclined portion 22) on the first mesa portion 20A side.

[0269] The second electrode 56b enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18 via the first electrode 56a. In this configuration, the second electrode 56b has a portion that covers the multiple first side walls 11 via the first electrode 56a, and is electrically connected to the multiple body regions 26, multiple source regions 27, and multiple contact regions 28 via the first electrode 56a at the multiple first side walls 11.

[0270] The second electrode 56b covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the first electrode 56a with multiple second mesa portions 20B, and is electrically connected to multiple second mesa portions 20B (multiple diode regions 30).

[0271] In this configuration, the second electrode 56b covers the c-face and m-face of the multiple step surfaces S via the first electrode 56a on the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B, and is electrically connected to the c-face and m-face of the multiple step surfaces S via the first electrode 56a (see also Figure 11).

[0272] The second electrode 56b has a peripheral edge that faces the ends (a pair of second side walls 12) of the multiple gate structures 10 via the interlayer film 45. The peripheral edge of the second electrode 56b is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 45 and gate wiring 50. The peripheral edge of the second electrode 56b faces the outer well region 40 in the stacking direction.

[0273] The peripheral edge of the second electrode 56b is formed with a gap between it and the active region 8 from the multiple field regions 42. The peripheral edge of the second electrode 56b is formed with a gap between it and the active region 8 from the outer edge of the outer well region 40. The peripheral edge of the second electrode 56b is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 41.

[0274] The peripheral edge of the second electrode 56b may be formed with a gap between it and the inner edge of the outer contact region 41 toward the active region 8. The peripheral edge of the second electrode 56b is formed with a gap between it and the outer edge of the gate wiring 50 toward the active region 8. The peripheral edge of the second electrode 56b may be located on the outer contact region 41.

[0275] The second electrode 56b has a thickness less than the thickness of the interlayer film 45. In this embodiment, the thickness of the second electrode 56b is greater than the thickness of the first electrode 56a. The thickness of the second electrode 56b may be less than the thickness of the first electrode 56a. The thickness of the second electrode 56b may be greater than 0 nm and 300 nm or less.

[0276] The thickness of the second electrode 56b may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0277] The main electrode 57 consists of a metal film containing one of the aforementioned metals, an alloy film containing one of the aforementioned alloys, or a nonmetallic conductive film containing one of the aforementioned nonmetallic conductors. The main electrode 57 is made of a different conductor than the first electrode 56a and the second electrode 56b. In this embodiment, the main electrode 57 is made of an aluminum alloy. The aluminum alloy may contain at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0278] The main electrode 57 covers the base electrode 56 in a film-like manner and enters the source opening 51 from above the interlayer film 45. The main electrode 57 has a portion that covers the interlayer film 45 in a film-like manner via the base electrode 56, a portion that covers the wall surface of the source opening 51 in a film-like manner via the base electrode 56, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 56. Within the source opening 51, the main electrode 57 collectively covers multiple gate structures 10 and multiple mesa portions 20 in a film-like manner via the base electrode 56 and is electrically connected to the multiple mesa portions 20.

[0279] The main electrode 57 covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the base electrode 56 with multiple first mesa portions 20A, and is electrically connected to multiple body regions 26, multiple source regions 27, and multiple contact regions 28. In this configuration, the main electrode 57 covers the c-face and m-face of multiple step surfaces S via the base electrode 56 with the inclined side wall 14 (inclined portion 22) on the first mesa portion 20A side.

[0280] The main electrode 57 enters into the trenches 15 via the inclined side walls 14 and covers the insulating surfaces of the embedded insulators 18 via the base electrode 56. In this configuration, the main electrode 57 has a portion that covers the first side walls 11 via the base electrode 56, and is electrically connected to the body regions 26, source regions 27, and contact regions 28 via the base electrode 56 at the first side walls 11.

[0281] The main electrode 57 covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) via the base electrode 56 with multiple second mesa portions 20B, and is electrically connected to multiple second mesa portions 20B (multiple diode regions 30).

[0282] In this configuration, the main electrode 57 covers the c-plane and m-plane of the multiple step surfaces S via the base electrode 56 on the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B, and is electrically connected to the c-plane and m-plane of the multiple step surfaces S via the base electrode 56 (see also Figure 11).

[0283] The main electrode 57 has a peripheral edge that faces the ends (a pair of second side walls 12) of the multiple gate structures 10 via the interlayer film 45. The peripheral edge of the main electrode 57 is drawn out from the active region 8 to the outer region 9 and faces the first main surface 3 via the interlayer film 45 and gate wiring 50. The peripheral edge of the main electrode 57 faces the outer well region 40 in the stacking direction.

[0284] The peripheral edge of the main electrode 57 is formed with a gap between it and the active region 8 from the multiple field regions 42. The peripheral edge of the main electrode 57 is formed with a gap between it and the active region 8 from the outer edge of the outer well region 40. The peripheral edge of the main electrode 57 is formed with a gap between it and the active region 8 from the outer edge of the outer contact region 41.

[0285] The peripheral edge of the main electrode 57 may be formed with a gap between it and the inner edge of the outer contact region 41 toward the active region 8. The peripheral edge of the main electrode 57 is formed with a gap between it and the outer edge of the gate wiring 50 toward the active region 8. The peripheral edge of the main electrode 57 may be located on top of the outer contact region 41.

[0286] The main electrode 57 has a thickness greater than the thickness of the base electrode 56 (the total thickness of the first electrode 56a and the second electrode 56b). In this embodiment, the thickness of the main electrode 57 is greater than the thickness of the interlayer film 45. The thickness of the main electrode 57 may be less than the thickness of the interlayer film 45. The thickness of the main electrode 57 may be greater than 0 μm and 5 μm or less.

[0287] The thickness of the main electrode 57 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0288] The semiconductor device 1A includes a source finger 60 drawn out from the source electrode 55 onto the first main surface 3. The source finger 60 may also be called a "source wiring," "source finger electrode," etc. The source finger 60 is made of metal. The source finger 60 transmits the source potential applied to the source electrode 55 to other regions.

[0289] The source finger 60 is drawn out from the first pad portion 55a of the source electrode 55 onto the interlayer film 45. The source finger 60 is routed around the periphery of the first main surface 3 and the region between the source electrode 55, extending in a band shape along the active region 8. In this embodiment, the source finger 60 is drawn out from the side of the first pad portion 55a on the second side surface 5B side onto the outer opening 53.

[0290] The source finger 60 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y when viewed from above. In this embodiment, the source finger 60 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 55. The source finger 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0291] The source finger 60 enters the outer opening 53 from above the interlayer film 45 and is electrically connected to the outer contact region 41 within the outer opening 53. As a result, the source potential applied to the source electrode 55 is applied to the outer well region 40 via the outer contact region 41.

[0292] The source finger 60 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the source finger 60 is spaced apart from the plurality of gate structures 10 on the peripheral side of the first main surface 3 and faces the outer well region 40 in the stacking direction. The inner edge of the source finger 60 is spaced apart from the gate wiring 50 on the peripheral side of the first main surface 3.

[0293] The inner edge of the source finger 60 may be formed with a gap extending from the middle of the outer well region 40 towards the periphery of the first main surface 3. The inner edge of the source finger 60 may also face the outer contact region 41 in the stacking direction.

[0294] The outer edge of the source finger 60 is formed with a gap between it and the multiple field regions 42 on the inward side of the first main surface 3. This prevents the dispersion path of the electric field from being shielded by the source finger 60, and allows the electric field (electric field lines) to be appropriately dispersed by the multiple field regions 42.

[0295] In this configuration, the outer edge of the source finger 60 is formed at a distance from the outer edge of the outer well region 40 toward the inward side of the first main surface 3, and extends substantially parallel to the inner edge of the source finger 60.

[0296] The outer edge of the source finger 60 is located on the outer well region 40. The outer edge of the source finger 60 may also be located on the outer contact region 41. The outer edge of the source finger 60 may also be located on the second semiconductor layer 7.

[0297] The source finger 60, like the source electrode 55, has a laminated structure including a base electrode 56 and a main electrode 57 stacked in this order from the first main surface 3 side. The base electrode 56 has a laminated structure including a first electrode 56a and a second electrode 56b.

[0298] The first electrode 56a extends from above the interlayer film 45 into the outer opening 53. The first electrode 56a has a portion that covers the insulating surface of the interlayer film 45 in a film-like manner, a portion that covers the wall surface of the outer opening 53 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner. The first electrode 56a is mechanically and electrically connected to the outer contact region 41 within the outer opening 53.

[0299] The second electrode 56b covers the first electrode 56a in a film-like manner and enters the outer opening 53 from above the interlayer film 45. The second electrode 56b has a portion that covers the interlayer film 45 in a film-like manner via the first electrode 56a, a portion that covers the wall surface of the outer opening 53 in a film-like manner via the first electrode 56a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 56a. The second electrode 56b is electrically connected to the outer contact region 41 via the first electrode 56a within the outer opening 53.

[0300] The main electrode 57 covers the base electrode 56 in a film-like manner and enters the outer opening 53 from above the interlayer film 45. The main electrode 57 has a portion that covers the interlayer film 45 in a film-like manner via the base electrode 56, a portion that covers the wall surface of the outer opening 53 in a film-like manner via the base electrode 56, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 56. The main electrode 57 is electrically connected to the outer contact region 41 within the outer opening 53 via the base electrode 56.

[0301] The semiconductor device 1A includes a gate electrode 65 disposed on the first main surface 3. The gate electrode 65 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "gate pad electrode," etc. The gate electrode 65 is made of metal. The gate electrode 65 is disposed on the interlayer film 45 at a distance from the source electrode 55 and source finger 60.

[0302] The gate electrode 65 is positioned in the region on the fourth side surface 5D side relative to the first pad portion 55a, and faces the central portion of the fourth side surface 5D and the first pad portion 55a in the first direction X. The gate electrode 65 is interposed in the region between the second pad portion 55b and the third pad portion 55c, and faces both the second pad portion 55b and the third pad portion 55c in the second direction Y.

[0303] The gate electrode 65 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 65 has a planar area less than the planar area of ​​the source electrode 55. The planar area of ​​the gate electrode 65 is less than the planar area of ​​the first pad portion 55a. The planar area of ​​the gate electrode 65 may be larger or smaller than the planar area of ​​the second pad portion 55b (third pad portion 55c).

[0304] In this embodiment, the gate electrode 65 does not have a direct electrical connection to the gate wiring 50. The gate electrode 65 may be mechanically and electrically connected to the gate wiring 50 via one or more gate openings 52.

[0305] The gate electrode 65 has a portion that faces the outer well region 40 via the interlayer film 45. In this embodiment, the gate electrode 65 has a portion that faces the plurality of gate structures 10 via the interlayer film 45. The gate electrode 65 is formed at a distance from the plurality of gate structures 10 and does not necessarily face the plurality of gate structures 10 in the stacking direction.

[0306] Although not shown in the diagram, the gate electrode 65, like the source electrode 55, includes a base electrode 56 and a main electrode 57 stacked in this order from the interlayer film 45 side. The base electrode 56 has a stacked structure including a first electrode 56a and a second electrode 56b.

[0307] The semiconductor device 1A includes a gate finger 66 drawn out from the gate electrode 65 onto the first main surface 3. The gate finger 66 may also be called a "gate wiring," "gate finger electrode," etc. The gate finger 66 transmits the gate potential applied to the gate electrode 65 to other regions.

[0308] The gate finger 66 is drawn out from the gate electrode 65 onto the interlayer film 45. The gate finger 66 is routed in a strip-like manner in the region between the source electrode 55 and the source finger 60. The gate finger 66 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y when viewed in plan.

[0309] In this embodiment, the gate finger 66 is formed in the shape of an ended band having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 55. The gate finger 66 is positioned closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 10. The gate finger 66 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0310] The gate finger 66 enters a plurality of gate openings 52 from above the interlayer film 45 and is mechanically and electrically connected to the gate wiring 50 within the plurality of gate openings 52. As a result, the gate potential applied to the gate electrode 65 is applied to the plurality of gate structures 10 via the gate wiring 50 and the gate finger 66.

[0311] The gate finger 66 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger 66 is formed at a distance from the plurality of gate structures 10 on the peripheral side of the first main surface 3. In other words, the gate finger 66 does not face the plurality of gate structures 10 in the stacking direction.

[0312] The inner edge of the gate finger 66 is positioned on the gate wiring 50. The inner edge of the gate finger 66 is horizontally opposed to the peripheral edge of the source electrode 55 on the gate wiring 50. The inner edge of the gate finger 66 is formed with a gap from the middle of the gate wiring 50 toward the peripheral edge of the first main surface 3.

[0313] The outer edge of the gate finger 66 extends substantially parallel to the inner edge of the gate finger 66. The outer edge of the gate finger 66 is drawn out from above the gate wiring 50 towards the periphery of the first main surface 3 and does not face the gate wiring 50 in the stacking direction. The outer edge of the gate finger 66 is formed with a gap between the multiple field regions 42 (the innermost field region 42) and the inward side of the first main surface 3.

[0314] The outer edge of the gate finger 66 is formed with a gap between it and the outer edge of the outer well region 40, on the inward side of the first main surface 3. In this configuration, the outer edge of the gate finger 66 is formed with a gap between it and the inner edge of the outer contact region 41, on the inward side of the first main surface 3, and faces the outer well region 40.

[0315] The outer edge of the gate finger 66 is horizontally opposed to the inner edge of the source finger 60. The outer edge of the gate finger 66 may be located on the outer contact region 41. The outer edge of the gate finger 66 may be located on the second semiconductor layer 7.

[0316] The gate finger 66, like the source electrode 55 (gate electrode 65), has a laminated structure including a base electrode 56 and a main electrode 57 stacked in this order from the first main surface 3 side. The base electrode 56 has a laminated structure including a first electrode 56a and a second electrode 56b.

[0317] The first electrode 56a penetrates the multiple gate openings 52 from above the interlayer film 45. The first electrode 56a has a portion that covers the insulating surface of the interlayer film 45 in a film-like manner, a portion that covers the walls of the multiple gate openings 52 in a film-like manner, and a portion that covers the gate wiring 50 in a film-like manner. The first electrode 56a is mechanically and electrically connected to the gate wiring 50 within the multiple gate openings 52.

[0318] The second electrode 56b covers the first electrode 56a in a film-like manner and penetrates the multiple gate openings 52 from above the interlayer film 45. The second electrode 56b has a portion that covers the interlayer film 45 in a film-like manner via the first electrode 56a, a portion that covers the walls of the multiple gate openings 52 in a film-like manner via the first electrode 56a, and a portion that covers the gate wiring 50 in a film-like manner via the first electrode 56a. The second electrode 56b is electrically connected to the gate wiring 50 via the first electrode 56a within the multiple gate openings 52.

[0319] The main electrode 57 covers the base electrode 56 in a film-like manner and penetrates the multiple gate openings 52 from above the interlayer film 45. The main electrode 57 has a portion that covers the interlayer film 45 in a film-like manner via the base electrode 56, a portion that covers the wall surfaces of the multiple gate openings 52 in a film-like manner via the base electrode 56, and a portion that covers the gate wiring 50 in a film-like manner via the base electrode 56. The main electrode 57 is electrically connected to the gate wiring 50 via the base electrode 56 within the multiple gate openings 52.

[0320] The semiconductor device 1A includes a drain electrode 67 that covers the second main surface 4. The drain electrode 67 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," "drain pad electrode," etc. The drain electrode 67 is mechanically and electrically connected to the first semiconductor layer 6. The drain electrode 67 forms ohmic contact with the first semiconductor layer 6.

[0321] The drain electrode 67 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 67 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0322] The breakdown voltage that can be applied between the source electrode 55 and the drain electrode 67 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0323] Figures 13A to 13G are enlarged cross-sectional views showing the gate structure 10 (mesa portion 20) according to the second to eighth examples. The gate structure 10 (mesa portion 20) according to the first to eighth examples can be combined as appropriate. The semiconductor device 1A (including semiconductor devices according to other embodiments) may simultaneously have one, two, three, four, five, six, seven, or eight features of the gate structure 10 (mesa portion 20) according to the first to eighth examples.

[0324] Referring to Figure 13A (second example), the inclined side wall 14 of the gate structure 10 may be curved upward in an arc shape. In other words, the mesa portion 20 may have an inclined portion 22 that is curved upward in an arc shape (convex curve) from the main surface portion 21.

[0325] In this case, the first electrode 56a may cover the inclined side wall 14 (inclined portion 22) in a convex curved shape. The second electrode 56b may cover the inclined side wall 14 (inclined portion 22) in a convex curved shape via the first electrode 56a. The main electrode 57 may cover the inclined side wall 14 (inclined portion 22) in a convex curved shape via the base electrode 56.

[0326] Referring to Figure 13B (third example), the inclined side wall 14 of the gate structure 10 may be curved downward in an arc shape (concave curve). In other words, the mesa portion 20 may have an inclined portion 22 that is curved downward in an arc shape from the main surface portion 21.

[0327] In this case, the first electrode 56a may cover the inclined side wall 14 (inclined portion 22) in a concave curved shape. The second electrode 56b may cover the inclined side wall 14 (inclined portion 22) in a concave curved shape via the first electrode 56a. The main electrode 57 may cover the inclined side wall 14 (inclined portion 22) in a concave curved shape via the base electrode 56.

[0328] Referring to Figure 13C (Fourth Example), the embedded electrode 17 of the gate structure 10 may have an electrode surface located above the upper end of the insulating film 16 within the trench 15. Of course, the electrode surface of the embedded electrode 17 may also be located below the upper end of the insulating film 16.

[0329] In this embodiment, the embedded insulator 18 of the gate structure 10 covers the electrode surface of the embedded electrode 17 and the upper end of the insulating film 16 within the trench 15. The embedded insulator 18 has a portion that is in direct contact with the chip 2 (second semiconductor layer 7) on the inclined sidewall 14 side of the embedded electrode 17 and the insulating film 16. The configuration of the gate structure 10 (mesa portion 20) according to the fourth example is also applicable to any one of the gate structures 10 (mesa portion 20) according to the first to third examples.

[0330] Referring to Figure 13D (Fifth Example), the gate structure 10 may have an insulating projection 70 that protrudes above the lower end of the inclined side wall 14. In this embodiment, the insulating projection 70 is formed of an insulating film 16 and an embedded insulator 18 and has a protruding side wall 71 and a protruding surface 72.

[0331] The protruding side wall 71 is formed of an insulating film 16, and the protruding surface 72 is formed of the insulating film 16 and the embedded insulator 18. The protruding surface 72 may have a recess toward the bottom wall 13 of the trench 15. The protruding surface 72 may have an upwardly raised protrusion.

[0332] The insulating film 16 has an upper end that protrudes above the lower end of the inclined side wall 14. The upper end of the insulating film 16 may be located on the bottom wall 13 side of the trench 15, relative to the upper end (first main surface 3) of the inclined side wall 14. The upper end of the insulating film 16 may be facing the wall surface of the inclined side wall 14 in the horizontal direction. The upper end of the insulating film 16 may protrude above the upper end (first main surface 3) of the inclined side wall 14.

[0333] The buried insulator 18 may have an insulating surface that protrudes above the lower end of the inclined side wall 14. The insulating surface of the buried insulator 18 may face the wall surface of the inclined side wall 14 in the horizontal direction. The insulating surface of the buried insulator 18 may be located on the bottom wall 13 side of the trench 15, above the upper end (first main surface 3) of the inclined side wall 14. The insulating surface of the buried insulator 18 may protrude above the upper end (first main surface 3) of the inclined side wall 14.

[0334] From an alternative perspective, the mesa portion 20 may have a main surface portion 21 (first main surface 3) located above the protruding surface 72, and an inclined portion 22 that slopes downward from the main surface portion 21 toward the gate structure 10 and has a lower end portion located below the protruding surface 72. The inclined portion 22 may face the protruding side wall 71 in the horizontal direction. The main surface portion 21 of the mesa portion 20 may be located below the protruding surface 72.

[0335] The first electrode 56a has a portion that covers the protruding side wall 71 and may ride up onto the protruding surface 72 from the lower end of the inclined side wall 14 (inclined portion 22). The second electrode 56b has a portion that covers the protruding side wall 71 via the first electrode 56a and may ride up onto the protruding surface 72 from the lower end of the inclined side wall 14 (inclined portion 22).

[0336] The main electrode 57 has a portion that covers the protruding side wall 71 via the base electrode 56, and may also ride up onto the protruding surface 72 from the lower end of the inclined side wall 14 (inclined portion 22). The configuration of the gate structure 10 (mesa portion 20) according to the fifth example is also applicable to any one of the gate structures 10 (mesa portion 20) according to the first to fourth examples.

[0337] Referring to Figure 13E (Sixth Example), the insulating projection 70 according to the fifth example described above may have a protruding side wall 71 and a protruding surface 72 formed by the embedded insulator 18. The configuration of the gate structure 10 (mesa section 20) according to the sixth example is also applicable to any one of the gate structures 10 (mesa section 20) according to the first to fifth examples.

[0338] Referring to Figure 13F (Seventh Example), the insulating film 16 of the gate structure 10 may selectively cover the inclined sidewall 14. The insulating film 16 may expose the upper end of the inclined sidewall 14 and cover the lower end of the inclined sidewall 14. The insulating film 16 may be formed with a gap from the depth position of the middle part of the inclined sidewall 14 toward the bottom wall 13 of the trench 15.

[0339] The embedded insulator 18 of the gate structure 10 may selectively cover the inclined side wall 14 via the insulating film 16. The embedded insulator 18 may expose the upper end of the inclined side wall 14 and cover the lower end of the inclined side wall 14 via the insulating film 16. The embedded insulator 18 may be formed with a gap from the depth position of the middle part of the inclined side wall 14 toward the bottom wall 13 of the trench 15.

[0340] The first electrode 56a has a portion that covers the inclined side wall 14 and may overlap the insulating film 16 and the embedded insulator 18 from above the inclined side wall 14. The second electrode 56b has a portion that covers the inclined side wall 14 via the first electrode 56a and may overlap the insulating film 16 and the embedded insulator 18 from above the inclined side wall 14. The main electrode 57 has a portion that covers the inclined side wall 14 via the base electrode 56 and may overlap the insulating film 16 and the embedded insulator 18 from above the inclined side wall 14.

[0341] Referring to Figure 13G (8th example), the embedded electrode 17 of the gate structure 10 may have an electrode surface located above the upper end of the insulating film 16 within the trench 15. The electrode surface of the embedded electrode 17 may be located below the upper end of the insulating film 16.

[0342] In this configuration, the embedded insulator 18 covers the electrode surface of the embedded electrode 17 and the upper end of the insulating film 16 within the trench 15. The embedded insulator 18 has a portion that is in direct contact with the chip 2 (second semiconductor layer 7) on the inclined sidewall 14 side, relative to the embedded electrode 17 and the insulating film 16.

[0343] The buried insulator 18 may selectively cover the inclined side wall 14. The buried insulator 18 may expose the upper end of the inclined side wall 14 and cover the lower end of the inclined side wall 14. The buried insulator 18 may be formed with a gap from the depth position of the middle part of the inclined side wall 14 toward the bottom wall 13 of the trench 15.

[0344] The first electrode 56a has a portion that covers the inclined side wall 14 and may rest on top of the embedded insulator 18 from above the inclined side wall 14. The second electrode 56b has a portion that covers the inclined side wall 14 via the first electrode 56a and may rest on top of the embedded insulator 18 from above the inclined side wall 14. The main electrode 57 has a portion that covers the inclined side wall 14 via the base electrode 56 and may rest on top of the embedded insulator 18 from above the inclined side wall 14.

[0345] Figures 14A to 14C are enlarged plan views showing the inner portion of the active region 8 together with a plurality of mesa portions 20 according to the second to fourth layout examples. The plurality of mesa portions 20 according to the first to fourth layout examples can be combined among them as appropriate. The semiconductor device 1A (including semiconductor devices according to other embodiments) may simultaneously have one, two, three, or four features of the plurality of mesa portions 20 according to the first to fourth layout examples.

[0346] Referring to Figure 14A (Second Layout Example), each of the multiple first mesa units MU1 is composed of one first mesa section 20A, and each of the multiple second mesa units MU2 is composed of one second mesa section 20B. In other words, the number of second mesas is one, the same as the number of first mesas.

[0347] In other words, the multiple second mesa sections 20B are alternately partitioned with the multiple first mesa sections 20A in the first direction X. The multiple gate structures 10 (trenches 15) partition the first mesa sections 20A for transistors on one side of the first direction X, and the second mesa sections 20B for diodes on the other side of the first direction X.

[0348] Referring to Figure 14B (Third Layout Example), each of the multiple first mesa units MU1 is composed of one first mesa section 20A, and each of the multiple second mesa units MU2 is composed of multiple (two in this configuration) second mesa sections 20B. In other words, the number of second mesas is greater than the number of first mesas.

[0349] The first gate structure 10 (trench 15) demarcates a second mesa portion 20B for diodes on both sides in the first direction X. The second gate structure 10 (trench 15) demarcates a first mesa portion 20A for transistors on one side in the first direction X, and a second mesa portion 20B for diodes on the other side in the first direction X.

[0350] The third gate structure 10 (trench 15) demarcates a second mesa portion 20B for a diode on one side in the first direction X, and a first mesa portion 20A for a transistor on the other side in the first direction X.

[0351] Referring to Figure 14C (Example of the fourth layout), each of the multiple first mesa units MU1 is composed of multiple (two in this configuration) first mesa sections 20A, and each of the multiple second mesa units MU2 is composed of multiple (two in this configuration) second mesa sections 20B. In other words, the number of second mesas is two or more and the same as the number of first mesas. The number of second mesas may be more or less than the number of first mesas.

[0352] The first gate structure 10 (trench 15) demarcates a first mesa portion 20A for transistors on both sides in the first direction X. The second gate structure 10 (trench 15) demarcates a second mesa portion 20B for diodes on both sides in the first direction X.

[0353] The third gate structure 10 (trench 15) demarcates a first mesa portion 20A for a transistor on one side in the first direction X, and a second mesa portion 20B for a diode on the other side in the first direction X. The fourth gate structure 10 (trench 15) demarcates a second mesa portion 20B for a diode on one side in the first direction X, and a first mesa portion 20A for a transistor on the other side in the first direction X.

[0354] Figure 15 is a circuit diagram showing the electrical configuration of the semiconductor device 1A shown in Figure 1. The semiconductor device 1A includes a transistor structure Tr, a bipolar type bipolar diode DB, a unipolar type unipolar diode DU, a source electrode 55, a gate electrode 65, and a drain electrode 67. The transistor structure Tr is formed by a plurality of FET structures 25 and includes a gate, source, and drain.

[0355] The gate of the transistor structure Tr includes a plurality of gate structures 10 and is electrically connected to the gate electrode 65. The source of the transistor structure Tr includes a plurality of source regions 27 and is electrically connected to the source electrode 55. The drain of the transistor structure Tr includes a first semiconductor layer 6 and a second semiconductor layer 7 and is electrically connected to the drain electrode 67.

[0356] The bipolar diode DB consists of a pn junction diode and includes an anode and a cathode. The anode of the bipolar diode DB includes a plurality of body regions 26, a plurality of contact regions 28, a plurality of well regions 35, an outer well region 40, and an outer contact region 41. The cathode of the bipolar diode DB includes a first semiconductor layer 6 and a second semiconductor layer 7.

[0357] The anode of the bipolar diode DB is connected to the source of the transistor structure Tr, and the cathode of the bipolar diode DB is connected to the drain of the transistor structure Tr. The bipolar diode DB has a first threshold voltage Vth1. The bipolar diode DB has a first area. The first area is the total connection area of ​​the body region 26, the well region 35, and the outer well region 40 with respect to the second semiconductor layer 7.

[0358] The unipolar diode DU consists of a heterojunction diode (Schottky junction diode) and includes an anode and a cathode. The anode of the unipolar diode DU includes a source electrode 55. The cathode of the unipolar diode DU includes a second semiconductor layer 7 (multiple diode regions 30).

[0359] The anode of the unipolar diode DU is connected to the source of the transistor structure Tr, and the cathode of the unipolar diode DU is connected to the drain of the transistor structure Tr. In other words, the unipolar diode DU is connected in parallel with the bipolar diode DB, and together with the bipolar diode DB, it forms a freewheeling diode for the transistor structure Tr.

[0360] The unipolar diode DU has a second threshold voltage Vth2 which is less than the first threshold voltage Vth1. The unipolar diode DU has a second area which is less than the first area. The second area of ​​the unipolar diode DU is the connection area of ​​the source electrode 55 to the plurality of second mesa portions 20B.

[0361] The second area of ​​the unipolar diode DU is less than the connection area of ​​the body region 26 to the second semiconductor layer 7. The second area of ​​the unipolar diode DU is less than the connection area of ​​the well region 35 to the second semiconductor layer 7. The second area of ​​the unipolar diode DU is less than the connection area of ​​the outer well region 40 to the second semiconductor layer 7.

[0362] The source electrode 55 is electrically connected to the source of the transistor structure Tr, the anode of the bipolar diode DB, and the anode of the unipolar diode DU. The gate electrode 65 is electrically connected to the gate of the transistor structure Tr. The drain electrode 67 is electrically connected to the drain of the transistor structure Tr, the cathode of the bipolar diode DB, and the cathode of the unipolar diode DU.

[0363] Figure 16 is a graph (simulation) showing the electrical behavior of the semiconductor device 1A shown in Figure 1. The graph in Figure 16 shows the characteristics of the forward current IF when a forward voltage VF is applied to the bipolar diode DB and the unipolar diode DU. In Figure 16, the vertical axis represents the forward current IF [A] and the horizontal axis represents the forward voltage VF [V].

[0364] The forward voltage VF is the voltage that brings the source electrode 55 to a positive potential and the drain electrode 67 to a negative potential. In other words, the forward voltage VF is the reverse bias voltage VDS related to the transistor structure Tr, and the forward current IF is the drain current IDS related to the transistor structure Tr.

[0365] Referring to Figure 16, when semiconductor device 1A switches from the ON state to the OFF state, a forward voltage VF as a back electromotive force is generated in the bipolar diode DB and the unipolar diode DU. As a result, the bipolar diode DB and the unipolar diode DU switch to freewheeling operation.

[0366] The unipolar diode DU has a second threshold voltage Vth2 which is less than the first threshold voltage Vth1 of the bipolar diode DB. Therefore, the unipolar diode DU turns on before the bipolar diode DB turns on and flows a forward current IF as a freewheeling current.

[0367] This reduces forward energy loss. In this configuration, the design ensures that only the single-pole diode DU is turned on during normal freewheeling operation. Therefore, the freewheeling current is handled solely by the single-pole diode DU.

[0368] The first semiconductor layer 6 may have basal plane dislocation (BPD) defects. Basal plane dislocation defects are dislocations located on the c-plane, which is the basal plane of a SiC single crystal. If the first semiconductor layer 6 has an off-direction and an off-angle, the basal plane dislocation defects extend in the off-direction with an inclination equal to the off-angle. Basal plane dislocation defects are typically 1 cm long. －２ More than 10000cm －２ It has the following density:

[0369] When holes, acting as minority carriers, are supplied to the second semiconductor layer 7 during reflux operation, the holes recombine with electrons, acting as majority carriers, within the second semiconductor layer 7 and release energy. The majority of holes recombine with electrons in the second semiconductor layer 7, but a small number of holes may reach the first semiconductor layer 6.

[0370] If a hole recombines with an electron at or near a basal plane dislocation defect, the atom at the basal plane dislocation defect may migrate from the first semiconductor layer 6 to the second semiconductor layer 7 due to the energy generated by the recombination. In this case, the atom migration caused by the basal plane dislocation defect may extend to the second semiconductor layer 7 as a single Shockley stacking fault (1SSF).

[0371] A single Shockley stacking fault (1SSF) can trap conduction carriers during freewheeling operation, potentially leading to increased on-voltage and on-resistance. This type of problem is known as bipolar degradation.

[0372] In semiconductor device 1A, the unipolar diode DU operates dominantly during freewheeling, thereby suppressing the supply of holes as minority carriers to the second semiconductor layer 7. As a result, the number of holes reaching the first semiconductor layer 6 is reduced, and bipolar degradation caused by basal plane dislocation defects is suppressed.

[0373] On the other hand, when a surge current Is occurs during freewheeling, the bipolar diode DB turns on in addition to the monopolar diode DU. The surge current Is, due to snapback, draws an inverted increase curve from the increase curve due to the monopolar diode DU, and then drops sharply (see dashed line).

[0374] As a result, the surge current Is is handled by both the bipolar diode DB and the unipolar diode DU, while simultaneously suppressing the increase in the forward voltage VF. Furthermore, the first area of ​​the bipolar diode DB is larger than the second area of ​​the unipolar diode DU. Therefore, when a surge current Is is applied, current concentration in the bipolar diode DB is suppressed, and the on-delay of the bipolar diode DB is also suppressed.

[0375] As described above, the semiconductor device 1A may include a second semiconductor layer 7 (semiconductor layer), a trench 15, and a source electrode 55 (electrode). The second semiconductor layer 7 contains SiC and has a first main surface 3. The first main surface 3 may have a first barrier height BH1. The trench 15 is formed on the first main surface 3 and may have a first side wall 11 and an inclined side wall 14. The inclined side wall 14 may slope downward from the first main surface 3 toward the first side wall 11.

[0376] The first sidewall 11 may have a second barrier height BH2 that is lower than the first barrier height BH1. The inclined sidewall 14 may have a third barrier height BH3 that is higher than the second barrier height BH2 and lower than the first barrier height BH1. The source electrode 55 may cover the first main surface 3 and the inclined sidewall 14 in cross-sectional view, and may form a Schottky junction (heterojunction) with both the first main surface 3 and the inclined sidewall 14.

[0377] This configuration provides a novel semiconductor device 1A. For example, with this semiconductor device 1A, the barrier height difference between the first main surface 3 and the first side wall 11 is mitigated by the inclined side wall 14. This suppresses the source electrode 55 from being connected only to the first main surface 3 and the first side wall 11, and stabilizes the threshold voltage of the Schottky junction.

[0378] In particular, since SiC semiconductor devices are used in relatively high-voltage environments, stabilizing the threshold voltage of the Schottky junction is effective in suppressing increases in switching losses and leakage currents, and improving electrical characteristics.

[0379] The second semiconductor layer 7 may contain 4H-SiC as SiC. The second semiconductor layer 7 may have an off-angle. The off-angle may be 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC.

[0380] The first barrier height BH1 may be due to the c-plane of SiC. The second barrier height BH2 may be due to the m-plane of SiC. The third barrier height BH3 may be due to both the c-plane and the m-plane of SiC. In these cases, the trench 15 may extend in the a-axis direction of SiC.

[0381] The source electrode 55 may cover the entire area of ​​the inclined side wall 14 in cross-sectional view and form a Schottky junction with the entire area of ​​the inclined side wall 14. The semiconductor device 1A may include an insulating film 16 and an embedded electrode 17. The insulating film 16 may cover the first side wall 11 below the inclined side wall 14. The embedded electrode 17 may be embedded in the trench 15 below the inclined side wall 14 via the insulating film 16. A potential different from that of the embedded electrode 17 may be applied to the source electrode 55.

[0382] The semiconductor device 1A may include an embedded insulator 18. The embedded insulator 18 may be embedded in the trench 15 below the inclined side wall 14 and cover the embedded electrode 17. In this case, the source electrode 55 may cover the inclined side wall 14 and the embedded insulator 18 within the trench 15 and be electrically insulated from the embedded insulator 18 by the embedded insulator 18.

[0383] In a configuration where a portion of the source electrode 55 is embedded in the trench 15, a portion of the source electrode 55 is likely to come into contact with the first side wall 11. In this respect, according to the configuration of semiconductor device 1A, even in a structure where a portion of the source electrode 55 is embedded in the trench 15, stabilization of the Schottky junction threshold voltage by the inclined side wall 14 can be obtained.

[0384] The semiconductor device 1A may include an n-type second semiconductor layer 7 and a p-type body region 26. The body region 26 may be formed on the surface of the second semiconductor layer 7 and may form a pn junction with the second semiconductor layer 7. With this configuration, a bipolar diode DB including a pn junction and a unipolar diode DU including a Schottky junction are formed.

[0385] In this configuration, the freewheeling current during freewheeling operation is handled by the unipolar diode DU, while the surge current Is can be handled by both the bipolar diode DB and the unipolar diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0386] The semiconductor device 1A may include an n-type second semiconductor layer 7 and a p-type well region 35. The well region 35 may be formed in the region below the trench 15 within the second semiconductor layer 7 and may form a pn junction with the second semiconductor layer 7. With this configuration, a bipolar diode DB including a pn junction and a unipolar diode DU including a Schottky junction are formed.

[0387] In this configuration, the freewheeling current during freewheeling operation is handled by the unipolar diode DU, while the surge current Is can be handled by both the bipolar diode DB and the unipolar diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0388] The semiconductor device 1A may include an n-type second semiconductor layer 7, an FET structure 25, and an n-type diode region 30. The FET structure 25 may be formed along the trench 15 within the second semiconductor layer 7. The diode region 30 may be formed along the trench 15 within the second semiconductor layer 7.

[0389] In this case, the source electrode 55 is electrically connected to the FET structure 25 on the first main surface 3, and a Schottky junction may be formed with the diode region 30 on both the first main surface 3 and the inclined side wall 14. With this configuration, the electrical characteristics are improved in the configuration having the FET structure 25 and the Schottky junction.

[0390] The trench 15 may divide the second semiconductor layer 7 into a first mesa portion 20A (first region) on one side and a second mesa portion 20B (second region) on the other side. In this case, the FET structure 25 may be formed in the first mesa portion 20A (first region) of the second semiconductor layer 7.

[0391] The diode region 30 may be formed in the second mesa portion 20B (second region) of the second semiconductor layer 7. The diode region 30 may face the FET structure 25 via the trench 15 and be electrically connected to the FET structure 25 via the second semiconductor layer 7.

[0392] From an alternative perspective, the semiconductor device 1A may include a second semiconductor layer 7 (semiconductor layer), a trench electrode type gate structure 10, a mesa portion 20, and a source electrode 55 (electrode). The second semiconductor layer 7 may have a first main surface 3. The gate structure 10 may be formed on the first main surface 3. The mesa portion 20 may be partitioned in the second semiconductor layer 7 by the gate structure 10. The mesa portion 20 may have a main surface portion 21 and an inclined portion 22.

[0393] The main surface portion 21 may consist of a part of the first main surface 3. The inclined portion 22 may have an inclined portion 22 that slopes downward from the main surface portion 21 toward the gate structure 10. The source electrode 55 may form a Schottky junction (heterojunction) with both the main surface portion 21 and the inclined portion 22 of the mesa portion 20.

[0394] This configuration provides a novel semiconductor device 1A. For example, with this semiconductor device 1A, the barrier height difference between the main surface portion 21 and the first side wall 11 of the gate structure 10 is mitigated by the inclined portion 22.

[0395] This prevents the source electrode 55 from being connected only to the main surface portion 21 and the first side wall 11 of the gate structure 10, thereby stabilizing the threshold voltage of the Schottky junction. Such a configuration is also effective in suppressing the increase in switching losses and leakage current, and improving electrical characteristics.

[0396] The semiconductor device 1A may include a trench 15, an insulating film 16, and an embedded electrode 17. The trench 15 may be formed on the first main surface 3. The insulating film 16 may cover the wall surface of the trench 15. The embedded electrode 17 may be embedded in the trench 15 via the insulating film 16. The embedded insulator 18 may cover the embedded electrode 17 within the trench 15. The source electrode 55 may cover the embedded insulator 18 within the trench 15.

[0397] In a configuration where a portion of the source electrode 55 is embedded in the trench 15, a portion of the source electrode 55 is likely to come into contact with the wall surface of the trench 15. In this regard, according to the configuration of semiconductor device 1A, even in a structure where a portion of the source electrode 55 is embedded in the trench 15, stabilization of the Schottky junction threshold voltage by the inclined portion 22 can be obtained.

[0398] Figure 17 is an enlarged plan view showing the active region 8 of the semiconductor device 1B according to the second embodiment. Figure 18 is a cross-sectional view along the line XVIII-XVIII shown in Figure 17. Figure 19 is a cross-sectional view along the line XIX-XIX shown in Figure 17. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 17.

[0399] The semiconductor device 1B has a configuration in which the configuration of the multiple second mesa portions 20B of the semiconductor device 1A is changed. Specifically, in this configuration, the multiple second mesa portions 20B are formed as mesa portions 20 for dummy transistors and diodes.

[0400] The description of the multiple first mesa portions 20A (first mesa unit MU1) and the multiple second mesa portions 20B (second mesa unit MU2) is the same as the description for semiconductor device 1A (see also Figures 4 and 14A to 14C). The multiple gate structures 10 and the multiple mesa portions 20 may have at least one configuration from the first to eighth examples (see Figures 10 and 13A to 13G).

[0401] In this embodiment, the semiconductor device 1B includes a plurality of dummy FET structures 75 formed on each of the plurality of second mesa portions 20B. The plurality of dummy FET structures 75 are arranged in a one-to-many relationship with respect to one second mesa portion 20B, spaced apart in the second direction Y. The plurality of dummy FET structures 75 extend in a strip shape in the second direction Y, following the extending direction of the plurality of gate structures 10.

[0402] With respect to one and the other second mesa portion 20B, the plurality of dummy FET structures 75 of the other side face the plurality of dummy FET structures 75 of the one side in the first direction X. The plurality of dummy FET structures 75 of the other side may face the region between the plurality of dummy FET structures 75 of the one side in the first direction X.

[0403] Each of the dummy FET structures 75 includes a p-type body region 26 and a p-type contact region 28, respectively, but does not have a source region 27. The body region 26 is formed on the surface layer of the first main surface 3 by the corresponding second mesa portion 20B.

[0404] The body region 26 extends in the second direction Y, following the extension direction of the multiple gate structures 10, and is adjacent to two gate structures 10 corresponding to the first direction X. The body region 26 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the body region 26 as the anode region.

[0405] With respect to one and the other second mesa portion 20B, the plurality of body regions 26 of the other portion face the plurality of body regions 26 of the first portion in the first direction X. The plurality of body regions 26 of the other portion may face the region between the plurality of body regions 26 of the first portion in the first direction X.

[0406] The body region 26 of the dummy FET structure 75 faces the body region 26 of the FET structure 25 in the first direction X via the gate structure 10 (trench 15). The body region 26 of the dummy FET structure 75 may also face either or both of the source region 27 and contact region 28 of the FET structure 25 in the first direction X via the gate structure 10 (trench 15).

[0407] The contact region 28 is formed in the second mesa portion 20B on the surface of the body region 26. In this configuration, the contact region 28 has a protruding portion that crosses the periphery of the body region 26 and extends outward from the body region 26. The contact region 28 may also be formed at a distance from the periphery of the body region 26 inward from the body region 26.

[0408] With respect to one and the other second mesa portion 20B, the plurality of contact regions 28 of the other portion face the plurality of contact regions 28 of one portion in the first direction X. The plurality of contact regions 28 of the other portion may face the region between the plurality of contact regions 28 of one portion in the first direction X.

[0409] The contact region 28 of the dummy FET structure 75 faces the contact region 28 of the FET structure 25 in the first direction X via the gate structure 10 (trench 15). The contact region 28 of the dummy FET structure 75 may also face the source region 27 of the FET structure 25 in the first direction X via the gate structure 10 (trench 15).

[0410] The semiconductor device 1B includes a plurality of n-type diode regions 30 formed in a plurality of second mesa portions 20B. In this embodiment, the plurality of diode regions 30 are formed using a portion of the second semiconductor layer 7, similar to the case of semiconductor device 1A, and have an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode regions 30 may be higher or lower than that of the second semiconductor layer 7.

[0411] Multiple diode regions 30 are formed in a one-to-many relationship with respect to one second mesa portion 20B, spaced apart in the second direction Y. In this configuration, the multiple diode regions 30 are arranged alternately with multiple dummy FET structures 75 in the second direction Y. In this configuration, unipolar diodes DU are fabricated together with bipolar diodes DB in a common second mesa portion 20B.

[0412] The multiple diode regions 30 extend in the second direction Y, following the extension direction of the multiple gate structures 10, and are adjacent to two gate structures 10 corresponding to the first direction X. The multiple diode regions 30 face the body region 26 of the FET structure 25 in the first direction X via the gate structures 10 (trench 15).

[0413] Multiple diode regions 30 may face either or both of the source region 27 and contact region 28 of the FET structure 25 in the first direction X via the gate structure 10 (trench 15).

[0414] In this configuration, the multiple diode regions 30 have a portion demarcated by a plurality of contact regions 28 on the first main surface 3 side, and a portion demarcated by a plurality of body regions 26 on the bottom wall 13 side of the gate structure 10. If the entire area of ​​the plurality of contact regions 28 is located inside the body region 26, the plurality of diode regions 30 may be demarcated only by the plurality of body regions 26.

[0415] In one second mesa section 20B, the total planar area of ​​the multiple diode regions 30 may be greater than the total planar area of ​​the multiple dummy FET structures 75. Alternatively, the planar area of ​​the multiple diode regions 30 may be less than the total planar area of ​​the multiple dummy FET structures 75.

[0416] The semiconductor device 1B, like the semiconductor device 1A, includes a plurality of p-type well contact regions 37 formed in the inner portion (active region 8) of the second semiconductor layer 7. In this configuration, the plurality of well contact regions 37 are interposed in the regions between the plurality of contact regions 28 on the first mesa portion 20A side and the plurality of contact regions 28 on the second mesa portion 20B side.

[0417] Multiple well contact regions 37 extend along the first side wall 11 and bottom wall 13 of the corresponding gate structure 10, electrically connecting the corresponding well region 35 to multiple body regions 26 on the first mesa portion 20A side and multiple body regions 26 on the second mesa portion 20B side.

[0418] In this configuration, the multiple well contact regions 37 electrically connect the corresponding well region 35 to the multiple contact regions 28 on the first mesa portion 20A side and the multiple contact regions 28 on the second mesa portion 20B side.

[0419] Each of the multiple well contact regions 37 has multiple side walls and bottom walls. The multiple side walls are formed along a pair of first side walls 11 of the corresponding gate structure 10. In other words, in this configuration, the multiple side walls are formed along the first side wall 11 on the first mesa portion 20A side and the first side wall 11 on the second mesa portion 20B side.

[0420] Multiple sidewalls extend along a pair of first sidewalls 11 and face the embedded electrode 17 via an insulating film 16. The multiple sidewalls are connected to multiple body regions 26, increasing the p-type impurity concentration in the multiple body regions 26. In this embodiment, the multiple sidewalls are connected to multiple contact regions 28 adjacent to each other in the first direction X.

[0421] The bottom wall portion is formed along the bottom wall 13 of the corresponding gate structure 10 and faces the embedded electrode 17 via an insulating film 16. The bottom wall portion is connected to the upper end of the well region 35 and increases the p-type impurity concentration of the well region 35. In this configuration, the bottom wall portion extends from the corresponding gate structure 10 toward the first mesa portion 20A and the second mesa portion 20B, and is connected to a plurality of side walls.

[0422] The semiconductor device 1B, like the semiconductor device 1A, includes a source electrode 55. The source electrode 55 enters the source opening 51 from above the interlayer film 45 and collectively covers the multiple gate structures 10 and the multiple mesa portions 20 in a film-like manner. The connection configuration of the source electrode 55 to the multiple first mesa portions 20A is the same as in the case of semiconductor device 1A. The configuration of the source electrode 55 to the second mesa portion 20B will be described below.

[0423] The source electrode 55 is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via a plurality of second mesa portions 20B. In this configuration, the source electrode 55 is mechanically and electrically connected to the c-face and m-face of a plurality of step surfaces S via the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B.

[0424] The source electrode 55 has a portion that is mechanically and electrically connected to a plurality of dummy FET structures 75 via a plurality of second mesa portions 20B, and a portion that is mechanically and electrically connected to the region between the plurality of dummy FET structures 75 (i.e., the diode region 30) via a plurality of second mesa portions 20B.

[0425] The source electrode 55 is mechanically and electrically connected to multiple contact regions 28 (body regions 26) on the first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22) on the dummy FET structure 75 side. The source electrode 55 forms ohmic contact with the multiple contact regions 28.

[0426] The source electrode 55 forms a Schottky junction with the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) on the diode region 30 side. In other words, in this configuration, the source electrode 55 forms a Schottky junction with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0427] Specifically, the source electrode 55 forms Schottky junctions with the c-plane and m-plane of multiple step surfaces S at the inclined side wall 14 (inclined portion 22). The source electrode 55 penetrates into multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of multiple embedded insulators 18.

[0428] In this configuration, the source electrode 55 is mechanically and electrically connected to a plurality of first side walls 11. The source electrode 55 is mechanically and electrically connected to a plurality of contact regions 28 (body regions 26) on the first side wall 11 on the dummy FET structure 75 side. The source electrode 55 forms ohmic contact with the plurality of contact regions 28 on the first side wall 11.

[0429] The source electrode 55 forms a Schottky junction with the first sidewall 11 on the diode region 30 side. In other words, in this embodiment, the source electrode 55 forms a Schottky junction with the first sidewall 11 which has a second barrier height BH2.

[0430] This forms a unipolar diode DU including multiple diode regions 30 as cathode regions and a source electrode 55 as an anode region. In other words, in this configuration, the unipolar diode DU is connected in parallel with the bipolar diode DB by a common second mesa portion 20B.

[0431] The Schottky junction area of ​​the source electrode 55 with respect to the second mesa portion 20B (multiple diode regions 30) is smaller than the connection area of ​​the source electrode 55 with respect to the multiple dummy FET structures 75. The Schottky junction area of ​​the source electrode 55 with respect to the second mesa portion 20B (multiple diode regions 30) may be larger than the connection area of ​​the source electrode 55 with respect to the multiple dummy FET structures 75.

[0432] The source electrode 55 has a laminated structure including a base electrode 56 and an electrode body, similar to the semiconductor device 1A. The base electrode 56 includes a first electrode 56a and a second electrode 56b. The first electrode 56a is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 by a plurality of second mesa portions 20B.

[0433] In this configuration, the first electrode 56a is mechanically and electrically connected to the c-plane and m-plane of the multiple step surfaces S at the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B. The first electrode 56a has a portion that is mechanically and electrically connected to the multiple dummy FET structures 75 at the multiple second mesa portions 20B, and a portion that is mechanically and electrically connected to the region (diode region 30) between the multiple dummy FET structures 75 at the multiple second mesa portions 20B.

[0434] The first electrode 56a is mechanically and electrically connected to multiple contact regions 28 (body regions 26) on the first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22) on the dummy FET structure 75 side. The first electrode 56a forms ohmic contact with the multiple contact regions 28.

[0435] The first electrode 56a forms a Schottky junction with the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) on the diode region 30 side. In other words, in this configuration, the first electrode 56a forms a Schottky junction with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0436] Specifically, the first electrode 56a forms a Schottky junction with the c-plane and m-plane of multiple step surfaces S at the inclined side wall 14 (inclined portion 22). The first electrode 56a penetrates into multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of multiple embedded insulators 18.

[0437] In this configuration, the first electrode 56a is mechanically and electrically connected to a plurality of first side walls 11. The first electrode 56a is mechanically and electrically connected to a plurality of contact regions 28 (body regions 26) on the first side wall 11 on the dummy FET structure 75 side. The first electrode 56a forms ohmic contact with the plurality of contact regions 28 on the first side wall 11.

[0438] The first electrode 56a forms a Schottky junction with the first sidewall 11 on the diode region 30 side. In other words, in this configuration, the first electrode 56a forms a Schottky junction with the first sidewall 11 which has a second barrier height BH2.

[0439] The Schottky junction area of ​​the first electrode 56a with respect to the second mesa portion 20B (multiple diode regions 30) is smaller than the connection area of ​​the first electrode 56a with respect to the multiple dummy FET structures 75. The Schottky junction area of ​​the first electrode 56a with respect to the second mesa portion 20B (multiple diode regions 30) may be larger than the connection area of ​​the first electrode 56a with respect to the multiple dummy FET structures 75.

[0440] The second electrode 56b covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via the first electrode 56a with multiple second mesa portions 20B, and is electrically connected to multiple dummy FET structures 75 and multiple diode regions 30. The second electrode 56b covers the c-plane and m-plane of multiple step surfaces S via the first electrode 56a with the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B.

[0441] The second electrode 56b enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18 via the first electrode 56a. In this configuration, the second electrode 56b covers the multiple first side walls 11 via the first electrode 56a and is electrically connected to the multiple contact regions 28 (body regions 26) and multiple diode regions 30 via the first electrode 56a.

[0442] The main electrode 57 covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via the base electrode 56 with multiple second mesa portions 20B, and is electrically connected to multiple dummy FET structures 75 and multiple diode regions 30. The main electrode 57 covers the c-plane and m-plane of multiple step surfaces S via the base electrode 56 with the inclined side wall 14 (inclined portion 22) of the second mesa portion 20B.

[0443] The main electrode 57 enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18 via the base electrode 56. In this configuration, the main electrode 57 covers the multiple first side walls 11 via the base electrode 56 and is electrically connected to the multiple contact regions 28 (body regions 26) and multiple diode regions 30 via the base electrode 56.

[0444] As described above, the semiconductor device 1B may include a second semiconductor layer 7 (semiconductor layer), a trench 15, and a source electrode 55 (electrode). The second semiconductor layer 7 may contain SiC and have a first main surface 3. The first main surface 3 may have a first barrier height BH1. The trench 15 is formed on the first main surface 3 and may have a first side wall 11 and an inclined side wall 14. The inclined side wall 14 may slope downward from the first main surface 3 toward the first side wall 11.

[0445] The first sidewall 11 may have a second barrier height BH2 that is lower than the first barrier height BH1. The inclined sidewall 14 may have a third barrier height BH3 that is higher than the second barrier height BH2 and lower than the first barrier height BH1. The source electrode 55 may cover the first main surface 3 and the inclined sidewall 14 in cross-sectional view, and may form a Schottky junction (heterojunction) with both the first main surface 3 and the inclined sidewall 14.

[0446] This configuration provides a novel semiconductor device 1B. For example, with this semiconductor device 1B, the barrier height difference between the first main surface 3 and the first side wall 11 is mitigated by the inclined side wall 14. This suppresses the source electrode 55 from being connected only to the first main surface 3 and the first side wall 11, and stabilizes the threshold voltage of the Schottky junction.

[0447] The semiconductor device 1B may include an n-type second semiconductor layer 7, a p-type body region 26, and an n-type diode region 30. The body region 26 may be formed along the trench 15 within the second semiconductor layer 7 and may form a pn junction with the second semiconductor layer 7. The diode region 30 may be formed along the trench 15 within the second semiconductor layer 7.

[0448] The source electrode 55 is electrically connected to the body region 26 on the first main surface 3 and may form a Schottky junction with the diode region 30 on both the first main surface 3 and the inclined sidewall 14. According to this configuration, a bipolar diode DB including a pn junction and a unipolar diode DU including a Schottky junction are formed.

[0449] According to this configuration, the reflux current during the reflux operation is processed by the unipolar diode DU, and at the same time, the surge current Is is processed by both the bipolar diode DB and the unipolar diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0450] The trench 15 may partition the second semiconductor layer 7 into one mesa portion 20 (first region) and the other mesa portion 20 (second region). In this case, the diode region 30 may be adjacent to the body region 26 in one mesa portion 20. That is, the body region 26 may be formed in one mesa portion 20, and the diode region 30 may be formed in one mesa portion 20.

[0451] A plurality of body regions 26 may be formed at intervals in one mesa portion 20. In this case, the diode region 30 may be formed in the region between the plurality of body regions 26 in one mesa portion 20.

[0452] The semiconductor device 1B may include a contact region 28. The contact region 28 may be formed in the surface layer portion of the body region 26. The contact region 28 may have an overhanging portion that extends outside the body region 26. In this case, the diode region 30 may have a portion partitioned by the body region 26 and a portion partitioned by the contact region 28.

[0453] Figure 21 is an enlarged plan view showing the active region 8 of the semiconductor device 1C according to the third embodiment. Figure 22 is a cross-sectional view along the line XXII-XXII shown in Figure 21. Figure 23 is a cross-sectional view along the line XXIII-XXIII shown in Figure 21. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 21. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 21.

[0454] The semiconductor device 1C has a configuration in which the layout of the semiconductor device 1A has been modified. In this configuration, the multiple mesa portions 20 are formed as mesa portions 20 for transistors and diodes, respectively. The multiple gate structures 10 and the multiple mesa portions 20 may have at least one configuration from the first to eighth examples (see Figures 10, 13A to 13G).

[0455] The semiconductor device 1C includes a plurality of FET structures 25 formed on a plurality of mesa portions 20. The plurality of FET structures 25 are arranged in a one-to-many relationship with respect to one mesa portion 20, spaced apart in the second direction Y. The plurality of FET structures 25 extend in a strip shape in the second direction Y, following the extending direction of the plurality of gate structures 10.

[0456] With respect to one and the other mesa portion 20, the plurality of FET structures 25 of the other portion face the plurality of FET structures 25 arranged in the first direction X of the one mesa portion 20 via the gate structure 10. The plurality of FET structures 25 of the other portion may face the region between the plurality of FET structures 25 of the one portion in the first direction X.

[0457] Each of the multiple FET structures 25 includes a p-type body region 26, one or more (one in this embodiment) n-type source regions 27, and one or more (two in this embodiment) p-type contact regions 28.

[0458] The body region 26 extends in the second direction Y, following the extension direction of the multiple gate structures 10, and is adjacent to two gate structures 10 corresponding to the first direction X. The body region 26 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode DB including the second semiconductor layer 7 as the cathode region and the body region 26 as the anode region.

[0459] With respect to one and the other mesa portion 20, the plurality of body regions 26 of the other portion face the plurality of body regions 26 of the other portion in the first direction X via the gate structure 10. The plurality of body regions 26 of the other portion may face the region between the plurality of body regions 26 of the one portion in the first direction X.

[0460] The source region 27 is formed on the surface of the body region 26 and extends in the second direction Y, following the direction of extension of the multiple gate structures 10. In this configuration, the source region 27 is formed with a gap between both ends of the body region 26 and the inward side of the body region 26 with respect to the second direction Y. The source region 27 is adjacent to two gate structures 10 corresponding to the first direction X.

[0461] With respect to one and the other mesa portion 20, the plurality of source regions 27 of the other portion face the plurality of source regions 27 of the one portion in the first direction X via the gate structure 10. The plurality of source regions 27 of the other portion may face the region between the plurality of source regions 27 of the one portion in the first direction X.

[0462] Multiple contact regions 28 are formed in a region different from the source region 27 on the surface of the body region 26. In this configuration, the multiple contact regions 28 are formed on both sides of the source region 27 with respect to the second direction Y, and sandwich the source region 27 from both sides in the second direction Y.

[0463] In this configuration, each of the multiple contact regions 28 has an overhang that crosses the periphery of the body region 26 and extends outward from the body region 26. In the region between the multiple body regions 26, the overhangs of the multiple contact regions 28 are formed with a gap between them. The multiple contact regions 28 may also be formed with a gap between them, extending inward from the periphery of the body region 26.

[0464] With respect to one and the other mesa portion 20, the plurality of contact regions 28 of the other portion face the plurality of contact regions 28 of the other portion in the first direction X via the gate structure 10. The plurality of contact regions 28 of the other portion may face the region between the plurality of contact regions 28 of the one portion in the first direction X.

[0465] The semiconductor device 1C includes a plurality of n-type diode regions 30 formed in a plurality of mesa portions 20. In this embodiment, the plurality of diode regions 30 are formed using a portion of the second semiconductor layer 7 and have an n-type impurity concentration approximately equal to that of the second semiconductor layer 7. The n-type impurity concentration of the diode regions 30 may be higher or lower than that of the second semiconductor layer 7.

[0466] Multiple diode regions 30 are formed in a one-to-many relationship with respect to one mesa portion 20, spaced apart in the second direction Y. In this configuration, the multiple diode regions 30 are arranged alternately with the multiple FET structures 25 in the second direction Y. That is, the multiple diode regions 30 are each partitioned in the regions between the multiple FET structures 25 (multiple body regions 26). The multiple diode regions 30 extend in the second direction Y, following the extending direction of the multiple gate structures 10.

[0467] With respect to one and the other mesa portion 20, the plurality of diode regions 30 of the other portion face the plurality of diode regions 30 of the one portion in the first direction X via the gate structure 10. The plurality of diode regions 30 of the other portion may face the region between the plurality of diode regions 30 of the one portion (i.e., the plurality of FET structures 25) in the first direction X.

[0468] In this configuration, the multiple diode regions 30 have a portion partitioned by a plurality of contact regions 28 on the first main surface 3 side, and a portion partitioned by a plurality of body regions 26 on the bottom wall 13 side of the gate structure 10.

[0469] In other words, the multiple diode regions 30 are electrically isolated from the multiple source regions 27 by the multiple body regions 26 and the multiple contact regions 28. As a result, the multiple diode regions 30 do not form a current path that directly passes through the multiple source regions 27.

[0470] If the entire area of ​​the multiple contact regions 28 is located inside the body region 26, the multiple diode regions 30 may be demarcated only by the multiple body regions 26. In other words, the multiple diode regions 30 may be electrically isolated from the multiple source regions 27 by a portion of the multiple body regions 26 and the multiple contact regions 28.

[0471] In one mesa portion 20, the planar area of ​​the diode region 30 may be less than the planar area of ​​the FET structure 25. The planar area of ​​the diode region 30 may be greater than the planar area of ​​the FET structure 25. In one mesa portion 20, the total planar area of ​​multiple diode regions 30 may be less than the total planar area of ​​multiple FET structures 25. The total planar area of ​​multiple diode regions 30 may be greater than the total planar area of ​​multiple FET structures 25.

[0472] The semiconductor device 1C, like the semiconductor device 1A, includes a plurality of p-type well contact regions 37 formed in the inner portion (active region 8) of the second semiconductor layer 7. In this configuration, the plurality of well contact regions 37 are interposed in the regions between a plurality of adjacent contact regions 28 in the first direction X.

[0473] Multiple well contact regions 37 extend along a pair of first side walls 11 and bottom walls 13 of the corresponding gate structure 10, electrically connecting the corresponding well region 35 to multiple adjacent body regions 26 in the first direction X. In this embodiment, the multiple well contact regions 37 electrically connect the corresponding well region 35 to multiple adjacent contact regions 28 in the first direction X.

[0474] Each of the multiple well contact regions 37 has multiple sidewalls and bottom walls. The multiple sidewalls extend along a pair of first sidewalls 11 of the corresponding gate structure 10 and face the embedded electrode 17 via an insulating film 16. The multiple sidewalls are connected to a plurality of body regions 26, increasing the p-type impurity concentration of the plurality of body regions 26. In this embodiment, the multiple sidewalls are connected to a plurality of adjacent contact regions 28 in the first direction X.

[0475] The bottom wall portion is formed along the bottom wall 13 of the corresponding gate structure 10 and faces the embedded electrode 17 via an insulating film 16. The bottom wall portion is connected to the upper end of the well region 35 and increases the p-type impurity concentration of the well region 35. In this configuration, the bottom wall portion protrudes from the corresponding gate structure 10 to both sides and is connected to a plurality of side walls.

[0476] The semiconductor device 1C, like the semiconductor device 1A, includes a source electrode 55. The source electrode 55 enters the source opening 51 from above the interlayer film 45 and collectively covers the multiple gate structures 10 and the multiple mesa portions 20 in a film-like manner.

[0477] The source electrode 55 is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via a plurality of mesa portions 20. In this configuration, the source electrode 55 is mechanically and electrically connected to the c-face and m-face of a plurality of step surfaces S via the inclined side wall 14 (inclined portion 22).

[0478] The source electrode 55 has a portion that is mechanically and electrically connected to a plurality of FET structures 25 by a plurality of mesa portions 20, and a portion that is mechanically and electrically connected to the region between the plurality of FET structures 25 (i.e., the diode region 30) by a plurality of mesa portions 20.

[0479] The source electrode 55 is mechanically and electrically connected to multiple source regions 27 and multiple contact regions 28 (body region 26) on the first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22) on the FET structure 25 side. The source electrode 55 forms ohmic contact with the multiple source regions 27 and multiple contact regions 28.

[0480] The source electrode 55 forms a Schottky junction with the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) on the diode region 30 side. In other words, in this configuration, the source electrode 55 forms a Schottky junction with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0481] Specifically, the source electrode 55 forms Schottky junctions with the c-plane and m-plane of the plurality of step surfaces S on the inclined sidewalls 14 (inclined portions 22). The source electrode 55 enters into the plurality of trenches 15 through the plurality of inclined sidewalls 14 and covers the insulating surfaces of the plurality of buried insulators 18.

[0482] In this form, the source electrode 55 is mechanically and electrically connected to the plurality of first sidewalls 11. The source electrode 55 is mechanically and electrically connected to the plurality of source regions 27 and the plurality of contact regions 28 (body region 26) on the first sidewall 11 on the FET structure 25 side. The source electrode 55 forms ohmic contacts with the plurality of source regions 27 and the plurality of contact regions 28 on the first sidewall 11.

[0483] The source electrode 55 forms a Schottky junction with the first sidewall 11 on the diode region 30 side. That is, in this form, the source electrode 55 forms a Schottky junction with the first sidewall 11 having the second barrier height BH2.

[0484] As a result, a unipolar diode DU including the plurality of diode regions 30 as the cathode region and the source electrode 55 as the anode region is formed. That is, in this form, the unipolar diode DU is connected in parallel with the bipolar diode DB at the common mesa portion 20.

[0485] The Schottky junction area of the source electrode 55 with respect to the mesa portion 20 (the plurality of diode regions 30) is smaller than the connection area of the source electrode 55 with respect to the plurality of FET structures 25. The Schottky junction area of the source electrode 55 with respect to the mesa portion 20 (the plurality of diode regions 30) may be larger than the connection area of the source electrode 55 with respect to the plurality of FET structures 25.

[0486] Similar to the case of the semiconductor device 1A, the source electrode 55 has a laminated structure including a base electrode 56 and an electrode body. The base electrode 56 includes a first electrode 56a and a second electrode 56b. The first electrode 56a is mechanically and electrically connected to both the first main surface 3 (main surface portion 21) and the inclined sidewalls 14 (inclined portions 22) at the plurality of mesa portions 20.

[0487] In this configuration, the first electrode 56a is mechanically and electrically connected to the c-plane and m-plane of the multiple step surfaces S by the inclined side wall 14 (inclined portion 22). The first electrode 56a has a portion that is mechanically and electrically connected to the multiple FET structures 25 by the multiple mesa portions 20, and a portion that is mechanically and electrically connected to the region between the multiple FET structures 25 (i.e., the diode region 30) by the multiple mesa portions 20.

[0488] The first electrode 56a is mechanically and electrically connected to a plurality of source regions 27 and a plurality of contact regions 28 (body region 26) on the first main surface 3 (main surface portion 21) and inclined side wall 14 (inclined portion 22) on the FET structure 25 side. The first electrode 56a forms ohmic contact with the plurality of source regions 27 and a plurality of contact regions 28.

[0489] The first electrode 56a forms a Schottky junction with the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) on the diode region 30 side. In other words, in this configuration, the first electrode 56a forms a Schottky junction with the first main surface 3 (main surface portion 21) having a first barrier height BH1 and the inclined side wall 14 (inclined portion 22) having a third barrier height BH3.

[0490] Specifically, the first electrode 56a forms a Schottky junction with the c-plane and m-plane of the multiple step surfaces S at the inclined side wall 14 (inclined portion 22). The first electrode 56a enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18. In this configuration, the first electrode 56a is mechanically and electrically connected to the multiple first side walls 11.

[0491] The first electrode 56a is mechanically and electrically connected to a plurality of source regions 27 and a plurality of contact regions 28 (body region 26) at the first side wall 11 on the FET structure 25 side. The first electrode 56a forms ohmic contact with the plurality of source regions 27 and a plurality of contact regions 28 at the first side wall 11.

[0492] The first electrode 56a forms a Schottky junction with the first sidewall 11 on the diode region 30 side. In other words, in this configuration, the first electrode 56a forms a Schottky junction with the first sidewall 11 which has a second barrier height BH2.

[0493] The Schottky junction area of ​​the first electrode 56a with respect to the mesa portion 20 (multiple diode regions 30) is smaller than the connection area of ​​the first electrode 56a with respect to the multiple FET structures 25. The Schottky junction area of ​​the first electrode 56a with respect to the mesa portion 20 (multiple diode regions 30) may be larger than the connection area of ​​the first electrode 56a with respect to the multiple FET structures 25.

[0494] The second electrode 56b covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via the first electrode 56a with multiple mesa portions 20, and is electrically connected to multiple FET structures 25 and multiple diode regions 30. The second electrode 56b covers the c-plane and m-plane of multiple step surfaces S via the first electrode 56a with the inclined side wall 14 (inclined portion 22).

[0495] The second electrode 56b enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18 via the first electrode 56a. In this configuration, the second electrode 56b covers the multiple first side walls 11 via the first electrode 56a and is electrically connected to the multiple source regions 27, the multiple contact regions 28 (body regions 26), and the multiple diode regions 30 via the first electrode 56a.

[0496] The main electrode 57 covers the first main surface 3 (main surface portion 21) and the inclined side wall 14 (inclined portion 22) of the gate structure 10 via the base electrode 56 with multiple mesa portions 20, and is electrically connected to multiple FET structures 25 and multiple diode regions 30. The main electrode 57 covers the c-plane and m-plane of multiple step surfaces S via the base electrode 56 with the inclined side wall 14 (inclined portion 22).

[0497] The main electrode 57 enters into the multiple trenches 15 via the multiple inclined side walls 14 and covers the insulating surfaces of the multiple embedded insulators 18 via the base electrode 56. In this configuration, the main electrode 57 covers the multiple first side walls 11 via the base electrode 56 and is electrically connected to the multiple source regions 27, the multiple contact regions 28 (body regions 26), and the multiple diode regions 30 via the base electrode 56.

[0498] As described above, the semiconductor device 1C may include a second semiconductor layer 7 (semiconductor layer), a trench 15, and a source electrode 55 (electrode). The second semiconductor layer 7 may contain SiC and have a first main surface 3. The first main surface 3 may have a first barrier height BH1. The trench 15 is formed on the first main surface 3 and may have a first side wall 11 and an inclined side wall 14. The inclined side wall 14 may slope downward from the first main surface 3 toward the first side wall 11.

[0499] The first sidewall 11 may have a second barrier height BH2 that is lower than the first barrier height BH1. The inclined sidewall 14 may have a third barrier height BH3 that is higher than the second barrier height BH2 and lower than the first barrier height BH1. The source electrode 55 may cover the first main surface 3 and the inclined sidewall 14 in cross-sectional view, and may form a Schottky junction (heterojunction) with both the first main surface 3 and the inclined sidewall 14.

[0500] This configuration provides a novel semiconductor device 1C. For example, with this semiconductor device 1C, the barrier height difference between the first main surface 3 and the first side wall 11 is mitigated by the inclined side wall 14. This suppresses the source electrode 55 from being connected only to the first main surface 3 and the first side wall 11, and stabilizes the threshold voltage of the Schottky junction.

[0501] The semiconductor device 1C may include an n-type second semiconductor layer 7, a p-type body region 26, and an n-type diode region 30. The body region 26 may be formed along the trench 15 within the second semiconductor layer 7 and may form a pn junction with the second semiconductor layer 7. The diode region 30 may be formed along the trench 15 within the second semiconductor layer 7.

[0502] The source electrode 55 is electrically connected to the body region 26 on the first main surface 3, and may form a Schottky junction with the diode region 30 on both the first main surface 3 and the inclined side wall 14. With this configuration, a bipolar diode DB including a pn junction and a unipolar diode DU including a Schottky junction are formed.

[0503] In this configuration, the freewheeling current during freewheeling operation is handled by the unipolar diode DU, while the surge current Is is handled by both the bipolar diode DB and the unipolar diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0504] The trench 15 may divide the second semiconductor layer 7 into one mesa portion 20 (first region) and the other mesa portion 20 (second region). In this case, the diode region 30 may be adjacent to the body region 26 in one of the mesa portions 20. That is, the body region 26 may be formed in one of the mesa portions 20, and the diode region 30 may be formed in the other mesa portion 20.

[0505] Multiple body regions 26 may be formed in one mesa portion 20 at intervals. In this case, the diode region 30 may be formed in the region between the multiple body regions 26 in one mesa portion 20.

[0506] The semiconductor device 1C may include a contact region 28. The contact region 28 may be formed on the surface of the body region 26. The contact region 28 may have an overhang that extends outside the body region 26. In this case, the diode region 30 may have a portion demarcated by the body region 26 and a portion demarcated by the contact region 28.

[0507] The semiconductor device 1C may include an n-type second semiconductor layer 7, an FET structure 25, and an n-type diode region 30. The FET structure 25 may be formed along the trench 15 within the second semiconductor layer 7. The diode region 30 may be formed along the trench 15 within the second semiconductor layer 7.

[0508] The source electrode 55 is electrically connected to the FET structure 25 on the first main surface 3, and a Schottky junction may be formed with the diode region 30 on both the first main surface 3 and the inclined side wall 14. With this configuration, the electrical characteristics are improved in the configuration having the FET structure 25 and the Schottky junction.

[0509] In this configuration, the freewheeling current during freewheeling operation is handled by the unipolar diode DU, while the surge current Is is handled by both the bipolar diode DB and the unipolar diode DU. Such a configuration is effective in reducing energy loss and suppressing bipolar degradation.

[0510] The trench 15 may divide the second semiconductor layer 7 into one mesa portion 20 (first region) and the other mesa portion 20 (second region). In this case, the diode region 30 may be adjacent to the FET structure 25 in one of the mesa portions 20. That is, the FET structure 25 may be formed in one of the mesa portions 20, and the diode region 30 may be formed in the other mesa portion 20.

[0511] Multiple FET structures 25 may be formed at intervals in one of the mesa portions 20. In this case, the diode region 30 may be formed in the region between the multiple FET structures 25 in one of the mesa portions 20.

[0512] Multiple FET structures 25 may be formed in one mesa portion 20 and the other mesa portion 20. Multiple diode regions 30 may be formed in one mesa portion 20 and the other mesa portion 20. In this case, the other set of diode regions 30 may face the first set of diode regions 30 via trenches 15. The other set of diode regions 30 may face the first set of FET structures 25 via trenches 15.

[0513] Figure 26 is an enlarged plan view showing the active region 8 of the semiconductor device 1D according to the fourth embodiment. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 26. Figure 28 is a cross-sectional view along the line XXVIII-XXVIII shown in Figure 26. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 26.

[0514] The semiconductor device 1D has a layout that combines the layout of semiconductor device 1B and the layout of semiconductor device 1C. Specifically, the multiple mesa sections 20 in this embodiment have multiple first mesa units MU1 for transistors and diodes, and multiple second mesa units MU2 for dummy transistors and diodes.

[0515] The multiple gate structures 10 and the multiple mesa sections 20 may have at least one configuration from the first to eighth examples (Figures 10, 13A to 13G). The multiple first mesa units MU1 (first mesa section 20A) and the multiple second mesa units MU2 (second mesa section 20B) may have at least one layout example from the first to fourth layout examples described above (Figures 4, 14A to 14C).

[0516] The semiconductor device 1D includes a plurality of FET structures 25 and a plurality of diode regions 30 formed in the first mesa portion 20A. The layout of the plurality of FET structures 25 and the plurality of diode regions 30 is the same as in the case of semiconductor device 1C.

[0517] The semiconductor device 1D includes a plurality of dummy FET structures 75 and a plurality of diode regions 30 formed in the second mesa portion 20B. The layout of the plurality of dummy FET structures 75 and the plurality of diode regions 30 is the same as in the case of semiconductor device 1B. For other configurations relating to semiconductor device 1D, the descriptions of the configurations relating to semiconductor devices 1A, 1B, and 1C apply.

[0518] Figure 30 is a cross-sectional perspective view showing a modified well region 35. Although Figure 30 shows an example in which the modified well region 35 is applied to semiconductor device 1A, the modified well region 35 may be applied to any one of semiconductor devices 1B to 1D.

[0519] Referring to Figure 30, in this configuration, the multiple well regions 35 extend in directions that intersect the multiple gate structures 10. Specifically, the multiple well regions 35 are formed at intervals in the second direction Y and each extends in a strip-like manner in the first direction X. In other words, the multiple well regions 35 are perpendicular to the multiple gate structures 10.

[0520] In this embodiment, the multiple well regions 35 each have a portion located on the first main surface 3 side with respect to the depth position of the bottom wall 13 of the multiple gate structures 10, and a portion located on the bottom side of the second semiconductor layer 7 with respect to the depth position of the bottom wall 13 of the multiple gate structures 10.

[0521] The multiple well regions 35 have portions located in multiple first mesa portions 20A and portions located in multiple second mesa portions 20B. The multiple well regions 35 are connected to multiple body regions 26 in the multiple first mesa portions 20A. The multiple well regions 35, together with the multiple gate structures 10, define multiple diode regions 30 that extend in the thickness direction Z in the multiple second mesa portions 20B.

[0522] The multiple well regions 35 may have portions located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 17 in the multiple second mesa portions 20B. The multiple well regions 35 may have portions located on the first main surface 3 side with respect to the insulating surface of the embedded insulator 18. The multiple well regions 35 may have portions facing the embedded electrode 17 in the horizontal direction and portions facing the embedded insulator 18 in the horizontal direction.

[0523] The multiple well regions 35 may have portions along the first main surface 3, the first side wall 11 of the gate structure 10, and the inclined side wall 14 of the gate structure 10 in the multiple second mesa portions 20B. In other words, the multiple well regions 35 may have portions along the main surface portion 21 and the inclined portion 22 of the multiple second mesa portions 20B.

[0524] The aforementioned source electrode 55 may be mechanically and / or electrically connected to the multiple well regions 35 by a plurality of second mesa portions 20B. In this case, the source electrode 55 may be mechanically and / or electrically connected to the multiple well regions 35 by the first main surface 3 (main surface portion 21), the inclined side wall 14 (inclined portion 22), and the first side wall 11.

[0525] In other words, the first electrode 56a may be mechanically and / or electrically connected to a plurality of well regions 35 via a plurality of second mesa portions 20B. The second electrode 56b may be electrically connected to a plurality of well regions 35 via the first electrode 56a via a plurality of second mesa portions 20B. The main electrode 57 may be electrically connected to a plurality of well regions 35 via the base electrode 56 via a plurality of second mesa portions 20B.

[0526] Figure 31 is an enlarged cross-sectional view showing the mesa portion 20 of semiconductor device 1A according to a modified example. Although Figure 31 shows an example in which the configuration according to the modified example is applied to semiconductor device 1A, the configuration according to the modified example may be applied to any one of semiconductor devices 1B to 1D. In the aforementioned semiconductor devices 1A to 1D, the first direction X was the m-axis direction and the second direction Y was the a-axis direction. However, the first direction X may be the a-axis direction and the second direction Y may be the m-axis direction.

[0527] In other words, the first sidewall 11 (long side) of the gate structure 10 (trench 15) may be formed by the a-plane of the SiC single crystal, and the second sidewall 12 (short side) of the gate structure 10 (trench 15) may be formed by the m-plane of the SiC single crystal.

[0528] In this case, the inclined sidewall 14 (inclined portion 22) of the gate structure 10 may have a plurality of step surfaces S formed by the c-plane and a-plane of the SiC single crystal. In this embodiment, the third barrier height BH3 of the inclined sidewall 14 (inclined portion 22) is due to both the c-plane and a-plane of the SiC single crystal and is higher than the second barrier height BH2 and lower than the first barrier height BH1.

[0529] Each of the above-described embodiments (including variations) can be implemented in other forms. The features of the above-described semiconductor devices 1A to 1D (including variations) can be combined as appropriate. Therefore, semiconductor devices 1A to 1D may simultaneously include two, three, or four of the features of semiconductor devices 1A to 1D.

[0530] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. In this case, the specific configuration can be obtained by replacing n-type with p-type and p-type with n-type, as shown in the above description and attached drawings.

[0531] In the embodiments described above, an n-type first semiconductor layer 6 was shown. However, the conductivity type of the first semiconductor layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0532] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0533] [A1] A semiconductor device (1A to 1D) comprising: a semiconductor layer (2, 7) containing SiC and having a main surface (3) having a first barrier height (BH1); a side wall (11) having a second barrier height (BH2) lower than the first barrier height (BH1); and an inclined side wall (14) that is higher than the second barrier height (BH2) and lower than the first barrier height (BH1), and that slopes downward from the main surface (3) to the side wall (11); and an electrode (55) that covers the main surface (3) and the inclined side wall (14) and forms a Schottky junction with both the main surface (3) and the inclined side wall (14).

[0534] [A2] The semiconductor device described in A1 (1A to 1D), wherein the SiC is 4H (Hexagonal)-SiC.

[0535] [A3] The semiconductor device (1A to 1D) according to A1 or A2, wherein the semiconductor layer (2, 7) has an off-angle.

[0536] [A4] The semiconductor device described in A3 (1A to 1D), wherein the off-angle is 10° or less.

[0537] [A5] The semiconductor device (1A to 1D) according to A3 or A4, wherein the off-direction of the off-angle is the a-axis direction of the SiC.

[0538] [A6] The semiconductor device (1A to 1D) according to any one of A1 to A5, wherein the first barrier height (BH1) is due to the c-plane of the SiC, the second barrier height (BH2) is due to the m-plane of the SiC, and the third barrier height (BH3) is due to both the c-plane and the m-plane of the SiC.

[0539] [A7] The trench (15) extends in the a-axis direction of the SiC, as described in A6, semiconductor device (1A to 1D).

[0540] [A8] The semiconductor device (1A to 1D) according to any one of A1 to A5, wherein the first barrier height (BH1) is due to the c-plane of the SiC, the second barrier height (BH2) is due to the a-plane of the SiC, and the third barrier height (BH3) is due to both the c-plane and the a-plane of the SiC.

[0541] [A9] The trench (15) extends in the m-axis direction of the SiC, as described in A8, semiconductor device (1A to 1D).

[0542] [A10] The electrode (55) covers the entire area of ​​the inclined side wall (14) in cross-sectional view and forms the Schottky junction with the entire area of ​​the inclined side wall (14), as described in any one of A1 to A9 (1A to 1D).

[0543] [A11] A semiconductor device (1A to 1D) according to any one of A1 to A10, further comprising an insulating film (16) covering the side wall (11) below the inclined side wall (14), and an embedded electrode (17) embedded in the trench (15) via the insulating film (16) below the inclined side wall (14).

[0544] [A12] The semiconductor device (1A to 1D) according to A11, wherein the electrode (55) is provided with a potential different from that of the embedded electrode (17).

[0545] [A13] A semiconductor device (1A to 1D) according to A11 or A12, further comprising a buried insulator (18) embedded in the trench (15) below the inclined side wall (14) and covering the buried electrode (17), wherein the electrode (55) covers the inclined side wall (14) and the buried insulator (18) within the trench (15) and is electrically insulated from the buried electrode (17) by the buried insulator (18).

[0546] [A14] A semiconductor device (1A to 1D) according to any one of A1 to A13, further comprising: a semiconductor layer (2, 7) of a first conductivity type (n-type / p-type); and a well region (35) of a second conductivity type (p-type / n-type) formed in the region below the trench (15) within the semiconductor layer (2, 7).

[0547] [A15] A semiconductor device (1A to 1D) according to any one of A1 to A13, further comprising: a semiconductor layer (2, 7) of a first conductivity type (n-type / p-type); an FET structure (25) formed along the trench (15) within the semiconductor layer (2, 7); and a diode region (30) of a first conductivity type (n-type / p-type) formed along the trench (15) within the semiconductor layer (2, 7), wherein the electrode (55) is electrically connected to the FET structure (25) on the main surface (3), and the diode region (30) and the Schottky junction are formed on both the main surface (3) and the inclined side wall (14).

[0548] [A16] The semiconductor device (1A to 1D) according to A15, wherein the trench (15) divides the semiconductor layer (2, 7) into a first region (20, 20A / 20B) on one side and a second region (20, 20B / 20A) on the other side, the FET structure (25) is formed in the first region (20, 20A / 20B) of the semiconductor layer (2, 7), and the diode region (30) is formed in the second region (20, 20B / 20A) of the semiconductor layer (2, 7).

[0549] [A17] The semiconductor device (1A to 1D) according to A15, wherein the trench (15) divides the semiconductor layer (2, 7) into a first region (20, 20A / 20B) on one side and a second region (20, 20B / 20A) on the other side, the FET structure (25) is formed in the first region (20, 20A / 20B) of the semiconductor layer (2, 7), and the diode region (30) is formed in the first region (20, 20A / 20B) of the semiconductor layer (2, 7).

[0550] [A18] A semiconductor device (1A to 1D) according to any one of A15 to A17, further comprising a well region (35) of a second conductivity type (p-type / n-type) formed in the region below the trench (15) within the semiconductor layer (2, 7).

[0551] [A19] A semiconductor device (1A to 1D) comprising: a semiconductor layer (2, 7) having a main surface (3); a trench electrode type gate structure (10) formed on the main surface (3); a mesa portion (20, 20B / 20A) having a main surface portion (21) that is part of the main surface (3) and an inclined portion (22) that slopes downward from the main surface (3) portion toward the gate structure (10), and partitioned in the semiconductor layer (2, 7) by the gate structure (10); and an electrode (55) that forms a Schottky junction with both the main surface (3) portion and the inclined portion (22) of the mesa portion (20, 20B / 20A).

[0552] [A20] The semiconductor device (1A to 1D) according to A19, wherein the gate structure (10) includes a trench (15) formed on the main surface (3), an insulating film (16) covering the wall surface of the trench (15), an embedded electrode (17) embedded in the trench (15) via the insulating film (16), and an embedded insulator (18) covering the embedded electrode (17) within the trench (15), and the electrode (55) covers the embedded insulator (18) within the trench (15).

[0553] Although specific forms have been described in detail above, these are merely examples to illustrate the technical content. The various technical ideas extracted from this specification can be combined as appropriate, without being limited by the order of explanation, the order of the examples of forms, or the order of the modifications within the specification.

[0554] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 2 Chip (semiconductor layer) 3 First main surface 7 Second semiconductor layer (semiconductor layer) 10 Gate structure 11 First sidewall (side wall) 14 Inclined sidewall 15 Trench 16 Insulating film 17 Embedded electrode 18 Embedded insulator 20 Mesa section 20A First mesa section (first region) 20B Second mesa section (second region) 21 Main surface section 22 Inclined section 25 FET structure 30 Diode region 35 Well region 55 Source electrode (electrode) BH1 First barrier height BH2 Second barrier height BH3 Third barrier height

Claims

1. A semiconductor device comprising: a semiconductor layer containing SiC and having a main surface having a first barrier height; a side wall having a second barrier height lower than the first barrier height; a trench formed in the main surface having a third barrier height higher than the second barrier height and lower than the first barrier height, and sloping downward from the main surface to the side wall; and an electrode covering the main surface and the sloping side wall, forming a Schottky junction with both the main surface and the sloping side wall.

2. The semiconductor device according to claim 1, wherein the SiC is 4H (Hexagonal)-SiC.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor layer has an off-angle.

4. The semiconductor device according to claim 3, wherein the off-angle is 10° or less.

5. The semiconductor device according to claim 3 or 4, wherein the off-direction of the off-angle is the a-axis direction of the SiC.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first barrier height is due to the c-plane of the SiC, the second barrier height is due to the m-plane of the SiC, and the third barrier height is due to both the c-plane and the m-plane of the SiC.

7. The semiconductor device according to claim 6, wherein the trench extends in the a-axis direction of the SiC.

8. The semiconductor device according to any one of claims 1 to 7, wherein the first barrier height is due to the c-plane of the SiC, the second barrier height is due to the a-plane of the SiC, and the third barrier height is due to both the c-plane and the a-plane of the SiC.

9. The semiconductor device according to claim 8, wherein the trench extends in the m-axis direction of the SiC.

10. The semiconductor device according to any one of claims 1 to 9, wherein the electrode covers the entire area of ​​the inclined side wall in a cross-sectional view and forms the Schottky junction with the entire area of ​​the inclined side wall.

11. The semiconductor device according to any one of claims 1 to 10, further comprising: an insulating film covering the side wall below the inclined side wall; and an embedded electrode embedded in the trench via the insulating film below the inclined side wall.

12. The semiconductor device according to claim 11, wherein the electrode is provided with a potential different from that of the embedded electrode.

13. The semiconductor device according to claim 11 or 12, further comprising an embedded insulator embedded in the trench below the inclined side wall and covering the embedded electrode, wherein the electrode covers the inclined side wall and the embedded insulator within the trench and is electrically insulated from the embedded electrode by the embedded insulator.

14. The semiconductor device according to any one of claims 1 to 13, further comprising: a semiconductor layer of a first conductivity type; and a well region of a second conductivity type formed in the region below the trench within the semiconductor layer.

15. The semiconductor device according to any one of claims 1 to 14, further comprising: a semiconductor layer of a first conductivity type; an FET structure formed along the trench within the semiconductor layer; and a diode region of a first conductivity type formed along the trench within the semiconductor layer, wherein the electrode is electrically connected to the FET structure on the main surface, and the diode region and the Schottky junction are formed on both the main surface and the inclined side wall.

16. The semiconductor device according to claim 15, wherein the trench divides the semiconductor layer into a first region on one side and a second region on the other side, the FET structure is formed in the first region of the semiconductor layer, and the diode region is formed in the second region of the semiconductor layer.

17. The semiconductor device according to claim 15, wherein the trench divides the semiconductor layer into a first region on one side and a second region on the other side, the FET structure is formed in the first region of the semiconductor layer, and the diode region is formed in the first region of the semiconductor layer.

18. The semiconductor device according to any one of claims 15 to 17, further comprising a second conductivity type well region formed in the region below the trench within the semiconductor layer.

19. A semiconductor device comprising: a semiconductor layer having a main surface; a trench electrode type gate structure formed on the main surface; a mesa portion having a main surface portion consisting of a part of the main surface and an inclined portion that slopes downward from the main surface portion toward the gate structure, and partitioned in the semiconductor layer by the gate structure; and an electrode that forms a Schottky junction with both the main surface portion and the inclined portion of the mesa portion.

20. The semiconductor device according to claim 19, wherein the gate structure includes a trench formed on the main surface, an insulating film covering the wall surface of the trench, an embedded electrode embedded in the trench via the insulating film, and an embedded insulator covering the embedded electrode within the trench, the electrode covering the embedded insulator within the trench.

Images